1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <dt-bindings/interconnect/qcom,sdx65.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 #include "sdx65.h" 16 17 DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1); 18 DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); 19 DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC); 20 DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); 21 DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC); 22 DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC); 23 DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); 24 DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); 25 DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC); 26 DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); 27 DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); 28 DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM); 29 DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); 30 DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0); 31 DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); 32 DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0); 33 DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC); 34 DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); 35 DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); 36 DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC); 37 DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4); 38 DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC); 39 DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC); 40 DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC); 41 DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4); 42 DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4); 43 DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4); 44 DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4); 45 DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4); 46 DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4); 47 DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4); 48 DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4); 49 DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4); 50 DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4); 51 DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4); 52 DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4); 53 DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4); 54 DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4); 55 DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4); 56 DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4); 57 DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4); 58 DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG); 59 DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4); 60 DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4); 61 DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4); 62 DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4); 63 DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4); 64 DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4); 65 DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC); 66 DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC); 67 DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8); 68 DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4); 69 DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8); 70 DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4); 71 DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8); 72 73 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); 74 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); 75 DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc); 76 DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); 77 DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); 78 DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); 79 DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto); 80 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); 81 DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc); 82 DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); 83 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); 84 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); 85 DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm); 86 DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg); 87 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie); 88 DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr); 89 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc); 90 DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc); 91 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie); 92 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv); 93 94 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 95 &bcm_mc0, 96 }; 97 98 static struct qcom_icc_node * const mc_virt_nodes[] = { 99 [MASTER_LLCC] = &llcc_mc, 100 [SLAVE_EBI1] = &ebi, 101 }; 102 103 static const struct qcom_icc_desc sdx65_mc_virt = { 104 .nodes = mc_virt_nodes, 105 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 106 .bcms = mc_virt_bcms, 107 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 108 }; 109 110 static struct qcom_icc_bcm * const mem_noc_bcms[] = { 111 &bcm_sh0, 112 &bcm_sh1, 113 &bcm_sh3, 114 }; 115 116 static struct qcom_icc_node * const mem_noc_nodes[] = { 117 [MASTER_TCU_0] = &acm_tcu, 118 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 119 [MASTER_APPSS_PROC] = &xm_apps_rdwr, 120 [SLAVE_LLCC] = &qns_llcc, 121 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 122 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 123 }; 124 125 static const struct qcom_icc_desc sdx65_mem_noc = { 126 .nodes = mem_noc_nodes, 127 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 128 .bcms = mem_noc_bcms, 129 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 130 }; 131 132 static struct qcom_icc_bcm * const system_noc_bcms[] = { 133 &bcm_ce0, 134 &bcm_pn0, 135 &bcm_pn1, 136 &bcm_pn2, 137 &bcm_pn3, 138 &bcm_pn4, 139 &bcm_sn0, 140 &bcm_sn1, 141 &bcm_sn2, 142 &bcm_sn3, 143 &bcm_sn5, 144 &bcm_sn6, 145 &bcm_sn7, 146 &bcm_sn8, 147 &bcm_sn9, 148 &bcm_sn10, 149 }; 150 151 static struct qcom_icc_node * const system_noc_nodes[] = { 152 [MASTER_AUDIO] = &qhm_audio, 153 [MASTER_BLSP_1] = &qhm_blsp1, 154 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 155 [MASTER_QPIC] = &qhm_qpic, 156 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 157 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, 158 [MASTER_ANOC_SNOC] = &qnm_aggre_noc, 159 [MASTER_IPA] = &qnm_ipa, 160 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 161 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, 162 [MASTER_CRYPTO] = &qxm_crypto, 163 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, 164 [MASTER_PCIE_0] = &xm_pcie, 165 [MASTER_QDSS_ETR] = &xm_qdss_etr, 166 [MASTER_SDCC_1] = &xm_sdc1, 167 [MASTER_USB3] = &xm_usb3, 168 [SLAVE_AOSS] = &qhs_aoss, 169 [SLAVE_APPSS] = &qhs_apss, 170 [SLAVE_AUDIO] = &qhs_audio, 171 [SLAVE_BLSP_1] = &qhs_blsp1, 172 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 173 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 174 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 175 [SLAVE_ECC_CFG] = &qhs_ecc_cfg, 176 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 177 [SLAVE_IPA_CFG] = &qhs_ipa, 178 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 179 [SLAVE_PCIE_PARF] = &qhs_pcie_parf, 180 [SLAVE_PDM] = &qhs_pdm, 181 [SLAVE_PRNG] = &qhs_prng, 182 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 183 [SLAVE_QPIC] = &qhs_qpic, 184 [SLAVE_SDCC_1] = &qhs_sdc1, 185 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 186 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, 187 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, 188 [SLAVE_TCSR] = &qhs_tcsr, 189 [SLAVE_TLMM] = &qhs_tlmm, 190 [SLAVE_USB3] = &qhs_usb3, 191 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, 192 [SLAVE_ANOC_SNOC] = &qns_aggre_noc, 193 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, 194 [SLAVE_IMEM] = &qxs_imem, 195 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 196 [SLAVE_PCIE_0] = &xs_pcie, 197 [SLAVE_QDSS_STM] = &xs_qdss_stm, 198 [SLAVE_TCU] = &xs_sys_tcu_cfg, 199 }; 200 201 static const struct qcom_icc_desc sdx65_system_noc = { 202 .nodes = system_noc_nodes, 203 .num_nodes = ARRAY_SIZE(system_noc_nodes), 204 .bcms = system_noc_bcms, 205 .num_bcms = ARRAY_SIZE(system_noc_bcms), 206 }; 207 208 static const struct of_device_id qnoc_of_match[] = { 209 { .compatible = "qcom,sdx65-mc-virt", 210 .data = &sdx65_mc_virt}, 211 { .compatible = "qcom,sdx65-mem-noc", 212 .data = &sdx65_mem_noc}, 213 { .compatible = "qcom,sdx65-system-noc", 214 .data = &sdx65_system_noc}, 215 { } 216 }; 217 MODULE_DEVICE_TABLE(of, qnoc_of_match); 218 219 static struct platform_driver qnoc_driver = { 220 .probe = qcom_icc_rpmh_probe, 221 .remove = qcom_icc_rpmh_remove, 222 .driver = { 223 .name = "qnoc-sdx65", 224 .of_match_table = qnoc_of_match, 225 .sync_state = icc_sync_state, 226 }, 227 }; 228 module_platform_driver(qnoc_driver); 229 230 MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver"); 231 MODULE_LICENSE("GPL v2"); 232