1*39a53928SRohit Agarwal // SPDX-License-Identifier: GPL-2.0-only 2*39a53928SRohit Agarwal /* 3*39a53928SRohit Agarwal * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4*39a53928SRohit Agarwal */ 5*39a53928SRohit Agarwal 6*39a53928SRohit Agarwal #include <linux/device.h> 7*39a53928SRohit Agarwal #include <linux/interconnect.h> 8*39a53928SRohit Agarwal #include <linux/interconnect-provider.h> 9*39a53928SRohit Agarwal #include <linux/module.h> 10*39a53928SRohit Agarwal #include <linux/of_platform.h> 11*39a53928SRohit Agarwal #include <dt-bindings/interconnect/qcom,sdx65.h> 12*39a53928SRohit Agarwal 13*39a53928SRohit Agarwal #include "bcm-voter.h" 14*39a53928SRohit Agarwal #include "icc-rpmh.h" 15*39a53928SRohit Agarwal #include "sdx65.h" 16*39a53928SRohit Agarwal 17*39a53928SRohit Agarwal DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1); 18*39a53928SRohit Agarwal DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); 19*39a53928SRohit Agarwal DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC); 20*39a53928SRohit Agarwal DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); 21*39a53928SRohit Agarwal DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC); 22*39a53928SRohit Agarwal DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC); 23*39a53928SRohit Agarwal DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); 24*39a53928SRohit Agarwal DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); 25*39a53928SRohit Agarwal DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC); 26*39a53928SRohit Agarwal DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); 27*39a53928SRohit Agarwal DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); 28*39a53928SRohit Agarwal DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM); 29*39a53928SRohit Agarwal DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); 30*39a53928SRohit Agarwal DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0); 31*39a53928SRohit Agarwal DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); 32*39a53928SRohit Agarwal DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0); 33*39a53928SRohit Agarwal DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC); 34*39a53928SRohit Agarwal DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); 35*39a53928SRohit Agarwal DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); 36*39a53928SRohit Agarwal DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC); 37*39a53928SRohit Agarwal DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4); 38*39a53928SRohit Agarwal DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC); 39*39a53928SRohit Agarwal DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC); 40*39a53928SRohit Agarwal DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC); 41*39a53928SRohit Agarwal DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4); 42*39a53928SRohit Agarwal DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4); 43*39a53928SRohit Agarwal DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4); 44*39a53928SRohit Agarwal DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4); 45*39a53928SRohit Agarwal DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4); 46*39a53928SRohit Agarwal DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4); 47*39a53928SRohit Agarwal DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4); 48*39a53928SRohit Agarwal DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4); 49*39a53928SRohit Agarwal DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4); 50*39a53928SRohit Agarwal DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4); 51*39a53928SRohit Agarwal DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4); 52*39a53928SRohit Agarwal DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4); 53*39a53928SRohit Agarwal DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4); 54*39a53928SRohit Agarwal DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4); 55*39a53928SRohit Agarwal DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4); 56*39a53928SRohit Agarwal DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4); 57*39a53928SRohit Agarwal DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4); 58*39a53928SRohit Agarwal DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG); 59*39a53928SRohit Agarwal DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4); 60*39a53928SRohit Agarwal DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4); 61*39a53928SRohit Agarwal DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4); 62*39a53928SRohit Agarwal DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4); 63*39a53928SRohit Agarwal DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4); 64*39a53928SRohit Agarwal DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4); 65*39a53928SRohit Agarwal DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC); 66*39a53928SRohit Agarwal DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC); 67*39a53928SRohit Agarwal DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8); 68*39a53928SRohit Agarwal DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4); 69*39a53928SRohit Agarwal DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8); 70*39a53928SRohit Agarwal DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4); 71*39a53928SRohit Agarwal DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8); 72*39a53928SRohit Agarwal 73*39a53928SRohit Agarwal DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); 74*39a53928SRohit Agarwal DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); 75*39a53928SRohit Agarwal DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc); 76*39a53928SRohit Agarwal DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); 77*39a53928SRohit Agarwal DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); 78*39a53928SRohit Agarwal DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); 79*39a53928SRohit Agarwal DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto); 80*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); 81*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc); 82*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); 83*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); 84*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); 85*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm); 86*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg); 87*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie); 88*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr); 89*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc); 90*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc); 91*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie); 92*39a53928SRohit Agarwal DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv); 93*39a53928SRohit Agarwal 94*39a53928SRohit Agarwal static struct qcom_icc_bcm * const mc_virt_bcms[] = { 95*39a53928SRohit Agarwal &bcm_mc0, 96*39a53928SRohit Agarwal }; 97*39a53928SRohit Agarwal 98*39a53928SRohit Agarwal static struct qcom_icc_node * const mc_virt_nodes[] = { 99*39a53928SRohit Agarwal [MASTER_LLCC] = &llcc_mc, 100*39a53928SRohit Agarwal [SLAVE_EBI1] = &ebi, 101*39a53928SRohit Agarwal }; 102*39a53928SRohit Agarwal 103*39a53928SRohit Agarwal static const struct qcom_icc_desc sdx65_mc_virt = { 104*39a53928SRohit Agarwal .nodes = mc_virt_nodes, 105*39a53928SRohit Agarwal .num_nodes = ARRAY_SIZE(mc_virt_nodes), 106*39a53928SRohit Agarwal .bcms = mc_virt_bcms, 107*39a53928SRohit Agarwal .num_bcms = ARRAY_SIZE(mc_virt_bcms), 108*39a53928SRohit Agarwal }; 109*39a53928SRohit Agarwal 110*39a53928SRohit Agarwal static struct qcom_icc_bcm * const mem_noc_bcms[] = { 111*39a53928SRohit Agarwal &bcm_sh0, 112*39a53928SRohit Agarwal &bcm_sh1, 113*39a53928SRohit Agarwal &bcm_sh3, 114*39a53928SRohit Agarwal }; 115*39a53928SRohit Agarwal 116*39a53928SRohit Agarwal static struct qcom_icc_node * const mem_noc_nodes[] = { 117*39a53928SRohit Agarwal [MASTER_TCU_0] = &acm_tcu, 118*39a53928SRohit Agarwal [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 119*39a53928SRohit Agarwal [MASTER_APPSS_PROC] = &xm_apps_rdwr, 120*39a53928SRohit Agarwal [SLAVE_LLCC] = &qns_llcc, 121*39a53928SRohit Agarwal [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 122*39a53928SRohit Agarwal [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 123*39a53928SRohit Agarwal }; 124*39a53928SRohit Agarwal 125*39a53928SRohit Agarwal static const struct qcom_icc_desc sdx65_mem_noc = { 126*39a53928SRohit Agarwal .nodes = mem_noc_nodes, 127*39a53928SRohit Agarwal .num_nodes = ARRAY_SIZE(mem_noc_nodes), 128*39a53928SRohit Agarwal .bcms = mem_noc_bcms, 129*39a53928SRohit Agarwal .num_bcms = ARRAY_SIZE(mem_noc_bcms), 130*39a53928SRohit Agarwal }; 131*39a53928SRohit Agarwal 132*39a53928SRohit Agarwal static struct qcom_icc_bcm * const system_noc_bcms[] = { 133*39a53928SRohit Agarwal &bcm_ce0, 134*39a53928SRohit Agarwal &bcm_pn0, 135*39a53928SRohit Agarwal &bcm_pn1, 136*39a53928SRohit Agarwal &bcm_pn2, 137*39a53928SRohit Agarwal &bcm_pn3, 138*39a53928SRohit Agarwal &bcm_pn4, 139*39a53928SRohit Agarwal &bcm_sn0, 140*39a53928SRohit Agarwal &bcm_sn1, 141*39a53928SRohit Agarwal &bcm_sn2, 142*39a53928SRohit Agarwal &bcm_sn3, 143*39a53928SRohit Agarwal &bcm_sn5, 144*39a53928SRohit Agarwal &bcm_sn6, 145*39a53928SRohit Agarwal &bcm_sn7, 146*39a53928SRohit Agarwal &bcm_sn8, 147*39a53928SRohit Agarwal &bcm_sn9, 148*39a53928SRohit Agarwal &bcm_sn10, 149*39a53928SRohit Agarwal }; 150*39a53928SRohit Agarwal 151*39a53928SRohit Agarwal static struct qcom_icc_node * const system_noc_nodes[] = { 152*39a53928SRohit Agarwal [MASTER_AUDIO] = &qhm_audio, 153*39a53928SRohit Agarwal [MASTER_BLSP_1] = &qhm_blsp1, 154*39a53928SRohit Agarwal [MASTER_QDSS_BAM] = &qhm_qdss_bam, 155*39a53928SRohit Agarwal [MASTER_QPIC] = &qhm_qpic, 156*39a53928SRohit Agarwal [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 157*39a53928SRohit Agarwal [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, 158*39a53928SRohit Agarwal [MASTER_ANOC_SNOC] = &qnm_aggre_noc, 159*39a53928SRohit Agarwal [MASTER_IPA] = &qnm_ipa, 160*39a53928SRohit Agarwal [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 161*39a53928SRohit Agarwal [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, 162*39a53928SRohit Agarwal [MASTER_CRYPTO] = &qxm_crypto, 163*39a53928SRohit Agarwal [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, 164*39a53928SRohit Agarwal [MASTER_PCIE_0] = &xm_pcie, 165*39a53928SRohit Agarwal [MASTER_QDSS_ETR] = &xm_qdss_etr, 166*39a53928SRohit Agarwal [MASTER_SDCC_1] = &xm_sdc1, 167*39a53928SRohit Agarwal [MASTER_USB3] = &xm_usb3, 168*39a53928SRohit Agarwal [SLAVE_AOSS] = &qhs_aoss, 169*39a53928SRohit Agarwal [SLAVE_APPSS] = &qhs_apss, 170*39a53928SRohit Agarwal [SLAVE_AUDIO] = &qhs_audio, 171*39a53928SRohit Agarwal [SLAVE_BLSP_1] = &qhs_blsp1, 172*39a53928SRohit Agarwal [SLAVE_CLK_CTL] = &qhs_clk_ctl, 173*39a53928SRohit Agarwal [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 174*39a53928SRohit Agarwal [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 175*39a53928SRohit Agarwal [SLAVE_ECC_CFG] = &qhs_ecc_cfg, 176*39a53928SRohit Agarwal [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 177*39a53928SRohit Agarwal [SLAVE_IPA_CFG] = &qhs_ipa, 178*39a53928SRohit Agarwal [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 179*39a53928SRohit Agarwal [SLAVE_PCIE_PARF] = &qhs_pcie_parf, 180*39a53928SRohit Agarwal [SLAVE_PDM] = &qhs_pdm, 181*39a53928SRohit Agarwal [SLAVE_PRNG] = &qhs_prng, 182*39a53928SRohit Agarwal [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 183*39a53928SRohit Agarwal [SLAVE_QPIC] = &qhs_qpic, 184*39a53928SRohit Agarwal [SLAVE_SDCC_1] = &qhs_sdc1, 185*39a53928SRohit Agarwal [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 186*39a53928SRohit Agarwal [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, 187*39a53928SRohit Agarwal [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, 188*39a53928SRohit Agarwal [SLAVE_TCSR] = &qhs_tcsr, 189*39a53928SRohit Agarwal [SLAVE_TLMM] = &qhs_tlmm, 190*39a53928SRohit Agarwal [SLAVE_USB3] = &qhs_usb3, 191*39a53928SRohit Agarwal [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, 192*39a53928SRohit Agarwal [SLAVE_ANOC_SNOC] = &qns_aggre_noc, 193*39a53928SRohit Agarwal [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, 194*39a53928SRohit Agarwal [SLAVE_IMEM] = &qxs_imem, 195*39a53928SRohit Agarwal [SLAVE_SERVICE_SNOC] = &srvc_snoc, 196*39a53928SRohit Agarwal [SLAVE_PCIE_0] = &xs_pcie, 197*39a53928SRohit Agarwal [SLAVE_QDSS_STM] = &xs_qdss_stm, 198*39a53928SRohit Agarwal [SLAVE_TCU] = &xs_sys_tcu_cfg, 199*39a53928SRohit Agarwal }; 200*39a53928SRohit Agarwal 201*39a53928SRohit Agarwal static const struct qcom_icc_desc sdx65_system_noc = { 202*39a53928SRohit Agarwal .nodes = system_noc_nodes, 203*39a53928SRohit Agarwal .num_nodes = ARRAY_SIZE(system_noc_nodes), 204*39a53928SRohit Agarwal .bcms = system_noc_bcms, 205*39a53928SRohit Agarwal .num_bcms = ARRAY_SIZE(system_noc_bcms), 206*39a53928SRohit Agarwal }; 207*39a53928SRohit Agarwal 208*39a53928SRohit Agarwal static const struct of_device_id qnoc_of_match[] = { 209*39a53928SRohit Agarwal { .compatible = "qcom,sdx65-mc-virt", 210*39a53928SRohit Agarwal .data = &sdx65_mc_virt}, 211*39a53928SRohit Agarwal { .compatible = "qcom,sdx65-mem-noc", 212*39a53928SRohit Agarwal .data = &sdx65_mem_noc}, 213*39a53928SRohit Agarwal { .compatible = "qcom,sdx65-system-noc", 214*39a53928SRohit Agarwal .data = &sdx65_system_noc}, 215*39a53928SRohit Agarwal { } 216*39a53928SRohit Agarwal }; 217*39a53928SRohit Agarwal MODULE_DEVICE_TABLE(of, qnoc_of_match); 218*39a53928SRohit Agarwal 219*39a53928SRohit Agarwal static struct platform_driver qnoc_driver = { 220*39a53928SRohit Agarwal .probe = qcom_icc_rpmh_probe, 221*39a53928SRohit Agarwal .remove = qcom_icc_rpmh_remove, 222*39a53928SRohit Agarwal .driver = { 223*39a53928SRohit Agarwal .name = "qnoc-sdx65", 224*39a53928SRohit Agarwal .of_match_table = qnoc_of_match, 225*39a53928SRohit Agarwal .sync_state = icc_sync_state, 226*39a53928SRohit Agarwal }, 227*39a53928SRohit Agarwal }; 228*39a53928SRohit Agarwal module_platform_driver(qnoc_driver); 229*39a53928SRohit Agarwal 230*39a53928SRohit Agarwal MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver"); 231*39a53928SRohit Agarwal MODULE_LICENSE("GPL v2"); 232