1*cbb382c5SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0 */ 2*cbb382c5SManivannan Sadhasivam /* 3*cbb382c5SManivannan Sadhasivam * Copyright (c) 2021, Linaro Ltd. 4*cbb382c5SManivannan Sadhasivam */ 5*cbb382c5SManivannan Sadhasivam 6*cbb382c5SManivannan Sadhasivam #ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H 7*cbb382c5SManivannan Sadhasivam #define __DRIVERS_INTERCONNECT_QCOM_SDX55_H 8*cbb382c5SManivannan Sadhasivam 9*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_IPA_CORE 0 10*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_LLCC 1 11*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_TCU_0 2 12*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SNOC_GC_MEM_NOC 3 13*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_AMPSS_M0 4 14*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_AUDIO 5 15*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_BLSP_1 6 16*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_QDSS_BAM 7 17*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_QPIC 8 18*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SNOC_CFG 9 19*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SPMI_FETCHER 10 20*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_ANOC_SNOC 11 21*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_IPA 12 22*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_MEM_NOC_SNOC 13 23*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14 24*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_CRYPTO_CORE_0 15 25*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_EMAC 16 26*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_IPA_PCIE 17 27*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_PCIE 18 28*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_QDSS_ETR 19 29*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SDCC_1 20 30*cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_USB3 21 31*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_IPA_CORE 22 32*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_EBI_CH0 23 33*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_LLCC 24 34*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_MEM_NOC_SNOC 25 35*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26 36*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_ANOC_SNOC 27 37*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SNOC_CFG 28 38*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_EMAC_CFG 29 39*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_USB3 30 40*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_TLMM 31 41*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SPMI_FETCHER 32 42*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_QDSS_CFG 33 43*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PDM 34 44*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SNOC_MEM_NOC_GC 35 45*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_TCSR 36 46*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CNOC_DDRSS 37 47*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SPMI_VGI_COEX 38 48*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_QPIC 39 49*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_OCIMEM 40 50*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_IPA_CFG 41 51*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_USB3_PHY_CFG 42 52*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_AOP 43 53*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_BLSP_1 44 54*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SDCC_1 45 55*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CNOC_MSS 46 56*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PCIE_PARF 47 57*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_ECC_CFG 48 58*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_AUDIO 49 59*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_AOSS 51 60*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PRNG 52 61*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CRYPTO_0_CFG 53 62*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_TCU 54 63*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CLK_CTL 55 64*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_IMEM_CFG 56 65*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SERVICE_SNOC 57 66*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PCIE_0 58 67*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_QDSS_STM 59 68*cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_APPSS 60 69*cbb382c5SManivannan Sadhasivam 70*cbb382c5SManivannan Sadhasivam #endif 71