1cbb382c5SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0 */ 2cbb382c5SManivannan Sadhasivam /* 3cbb382c5SManivannan Sadhasivam * Copyright (c) 2021, Linaro Ltd. 4cbb382c5SManivannan Sadhasivam */ 5cbb382c5SManivannan Sadhasivam 6cbb382c5SManivannan Sadhasivam #ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H 7cbb382c5SManivannan Sadhasivam #define __DRIVERS_INTERCONNECT_QCOM_SDX55_H 8cbb382c5SManivannan Sadhasivam 9*7d6d7bfdSDmitry Baryshkov /* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ 10cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_LLCC 1 11cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_TCU_0 2 12cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SNOC_GC_MEM_NOC 3 13cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_AMPSS_M0 4 14cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_AUDIO 5 15cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_BLSP_1 6 16cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_QDSS_BAM 7 17cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_QPIC 8 18cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SNOC_CFG 9 19cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SPMI_FETCHER 10 20cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_ANOC_SNOC 11 21cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_IPA 12 22cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_MEM_NOC_SNOC 13 23cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14 24cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_CRYPTO_CORE_0 15 25cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_EMAC 16 26cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_IPA_PCIE 17 27cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_PCIE 18 28cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_QDSS_ETR 19 29cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_SDCC_1 20 30cbb382c5SManivannan Sadhasivam #define SDX55_MASTER_USB3 21 31*7d6d7bfdSDmitry Baryshkov /* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ 32cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_EBI_CH0 23 33cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_LLCC 24 34cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_MEM_NOC_SNOC 25 35cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26 36cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_ANOC_SNOC 27 37cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SNOC_CFG 28 38cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_EMAC_CFG 29 39cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_USB3 30 40cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_TLMM 31 41cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SPMI_FETCHER 32 42cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_QDSS_CFG 33 43cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PDM 34 44cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SNOC_MEM_NOC_GC 35 45cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_TCSR 36 46cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CNOC_DDRSS 37 47cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SPMI_VGI_COEX 38 48cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_QPIC 39 49cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_OCIMEM 40 50cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_IPA_CFG 41 51cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_USB3_PHY_CFG 42 52cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_AOP 43 53cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_BLSP_1 44 54cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SDCC_1 45 55cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CNOC_MSS 46 56cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PCIE_PARF 47 57cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_ECC_CFG 48 58cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_AUDIO 49 59cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_AOSS 51 60cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PRNG 52 61cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CRYPTO_0_CFG 53 62cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_TCU 54 63cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_CLK_CTL 55 64cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_IMEM_CFG 56 65cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_SERVICE_SNOC 57 66cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_PCIE_0 58 67cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_QDSS_STM 59 68cbb382c5SManivannan Sadhasivam #define SDX55_SLAVE_APPSS 60 69cbb382c5SManivannan Sadhasivam 70cbb382c5SManivannan Sadhasivam #endif 71