1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver 4 * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7 #include <dt-bindings/interconnect/qcom,sdm660.h> 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 19 #include "icc-rpm.h" 20 #include "smd-rpm.h" 21 22 enum { 23 SDM660_MASTER_IPA = 1, 24 SDM660_MASTER_CNOC_A2NOC, 25 SDM660_MASTER_SDCC_1, 26 SDM660_MASTER_SDCC_2, 27 SDM660_MASTER_BLSP_1, 28 SDM660_MASTER_BLSP_2, 29 SDM660_MASTER_UFS, 30 SDM660_MASTER_USB_HS, 31 SDM660_MASTER_USB3, 32 SDM660_MASTER_CRYPTO_C0, 33 SDM660_MASTER_GNOC_BIMC, 34 SDM660_MASTER_OXILI, 35 SDM660_MASTER_MNOC_BIMC, 36 SDM660_MASTER_SNOC_BIMC, 37 SDM660_MASTER_PIMEM, 38 SDM660_MASTER_SNOC_CNOC, 39 SDM660_MASTER_QDSS_DAP, 40 SDM660_MASTER_APPS_PROC, 41 SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 42 SDM660_MASTER_CNOC_MNOC_CFG, 43 SDM660_MASTER_CPP, 44 SDM660_MASTER_JPEG, 45 SDM660_MASTER_MDP_P0, 46 SDM660_MASTER_MDP_P1, 47 SDM660_MASTER_VENUS, 48 SDM660_MASTER_VFE, 49 SDM660_MASTER_QDSS_ETR, 50 SDM660_MASTER_QDSS_BAM, 51 SDM660_MASTER_SNOC_CFG, 52 SDM660_MASTER_BIMC_SNOC, 53 SDM660_MASTER_A2NOC_SNOC, 54 SDM660_MASTER_GNOC_SNOC, 55 56 SDM660_SLAVE_A2NOC_SNOC, 57 SDM660_SLAVE_EBI, 58 SDM660_SLAVE_HMSS_L3, 59 SDM660_SLAVE_BIMC_SNOC, 60 SDM660_SLAVE_CNOC_A2NOC, 61 SDM660_SLAVE_MPM, 62 SDM660_SLAVE_PMIC_ARB, 63 SDM660_SLAVE_TLMM_NORTH, 64 SDM660_SLAVE_TCSR, 65 SDM660_SLAVE_PIMEM_CFG, 66 SDM660_SLAVE_IMEM_CFG, 67 SDM660_SLAVE_MESSAGE_RAM, 68 SDM660_SLAVE_GLM, 69 SDM660_SLAVE_BIMC_CFG, 70 SDM660_SLAVE_PRNG, 71 SDM660_SLAVE_SPDM, 72 SDM660_SLAVE_QDSS_CFG, 73 SDM660_SLAVE_CNOC_MNOC_CFG, 74 SDM660_SLAVE_SNOC_CFG, 75 SDM660_SLAVE_QM_CFG, 76 SDM660_SLAVE_CLK_CTL, 77 SDM660_SLAVE_MSS_CFG, 78 SDM660_SLAVE_TLMM_SOUTH, 79 SDM660_SLAVE_UFS_CFG, 80 SDM660_SLAVE_A2NOC_CFG, 81 SDM660_SLAVE_A2NOC_SMMU_CFG, 82 SDM660_SLAVE_GPUSS_CFG, 83 SDM660_SLAVE_AHB2PHY, 84 SDM660_SLAVE_BLSP_1, 85 SDM660_SLAVE_SDCC_1, 86 SDM660_SLAVE_SDCC_2, 87 SDM660_SLAVE_TLMM_CENTER, 88 SDM660_SLAVE_BLSP_2, 89 SDM660_SLAVE_PDM, 90 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 91 SDM660_SLAVE_USB_HS, 92 SDM660_SLAVE_USB3_0, 93 SDM660_SLAVE_SRVC_CNOC, 94 SDM660_SLAVE_GNOC_BIMC, 95 SDM660_SLAVE_GNOC_SNOC, 96 SDM660_SLAVE_CAMERA_CFG, 97 SDM660_SLAVE_CAMERA_THROTTLE_CFG, 98 SDM660_SLAVE_MISC_CFG, 99 SDM660_SLAVE_VENUS_THROTTLE_CFG, 100 SDM660_SLAVE_VENUS_CFG, 101 SDM660_SLAVE_MMSS_CLK_XPU_CFG, 102 SDM660_SLAVE_MMSS_CLK_CFG, 103 SDM660_SLAVE_MNOC_MPU_CFG, 104 SDM660_SLAVE_DISPLAY_CFG, 105 SDM660_SLAVE_CSI_PHY_CFG, 106 SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 107 SDM660_SLAVE_SMMU_CFG, 108 SDM660_SLAVE_MNOC_BIMC, 109 SDM660_SLAVE_SRVC_MNOC, 110 SDM660_SLAVE_HMSS, 111 SDM660_SLAVE_LPASS, 112 SDM660_SLAVE_WLAN, 113 SDM660_SLAVE_CDSP, 114 SDM660_SLAVE_IPA, 115 SDM660_SLAVE_SNOC_BIMC, 116 SDM660_SLAVE_SNOC_CNOC, 117 SDM660_SLAVE_IMEM, 118 SDM660_SLAVE_PIMEM, 119 SDM660_SLAVE_QDSS_STM, 120 SDM660_SLAVE_SRVC_SNOC, 121 122 SDM660_A2NOC, 123 SDM660_BIMC, 124 SDM660_CNOC, 125 SDM660_GNOC, 126 SDM660_MNOC, 127 SDM660_SNOC, 128 }; 129 130 static const char * const mm_intf_clocks[] = { 131 "iface", 132 }; 133 134 static const char * const a2noc_intf_clocks[] = { 135 "ipa", 136 "ufs_axi", 137 "aggre2_ufs_axi", 138 "aggre2_usb3_axi", 139 "cfg_noc_usb2_axi", 140 }; 141 142 static const u16 mas_ipa_links[] = { 143 SDM660_SLAVE_A2NOC_SNOC 144 }; 145 146 static struct qcom_icc_node mas_ipa = { 147 .name = "mas_ipa", 148 .id = SDM660_MASTER_IPA, 149 .buswidth = 8, 150 .mas_rpm_id = 59, 151 .slv_rpm_id = -1, 152 .qos.ap_owned = true, 153 .qos.qos_mode = NOC_QOS_MODE_FIXED, 154 .qos.areq_prio = 1, 155 .qos.prio_level = 1, 156 .qos.qos_port = 3, 157 .num_links = ARRAY_SIZE(mas_ipa_links), 158 .links = mas_ipa_links, 159 }; 160 161 static const u16 mas_cnoc_a2noc_links[] = { 162 SDM660_SLAVE_A2NOC_SNOC 163 }; 164 165 static struct qcom_icc_node mas_cnoc_a2noc = { 166 .name = "mas_cnoc_a2noc", 167 .id = SDM660_MASTER_CNOC_A2NOC, 168 .buswidth = 8, 169 .mas_rpm_id = 146, 170 .slv_rpm_id = -1, 171 .qos.ap_owned = true, 172 .qos.qos_mode = NOC_QOS_MODE_INVALID, 173 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links), 174 .links = mas_cnoc_a2noc_links, 175 }; 176 177 static const u16 mas_sdcc_1_links[] = { 178 SDM660_SLAVE_A2NOC_SNOC 179 }; 180 181 static struct qcom_icc_node mas_sdcc_1 = { 182 .name = "mas_sdcc_1", 183 .id = SDM660_MASTER_SDCC_1, 184 .buswidth = 8, 185 .mas_rpm_id = 33, 186 .slv_rpm_id = -1, 187 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 188 .links = mas_sdcc_1_links, 189 }; 190 191 static const u16 mas_sdcc_2_links[] = { 192 SDM660_SLAVE_A2NOC_SNOC 193 }; 194 195 static struct qcom_icc_node mas_sdcc_2 = { 196 .name = "mas_sdcc_2", 197 .id = SDM660_MASTER_SDCC_2, 198 .buswidth = 8, 199 .mas_rpm_id = 35, 200 .slv_rpm_id = -1, 201 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 202 .links = mas_sdcc_2_links, 203 }; 204 205 static const u16 mas_blsp_1_links[] = { 206 SDM660_SLAVE_A2NOC_SNOC 207 }; 208 209 static struct qcom_icc_node mas_blsp_1 = { 210 .name = "mas_blsp_1", 211 .id = SDM660_MASTER_BLSP_1, 212 .buswidth = 4, 213 .mas_rpm_id = 41, 214 .slv_rpm_id = -1, 215 .num_links = ARRAY_SIZE(mas_blsp_1_links), 216 .links = mas_blsp_1_links, 217 }; 218 219 static const u16 mas_blsp_2_links[] = { 220 SDM660_SLAVE_A2NOC_SNOC 221 }; 222 223 static struct qcom_icc_node mas_blsp_2 = { 224 .name = "mas_blsp_2", 225 .id = SDM660_MASTER_BLSP_2, 226 .buswidth = 4, 227 .mas_rpm_id = 39, 228 .slv_rpm_id = -1, 229 .num_links = ARRAY_SIZE(mas_blsp_2_links), 230 .links = mas_blsp_2_links, 231 }; 232 233 static const u16 mas_ufs_links[] = { 234 SDM660_SLAVE_A2NOC_SNOC 235 }; 236 237 static struct qcom_icc_node mas_ufs = { 238 .name = "mas_ufs", 239 .id = SDM660_MASTER_UFS, 240 .buswidth = 8, 241 .mas_rpm_id = 68, 242 .slv_rpm_id = -1, 243 .qos.ap_owned = true, 244 .qos.qos_mode = NOC_QOS_MODE_FIXED, 245 .qos.areq_prio = 1, 246 .qos.prio_level = 1, 247 .qos.qos_port = 4, 248 .num_links = ARRAY_SIZE(mas_ufs_links), 249 .links = mas_ufs_links, 250 }; 251 252 static const u16 mas_usb_hs_links[] = { 253 SDM660_SLAVE_A2NOC_SNOC 254 }; 255 256 static struct qcom_icc_node mas_usb_hs = { 257 .name = "mas_usb_hs", 258 .id = SDM660_MASTER_USB_HS, 259 .buswidth = 8, 260 .mas_rpm_id = 42, 261 .slv_rpm_id = -1, 262 .qos.ap_owned = true, 263 .qos.qos_mode = NOC_QOS_MODE_FIXED, 264 .qos.areq_prio = 1, 265 .qos.prio_level = 1, 266 .qos.qos_port = 1, 267 .num_links = ARRAY_SIZE(mas_usb_hs_links), 268 .links = mas_usb_hs_links, 269 }; 270 271 static const u16 mas_usb3_links[] = { 272 SDM660_SLAVE_A2NOC_SNOC 273 }; 274 275 static struct qcom_icc_node mas_usb3 = { 276 .name = "mas_usb3", 277 .id = SDM660_MASTER_USB3, 278 .buswidth = 8, 279 .mas_rpm_id = 32, 280 .slv_rpm_id = -1, 281 .qos.ap_owned = true, 282 .qos.qos_mode = NOC_QOS_MODE_FIXED, 283 .qos.areq_prio = 1, 284 .qos.prio_level = 1, 285 .qos.qos_port = 2, 286 .num_links = ARRAY_SIZE(mas_usb3_links), 287 .links = mas_usb3_links, 288 }; 289 290 static const u16 mas_crypto_links[] = { 291 SDM660_SLAVE_A2NOC_SNOC 292 }; 293 294 static struct qcom_icc_node mas_crypto = { 295 .name = "mas_crypto", 296 .id = SDM660_MASTER_CRYPTO_C0, 297 .buswidth = 8, 298 .mas_rpm_id = 23, 299 .slv_rpm_id = -1, 300 .qos.ap_owned = true, 301 .qos.qos_mode = NOC_QOS_MODE_FIXED, 302 .qos.areq_prio = 1, 303 .qos.prio_level = 1, 304 .qos.qos_port = 11, 305 .num_links = ARRAY_SIZE(mas_crypto_links), 306 .links = mas_crypto_links, 307 }; 308 309 static const u16 mas_gnoc_bimc_links[] = { 310 SDM660_SLAVE_EBI 311 }; 312 313 static struct qcom_icc_node mas_gnoc_bimc = { 314 .name = "mas_gnoc_bimc", 315 .id = SDM660_MASTER_GNOC_BIMC, 316 .buswidth = 4, 317 .mas_rpm_id = 144, 318 .slv_rpm_id = -1, 319 .qos.ap_owned = true, 320 .qos.qos_mode = NOC_QOS_MODE_FIXED, 321 .qos.areq_prio = 0, 322 .qos.prio_level = 0, 323 .qos.qos_port = 0, 324 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links), 325 .links = mas_gnoc_bimc_links, 326 }; 327 328 static const u16 mas_oxili_links[] = { 329 SDM660_SLAVE_HMSS_L3, 330 SDM660_SLAVE_EBI, 331 SDM660_SLAVE_BIMC_SNOC 332 }; 333 334 static struct qcom_icc_node mas_oxili = { 335 .name = "mas_oxili", 336 .id = SDM660_MASTER_OXILI, 337 .buswidth = 4, 338 .mas_rpm_id = 6, 339 .slv_rpm_id = -1, 340 .qos.ap_owned = true, 341 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 342 .qos.areq_prio = 0, 343 .qos.prio_level = 0, 344 .qos.qos_port = 1, 345 .num_links = ARRAY_SIZE(mas_oxili_links), 346 .links = mas_oxili_links, 347 }; 348 349 static const u16 mas_mnoc_bimc_links[] = { 350 SDM660_SLAVE_HMSS_L3, 351 SDM660_SLAVE_EBI, 352 SDM660_SLAVE_BIMC_SNOC 353 }; 354 355 static struct qcom_icc_node mas_mnoc_bimc = { 356 .name = "mas_mnoc_bimc", 357 .id = SDM660_MASTER_MNOC_BIMC, 358 .buswidth = 4, 359 .mas_rpm_id = 2, 360 .slv_rpm_id = -1, 361 .qos.ap_owned = true, 362 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 363 .qos.areq_prio = 0, 364 .qos.prio_level = 0, 365 .qos.qos_port = 2, 366 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links), 367 .links = mas_mnoc_bimc_links, 368 }; 369 370 static const u16 mas_snoc_bimc_links[] = { 371 SDM660_SLAVE_HMSS_L3, 372 SDM660_SLAVE_EBI 373 }; 374 375 static struct qcom_icc_node mas_snoc_bimc = { 376 .name = "mas_snoc_bimc", 377 .id = SDM660_MASTER_SNOC_BIMC, 378 .buswidth = 4, 379 .mas_rpm_id = 3, 380 .slv_rpm_id = -1, 381 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 382 .links = mas_snoc_bimc_links, 383 }; 384 385 static const u16 mas_pimem_links[] = { 386 SDM660_SLAVE_HMSS_L3, 387 SDM660_SLAVE_EBI 388 }; 389 390 static struct qcom_icc_node mas_pimem = { 391 .name = "mas_pimem", 392 .id = SDM660_MASTER_PIMEM, 393 .buswidth = 4, 394 .mas_rpm_id = 113, 395 .slv_rpm_id = -1, 396 .qos.ap_owned = true, 397 .qos.qos_mode = NOC_QOS_MODE_FIXED, 398 .qos.areq_prio = 1, 399 .qos.prio_level = 1, 400 .qos.qos_port = 4, 401 .num_links = ARRAY_SIZE(mas_pimem_links), 402 .links = mas_pimem_links, 403 }; 404 405 static const u16 mas_snoc_cnoc_links[] = { 406 SDM660_SLAVE_CLK_CTL, 407 SDM660_SLAVE_QDSS_CFG, 408 SDM660_SLAVE_QM_CFG, 409 SDM660_SLAVE_SRVC_CNOC, 410 SDM660_SLAVE_UFS_CFG, 411 SDM660_SLAVE_TCSR, 412 SDM660_SLAVE_A2NOC_SMMU_CFG, 413 SDM660_SLAVE_SNOC_CFG, 414 SDM660_SLAVE_TLMM_SOUTH, 415 SDM660_SLAVE_MPM, 416 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 417 SDM660_SLAVE_SDCC_2, 418 SDM660_SLAVE_SDCC_1, 419 SDM660_SLAVE_SPDM, 420 SDM660_SLAVE_PMIC_ARB, 421 SDM660_SLAVE_PRNG, 422 SDM660_SLAVE_MSS_CFG, 423 SDM660_SLAVE_GPUSS_CFG, 424 SDM660_SLAVE_IMEM_CFG, 425 SDM660_SLAVE_USB3_0, 426 SDM660_SLAVE_A2NOC_CFG, 427 SDM660_SLAVE_TLMM_NORTH, 428 SDM660_SLAVE_USB_HS, 429 SDM660_SLAVE_PDM, 430 SDM660_SLAVE_TLMM_CENTER, 431 SDM660_SLAVE_AHB2PHY, 432 SDM660_SLAVE_BLSP_2, 433 SDM660_SLAVE_BLSP_1, 434 SDM660_SLAVE_PIMEM_CFG, 435 SDM660_SLAVE_GLM, 436 SDM660_SLAVE_MESSAGE_RAM, 437 SDM660_SLAVE_BIMC_CFG, 438 SDM660_SLAVE_CNOC_MNOC_CFG 439 }; 440 441 static struct qcom_icc_node mas_snoc_cnoc = { 442 .name = "mas_snoc_cnoc", 443 .id = SDM660_MASTER_SNOC_CNOC, 444 .buswidth = 8, 445 .mas_rpm_id = 52, 446 .slv_rpm_id = -1, 447 .qos.ap_owned = true, 448 .qos.qos_mode = NOC_QOS_MODE_INVALID, 449 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 450 .links = mas_snoc_cnoc_links, 451 }; 452 453 static const u16 mas_qdss_dap_links[] = { 454 SDM660_SLAVE_CLK_CTL, 455 SDM660_SLAVE_QDSS_CFG, 456 SDM660_SLAVE_QM_CFG, 457 SDM660_SLAVE_SRVC_CNOC, 458 SDM660_SLAVE_UFS_CFG, 459 SDM660_SLAVE_TCSR, 460 SDM660_SLAVE_A2NOC_SMMU_CFG, 461 SDM660_SLAVE_SNOC_CFG, 462 SDM660_SLAVE_TLMM_SOUTH, 463 SDM660_SLAVE_MPM, 464 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 465 SDM660_SLAVE_SDCC_2, 466 SDM660_SLAVE_SDCC_1, 467 SDM660_SLAVE_SPDM, 468 SDM660_SLAVE_PMIC_ARB, 469 SDM660_SLAVE_PRNG, 470 SDM660_SLAVE_MSS_CFG, 471 SDM660_SLAVE_GPUSS_CFG, 472 SDM660_SLAVE_IMEM_CFG, 473 SDM660_SLAVE_USB3_0, 474 SDM660_SLAVE_A2NOC_CFG, 475 SDM660_SLAVE_TLMM_NORTH, 476 SDM660_SLAVE_USB_HS, 477 SDM660_SLAVE_PDM, 478 SDM660_SLAVE_TLMM_CENTER, 479 SDM660_SLAVE_AHB2PHY, 480 SDM660_SLAVE_BLSP_2, 481 SDM660_SLAVE_BLSP_1, 482 SDM660_SLAVE_PIMEM_CFG, 483 SDM660_SLAVE_GLM, 484 SDM660_SLAVE_MESSAGE_RAM, 485 SDM660_SLAVE_CNOC_A2NOC, 486 SDM660_SLAVE_BIMC_CFG, 487 SDM660_SLAVE_CNOC_MNOC_CFG 488 }; 489 490 static struct qcom_icc_node mas_qdss_dap = { 491 .name = "mas_qdss_dap", 492 .id = SDM660_MASTER_QDSS_DAP, 493 .buswidth = 8, 494 .mas_rpm_id = 49, 495 .slv_rpm_id = -1, 496 .qos.ap_owned = true, 497 .qos.qos_mode = NOC_QOS_MODE_INVALID, 498 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 499 .links = mas_qdss_dap_links, 500 }; 501 502 static const u16 mas_apss_proc_links[] = { 503 SDM660_SLAVE_GNOC_SNOC, 504 SDM660_SLAVE_GNOC_BIMC 505 }; 506 507 static struct qcom_icc_node mas_apss_proc = { 508 .name = "mas_apss_proc", 509 .id = SDM660_MASTER_APPS_PROC, 510 .buswidth = 16, 511 .mas_rpm_id = 0, 512 .slv_rpm_id = -1, 513 .qos.ap_owned = true, 514 .qos.qos_mode = NOC_QOS_MODE_INVALID, 515 .num_links = ARRAY_SIZE(mas_apss_proc_links), 516 .links = mas_apss_proc_links, 517 }; 518 519 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { 520 SDM660_SLAVE_VENUS_THROTTLE_CFG, 521 SDM660_SLAVE_VENUS_CFG, 522 SDM660_SLAVE_CAMERA_THROTTLE_CFG, 523 SDM660_SLAVE_SMMU_CFG, 524 SDM660_SLAVE_CAMERA_CFG, 525 SDM660_SLAVE_CSI_PHY_CFG, 526 SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 527 SDM660_SLAVE_DISPLAY_CFG, 528 SDM660_SLAVE_MMSS_CLK_CFG, 529 SDM660_SLAVE_MNOC_MPU_CFG, 530 SDM660_SLAVE_MISC_CFG, 531 SDM660_SLAVE_MMSS_CLK_XPU_CFG 532 }; 533 534 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { 535 .name = "mas_cnoc_mnoc_mmss_cfg", 536 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 537 .buswidth = 8, 538 .mas_rpm_id = 4, 539 .slv_rpm_id = -1, 540 .qos.ap_owned = true, 541 .qos.qos_mode = NOC_QOS_MODE_INVALID, 542 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), 543 .links = mas_cnoc_mnoc_mmss_cfg_links, 544 }; 545 546 static const u16 mas_cnoc_mnoc_cfg_links[] = { 547 SDM660_SLAVE_SRVC_MNOC 548 }; 549 550 static struct qcom_icc_node mas_cnoc_mnoc_cfg = { 551 .name = "mas_cnoc_mnoc_cfg", 552 .id = SDM660_MASTER_CNOC_MNOC_CFG, 553 .buswidth = 4, 554 .mas_rpm_id = 5, 555 .slv_rpm_id = -1, 556 .qos.ap_owned = true, 557 .qos.qos_mode = NOC_QOS_MODE_INVALID, 558 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), 559 .links = mas_cnoc_mnoc_cfg_links, 560 }; 561 562 static const u16 mas_cpp_links[] = { 563 SDM660_SLAVE_MNOC_BIMC 564 }; 565 566 static struct qcom_icc_node mas_cpp = { 567 .name = "mas_cpp", 568 .id = SDM660_MASTER_CPP, 569 .buswidth = 16, 570 .mas_rpm_id = 115, 571 .slv_rpm_id = -1, 572 .qos.ap_owned = true, 573 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 574 .qos.areq_prio = 0, 575 .qos.prio_level = 0, 576 .qos.qos_port = 4, 577 .num_links = ARRAY_SIZE(mas_cpp_links), 578 .links = mas_cpp_links, 579 }; 580 581 static const u16 mas_jpeg_links[] = { 582 SDM660_SLAVE_MNOC_BIMC 583 }; 584 585 static struct qcom_icc_node mas_jpeg = { 586 .name = "mas_jpeg", 587 .id = SDM660_MASTER_JPEG, 588 .buswidth = 16, 589 .mas_rpm_id = 7, 590 .slv_rpm_id = -1, 591 .qos.ap_owned = true, 592 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 593 .qos.areq_prio = 0, 594 .qos.prio_level = 0, 595 .qos.qos_port = 6, 596 .num_links = ARRAY_SIZE(mas_jpeg_links), 597 .links = mas_jpeg_links, 598 }; 599 600 static const u16 mas_mdp_p0_links[] = { 601 SDM660_SLAVE_MNOC_BIMC 602 }; 603 604 static struct qcom_icc_node mas_mdp_p0 = { 605 .name = "mas_mdp_p0", 606 .id = SDM660_MASTER_MDP_P0, 607 .buswidth = 16, 608 .mas_rpm_id = 8, 609 .slv_rpm_id = -1, 610 .qos.ap_owned = true, 611 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 612 .qos.areq_prio = 0, 613 .qos.prio_level = 0, 614 .qos.qos_port = 0, 615 .num_links = ARRAY_SIZE(mas_mdp_p0_links), 616 .links = mas_mdp_p0_links, 617 }; 618 619 static const u16 mas_mdp_p1_links[] = { 620 SDM660_SLAVE_MNOC_BIMC 621 }; 622 623 static struct qcom_icc_node mas_mdp_p1 = { 624 .name = "mas_mdp_p1", 625 .id = SDM660_MASTER_MDP_P1, 626 .buswidth = 16, 627 .mas_rpm_id = 61, 628 .slv_rpm_id = -1, 629 .qos.ap_owned = true, 630 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 631 .qos.areq_prio = 0, 632 .qos.prio_level = 0, 633 .qos.qos_port = 1, 634 .num_links = ARRAY_SIZE(mas_mdp_p1_links), 635 .links = mas_mdp_p1_links, 636 }; 637 638 static const u16 mas_venus_links[] = { 639 SDM660_SLAVE_MNOC_BIMC 640 }; 641 642 static struct qcom_icc_node mas_venus = { 643 .name = "mas_venus", 644 .id = SDM660_MASTER_VENUS, 645 .buswidth = 16, 646 .mas_rpm_id = 9, 647 .slv_rpm_id = -1, 648 .qos.ap_owned = true, 649 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 650 .qos.areq_prio = 0, 651 .qos.prio_level = 0, 652 .qos.qos_port = 1, 653 .num_links = ARRAY_SIZE(mas_venus_links), 654 .links = mas_venus_links, 655 }; 656 657 static const u16 mas_vfe_links[] = { 658 SDM660_SLAVE_MNOC_BIMC 659 }; 660 661 static struct qcom_icc_node mas_vfe = { 662 .name = "mas_vfe", 663 .id = SDM660_MASTER_VFE, 664 .buswidth = 16, 665 .mas_rpm_id = 11, 666 .slv_rpm_id = -1, 667 .qos.ap_owned = true, 668 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 669 .qos.areq_prio = 0, 670 .qos.prio_level = 0, 671 .qos.qos_port = 5, 672 .num_links = ARRAY_SIZE(mas_vfe_links), 673 .links = mas_vfe_links, 674 }; 675 676 static const u16 mas_qdss_etr_links[] = { 677 SDM660_SLAVE_PIMEM, 678 SDM660_SLAVE_IMEM, 679 SDM660_SLAVE_SNOC_CNOC, 680 SDM660_SLAVE_SNOC_BIMC 681 }; 682 683 static struct qcom_icc_node mas_qdss_etr = { 684 .name = "mas_qdss_etr", 685 .id = SDM660_MASTER_QDSS_ETR, 686 .buswidth = 8, 687 .mas_rpm_id = 31, 688 .slv_rpm_id = -1, 689 .qos.ap_owned = true, 690 .qos.qos_mode = NOC_QOS_MODE_FIXED, 691 .qos.areq_prio = 1, 692 .qos.prio_level = 1, 693 .qos.qos_port = 1, 694 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 695 .links = mas_qdss_etr_links, 696 }; 697 698 static const u16 mas_qdss_bam_links[] = { 699 SDM660_SLAVE_PIMEM, 700 SDM660_SLAVE_IMEM, 701 SDM660_SLAVE_SNOC_CNOC, 702 SDM660_SLAVE_SNOC_BIMC 703 }; 704 705 static struct qcom_icc_node mas_qdss_bam = { 706 .name = "mas_qdss_bam", 707 .id = SDM660_MASTER_QDSS_BAM, 708 .buswidth = 4, 709 .mas_rpm_id = 19, 710 .slv_rpm_id = -1, 711 .qos.ap_owned = true, 712 .qos.qos_mode = NOC_QOS_MODE_FIXED, 713 .qos.areq_prio = 1, 714 .qos.prio_level = 1, 715 .qos.qos_port = 0, 716 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 717 .links = mas_qdss_bam_links, 718 }; 719 720 static const u16 mas_snoc_cfg_links[] = { 721 SDM660_SLAVE_SRVC_SNOC 722 }; 723 724 static struct qcom_icc_node mas_snoc_cfg = { 725 .name = "mas_snoc_cfg", 726 .id = SDM660_MASTER_SNOC_CFG, 727 .buswidth = 4, 728 .mas_rpm_id = 20, 729 .slv_rpm_id = -1, 730 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 731 .links = mas_snoc_cfg_links, 732 }; 733 734 static const u16 mas_bimc_snoc_links[] = { 735 SDM660_SLAVE_PIMEM, 736 SDM660_SLAVE_IPA, 737 SDM660_SLAVE_QDSS_STM, 738 SDM660_SLAVE_LPASS, 739 SDM660_SLAVE_HMSS, 740 SDM660_SLAVE_CDSP, 741 SDM660_SLAVE_SNOC_CNOC, 742 SDM660_SLAVE_WLAN, 743 SDM660_SLAVE_IMEM 744 }; 745 746 static struct qcom_icc_node mas_bimc_snoc = { 747 .name = "mas_bimc_snoc", 748 .id = SDM660_MASTER_BIMC_SNOC, 749 .buswidth = 8, 750 .mas_rpm_id = 21, 751 .slv_rpm_id = -1, 752 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 753 .links = mas_bimc_snoc_links, 754 }; 755 756 static const u16 mas_gnoc_snoc_links[] = { 757 SDM660_SLAVE_PIMEM, 758 SDM660_SLAVE_IPA, 759 SDM660_SLAVE_QDSS_STM, 760 SDM660_SLAVE_LPASS, 761 SDM660_SLAVE_HMSS, 762 SDM660_SLAVE_CDSP, 763 SDM660_SLAVE_SNOC_CNOC, 764 SDM660_SLAVE_WLAN, 765 SDM660_SLAVE_IMEM 766 }; 767 768 static struct qcom_icc_node mas_gnoc_snoc = { 769 .name = "mas_gnoc_snoc", 770 .id = SDM660_MASTER_GNOC_SNOC, 771 .buswidth = 8, 772 .mas_rpm_id = 150, 773 .slv_rpm_id = -1, 774 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links), 775 .links = mas_gnoc_snoc_links, 776 }; 777 778 static const u16 mas_a2noc_snoc_links[] = { 779 SDM660_SLAVE_PIMEM, 780 SDM660_SLAVE_IPA, 781 SDM660_SLAVE_QDSS_STM, 782 SDM660_SLAVE_LPASS, 783 SDM660_SLAVE_HMSS, 784 SDM660_SLAVE_SNOC_BIMC, 785 SDM660_SLAVE_CDSP, 786 SDM660_SLAVE_SNOC_CNOC, 787 SDM660_SLAVE_WLAN, 788 SDM660_SLAVE_IMEM 789 }; 790 791 static struct qcom_icc_node mas_a2noc_snoc = { 792 .name = "mas_a2noc_snoc", 793 .id = SDM660_MASTER_A2NOC_SNOC, 794 .buswidth = 16, 795 .mas_rpm_id = 112, 796 .slv_rpm_id = -1, 797 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), 798 .links = mas_a2noc_snoc_links, 799 }; 800 801 static const u16 slv_a2noc_snoc_links[] = { 802 SDM660_MASTER_A2NOC_SNOC 803 }; 804 805 static struct qcom_icc_node slv_a2noc_snoc = { 806 .name = "slv_a2noc_snoc", 807 .id = SDM660_SLAVE_A2NOC_SNOC, 808 .buswidth = 16, 809 .mas_rpm_id = -1, 810 .slv_rpm_id = 143, 811 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), 812 .links = slv_a2noc_snoc_links, 813 }; 814 815 static struct qcom_icc_node slv_ebi = { 816 .name = "slv_ebi", 817 .id = SDM660_SLAVE_EBI, 818 .buswidth = 4, 819 .mas_rpm_id = -1, 820 .slv_rpm_id = 0, 821 }; 822 823 static struct qcom_icc_node slv_hmss_l3 = { 824 .name = "slv_hmss_l3", 825 .id = SDM660_SLAVE_HMSS_L3, 826 .buswidth = 4, 827 .mas_rpm_id = -1, 828 .slv_rpm_id = 160, 829 }; 830 831 static const u16 slv_bimc_snoc_links[] = { 832 SDM660_MASTER_BIMC_SNOC 833 }; 834 835 static struct qcom_icc_node slv_bimc_snoc = { 836 .name = "slv_bimc_snoc", 837 .id = SDM660_SLAVE_BIMC_SNOC, 838 .buswidth = 4, 839 .mas_rpm_id = -1, 840 .slv_rpm_id = 2, 841 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 842 .links = slv_bimc_snoc_links, 843 }; 844 845 static const u16 slv_cnoc_a2noc_links[] = { 846 SDM660_MASTER_CNOC_A2NOC 847 }; 848 849 static struct qcom_icc_node slv_cnoc_a2noc = { 850 .name = "slv_cnoc_a2noc", 851 .id = SDM660_SLAVE_CNOC_A2NOC, 852 .buswidth = 8, 853 .mas_rpm_id = -1, 854 .slv_rpm_id = 208, 855 .qos.ap_owned = true, 856 .qos.qos_mode = NOC_QOS_MODE_INVALID, 857 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links), 858 .links = slv_cnoc_a2noc_links, 859 }; 860 861 static struct qcom_icc_node slv_mpm = { 862 .name = "slv_mpm", 863 .id = SDM660_SLAVE_MPM, 864 .buswidth = 4, 865 .mas_rpm_id = -1, 866 .slv_rpm_id = 62, 867 .qos.ap_owned = true, 868 .qos.qos_mode = NOC_QOS_MODE_INVALID, 869 }; 870 871 static struct qcom_icc_node slv_pmic_arb = { 872 .name = "slv_pmic_arb", 873 .id = SDM660_SLAVE_PMIC_ARB, 874 .buswidth = 4, 875 .mas_rpm_id = -1, 876 .slv_rpm_id = 59, 877 .qos.ap_owned = true, 878 .qos.qos_mode = NOC_QOS_MODE_INVALID, 879 }; 880 881 static struct qcom_icc_node slv_tlmm_north = { 882 .name = "slv_tlmm_north", 883 .id = SDM660_SLAVE_TLMM_NORTH, 884 .buswidth = 8, 885 .mas_rpm_id = -1, 886 .slv_rpm_id = 214, 887 .qos.ap_owned = true, 888 .qos.qos_mode = NOC_QOS_MODE_INVALID, 889 }; 890 891 static struct qcom_icc_node slv_tcsr = { 892 .name = "slv_tcsr", 893 .id = SDM660_SLAVE_TCSR, 894 .buswidth = 4, 895 .mas_rpm_id = -1, 896 .slv_rpm_id = 50, 897 .qos.ap_owned = true, 898 .qos.qos_mode = NOC_QOS_MODE_INVALID, 899 }; 900 901 static struct qcom_icc_node slv_pimem_cfg = { 902 .name = "slv_pimem_cfg", 903 .id = SDM660_SLAVE_PIMEM_CFG, 904 .buswidth = 4, 905 .mas_rpm_id = -1, 906 .slv_rpm_id = 167, 907 .qos.ap_owned = true, 908 .qos.qos_mode = NOC_QOS_MODE_INVALID, 909 }; 910 911 static struct qcom_icc_node slv_imem_cfg = { 912 .name = "slv_imem_cfg", 913 .id = SDM660_SLAVE_IMEM_CFG, 914 .buswidth = 4, 915 .mas_rpm_id = -1, 916 .slv_rpm_id = 54, 917 .qos.ap_owned = true, 918 .qos.qos_mode = NOC_QOS_MODE_INVALID, 919 }; 920 921 static struct qcom_icc_node slv_message_ram = { 922 .name = "slv_message_ram", 923 .id = SDM660_SLAVE_MESSAGE_RAM, 924 .buswidth = 4, 925 .mas_rpm_id = -1, 926 .slv_rpm_id = 55, 927 .qos.ap_owned = true, 928 .qos.qos_mode = NOC_QOS_MODE_INVALID, 929 }; 930 931 static struct qcom_icc_node slv_glm = { 932 .name = "slv_glm", 933 .id = SDM660_SLAVE_GLM, 934 .buswidth = 4, 935 .mas_rpm_id = -1, 936 .slv_rpm_id = 209, 937 .qos.ap_owned = true, 938 .qos.qos_mode = NOC_QOS_MODE_INVALID, 939 }; 940 941 static struct qcom_icc_node slv_bimc_cfg = { 942 .name = "slv_bimc_cfg", 943 .id = SDM660_SLAVE_BIMC_CFG, 944 .buswidth = 4, 945 .mas_rpm_id = -1, 946 .slv_rpm_id = 56, 947 .qos.ap_owned = true, 948 .qos.qos_mode = NOC_QOS_MODE_INVALID, 949 }; 950 951 static struct qcom_icc_node slv_prng = { 952 .name = "slv_prng", 953 .id = SDM660_SLAVE_PRNG, 954 .buswidth = 4, 955 .mas_rpm_id = -1, 956 .slv_rpm_id = 44, 957 .qos.ap_owned = true, 958 .qos.qos_mode = NOC_QOS_MODE_INVALID, 959 }; 960 961 static struct qcom_icc_node slv_spdm = { 962 .name = "slv_spdm", 963 .id = SDM660_SLAVE_SPDM, 964 .buswidth = 4, 965 .mas_rpm_id = -1, 966 .slv_rpm_id = 60, 967 .qos.ap_owned = true, 968 .qos.qos_mode = NOC_QOS_MODE_INVALID, 969 }; 970 971 static struct qcom_icc_node slv_qdss_cfg = { 972 .name = "slv_qdss_cfg", 973 .id = SDM660_SLAVE_QDSS_CFG, 974 .buswidth = 4, 975 .mas_rpm_id = -1, 976 .slv_rpm_id = 63, 977 .qos.ap_owned = true, 978 .qos.qos_mode = NOC_QOS_MODE_INVALID, 979 }; 980 981 static const u16 slv_cnoc_mnoc_cfg_links[] = { 982 SDM660_MASTER_CNOC_MNOC_CFG 983 }; 984 985 static struct qcom_icc_node slv_cnoc_mnoc_cfg = { 986 .name = "slv_cnoc_mnoc_cfg", 987 .id = SDM660_SLAVE_CNOC_MNOC_CFG, 988 .buswidth = 4, 989 .mas_rpm_id = -1, 990 .slv_rpm_id = 66, 991 .qos.ap_owned = true, 992 .qos.qos_mode = NOC_QOS_MODE_INVALID, 993 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), 994 .links = slv_cnoc_mnoc_cfg_links, 995 }; 996 997 static struct qcom_icc_node slv_snoc_cfg = { 998 .name = "slv_snoc_cfg", 999 .id = SDM660_SLAVE_SNOC_CFG, 1000 .buswidth = 4, 1001 .mas_rpm_id = -1, 1002 .slv_rpm_id = 70, 1003 .qos.ap_owned = true, 1004 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1005 }; 1006 1007 static struct qcom_icc_node slv_qm_cfg = { 1008 .name = "slv_qm_cfg", 1009 .id = SDM660_SLAVE_QM_CFG, 1010 .buswidth = 4, 1011 .mas_rpm_id = -1, 1012 .slv_rpm_id = 212, 1013 .qos.ap_owned = true, 1014 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1015 }; 1016 1017 static struct qcom_icc_node slv_clk_ctl = { 1018 .name = "slv_clk_ctl", 1019 .id = SDM660_SLAVE_CLK_CTL, 1020 .buswidth = 4, 1021 .mas_rpm_id = -1, 1022 .slv_rpm_id = 47, 1023 .qos.ap_owned = true, 1024 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1025 }; 1026 1027 static struct qcom_icc_node slv_mss_cfg = { 1028 .name = "slv_mss_cfg", 1029 .id = SDM660_SLAVE_MSS_CFG, 1030 .buswidth = 4, 1031 .mas_rpm_id = -1, 1032 .slv_rpm_id = 48, 1033 .qos.ap_owned = true, 1034 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1035 }; 1036 1037 static struct qcom_icc_node slv_tlmm_south = { 1038 .name = "slv_tlmm_south", 1039 .id = SDM660_SLAVE_TLMM_SOUTH, 1040 .buswidth = 4, 1041 .mas_rpm_id = -1, 1042 .slv_rpm_id = 217, 1043 .qos.ap_owned = true, 1044 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1045 }; 1046 1047 static struct qcom_icc_node slv_ufs_cfg = { 1048 .name = "slv_ufs_cfg", 1049 .id = SDM660_SLAVE_UFS_CFG, 1050 .buswidth = 4, 1051 .mas_rpm_id = -1, 1052 .slv_rpm_id = 92, 1053 .qos.ap_owned = true, 1054 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1055 }; 1056 1057 static struct qcom_icc_node slv_a2noc_cfg = { 1058 .name = "slv_a2noc_cfg", 1059 .id = SDM660_SLAVE_A2NOC_CFG, 1060 .buswidth = 4, 1061 .mas_rpm_id = -1, 1062 .slv_rpm_id = 150, 1063 .qos.ap_owned = true, 1064 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1065 }; 1066 1067 static struct qcom_icc_node slv_a2noc_smmu_cfg = { 1068 .name = "slv_a2noc_smmu_cfg", 1069 .id = SDM660_SLAVE_A2NOC_SMMU_CFG, 1070 .buswidth = 8, 1071 .mas_rpm_id = -1, 1072 .slv_rpm_id = 152, 1073 .qos.ap_owned = true, 1074 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1075 }; 1076 1077 static struct qcom_icc_node slv_gpuss_cfg = { 1078 .name = "slv_gpuss_cfg", 1079 .id = SDM660_SLAVE_GPUSS_CFG, 1080 .buswidth = 8, 1081 .mas_rpm_id = -1, 1082 .slv_rpm_id = 11, 1083 .qos.ap_owned = true, 1084 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1085 }; 1086 1087 static struct qcom_icc_node slv_ahb2phy = { 1088 .name = "slv_ahb2phy", 1089 .id = SDM660_SLAVE_AHB2PHY, 1090 .buswidth = 4, 1091 .mas_rpm_id = -1, 1092 .slv_rpm_id = 163, 1093 .qos.ap_owned = true, 1094 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1095 }; 1096 1097 static struct qcom_icc_node slv_blsp_1 = { 1098 .name = "slv_blsp_1", 1099 .id = SDM660_SLAVE_BLSP_1, 1100 .buswidth = 4, 1101 .mas_rpm_id = -1, 1102 .slv_rpm_id = 39, 1103 .qos.ap_owned = true, 1104 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1105 }; 1106 1107 static struct qcom_icc_node slv_sdcc_1 = { 1108 .name = "slv_sdcc_1", 1109 .id = SDM660_SLAVE_SDCC_1, 1110 .buswidth = 4, 1111 .mas_rpm_id = -1, 1112 .slv_rpm_id = 31, 1113 .qos.ap_owned = true, 1114 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1115 }; 1116 1117 static struct qcom_icc_node slv_sdcc_2 = { 1118 .name = "slv_sdcc_2", 1119 .id = SDM660_SLAVE_SDCC_2, 1120 .buswidth = 4, 1121 .mas_rpm_id = -1, 1122 .slv_rpm_id = 33, 1123 .qos.ap_owned = true, 1124 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1125 }; 1126 1127 static struct qcom_icc_node slv_tlmm_center = { 1128 .name = "slv_tlmm_center", 1129 .id = SDM660_SLAVE_TLMM_CENTER, 1130 .buswidth = 4, 1131 .mas_rpm_id = -1, 1132 .slv_rpm_id = 218, 1133 .qos.ap_owned = true, 1134 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1135 }; 1136 1137 static struct qcom_icc_node slv_blsp_2 = { 1138 .name = "slv_blsp_2", 1139 .id = SDM660_SLAVE_BLSP_2, 1140 .buswidth = 4, 1141 .mas_rpm_id = -1, 1142 .slv_rpm_id = 37, 1143 .qos.ap_owned = true, 1144 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1145 }; 1146 1147 static struct qcom_icc_node slv_pdm = { 1148 .name = "slv_pdm", 1149 .id = SDM660_SLAVE_PDM, 1150 .buswidth = 4, 1151 .mas_rpm_id = -1, 1152 .slv_rpm_id = 41, 1153 .qos.ap_owned = true, 1154 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1155 }; 1156 1157 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { 1158 SDM660_MASTER_CNOC_MNOC_MMSS_CFG 1159 }; 1160 1161 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { 1162 .name = "slv_cnoc_mnoc_mmss_cfg", 1163 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 1164 .buswidth = 8, 1165 .mas_rpm_id = -1, 1166 .slv_rpm_id = 58, 1167 .qos.ap_owned = true, 1168 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1169 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), 1170 .links = slv_cnoc_mnoc_mmss_cfg_links, 1171 }; 1172 1173 static struct qcom_icc_node slv_usb_hs = { 1174 .name = "slv_usb_hs", 1175 .id = SDM660_SLAVE_USB_HS, 1176 .buswidth = 4, 1177 .mas_rpm_id = -1, 1178 .slv_rpm_id = 40, 1179 .qos.ap_owned = true, 1180 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1181 }; 1182 1183 static struct qcom_icc_node slv_usb3_0 = { 1184 .name = "slv_usb3_0", 1185 .id = SDM660_SLAVE_USB3_0, 1186 .buswidth = 4, 1187 .mas_rpm_id = -1, 1188 .slv_rpm_id = 22, 1189 .qos.ap_owned = true, 1190 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1191 }; 1192 1193 static struct qcom_icc_node slv_srvc_cnoc = { 1194 .name = "slv_srvc_cnoc", 1195 .id = SDM660_SLAVE_SRVC_CNOC, 1196 .buswidth = 4, 1197 .mas_rpm_id = -1, 1198 .slv_rpm_id = 76, 1199 .qos.ap_owned = true, 1200 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1201 }; 1202 1203 static const u16 slv_gnoc_bimc_links[] = { 1204 SDM660_MASTER_GNOC_BIMC 1205 }; 1206 1207 static struct qcom_icc_node slv_gnoc_bimc = { 1208 .name = "slv_gnoc_bimc", 1209 .id = SDM660_SLAVE_GNOC_BIMC, 1210 .buswidth = 16, 1211 .mas_rpm_id = -1, 1212 .slv_rpm_id = 210, 1213 .qos.ap_owned = true, 1214 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1215 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links), 1216 .links = slv_gnoc_bimc_links, 1217 }; 1218 1219 static const u16 slv_gnoc_snoc_links[] = { 1220 SDM660_MASTER_GNOC_SNOC 1221 }; 1222 1223 static struct qcom_icc_node slv_gnoc_snoc = { 1224 .name = "slv_gnoc_snoc", 1225 .id = SDM660_SLAVE_GNOC_SNOC, 1226 .buswidth = 8, 1227 .mas_rpm_id = -1, 1228 .slv_rpm_id = 211, 1229 .qos.ap_owned = true, 1230 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1231 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links), 1232 .links = slv_gnoc_snoc_links, 1233 }; 1234 1235 static struct qcom_icc_node slv_camera_cfg = { 1236 .name = "slv_camera_cfg", 1237 .id = SDM660_SLAVE_CAMERA_CFG, 1238 .buswidth = 4, 1239 .mas_rpm_id = -1, 1240 .slv_rpm_id = 3, 1241 .qos.ap_owned = true, 1242 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1243 }; 1244 1245 static struct qcom_icc_node slv_camera_throttle_cfg = { 1246 .name = "slv_camera_throttle_cfg", 1247 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG, 1248 .buswidth = 4, 1249 .mas_rpm_id = -1, 1250 .slv_rpm_id = 154, 1251 .qos.ap_owned = true, 1252 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1253 }; 1254 1255 static struct qcom_icc_node slv_misc_cfg = { 1256 .name = "slv_misc_cfg", 1257 .id = SDM660_SLAVE_MISC_CFG, 1258 .buswidth = 4, 1259 .mas_rpm_id = -1, 1260 .slv_rpm_id = 8, 1261 .qos.ap_owned = true, 1262 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1263 }; 1264 1265 static struct qcom_icc_node slv_venus_throttle_cfg = { 1266 .name = "slv_venus_throttle_cfg", 1267 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG, 1268 .buswidth = 4, 1269 .mas_rpm_id = -1, 1270 .slv_rpm_id = 178, 1271 .qos.ap_owned = true, 1272 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1273 }; 1274 1275 static struct qcom_icc_node slv_venus_cfg = { 1276 .name = "slv_venus_cfg", 1277 .id = SDM660_SLAVE_VENUS_CFG, 1278 .buswidth = 4, 1279 .mas_rpm_id = -1, 1280 .slv_rpm_id = 10, 1281 .qos.ap_owned = true, 1282 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1283 }; 1284 1285 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = { 1286 .name = "slv_mmss_clk_xpu_cfg", 1287 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG, 1288 .buswidth = 4, 1289 .mas_rpm_id = -1, 1290 .slv_rpm_id = 13, 1291 .qos.ap_owned = true, 1292 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1293 }; 1294 1295 static struct qcom_icc_node slv_mmss_clk_cfg = { 1296 .name = "slv_mmss_clk_cfg", 1297 .id = SDM660_SLAVE_MMSS_CLK_CFG, 1298 .buswidth = 4, 1299 .mas_rpm_id = -1, 1300 .slv_rpm_id = 12, 1301 .qos.ap_owned = true, 1302 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1303 }; 1304 1305 static struct qcom_icc_node slv_mnoc_mpu_cfg = { 1306 .name = "slv_mnoc_mpu_cfg", 1307 .id = SDM660_SLAVE_MNOC_MPU_CFG, 1308 .buswidth = 4, 1309 .mas_rpm_id = -1, 1310 .slv_rpm_id = 14, 1311 .qos.ap_owned = true, 1312 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1313 }; 1314 1315 static struct qcom_icc_node slv_display_cfg = { 1316 .name = "slv_display_cfg", 1317 .id = SDM660_SLAVE_DISPLAY_CFG, 1318 .buswidth = 4, 1319 .mas_rpm_id = -1, 1320 .slv_rpm_id = 4, 1321 .qos.ap_owned = true, 1322 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1323 }; 1324 1325 static struct qcom_icc_node slv_csi_phy_cfg = { 1326 .name = "slv_csi_phy_cfg", 1327 .id = SDM660_SLAVE_CSI_PHY_CFG, 1328 .buswidth = 4, 1329 .mas_rpm_id = -1, 1330 .slv_rpm_id = 224, 1331 .qos.ap_owned = true, 1332 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1333 }; 1334 1335 static struct qcom_icc_node slv_display_throttle_cfg = { 1336 .name = "slv_display_throttle_cfg", 1337 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 1338 .buswidth = 4, 1339 .mas_rpm_id = -1, 1340 .slv_rpm_id = 156, 1341 .qos.ap_owned = true, 1342 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1343 }; 1344 1345 static struct qcom_icc_node slv_smmu_cfg = { 1346 .name = "slv_smmu_cfg", 1347 .id = SDM660_SLAVE_SMMU_CFG, 1348 .buswidth = 8, 1349 .mas_rpm_id = -1, 1350 .slv_rpm_id = 205, 1351 .qos.ap_owned = true, 1352 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1353 }; 1354 1355 static const u16 slv_mnoc_bimc_links[] = { 1356 SDM660_MASTER_MNOC_BIMC 1357 }; 1358 1359 static struct qcom_icc_node slv_mnoc_bimc = { 1360 .name = "slv_mnoc_bimc", 1361 .id = SDM660_SLAVE_MNOC_BIMC, 1362 .buswidth = 16, 1363 .mas_rpm_id = -1, 1364 .slv_rpm_id = 16, 1365 .qos.ap_owned = true, 1366 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1367 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), 1368 .links = slv_mnoc_bimc_links, 1369 }; 1370 1371 static struct qcom_icc_node slv_srvc_mnoc = { 1372 .name = "slv_srvc_mnoc", 1373 .id = SDM660_SLAVE_SRVC_MNOC, 1374 .buswidth = 8, 1375 .mas_rpm_id = -1, 1376 .slv_rpm_id = 17, 1377 .qos.ap_owned = true, 1378 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1379 }; 1380 1381 static struct qcom_icc_node slv_hmss = { 1382 .name = "slv_hmss", 1383 .id = SDM660_SLAVE_HMSS, 1384 .buswidth = 8, 1385 .mas_rpm_id = -1, 1386 .slv_rpm_id = 20, 1387 .qos.ap_owned = true, 1388 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1389 }; 1390 1391 static struct qcom_icc_node slv_lpass = { 1392 .name = "slv_lpass", 1393 .id = SDM660_SLAVE_LPASS, 1394 .buswidth = 4, 1395 .mas_rpm_id = -1, 1396 .slv_rpm_id = 21, 1397 .qos.ap_owned = true, 1398 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1399 }; 1400 1401 static struct qcom_icc_node slv_wlan = { 1402 .name = "slv_wlan", 1403 .id = SDM660_SLAVE_WLAN, 1404 .buswidth = 4, 1405 .mas_rpm_id = -1, 1406 .slv_rpm_id = 206, 1407 }; 1408 1409 static struct qcom_icc_node slv_cdsp = { 1410 .name = "slv_cdsp", 1411 .id = SDM660_SLAVE_CDSP, 1412 .buswidth = 4, 1413 .mas_rpm_id = -1, 1414 .slv_rpm_id = 221, 1415 .qos.ap_owned = true, 1416 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1417 }; 1418 1419 static struct qcom_icc_node slv_ipa = { 1420 .name = "slv_ipa", 1421 .id = SDM660_SLAVE_IPA, 1422 .buswidth = 4, 1423 .mas_rpm_id = -1, 1424 .slv_rpm_id = 183, 1425 .qos.ap_owned = true, 1426 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1427 }; 1428 1429 static const u16 slv_snoc_bimc_links[] = { 1430 SDM660_MASTER_SNOC_BIMC 1431 }; 1432 1433 static struct qcom_icc_node slv_snoc_bimc = { 1434 .name = "slv_snoc_bimc", 1435 .id = SDM660_SLAVE_SNOC_BIMC, 1436 .buswidth = 16, 1437 .mas_rpm_id = -1, 1438 .slv_rpm_id = 24, 1439 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1440 .links = slv_snoc_bimc_links, 1441 }; 1442 1443 static const u16 slv_snoc_cnoc_links[] = { 1444 SDM660_MASTER_SNOC_CNOC 1445 }; 1446 1447 static struct qcom_icc_node slv_snoc_cnoc = { 1448 .name = "slv_snoc_cnoc", 1449 .id = SDM660_SLAVE_SNOC_CNOC, 1450 .buswidth = 8, 1451 .mas_rpm_id = -1, 1452 .slv_rpm_id = 25, 1453 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1454 .links = slv_snoc_cnoc_links, 1455 }; 1456 1457 static struct qcom_icc_node slv_imem = { 1458 .name = "slv_imem", 1459 .id = SDM660_SLAVE_IMEM, 1460 .buswidth = 8, 1461 .mas_rpm_id = -1, 1462 .slv_rpm_id = 26, 1463 }; 1464 1465 static struct qcom_icc_node slv_pimem = { 1466 .name = "slv_pimem", 1467 .id = SDM660_SLAVE_PIMEM, 1468 .buswidth = 8, 1469 .mas_rpm_id = -1, 1470 .slv_rpm_id = 166, 1471 }; 1472 1473 static struct qcom_icc_node slv_qdss_stm = { 1474 .name = "slv_qdss_stm", 1475 .id = SDM660_SLAVE_QDSS_STM, 1476 .buswidth = 4, 1477 .mas_rpm_id = -1, 1478 .slv_rpm_id = 30, 1479 }; 1480 1481 static struct qcom_icc_node slv_srvc_snoc = { 1482 .name = "slv_srvc_snoc", 1483 .id = SDM660_SLAVE_SRVC_SNOC, 1484 .buswidth = 16, 1485 .mas_rpm_id = -1, 1486 .slv_rpm_id = 29, 1487 }; 1488 1489 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = { 1490 [MASTER_IPA] = &mas_ipa, 1491 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc, 1492 [MASTER_SDCC_1] = &mas_sdcc_1, 1493 [MASTER_SDCC_2] = &mas_sdcc_2, 1494 [MASTER_BLSP_1] = &mas_blsp_1, 1495 [MASTER_BLSP_2] = &mas_blsp_2, 1496 [MASTER_UFS] = &mas_ufs, 1497 [MASTER_USB_HS] = &mas_usb_hs, 1498 [MASTER_USB3] = &mas_usb3, 1499 [MASTER_CRYPTO_C0] = &mas_crypto, 1500 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, 1501 }; 1502 1503 static const struct regmap_config sdm660_a2noc_regmap_config = { 1504 .reg_bits = 32, 1505 .reg_stride = 4, 1506 .val_bits = 32, 1507 .max_register = 0x20000, 1508 .fast_io = true, 1509 }; 1510 1511 static const struct qcom_icc_desc sdm660_a2noc = { 1512 .type = QCOM_ICC_NOC, 1513 .nodes = sdm660_a2noc_nodes, 1514 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), 1515 .intf_clocks = a2noc_intf_clocks, 1516 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks), 1517 .regmap_cfg = &sdm660_a2noc_regmap_config, 1518 }; 1519 1520 static struct qcom_icc_node * const sdm660_bimc_nodes[] = { 1521 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc, 1522 [MASTER_OXILI] = &mas_oxili, 1523 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, 1524 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1525 [MASTER_PIMEM] = &mas_pimem, 1526 [SLAVE_EBI] = &slv_ebi, 1527 [SLAVE_HMSS_L3] = &slv_hmss_l3, 1528 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1529 }; 1530 1531 static const struct regmap_config sdm660_bimc_regmap_config = { 1532 .reg_bits = 32, 1533 .reg_stride = 4, 1534 .val_bits = 32, 1535 .max_register = 0x80000, 1536 .fast_io = true, 1537 }; 1538 1539 static const struct qcom_icc_desc sdm660_bimc = { 1540 .type = QCOM_ICC_BIMC, 1541 .nodes = sdm660_bimc_nodes, 1542 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), 1543 .regmap_cfg = &sdm660_bimc_regmap_config, 1544 }; 1545 1546 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { 1547 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1548 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1549 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc, 1550 [SLAVE_MPM] = &slv_mpm, 1551 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1552 [SLAVE_TLMM_NORTH] = &slv_tlmm_north, 1553 [SLAVE_TCSR] = &slv_tcsr, 1554 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1555 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1556 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1557 [SLAVE_GLM] = &slv_glm, 1558 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1559 [SLAVE_PRNG] = &slv_prng, 1560 [SLAVE_SPDM] = &slv_spdm, 1561 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1562 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, 1563 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1564 [SLAVE_QM_CFG] = &slv_qm_cfg, 1565 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1566 [SLAVE_MSS_CFG] = &slv_mss_cfg, 1567 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south, 1568 [SLAVE_UFS_CFG] = &slv_ufs_cfg, 1569 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, 1570 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, 1571 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg, 1572 [SLAVE_AHB2PHY] = &slv_ahb2phy, 1573 [SLAVE_BLSP_1] = &slv_blsp_1, 1574 [SLAVE_SDCC_1] = &slv_sdcc_1, 1575 [SLAVE_SDCC_2] = &slv_sdcc_2, 1576 [SLAVE_TLMM_CENTER] = &slv_tlmm_center, 1577 [SLAVE_BLSP_2] = &slv_blsp_2, 1578 [SLAVE_PDM] = &slv_pdm, 1579 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, 1580 [SLAVE_USB_HS] = &slv_usb_hs, 1581 [SLAVE_USB3_0] = &slv_usb3_0, 1582 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc, 1583 }; 1584 1585 static const struct regmap_config sdm660_cnoc_regmap_config = { 1586 .reg_bits = 32, 1587 .reg_stride = 4, 1588 .val_bits = 32, 1589 .max_register = 0x10000, 1590 .fast_io = true, 1591 }; 1592 1593 static const struct qcom_icc_desc sdm660_cnoc = { 1594 .type = QCOM_ICC_NOC, 1595 .nodes = sdm660_cnoc_nodes, 1596 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), 1597 .regmap_cfg = &sdm660_cnoc_regmap_config, 1598 }; 1599 1600 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = { 1601 [MASTER_APSS_PROC] = &mas_apss_proc, 1602 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc, 1603 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc, 1604 }; 1605 1606 static const struct regmap_config sdm660_gnoc_regmap_config = { 1607 .reg_bits = 32, 1608 .reg_stride = 4, 1609 .val_bits = 32, 1610 .max_register = 0xe000, 1611 .fast_io = true, 1612 }; 1613 1614 static const struct qcom_icc_desc sdm660_gnoc = { 1615 .type = QCOM_ICC_NOC, 1616 .nodes = sdm660_gnoc_nodes, 1617 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes), 1618 .regmap_cfg = &sdm660_gnoc_regmap_config, 1619 .no_clk_scaling = true, 1620 }; 1621 1622 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = { 1623 [MASTER_CPP] = &mas_cpp, 1624 [MASTER_JPEG] = &mas_jpeg, 1625 [MASTER_MDP_P0] = &mas_mdp_p0, 1626 [MASTER_MDP_P1] = &mas_mdp_p1, 1627 [MASTER_VENUS] = &mas_venus, 1628 [MASTER_VFE] = &mas_vfe, 1629 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, 1630 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, 1631 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1632 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, 1633 [SLAVE_MISC_CFG] = &slv_misc_cfg, 1634 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1635 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1636 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, 1637 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, 1638 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, 1639 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1640 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg, 1641 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1642 [SLAVE_SMMU_CFG] = &slv_smmu_cfg, 1643 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc, 1644 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, 1645 }; 1646 1647 static const struct regmap_config sdm660_mnoc_regmap_config = { 1648 .reg_bits = 32, 1649 .reg_stride = 4, 1650 .val_bits = 32, 1651 .max_register = 0x10000, 1652 .fast_io = true, 1653 }; 1654 1655 static const struct qcom_icc_desc sdm660_mnoc = { 1656 .type = QCOM_ICC_NOC, 1657 .nodes = sdm660_mnoc_nodes, 1658 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), 1659 .intf_clocks = mm_intf_clocks, 1660 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), 1661 .regmap_cfg = &sdm660_mnoc_regmap_config, 1662 }; 1663 1664 static struct qcom_icc_node * const sdm660_snoc_nodes[] = { 1665 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1666 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1667 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1668 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1669 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, 1670 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc, 1671 [SLAVE_HMSS] = &slv_hmss, 1672 [SLAVE_LPASS] = &slv_lpass, 1673 [SLAVE_WLAN] = &slv_wlan, 1674 [SLAVE_CDSP] = &slv_cdsp, 1675 [SLAVE_IPA] = &slv_ipa, 1676 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1677 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1678 [SLAVE_IMEM] = &slv_imem, 1679 [SLAVE_PIMEM] = &slv_pimem, 1680 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1681 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, 1682 }; 1683 1684 static const struct regmap_config sdm660_snoc_regmap_config = { 1685 .reg_bits = 32, 1686 .reg_stride = 4, 1687 .val_bits = 32, 1688 .max_register = 0x20000, 1689 .fast_io = true, 1690 }; 1691 1692 static const struct qcom_icc_desc sdm660_snoc = { 1693 .type = QCOM_ICC_NOC, 1694 .nodes = sdm660_snoc_nodes, 1695 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), 1696 .regmap_cfg = &sdm660_snoc_regmap_config, 1697 }; 1698 1699 static const struct of_device_id sdm660_noc_of_match[] = { 1700 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc }, 1701 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc }, 1702 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc }, 1703 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc }, 1704 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc }, 1705 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc }, 1706 { }, 1707 }; 1708 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match); 1709 1710 static struct platform_driver sdm660_noc_driver = { 1711 .probe = qnoc_probe, 1712 .remove = qnoc_remove, 1713 .driver = { 1714 .name = "qnoc-sdm660", 1715 .of_match_table = sdm660_noc_of_match, 1716 }, 1717 }; 1718 module_platform_driver(sdm660_noc_driver); 1719 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver"); 1720 MODULE_LICENSE("GPL v2"); 1721