1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Ltd. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 12 #include <dt-bindings/interconnect/qcom,sc8180x.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "sc8180x.h" 17 18 static struct qcom_icc_node mas_qhm_a1noc_cfg = { 19 .name = "mas_qhm_a1noc_cfg", 20 .id = SC8180X_MASTER_A1NOC_CFG, 21 .channels = 1, 22 .buswidth = 4, 23 .num_links = 1, 24 .links = { SC8180X_SLAVE_SERVICE_A1NOC } 25 }; 26 27 static struct qcom_icc_node mas_xm_ufs_card = { 28 .name = "mas_xm_ufs_card", 29 .id = SC8180X_MASTER_UFS_CARD, 30 .channels = 1, 31 .buswidth = 8, 32 .num_links = 1, 33 .links = { SC8180X_A1NOC_SNOC_SLV } 34 }; 35 36 static struct qcom_icc_node mas_xm_ufs_g4 = { 37 .name = "mas_xm_ufs_g4", 38 .id = SC8180X_MASTER_UFS_GEN4, 39 .channels = 1, 40 .buswidth = 8, 41 .num_links = 1, 42 .links = { SC8180X_A1NOC_SNOC_SLV } 43 }; 44 45 static struct qcom_icc_node mas_xm_ufs_mem = { 46 .name = "mas_xm_ufs_mem", 47 .id = SC8180X_MASTER_UFS_MEM, 48 .channels = 1, 49 .buswidth = 8, 50 .num_links = 1, 51 .links = { SC8180X_A1NOC_SNOC_SLV } 52 }; 53 54 static struct qcom_icc_node mas_xm_usb3_0 = { 55 .name = "mas_xm_usb3_0", 56 .id = SC8180X_MASTER_USB3, 57 .channels = 1, 58 .buswidth = 8, 59 .num_links = 1, 60 .links = { SC8180X_A1NOC_SNOC_SLV } 61 }; 62 63 static struct qcom_icc_node mas_xm_usb3_1 = { 64 .name = "mas_xm_usb3_1", 65 .id = SC8180X_MASTER_USB3_1, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { SC8180X_A1NOC_SNOC_SLV } 70 }; 71 72 static struct qcom_icc_node mas_xm_usb3_2 = { 73 .name = "mas_xm_usb3_2", 74 .id = SC8180X_MASTER_USB3_2, 75 .channels = 1, 76 .buswidth = 16, 77 .num_links = 1, 78 .links = { SC8180X_A1NOC_SNOC_SLV } 79 }; 80 81 static struct qcom_icc_node mas_qhm_a2noc_cfg = { 82 .name = "mas_qhm_a2noc_cfg", 83 .id = SC8180X_MASTER_A2NOC_CFG, 84 .channels = 1, 85 .buswidth = 4, 86 .num_links = 1, 87 .links = { SC8180X_SLAVE_SERVICE_A2NOC } 88 }; 89 90 static struct qcom_icc_node mas_qhm_qdss_bam = { 91 .name = "mas_qhm_qdss_bam", 92 .id = SC8180X_MASTER_QDSS_BAM, 93 .channels = 1, 94 .buswidth = 4, 95 .num_links = 1, 96 .links = { SC8180X_A2NOC_SNOC_SLV } 97 }; 98 99 static struct qcom_icc_node mas_qhm_qspi = { 100 .name = "mas_qhm_qspi", 101 .id = SC8180X_MASTER_QSPI_0, 102 .channels = 1, 103 .buswidth = 4, 104 .num_links = 1, 105 .links = { SC8180X_A2NOC_SNOC_SLV } 106 }; 107 108 static struct qcom_icc_node mas_qhm_qspi1 = { 109 .name = "mas_qhm_qspi1", 110 .id = SC8180X_MASTER_QSPI_1, 111 .channels = 1, 112 .buswidth = 4, 113 .num_links = 1, 114 .links = { SC8180X_A2NOC_SNOC_SLV } 115 }; 116 117 static struct qcom_icc_node mas_qhm_qup0 = { 118 .name = "mas_qhm_qup0", 119 .id = SC8180X_MASTER_QUP_0, 120 .channels = 1, 121 .buswidth = 4, 122 .num_links = 1, 123 .links = { SC8180X_A2NOC_SNOC_SLV } 124 }; 125 126 static struct qcom_icc_node mas_qhm_qup1 = { 127 .name = "mas_qhm_qup1", 128 .id = SC8180X_MASTER_QUP_1, 129 .channels = 1, 130 .buswidth = 4, 131 .num_links = 1, 132 .links = { SC8180X_A2NOC_SNOC_SLV } 133 }; 134 135 static struct qcom_icc_node mas_qhm_qup2 = { 136 .name = "mas_qhm_qup2", 137 .id = SC8180X_MASTER_QUP_2, 138 .channels = 1, 139 .buswidth = 4, 140 .num_links = 1, 141 .links = { SC8180X_A2NOC_SNOC_SLV } 142 }; 143 144 static struct qcom_icc_node mas_qhm_sensorss_ahb = { 145 .name = "mas_qhm_sensorss_ahb", 146 .id = SC8180X_MASTER_SENSORS_AHB, 147 .channels = 1, 148 .buswidth = 4, 149 .num_links = 1, 150 .links = { SC8180X_A2NOC_SNOC_SLV } 151 }; 152 153 static struct qcom_icc_node mas_qxm_crypto = { 154 .name = "mas_qxm_crypto", 155 .id = SC8180X_MASTER_CRYPTO_CORE_0, 156 .channels = 1, 157 .buswidth = 8, 158 .num_links = 1, 159 .links = { SC8180X_A2NOC_SNOC_SLV } 160 }; 161 162 static struct qcom_icc_node mas_qxm_ipa = { 163 .name = "mas_qxm_ipa", 164 .id = SC8180X_MASTER_IPA, 165 .channels = 1, 166 .buswidth = 8, 167 .num_links = 1, 168 .links = { SC8180X_A2NOC_SNOC_SLV } 169 }; 170 171 static struct qcom_icc_node mas_xm_emac = { 172 .name = "mas_xm_emac", 173 .id = SC8180X_MASTER_EMAC, 174 .channels = 1, 175 .buswidth = 8, 176 .num_links = 1, 177 .links = { SC8180X_A2NOC_SNOC_SLV } 178 }; 179 180 static struct qcom_icc_node mas_xm_pcie3_0 = { 181 .name = "mas_xm_pcie3_0", 182 .id = SC8180X_MASTER_PCIE, 183 .channels = 1, 184 .buswidth = 8, 185 .num_links = 1, 186 .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } 187 }; 188 189 static struct qcom_icc_node mas_xm_pcie3_1 = { 190 .name = "mas_xm_pcie3_1", 191 .id = SC8180X_MASTER_PCIE_1, 192 .channels = 1, 193 .buswidth = 16, 194 .num_links = 1, 195 .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } 196 }; 197 198 static struct qcom_icc_node mas_xm_pcie3_2 = { 199 .name = "mas_xm_pcie3_2", 200 .id = SC8180X_MASTER_PCIE_2, 201 .channels = 1, 202 .buswidth = 8, 203 .num_links = 1, 204 .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } 205 }; 206 207 static struct qcom_icc_node mas_xm_pcie3_3 = { 208 .name = "mas_xm_pcie3_3", 209 .id = SC8180X_MASTER_PCIE_3, 210 .channels = 1, 211 .buswidth = 16, 212 .num_links = 1, 213 .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } 214 }; 215 216 static struct qcom_icc_node mas_xm_qdss_etr = { 217 .name = "mas_xm_qdss_etr", 218 .id = SC8180X_MASTER_QDSS_ETR, 219 .channels = 1, 220 .buswidth = 8, 221 .num_links = 1, 222 .links = { SC8180X_A2NOC_SNOC_SLV } 223 }; 224 225 static struct qcom_icc_node mas_xm_sdc2 = { 226 .name = "mas_xm_sdc2", 227 .id = SC8180X_MASTER_SDCC_2, 228 .channels = 1, 229 .buswidth = 8, 230 .num_links = 1, 231 .links = { SC8180X_A2NOC_SNOC_SLV } 232 }; 233 234 static struct qcom_icc_node mas_xm_sdc4 = { 235 .name = "mas_xm_sdc4", 236 .id = SC8180X_MASTER_SDCC_4, 237 .channels = 1, 238 .buswidth = 8, 239 .num_links = 1, 240 .links = { SC8180X_A2NOC_SNOC_SLV } 241 }; 242 243 static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { 244 .name = "mas_qxm_camnoc_hf0_uncomp", 245 .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP, 246 .channels = 1, 247 .buswidth = 32, 248 .num_links = 1, 249 .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } 250 }; 251 252 static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { 253 .name = "mas_qxm_camnoc_hf1_uncomp", 254 .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP, 255 .channels = 1, 256 .buswidth = 32, 257 .num_links = 1, 258 .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } 259 }; 260 261 static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { 262 .name = "mas_qxm_camnoc_sf_uncomp", 263 .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP, 264 .channels = 1, 265 .buswidth = 32, 266 .num_links = 1, 267 .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } 268 }; 269 270 static struct qcom_icc_node mas_qnm_npu = { 271 .name = "mas_qnm_npu", 272 .id = SC8180X_MASTER_NPU, 273 .channels = 1, 274 .buswidth = 32, 275 .num_links = 1, 276 .links = { SC8180X_SLAVE_CDSP_MEM_NOC } 277 }; 278 279 static struct qcom_icc_node mas_qnm_snoc = { 280 .name = "mas_qnm_snoc", 281 .id = SC8180X_SNOC_CNOC_MAS, 282 .channels = 1, 283 .buswidth = 8, 284 .num_links = 56, 285 .links = { SC8180X_SLAVE_TLMM_SOUTH, 286 SC8180X_SLAVE_CDSP_CFG, 287 SC8180X_SLAVE_SPSS_CFG, 288 SC8180X_SLAVE_CAMERA_CFG, 289 SC8180X_SLAVE_SDCC_4, 290 SC8180X_SLAVE_AHB2PHY_CENTER, 291 SC8180X_SLAVE_SDCC_2, 292 SC8180X_SLAVE_PCIE_2_CFG, 293 SC8180X_SLAVE_CNOC_MNOC_CFG, 294 SC8180X_SLAVE_EMAC_CFG, 295 SC8180X_SLAVE_QSPI_0, 296 SC8180X_SLAVE_QSPI_1, 297 SC8180X_SLAVE_TLMM_EAST, 298 SC8180X_SLAVE_SNOC_CFG, 299 SC8180X_SLAVE_AHB2PHY_EAST, 300 SC8180X_SLAVE_GLM, 301 SC8180X_SLAVE_PDM, 302 SC8180X_SLAVE_PCIE_1_CFG, 303 SC8180X_SLAVE_A2NOC_CFG, 304 SC8180X_SLAVE_QDSS_CFG, 305 SC8180X_SLAVE_DISPLAY_CFG, 306 SC8180X_SLAVE_TCSR, 307 SC8180X_SLAVE_UFS_MEM_0_CFG, 308 SC8180X_SLAVE_CNOC_DDRSS, 309 SC8180X_SLAVE_PCIE_0_CFG, 310 SC8180X_SLAVE_QUP_1, 311 SC8180X_SLAVE_QUP_2, 312 SC8180X_SLAVE_NPU_CFG, 313 SC8180X_SLAVE_CRYPTO_0_CFG, 314 SC8180X_SLAVE_GRAPHICS_3D_CFG, 315 SC8180X_SLAVE_VENUS_CFG, 316 SC8180X_SLAVE_TSIF, 317 SC8180X_SLAVE_IPA_CFG, 318 SC8180X_SLAVE_CLK_CTL, 319 SC8180X_SLAVE_SECURITY, 320 SC8180X_SLAVE_AOP, 321 SC8180X_SLAVE_AHB2PHY_WEST, 322 SC8180X_SLAVE_AHB2PHY_SOUTH, 323 SC8180X_SLAVE_SERVICE_CNOC, 324 SC8180X_SLAVE_UFS_CARD_CFG, 325 SC8180X_SLAVE_USB3_1, 326 SC8180X_SLAVE_USB3_2, 327 SC8180X_SLAVE_PCIE_3_CFG, 328 SC8180X_SLAVE_RBCPR_CX_CFG, 329 SC8180X_SLAVE_TLMM_WEST, 330 SC8180X_SLAVE_A1NOC_CFG, 331 SC8180X_SLAVE_AOSS, 332 SC8180X_SLAVE_PRNG, 333 SC8180X_SLAVE_VSENSE_CTRL_CFG, 334 SC8180X_SLAVE_QUP_0, 335 SC8180X_SLAVE_USB3, 336 SC8180X_SLAVE_RBCPR_MMCX_CFG, 337 SC8180X_SLAVE_PIMEM_CFG, 338 SC8180X_SLAVE_UFS_MEM_1_CFG, 339 SC8180X_SLAVE_RBCPR_MX_CFG, 340 SC8180X_SLAVE_IMEM_CFG } 341 }; 342 343 static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { 344 .name = "mas_qhm_cnoc_dc_noc", 345 .id = SC8180X_MASTER_CNOC_DC_NOC, 346 .channels = 1, 347 .buswidth = 4, 348 .num_links = 2, 349 .links = { SC8180X_SLAVE_LLCC_CFG, 350 SC8180X_SLAVE_GEM_NOC_CFG } 351 }; 352 353 static struct qcom_icc_node mas_acm_apps = { 354 .name = "mas_acm_apps", 355 .id = SC8180X_MASTER_AMPSS_M0, 356 .channels = 4, 357 .buswidth = 64, 358 .num_links = 3, 359 .links = { SC8180X_SLAVE_ECC, 360 SC8180X_SLAVE_LLCC, 361 SC8180X_SLAVE_GEM_NOC_SNOC } 362 }; 363 364 static struct qcom_icc_node mas_acm_gpu_tcu = { 365 .name = "mas_acm_gpu_tcu", 366 .id = SC8180X_MASTER_GPU_TCU, 367 .channels = 1, 368 .buswidth = 8, 369 .num_links = 2, 370 .links = { SC8180X_SLAVE_LLCC, 371 SC8180X_SLAVE_GEM_NOC_SNOC } 372 }; 373 374 static struct qcom_icc_node mas_acm_sys_tcu = { 375 .name = "mas_acm_sys_tcu", 376 .id = SC8180X_MASTER_SYS_TCU, 377 .channels = 1, 378 .buswidth = 8, 379 .num_links = 2, 380 .links = { SC8180X_SLAVE_LLCC, 381 SC8180X_SLAVE_GEM_NOC_SNOC } 382 }; 383 384 static struct qcom_icc_node mas_qhm_gemnoc_cfg = { 385 .name = "mas_qhm_gemnoc_cfg", 386 .id = SC8180X_MASTER_GEM_NOC_CFG, 387 .channels = 1, 388 .buswidth = 4, 389 .num_links = 3, 390 .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1, 391 SC8180X_SLAVE_SERVICE_GEM_NOC, 392 SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } 393 }; 394 395 static struct qcom_icc_node mas_qnm_cmpnoc = { 396 .name = "mas_qnm_cmpnoc", 397 .id = SC8180X_MASTER_COMPUTE_NOC, 398 .channels = 2, 399 .buswidth = 32, 400 .num_links = 3, 401 .links = { SC8180X_SLAVE_ECC, 402 SC8180X_SLAVE_LLCC, 403 SC8180X_SLAVE_GEM_NOC_SNOC } 404 }; 405 406 static struct qcom_icc_node mas_qnm_gpu = { 407 .name = "mas_qnm_gpu", 408 .id = SC8180X_MASTER_GRAPHICS_3D, 409 .channels = 4, 410 .buswidth = 32, 411 .num_links = 2, 412 .links = { SC8180X_SLAVE_LLCC, 413 SC8180X_SLAVE_GEM_NOC_SNOC } 414 }; 415 416 static struct qcom_icc_node mas_qnm_mnoc_hf = { 417 .name = "mas_qnm_mnoc_hf", 418 .id = SC8180X_MASTER_MNOC_HF_MEM_NOC, 419 .channels = 2, 420 .buswidth = 32, 421 .num_links = 1, 422 .links = { SC8180X_SLAVE_LLCC } 423 }; 424 425 static struct qcom_icc_node mas_qnm_mnoc_sf = { 426 .name = "mas_qnm_mnoc_sf", 427 .id = SC8180X_MASTER_MNOC_SF_MEM_NOC, 428 .channels = 1, 429 .buswidth = 32, 430 .num_links = 2, 431 .links = { SC8180X_SLAVE_LLCC, 432 SC8180X_SLAVE_GEM_NOC_SNOC } 433 }; 434 435 static struct qcom_icc_node mas_qnm_pcie = { 436 .name = "mas_qnm_pcie", 437 .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC, 438 .channels = 1, 439 .buswidth = 32, 440 .num_links = 2, 441 .links = { SC8180X_SLAVE_LLCC, 442 SC8180X_SLAVE_GEM_NOC_SNOC } 443 }; 444 445 static struct qcom_icc_node mas_qnm_snoc_gc = { 446 .name = "mas_qnm_snoc_gc", 447 .id = SC8180X_MASTER_SNOC_GC_MEM_NOC, 448 .channels = 1, 449 .buswidth = 8, 450 .num_links = 1, 451 .links = { SC8180X_SLAVE_LLCC } 452 }; 453 454 static struct qcom_icc_node mas_qnm_snoc_sf = { 455 .name = "mas_qnm_snoc_sf", 456 .id = SC8180X_MASTER_SNOC_SF_MEM_NOC, 457 .channels = 1, 458 .buswidth = 32, 459 .num_links = 1, 460 .links = { SC8180X_SLAVE_LLCC } 461 }; 462 463 static struct qcom_icc_node mas_qxm_ecc = { 464 .name = "mas_qxm_ecc", 465 .id = SC8180X_MASTER_ECC, 466 .channels = 2, 467 .buswidth = 32, 468 .num_links = 1, 469 .links = { SC8180X_SLAVE_LLCC } 470 }; 471 472 static struct qcom_icc_node mas_llcc_mc = { 473 .name = "mas_llcc_mc", 474 .id = SC8180X_MASTER_LLCC, 475 .channels = 8, 476 .buswidth = 4, 477 .num_links = 1, 478 .links = { SC8180X_SLAVE_EBI_CH0 } 479 }; 480 481 static struct qcom_icc_node mas_qhm_mnoc_cfg = { 482 .name = "mas_qhm_mnoc_cfg", 483 .id = SC8180X_MASTER_CNOC_MNOC_CFG, 484 .channels = 1, 485 .buswidth = 4, 486 .num_links = 1, 487 .links = { SC8180X_SLAVE_SERVICE_MNOC } 488 }; 489 490 static struct qcom_icc_node mas_qxm_camnoc_hf0 = { 491 .name = "mas_qxm_camnoc_hf0", 492 .id = SC8180X_MASTER_CAMNOC_HF0, 493 .channels = 1, 494 .buswidth = 32, 495 .num_links = 1, 496 .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } 497 }; 498 499 static struct qcom_icc_node mas_qxm_camnoc_hf1 = { 500 .name = "mas_qxm_camnoc_hf1", 501 .id = SC8180X_MASTER_CAMNOC_HF1, 502 .channels = 1, 503 .buswidth = 32, 504 .num_links = 1, 505 .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } 506 }; 507 508 static struct qcom_icc_node mas_qxm_camnoc_sf = { 509 .name = "mas_qxm_camnoc_sf", 510 .id = SC8180X_MASTER_CAMNOC_SF, 511 .channels = 1, 512 .buswidth = 32, 513 .num_links = 1, 514 .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } 515 }; 516 517 static struct qcom_icc_node mas_qxm_mdp0 = { 518 .name = "mas_qxm_mdp0", 519 .id = SC8180X_MASTER_MDP_PORT0, 520 .channels = 1, 521 .buswidth = 32, 522 .num_links = 1, 523 .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } 524 }; 525 526 static struct qcom_icc_node mas_qxm_mdp1 = { 527 .name = "mas_qxm_mdp1", 528 .id = SC8180X_MASTER_MDP_PORT1, 529 .channels = 1, 530 .buswidth = 32, 531 .num_links = 1, 532 .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } 533 }; 534 535 static struct qcom_icc_node mas_qxm_rot = { 536 .name = "mas_qxm_rot", 537 .id = SC8180X_MASTER_ROTATOR, 538 .channels = 1, 539 .buswidth = 32, 540 .num_links = 1, 541 .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } 542 }; 543 544 static struct qcom_icc_node mas_qxm_venus0 = { 545 .name = "mas_qxm_venus0", 546 .id = SC8180X_MASTER_VIDEO_P0, 547 .channels = 1, 548 .buswidth = 32, 549 .num_links = 1, 550 .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } 551 }; 552 553 static struct qcom_icc_node mas_qxm_venus1 = { 554 .name = "mas_qxm_venus1", 555 .id = SC8180X_MASTER_VIDEO_P1, 556 .channels = 1, 557 .buswidth = 32, 558 .num_links = 1, 559 .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } 560 }; 561 562 static struct qcom_icc_node mas_qxm_venus_arm9 = { 563 .name = "mas_qxm_venus_arm9", 564 .id = SC8180X_MASTER_VIDEO_PROC, 565 .channels = 1, 566 .buswidth = 8, 567 .num_links = 1, 568 .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } 569 }; 570 571 static struct qcom_icc_node mas_qhm_snoc_cfg = { 572 .name = "mas_qhm_snoc_cfg", 573 .id = SC8180X_MASTER_SNOC_CFG, 574 .channels = 1, 575 .buswidth = 4, 576 .num_links = 1, 577 .links = { SC8180X_SLAVE_SERVICE_SNOC } 578 }; 579 580 static struct qcom_icc_node mas_qnm_aggre1_noc = { 581 .name = "mas_qnm_aggre1_noc", 582 .id = SC8180X_A1NOC_SNOC_MAS, 583 .channels = 1, 584 .buswidth = 32, 585 .num_links = 6, 586 .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, 587 SC8180X_SLAVE_PIMEM, 588 SC8180X_SLAVE_OCIMEM, 589 SC8180X_SLAVE_APPSS, 590 SC8180X_SNOC_CNOC_SLV, 591 SC8180X_SLAVE_QDSS_STM } 592 }; 593 594 static struct qcom_icc_node mas_qnm_aggre2_noc = { 595 .name = "mas_qnm_aggre2_noc", 596 .id = SC8180X_A2NOC_SNOC_MAS, 597 .channels = 1, 598 .buswidth = 16, 599 .num_links = 11, 600 .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, 601 SC8180X_SLAVE_PIMEM, 602 SC8180X_SLAVE_PCIE_3, 603 SC8180X_SLAVE_OCIMEM, 604 SC8180X_SLAVE_APPSS, 605 SC8180X_SLAVE_PCIE_2, 606 SC8180X_SNOC_CNOC_SLV, 607 SC8180X_SLAVE_PCIE_0, 608 SC8180X_SLAVE_PCIE_1, 609 SC8180X_SLAVE_TCU, 610 SC8180X_SLAVE_QDSS_STM } 611 }; 612 613 static struct qcom_icc_node mas_qnm_gemnoc = { 614 .name = "mas_qnm_gemnoc", 615 .id = SC8180X_MASTER_GEM_NOC_SNOC, 616 .channels = 1, 617 .buswidth = 8, 618 .num_links = 6, 619 .links = { SC8180X_SLAVE_PIMEM, 620 SC8180X_SLAVE_OCIMEM, 621 SC8180X_SLAVE_APPSS, 622 SC8180X_SNOC_CNOC_SLV, 623 SC8180X_SLAVE_TCU, 624 SC8180X_SLAVE_QDSS_STM } 625 }; 626 627 static struct qcom_icc_node mas_qxm_pimem = { 628 .name = "mas_qxm_pimem", 629 .id = SC8180X_MASTER_PIMEM, 630 .channels = 1, 631 .buswidth = 8, 632 .num_links = 2, 633 .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, 634 SC8180X_SLAVE_OCIMEM } 635 }; 636 637 static struct qcom_icc_node mas_xm_gic = { 638 .name = "mas_xm_gic", 639 .id = SC8180X_MASTER_GIC, 640 .channels = 1, 641 .buswidth = 8, 642 .num_links = 2, 643 .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, 644 SC8180X_SLAVE_OCIMEM } 645 }; 646 647 static struct qcom_icc_node mas_qup_core_0 = { 648 .name = "mas_qup_core_0", 649 .id = SC8180X_MASTER_QUP_CORE_0, 650 .channels = 1, 651 .buswidth = 4, 652 .num_links = 1, 653 .links = { SC8180X_SLAVE_QUP_CORE_0 } 654 }; 655 656 static struct qcom_icc_node mas_qup_core_1 = { 657 .name = "mas_qup_core_1", 658 .id = SC8180X_MASTER_QUP_CORE_1, 659 .channels = 1, 660 .buswidth = 4, 661 .num_links = 1, 662 .links = { SC8180X_SLAVE_QUP_CORE_1 } 663 }; 664 665 static struct qcom_icc_node mas_qup_core_2 = { 666 .name = "mas_qup_core_2", 667 .id = SC8180X_MASTER_QUP_CORE_2, 668 .channels = 1, 669 .buswidth = 4, 670 .num_links = 1, 671 .links = { SC8180X_SLAVE_QUP_CORE_2 } 672 }; 673 674 static struct qcom_icc_node slv_qns_a1noc_snoc = { 675 .name = "slv_qns_a1noc_snoc", 676 .id = SC8180X_A1NOC_SNOC_SLV, 677 .channels = 1, 678 .buswidth = 32, 679 .num_links = 1, 680 .links = { SC8180X_A1NOC_SNOC_MAS } 681 }; 682 683 static struct qcom_icc_node slv_srvc_aggre1_noc = { 684 .name = "slv_srvc_aggre1_noc", 685 .id = SC8180X_SLAVE_SERVICE_A1NOC, 686 .channels = 1, 687 .buswidth = 4 688 }; 689 690 static struct qcom_icc_node slv_qns_a2noc_snoc = { 691 .name = "slv_qns_a2noc_snoc", 692 .id = SC8180X_A2NOC_SNOC_SLV, 693 .channels = 1, 694 .buswidth = 16, 695 .num_links = 1, 696 .links = { SC8180X_A2NOC_SNOC_MAS } 697 }; 698 699 static struct qcom_icc_node slv_qns_pcie_mem_noc = { 700 .name = "slv_qns_pcie_mem_noc", 701 .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, 702 .channels = 1, 703 .buswidth = 32, 704 .num_links = 1, 705 .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } 706 }; 707 708 static struct qcom_icc_node slv_srvc_aggre2_noc = { 709 .name = "slv_srvc_aggre2_noc", 710 .id = SC8180X_SLAVE_SERVICE_A2NOC, 711 .channels = 1, 712 .buswidth = 4 713 }; 714 715 static struct qcom_icc_node slv_qns_camnoc_uncomp = { 716 .name = "slv_qns_camnoc_uncomp", 717 .id = SC8180X_SLAVE_CAMNOC_UNCOMP, 718 .channels = 1, 719 .buswidth = 32 720 }; 721 722 static struct qcom_icc_node slv_qns_cdsp_mem_noc = { 723 .name = "slv_qns_cdsp_mem_noc", 724 .id = SC8180X_SLAVE_CDSP_MEM_NOC, 725 .channels = 2, 726 .buswidth = 32, 727 .num_links = 1, 728 .links = { SC8180X_MASTER_COMPUTE_NOC } 729 }; 730 731 static struct qcom_icc_node slv_qhs_a1_noc_cfg = { 732 .name = "slv_qhs_a1_noc_cfg", 733 .id = SC8180X_SLAVE_A1NOC_CFG, 734 .channels = 1, 735 .buswidth = 4, 736 .num_links = 1, 737 .links = { SC8180X_MASTER_A1NOC_CFG } 738 }; 739 740 static struct qcom_icc_node slv_qhs_a2_noc_cfg = { 741 .name = "slv_qhs_a2_noc_cfg", 742 .id = SC8180X_SLAVE_A2NOC_CFG, 743 .channels = 1, 744 .buswidth = 4, 745 .num_links = 1, 746 .links = { SC8180X_MASTER_A2NOC_CFG } 747 }; 748 749 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { 750 .name = "slv_qhs_ahb2phy_refgen_center", 751 .id = SC8180X_SLAVE_AHB2PHY_CENTER, 752 .channels = 1, 753 .buswidth = 4 754 }; 755 756 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { 757 .name = "slv_qhs_ahb2phy_refgen_east", 758 .id = SC8180X_SLAVE_AHB2PHY_EAST, 759 .channels = 1, 760 .buswidth = 4 761 }; 762 763 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { 764 .name = "slv_qhs_ahb2phy_refgen_west", 765 .id = SC8180X_SLAVE_AHB2PHY_WEST, 766 .channels = 1, 767 .buswidth = 4 768 }; 769 770 static struct qcom_icc_node slv_qhs_ahb2phy_south = { 771 .name = "slv_qhs_ahb2phy_south", 772 .id = SC8180X_SLAVE_AHB2PHY_SOUTH, 773 .channels = 1, 774 .buswidth = 4 775 }; 776 777 static struct qcom_icc_node slv_qhs_aop = { 778 .name = "slv_qhs_aop", 779 .id = SC8180X_SLAVE_AOP, 780 .channels = 1, 781 .buswidth = 4 782 }; 783 784 static struct qcom_icc_node slv_qhs_aoss = { 785 .name = "slv_qhs_aoss", 786 .id = SC8180X_SLAVE_AOSS, 787 .channels = 1, 788 .buswidth = 4 789 }; 790 791 static struct qcom_icc_node slv_qhs_camera_cfg = { 792 .name = "slv_qhs_camera_cfg", 793 .id = SC8180X_SLAVE_CAMERA_CFG, 794 .channels = 1, 795 .buswidth = 4 796 }; 797 798 static struct qcom_icc_node slv_qhs_clk_ctl = { 799 .name = "slv_qhs_clk_ctl", 800 .id = SC8180X_SLAVE_CLK_CTL, 801 .channels = 1, 802 .buswidth = 4 803 }; 804 805 static struct qcom_icc_node slv_qhs_compute_dsp = { 806 .name = "slv_qhs_compute_dsp", 807 .id = SC8180X_SLAVE_CDSP_CFG, 808 .channels = 1, 809 .buswidth = 4 810 }; 811 812 static struct qcom_icc_node slv_qhs_cpr_cx = { 813 .name = "slv_qhs_cpr_cx", 814 .id = SC8180X_SLAVE_RBCPR_CX_CFG, 815 .channels = 1, 816 .buswidth = 4 817 }; 818 819 static struct qcom_icc_node slv_qhs_cpr_mmcx = { 820 .name = "slv_qhs_cpr_mmcx", 821 .id = SC8180X_SLAVE_RBCPR_MMCX_CFG, 822 .channels = 1, 823 .buswidth = 4 824 }; 825 826 static struct qcom_icc_node slv_qhs_cpr_mx = { 827 .name = "slv_qhs_cpr_mx", 828 .id = SC8180X_SLAVE_RBCPR_MX_CFG, 829 .channels = 1, 830 .buswidth = 4 831 }; 832 833 static struct qcom_icc_node slv_qhs_crypto0_cfg = { 834 .name = "slv_qhs_crypto0_cfg", 835 .id = SC8180X_SLAVE_CRYPTO_0_CFG, 836 .channels = 1, 837 .buswidth = 4 838 }; 839 840 static struct qcom_icc_node slv_qhs_ddrss_cfg = { 841 .name = "slv_qhs_ddrss_cfg", 842 .id = SC8180X_SLAVE_CNOC_DDRSS, 843 .channels = 1, 844 .buswidth = 4, 845 .num_links = 1, 846 .links = { SC8180X_MASTER_CNOC_DC_NOC } 847 }; 848 849 static struct qcom_icc_node slv_qhs_display_cfg = { 850 .name = "slv_qhs_display_cfg", 851 .id = SC8180X_SLAVE_DISPLAY_CFG, 852 .channels = 1, 853 .buswidth = 4 854 }; 855 856 static struct qcom_icc_node slv_qhs_emac_cfg = { 857 .name = "slv_qhs_emac_cfg", 858 .id = SC8180X_SLAVE_EMAC_CFG, 859 .channels = 1, 860 .buswidth = 4 861 }; 862 863 static struct qcom_icc_node slv_qhs_glm = { 864 .name = "slv_qhs_glm", 865 .id = SC8180X_SLAVE_GLM, 866 .channels = 1, 867 .buswidth = 4 868 }; 869 870 static struct qcom_icc_node slv_qhs_gpuss_cfg = { 871 .name = "slv_qhs_gpuss_cfg", 872 .id = SC8180X_SLAVE_GRAPHICS_3D_CFG, 873 .channels = 1, 874 .buswidth = 8 875 }; 876 877 static struct qcom_icc_node slv_qhs_imem_cfg = { 878 .name = "slv_qhs_imem_cfg", 879 .id = SC8180X_SLAVE_IMEM_CFG, 880 .channels = 1, 881 .buswidth = 4 882 }; 883 884 static struct qcom_icc_node slv_qhs_ipa = { 885 .name = "slv_qhs_ipa", 886 .id = SC8180X_SLAVE_IPA_CFG, 887 .channels = 1, 888 .buswidth = 4 889 }; 890 891 static struct qcom_icc_node slv_qhs_mnoc_cfg = { 892 .name = "slv_qhs_mnoc_cfg", 893 .id = SC8180X_SLAVE_CNOC_MNOC_CFG, 894 .channels = 1, 895 .buswidth = 4, 896 .num_links = 1, 897 .links = { SC8180X_MASTER_CNOC_MNOC_CFG } 898 }; 899 900 static struct qcom_icc_node slv_qhs_npu_cfg = { 901 .name = "slv_qhs_npu_cfg", 902 .id = SC8180X_SLAVE_NPU_CFG, 903 .channels = 1, 904 .buswidth = 4 905 }; 906 907 static struct qcom_icc_node slv_qhs_pcie0_cfg = { 908 .name = "slv_qhs_pcie0_cfg", 909 .id = SC8180X_SLAVE_PCIE_0_CFG, 910 .channels = 1, 911 .buswidth = 4 912 }; 913 914 static struct qcom_icc_node slv_qhs_pcie1_cfg = { 915 .name = "slv_qhs_pcie1_cfg", 916 .id = SC8180X_SLAVE_PCIE_1_CFG, 917 .channels = 1, 918 .buswidth = 4 919 }; 920 921 static struct qcom_icc_node slv_qhs_pcie2_cfg = { 922 .name = "slv_qhs_pcie2_cfg", 923 .id = SC8180X_SLAVE_PCIE_2_CFG, 924 .channels = 1, 925 .buswidth = 4 926 }; 927 928 static struct qcom_icc_node slv_qhs_pcie3_cfg = { 929 .name = "slv_qhs_pcie3_cfg", 930 .id = SC8180X_SLAVE_PCIE_3_CFG, 931 .channels = 1, 932 .buswidth = 4 933 }; 934 935 static struct qcom_icc_node slv_qhs_pdm = { 936 .name = "slv_qhs_pdm", 937 .id = SC8180X_SLAVE_PDM, 938 .channels = 1, 939 .buswidth = 4 940 }; 941 942 static struct qcom_icc_node slv_qhs_pimem_cfg = { 943 .name = "slv_qhs_pimem_cfg", 944 .id = SC8180X_SLAVE_PIMEM_CFG, 945 .channels = 1, 946 .buswidth = 4 947 }; 948 949 static struct qcom_icc_node slv_qhs_prng = { 950 .name = "slv_qhs_prng", 951 .id = SC8180X_SLAVE_PRNG, 952 .channels = 1, 953 .buswidth = 4 954 }; 955 956 static struct qcom_icc_node slv_qhs_qdss_cfg = { 957 .name = "slv_qhs_qdss_cfg", 958 .id = SC8180X_SLAVE_QDSS_CFG, 959 .channels = 1, 960 .buswidth = 4 961 }; 962 963 static struct qcom_icc_node slv_qhs_qspi_0 = { 964 .name = "slv_qhs_qspi_0", 965 .id = SC8180X_SLAVE_QSPI_0, 966 .channels = 1, 967 .buswidth = 4 968 }; 969 970 static struct qcom_icc_node slv_qhs_qspi_1 = { 971 .name = "slv_qhs_qspi_1", 972 .id = SC8180X_SLAVE_QSPI_1, 973 .channels = 1, 974 .buswidth = 4 975 }; 976 977 static struct qcom_icc_node slv_qhs_qupv3_east0 = { 978 .name = "slv_qhs_qupv3_east0", 979 .id = SC8180X_SLAVE_QUP_1, 980 .channels = 1, 981 .buswidth = 4 982 }; 983 984 static struct qcom_icc_node slv_qhs_qupv3_east1 = { 985 .name = "slv_qhs_qupv3_east1", 986 .id = SC8180X_SLAVE_QUP_2, 987 .channels = 1, 988 .buswidth = 4 989 }; 990 991 static struct qcom_icc_node slv_qhs_qupv3_west = { 992 .name = "slv_qhs_qupv3_west", 993 .id = SC8180X_SLAVE_QUP_0, 994 .channels = 1, 995 .buswidth = 4 996 }; 997 998 static struct qcom_icc_node slv_qhs_sdc2 = { 999 .name = "slv_qhs_sdc2", 1000 .id = SC8180X_SLAVE_SDCC_2, 1001 .channels = 1, 1002 .buswidth = 4 1003 }; 1004 1005 static struct qcom_icc_node slv_qhs_sdc4 = { 1006 .name = "slv_qhs_sdc4", 1007 .id = SC8180X_SLAVE_SDCC_4, 1008 .channels = 1, 1009 .buswidth = 4 1010 }; 1011 1012 static struct qcom_icc_node slv_qhs_security = { 1013 .name = "slv_qhs_security", 1014 .id = SC8180X_SLAVE_SECURITY, 1015 .channels = 1, 1016 .buswidth = 4 1017 }; 1018 1019 static struct qcom_icc_node slv_qhs_snoc_cfg = { 1020 .name = "slv_qhs_snoc_cfg", 1021 .id = SC8180X_SLAVE_SNOC_CFG, 1022 .channels = 1, 1023 .buswidth = 4, 1024 .num_links = 1, 1025 .links = { SC8180X_MASTER_SNOC_CFG } 1026 }; 1027 1028 static struct qcom_icc_node slv_qhs_spss_cfg = { 1029 .name = "slv_qhs_spss_cfg", 1030 .id = SC8180X_SLAVE_SPSS_CFG, 1031 .channels = 1, 1032 .buswidth = 4 1033 }; 1034 1035 static struct qcom_icc_node slv_qhs_tcsr = { 1036 .name = "slv_qhs_tcsr", 1037 .id = SC8180X_SLAVE_TCSR, 1038 .channels = 1, 1039 .buswidth = 4 1040 }; 1041 1042 static struct qcom_icc_node slv_qhs_tlmm_east = { 1043 .name = "slv_qhs_tlmm_east", 1044 .id = SC8180X_SLAVE_TLMM_EAST, 1045 .channels = 1, 1046 .buswidth = 4 1047 }; 1048 1049 static struct qcom_icc_node slv_qhs_tlmm_south = { 1050 .name = "slv_qhs_tlmm_south", 1051 .id = SC8180X_SLAVE_TLMM_SOUTH, 1052 .channels = 1, 1053 .buswidth = 4 1054 }; 1055 1056 static struct qcom_icc_node slv_qhs_tlmm_west = { 1057 .name = "slv_qhs_tlmm_west", 1058 .id = SC8180X_SLAVE_TLMM_WEST, 1059 .channels = 1, 1060 .buswidth = 4 1061 }; 1062 1063 static struct qcom_icc_node slv_qhs_tsif = { 1064 .name = "slv_qhs_tsif", 1065 .id = SC8180X_SLAVE_TSIF, 1066 .channels = 1, 1067 .buswidth = 4 1068 }; 1069 1070 static struct qcom_icc_node slv_qhs_ufs_card_cfg = { 1071 .name = "slv_qhs_ufs_card_cfg", 1072 .id = SC8180X_SLAVE_UFS_CARD_CFG, 1073 .channels = 1, 1074 .buswidth = 4 1075 }; 1076 1077 static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { 1078 .name = "slv_qhs_ufs_mem0_cfg", 1079 .id = SC8180X_SLAVE_UFS_MEM_0_CFG, 1080 .channels = 1, 1081 .buswidth = 4 1082 }; 1083 1084 static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { 1085 .name = "slv_qhs_ufs_mem1_cfg", 1086 .id = SC8180X_SLAVE_UFS_MEM_1_CFG, 1087 .channels = 1, 1088 .buswidth = 4 1089 }; 1090 1091 static struct qcom_icc_node slv_qhs_usb3_0 = { 1092 .name = "slv_qhs_usb3_0", 1093 .id = SC8180X_SLAVE_USB3, 1094 .channels = 1, 1095 .buswidth = 4 1096 }; 1097 1098 static struct qcom_icc_node slv_qhs_usb3_1 = { 1099 .name = "slv_qhs_usb3_1", 1100 .id = SC8180X_SLAVE_USB3_1, 1101 .channels = 1, 1102 .buswidth = 4 1103 }; 1104 1105 static struct qcom_icc_node slv_qhs_usb3_2 = { 1106 .name = "slv_qhs_usb3_2", 1107 .id = SC8180X_SLAVE_USB3_2, 1108 .channels = 1, 1109 .buswidth = 4 1110 }; 1111 1112 static struct qcom_icc_node slv_qhs_venus_cfg = { 1113 .name = "slv_qhs_venus_cfg", 1114 .id = SC8180X_SLAVE_VENUS_CFG, 1115 .channels = 1, 1116 .buswidth = 4 1117 }; 1118 1119 static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { 1120 .name = "slv_qhs_vsense_ctrl_cfg", 1121 .id = SC8180X_SLAVE_VSENSE_CTRL_CFG, 1122 .channels = 1, 1123 .buswidth = 4 1124 }; 1125 1126 static struct qcom_icc_node slv_srvc_cnoc = { 1127 .name = "slv_srvc_cnoc", 1128 .id = SC8180X_SLAVE_SERVICE_CNOC, 1129 .channels = 1, 1130 .buswidth = 4 1131 }; 1132 1133 static struct qcom_icc_node slv_qhs_gemnoc = { 1134 .name = "slv_qhs_gemnoc", 1135 .id = SC8180X_SLAVE_GEM_NOC_CFG, 1136 .channels = 1, 1137 .buswidth = 4, 1138 .num_links = 1, 1139 .links = { SC8180X_MASTER_GEM_NOC_CFG } 1140 }; 1141 1142 static struct qcom_icc_node slv_qhs_llcc = { 1143 .name = "slv_qhs_llcc", 1144 .id = SC8180X_SLAVE_LLCC_CFG, 1145 .channels = 1, 1146 .buswidth = 4 1147 }; 1148 1149 static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { 1150 .name = "slv_qhs_mdsp_ms_mpu_cfg", 1151 .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, 1152 .channels = 1, 1153 .buswidth = 4 1154 }; 1155 1156 static struct qcom_icc_node slv_qns_ecc = { 1157 .name = "slv_qns_ecc", 1158 .id = SC8180X_SLAVE_ECC, 1159 .channels = 1, 1160 .buswidth = 32 1161 }; 1162 1163 static struct qcom_icc_node slv_qns_gem_noc_snoc = { 1164 .name = "slv_qns_gem_noc_snoc", 1165 .id = SC8180X_SLAVE_GEM_NOC_SNOC, 1166 .channels = 1, 1167 .buswidth = 8, 1168 .num_links = 1, 1169 .links = { SC8180X_MASTER_GEM_NOC_SNOC } 1170 }; 1171 1172 static struct qcom_icc_node slv_qns_llcc = { 1173 .name = "slv_qns_llcc", 1174 .id = SC8180X_SLAVE_LLCC, 1175 .channels = 8, 1176 .buswidth = 16, 1177 .num_links = 1, 1178 .links = { SC8180X_MASTER_LLCC } 1179 }; 1180 1181 static struct qcom_icc_node slv_srvc_gemnoc = { 1182 .name = "slv_srvc_gemnoc", 1183 .id = SC8180X_SLAVE_SERVICE_GEM_NOC, 1184 .channels = 1, 1185 .buswidth = 4 1186 }; 1187 1188 static struct qcom_icc_node slv_srvc_gemnoc1 = { 1189 .name = "slv_srvc_gemnoc1", 1190 .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1, 1191 .channels = 1, 1192 .buswidth = 4 1193 }; 1194 1195 static struct qcom_icc_node slv_ebi = { 1196 .name = "slv_ebi", 1197 .id = SC8180X_SLAVE_EBI_CH0, 1198 .channels = 8, 1199 .buswidth = 4 1200 }; 1201 1202 static struct qcom_icc_node slv_qns2_mem_noc = { 1203 .name = "slv_qns2_mem_noc", 1204 .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC, 1205 .channels = 1, 1206 .buswidth = 32, 1207 .num_links = 1, 1208 .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC } 1209 }; 1210 1211 static struct qcom_icc_node slv_qns_mem_noc_hf = { 1212 .name = "slv_qns_mem_noc_hf", 1213 .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC, 1214 .channels = 2, 1215 .buswidth = 32, 1216 .num_links = 1, 1217 .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC } 1218 }; 1219 1220 static struct qcom_icc_node slv_srvc_mnoc = { 1221 .name = "slv_srvc_mnoc", 1222 .id = SC8180X_SLAVE_SERVICE_MNOC, 1223 .channels = 1, 1224 .buswidth = 4 1225 }; 1226 1227 static struct qcom_icc_node slv_qhs_apss = { 1228 .name = "slv_qhs_apss", 1229 .id = SC8180X_SLAVE_APPSS, 1230 .channels = 1, 1231 .buswidth = 8 1232 }; 1233 1234 static struct qcom_icc_node slv_qns_cnoc = { 1235 .name = "slv_qns_cnoc", 1236 .id = SC8180X_SNOC_CNOC_SLV, 1237 .channels = 1, 1238 .buswidth = 8, 1239 .num_links = 1, 1240 .links = { SC8180X_SNOC_CNOC_MAS } 1241 }; 1242 1243 static struct qcom_icc_node slv_qns_gemnoc_gc = { 1244 .name = "slv_qns_gemnoc_gc", 1245 .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC, 1246 .channels = 1, 1247 .buswidth = 8, 1248 .num_links = 1, 1249 .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC } 1250 }; 1251 1252 static struct qcom_icc_node slv_qns_gemnoc_sf = { 1253 .name = "slv_qns_gemnoc_sf", 1254 .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF, 1255 .channels = 1, 1256 .buswidth = 32, 1257 .num_links = 1, 1258 .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC } 1259 }; 1260 1261 static struct qcom_icc_node slv_qxs_imem = { 1262 .name = "slv_qxs_imem", 1263 .id = SC8180X_SLAVE_OCIMEM, 1264 .channels = 1, 1265 .buswidth = 8 1266 }; 1267 1268 static struct qcom_icc_node slv_qxs_pimem = { 1269 .name = "slv_qxs_pimem", 1270 .id = SC8180X_SLAVE_PIMEM, 1271 .channels = 1, 1272 .buswidth = 8 1273 }; 1274 1275 static struct qcom_icc_node slv_srvc_snoc = { 1276 .name = "slv_srvc_snoc", 1277 .id = SC8180X_SLAVE_SERVICE_SNOC, 1278 .channels = 1, 1279 .buswidth = 4 1280 }; 1281 1282 static struct qcom_icc_node slv_xs_pcie_0 = { 1283 .name = "slv_xs_pcie_0", 1284 .id = SC8180X_SLAVE_PCIE_0, 1285 .channels = 1, 1286 .buswidth = 8 1287 }; 1288 1289 static struct qcom_icc_node slv_xs_pcie_1 = { 1290 .name = "slv_xs_pcie_1", 1291 .id = SC8180X_SLAVE_PCIE_1, 1292 .channels = 1, 1293 .buswidth = 8 1294 }; 1295 1296 static struct qcom_icc_node slv_xs_pcie_2 = { 1297 .name = "slv_xs_pcie_2", 1298 .id = SC8180X_SLAVE_PCIE_2, 1299 .channels = 1, 1300 .buswidth = 8 1301 }; 1302 1303 static struct qcom_icc_node slv_xs_pcie_3 = { 1304 .name = "slv_xs_pcie_3", 1305 .id = SC8180X_SLAVE_PCIE_3, 1306 .channels = 1, 1307 .buswidth = 8 1308 }; 1309 1310 static struct qcom_icc_node slv_xs_qdss_stm = { 1311 .name = "slv_xs_qdss_stm", 1312 .id = SC8180X_SLAVE_QDSS_STM, 1313 .channels = 1, 1314 .buswidth = 4 1315 }; 1316 1317 static struct qcom_icc_node slv_xs_sys_tcu_cfg = { 1318 .name = "slv_xs_sys_tcu_cfg", 1319 .id = SC8180X_SLAVE_TCU, 1320 .channels = 1, 1321 .buswidth = 8 1322 }; 1323 1324 static struct qcom_icc_node slv_qup_core_0 = { 1325 .name = "slv_qup_core_0", 1326 .id = SC8180X_SLAVE_QUP_CORE_0, 1327 .channels = 1, 1328 .buswidth = 4 1329 }; 1330 1331 static struct qcom_icc_node slv_qup_core_1 = { 1332 .name = "slv_qup_core_1", 1333 .id = SC8180X_SLAVE_QUP_CORE_1, 1334 .channels = 1, 1335 .buswidth = 4 1336 }; 1337 1338 static struct qcom_icc_node slv_qup_core_2 = { 1339 .name = "slv_qup_core_2", 1340 .id = SC8180X_SLAVE_QUP_CORE_2, 1341 .channels = 1, 1342 .buswidth = 4 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_acv = { 1346 .name = "ACV", 1347 .num_nodes = 1, 1348 .nodes = { &slv_ebi } 1349 }; 1350 1351 static struct qcom_icc_bcm bcm_mc0 = { 1352 .name = "MC0", 1353 .keepalive = true, 1354 .num_nodes = 1, 1355 .nodes = { &slv_ebi } 1356 }; 1357 1358 static struct qcom_icc_bcm bcm_sh0 = { 1359 .name = "SH0", 1360 .keepalive = true, 1361 .num_nodes = 1, 1362 .nodes = { &slv_qns_llcc } 1363 }; 1364 1365 static struct qcom_icc_bcm bcm_mm0 = { 1366 .name = "MM0", 1367 .num_nodes = 1, 1368 .nodes = { &slv_qns_mem_noc_hf } 1369 }; 1370 1371 static struct qcom_icc_bcm bcm_co0 = { 1372 .name = "CO0", 1373 .num_nodes = 1, 1374 .nodes = { &slv_qns_cdsp_mem_noc } 1375 }; 1376 1377 static struct qcom_icc_bcm bcm_ce0 = { 1378 .name = "CE0", 1379 .num_nodes = 1, 1380 .nodes = { &mas_qxm_crypto } 1381 }; 1382 1383 static struct qcom_icc_bcm bcm_cn0 = { 1384 .name = "CN0", 1385 .keepalive = true, 1386 .num_nodes = 57, 1387 .nodes = { &mas_qnm_snoc, 1388 &slv_qhs_a1_noc_cfg, 1389 &slv_qhs_a2_noc_cfg, 1390 &slv_qhs_ahb2phy_refgen_center, 1391 &slv_qhs_ahb2phy_refgen_east, 1392 &slv_qhs_ahb2phy_refgen_west, 1393 &slv_qhs_ahb2phy_south, 1394 &slv_qhs_aop, 1395 &slv_qhs_aoss, 1396 &slv_qhs_camera_cfg, 1397 &slv_qhs_clk_ctl, 1398 &slv_qhs_compute_dsp, 1399 &slv_qhs_cpr_cx, 1400 &slv_qhs_cpr_mmcx, 1401 &slv_qhs_cpr_mx, 1402 &slv_qhs_crypto0_cfg, 1403 &slv_qhs_ddrss_cfg, 1404 &slv_qhs_display_cfg, 1405 &slv_qhs_emac_cfg, 1406 &slv_qhs_glm, 1407 &slv_qhs_gpuss_cfg, 1408 &slv_qhs_imem_cfg, 1409 &slv_qhs_ipa, 1410 &slv_qhs_mnoc_cfg, 1411 &slv_qhs_npu_cfg, 1412 &slv_qhs_pcie0_cfg, 1413 &slv_qhs_pcie1_cfg, 1414 &slv_qhs_pcie2_cfg, 1415 &slv_qhs_pcie3_cfg, 1416 &slv_qhs_pdm, 1417 &slv_qhs_pimem_cfg, 1418 &slv_qhs_prng, 1419 &slv_qhs_qdss_cfg, 1420 &slv_qhs_qspi_0, 1421 &slv_qhs_qspi_1, 1422 &slv_qhs_qupv3_east0, 1423 &slv_qhs_qupv3_east1, 1424 &slv_qhs_qupv3_west, 1425 &slv_qhs_sdc2, 1426 &slv_qhs_sdc4, 1427 &slv_qhs_security, 1428 &slv_qhs_snoc_cfg, 1429 &slv_qhs_spss_cfg, 1430 &slv_qhs_tcsr, 1431 &slv_qhs_tlmm_east, 1432 &slv_qhs_tlmm_south, 1433 &slv_qhs_tlmm_west, 1434 &slv_qhs_tsif, 1435 &slv_qhs_ufs_card_cfg, 1436 &slv_qhs_ufs_mem0_cfg, 1437 &slv_qhs_ufs_mem1_cfg, 1438 &slv_qhs_usb3_0, 1439 &slv_qhs_usb3_1, 1440 &slv_qhs_usb3_2, 1441 &slv_qhs_venus_cfg, 1442 &slv_qhs_vsense_ctrl_cfg, 1443 &slv_srvc_cnoc } 1444 }; 1445 1446 static struct qcom_icc_bcm bcm_mm1 = { 1447 .name = "MM1", 1448 .num_nodes = 7, 1449 .nodes = { &mas_qxm_camnoc_hf0_uncomp, 1450 &mas_qxm_camnoc_hf1_uncomp, 1451 &mas_qxm_camnoc_sf_uncomp, 1452 &mas_qxm_camnoc_hf0, 1453 &mas_qxm_camnoc_hf1, 1454 &mas_qxm_mdp0, 1455 &mas_qxm_mdp1 } 1456 }; 1457 1458 static struct qcom_icc_bcm bcm_qup0 = { 1459 .name = "QUP0", 1460 .num_nodes = 3, 1461 .nodes = { &mas_qup_core_0, 1462 &mas_qup_core_1, 1463 &mas_qup_core_2 } 1464 }; 1465 1466 static struct qcom_icc_bcm bcm_sh2 = { 1467 .name = "SH2", 1468 .num_nodes = 1, 1469 .nodes = { &slv_qns_gem_noc_snoc } 1470 }; 1471 1472 static struct qcom_icc_bcm bcm_mm2 = { 1473 .name = "MM2", 1474 .num_nodes = 6, 1475 .nodes = { &mas_qxm_camnoc_sf, 1476 &mas_qxm_rot, 1477 &mas_qxm_venus0, 1478 &mas_qxm_venus1, 1479 &mas_qxm_venus_arm9, 1480 &slv_qns2_mem_noc } 1481 }; 1482 1483 static struct qcom_icc_bcm bcm_sh3 = { 1484 .name = "SH3", 1485 .keepalive = true, 1486 .num_nodes = 1, 1487 .nodes = { &mas_acm_apps } 1488 }; 1489 1490 static struct qcom_icc_bcm bcm_sn0 = { 1491 .name = "SN0", 1492 .nodes = { &slv_qns_gemnoc_sf } 1493 }; 1494 1495 static struct qcom_icc_bcm bcm_sn1 = { 1496 .name = "SN1", 1497 .nodes = { &slv_qxs_imem } 1498 }; 1499 1500 static struct qcom_icc_bcm bcm_sn2 = { 1501 .name = "SN2", 1502 .keepalive = true, 1503 .nodes = { &slv_qns_gemnoc_gc } 1504 }; 1505 1506 static struct qcom_icc_bcm bcm_co2 = { 1507 .name = "CO2", 1508 .nodes = { &mas_qnm_npu } 1509 }; 1510 1511 static struct qcom_icc_bcm bcm_sn3 = { 1512 .name = "SN3", 1513 .keepalive = true, 1514 .nodes = { &slv_srvc_aggre1_noc, 1515 &slv_qns_cnoc } 1516 }; 1517 1518 static struct qcom_icc_bcm bcm_sn4 = { 1519 .name = "SN4", 1520 .nodes = { &slv_qxs_pimem } 1521 }; 1522 1523 static struct qcom_icc_bcm bcm_sn8 = { 1524 .name = "SN8", 1525 .num_nodes = 4, 1526 .nodes = { &slv_xs_pcie_0, 1527 &slv_xs_pcie_1, 1528 &slv_xs_pcie_2, 1529 &slv_xs_pcie_3 } 1530 }; 1531 1532 static struct qcom_icc_bcm bcm_sn9 = { 1533 .name = "SN9", 1534 .num_nodes = 1, 1535 .nodes = { &mas_qnm_aggre1_noc } 1536 }; 1537 1538 static struct qcom_icc_bcm bcm_sn11 = { 1539 .name = "SN11", 1540 .num_nodes = 1, 1541 .nodes = { &mas_qnm_aggre2_noc } 1542 }; 1543 1544 static struct qcom_icc_bcm bcm_sn14 = { 1545 .name = "SN14", 1546 .num_nodes = 1, 1547 .nodes = { &slv_qns_pcie_mem_noc } 1548 }; 1549 1550 static struct qcom_icc_bcm bcm_sn15 = { 1551 .name = "SN15", 1552 .keepalive = true, 1553 .num_nodes = 1, 1554 .nodes = { &mas_qnm_gemnoc } 1555 }; 1556 1557 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1558 &bcm_sn3, 1559 &bcm_ce0, 1560 }; 1561 1562 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1563 &bcm_sn14, 1564 &bcm_ce0, 1565 }; 1566 1567 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1568 &bcm_mm1, 1569 }; 1570 1571 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1572 &bcm_co0, 1573 &bcm_co2, 1574 }; 1575 1576 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1577 &bcm_cn0, 1578 }; 1579 1580 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1581 &bcm_sh0, 1582 &bcm_sh2, 1583 &bcm_sh3, 1584 }; 1585 1586 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1587 &bcm_mc0, 1588 &bcm_acv, 1589 }; 1590 1591 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1592 &bcm_mm0, 1593 &bcm_mm1, 1594 &bcm_mm2, 1595 }; 1596 1597 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1598 &bcm_sn0, 1599 &bcm_sn1, 1600 &bcm_sn2, 1601 &bcm_sn3, 1602 &bcm_sn4, 1603 &bcm_sn8, 1604 &bcm_sn9, 1605 &bcm_sn11, 1606 &bcm_sn15, 1607 }; 1608 1609 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1610 [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg, 1611 [MASTER_UFS_CARD] = &mas_xm_ufs_card, 1612 [MASTER_UFS_GEN4] = &mas_xm_ufs_g4, 1613 [MASTER_UFS_MEM] = &mas_xm_ufs_mem, 1614 [MASTER_USB3] = &mas_xm_usb3_0, 1615 [MASTER_USB3_1] = &mas_xm_usb3_1, 1616 [MASTER_USB3_2] = &mas_xm_usb3_2, 1617 [A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc, 1618 [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc, 1619 }; 1620 1621 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1622 [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg, 1623 [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam, 1624 [MASTER_QSPI_0] = &mas_qhm_qspi, 1625 [MASTER_QSPI_1] = &mas_qhm_qspi1, 1626 [MASTER_QUP_0] = &mas_qhm_qup0, 1627 [MASTER_QUP_1] = &mas_qhm_qup1, 1628 [MASTER_QUP_2] = &mas_qhm_qup2, 1629 [MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb, 1630 [MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto, 1631 [MASTER_IPA] = &mas_qxm_ipa, 1632 [MASTER_EMAC] = &mas_xm_emac, 1633 [MASTER_PCIE] = &mas_xm_pcie3_0, 1634 [MASTER_PCIE_1] = &mas_xm_pcie3_1, 1635 [MASTER_PCIE_2] = &mas_xm_pcie3_2, 1636 [MASTER_PCIE_3] = &mas_xm_pcie3_3, 1637 [MASTER_QDSS_ETR] = &mas_xm_qdss_etr, 1638 [MASTER_SDCC_2] = &mas_xm_sdc2, 1639 [MASTER_SDCC_4] = &mas_xm_sdc4, 1640 [A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc, 1641 [SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc, 1642 [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc, 1643 }; 1644 1645 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1646 [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp, 1647 [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp, 1648 [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp, 1649 [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp, 1650 }; 1651 1652 static struct qcom_icc_node * const compute_noc_nodes[] = { 1653 [MASTER_NPU] = &mas_qnm_npu, 1654 [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc, 1655 }; 1656 1657 static struct qcom_icc_node * const config_noc_nodes[] = { 1658 [SNOC_CNOC_MAS] = &mas_qnm_snoc, 1659 [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg, 1660 [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg, 1661 [SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center, 1662 [SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east, 1663 [SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west, 1664 [SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south, 1665 [SLAVE_AOP] = &slv_qhs_aop, 1666 [SLAVE_AOSS] = &slv_qhs_aoss, 1667 [SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg, 1668 [SLAVE_CLK_CTL] = &slv_qhs_clk_ctl, 1669 [SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp, 1670 [SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx, 1671 [SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx, 1672 [SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx, 1673 [SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg, 1674 [SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg, 1675 [SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg, 1676 [SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg, 1677 [SLAVE_GLM] = &slv_qhs_glm, 1678 [SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg, 1679 [SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg, 1680 [SLAVE_IPA_CFG] = &slv_qhs_ipa, 1681 [SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg, 1682 [SLAVE_NPU_CFG] = &slv_qhs_npu_cfg, 1683 [SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg, 1684 [SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg, 1685 [SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg, 1686 [SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg, 1687 [SLAVE_PDM] = &slv_qhs_pdm, 1688 [SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg, 1689 [SLAVE_PRNG] = &slv_qhs_prng, 1690 [SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg, 1691 [SLAVE_QSPI_0] = &slv_qhs_qspi_0, 1692 [SLAVE_QSPI_1] = &slv_qhs_qspi_1, 1693 [SLAVE_QUP_1] = &slv_qhs_qupv3_east0, 1694 [SLAVE_QUP_2] = &slv_qhs_qupv3_east1, 1695 [SLAVE_QUP_0] = &slv_qhs_qupv3_west, 1696 [SLAVE_SDCC_2] = &slv_qhs_sdc2, 1697 [SLAVE_SDCC_4] = &slv_qhs_sdc4, 1698 [SLAVE_SECURITY] = &slv_qhs_security, 1699 [SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg, 1700 [SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg, 1701 [SLAVE_TCSR] = &slv_qhs_tcsr, 1702 [SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east, 1703 [SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south, 1704 [SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west, 1705 [SLAVE_TSIF] = &slv_qhs_tsif, 1706 [SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg, 1707 [SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg, 1708 [SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg, 1709 [SLAVE_USB3] = &slv_qhs_usb3_0, 1710 [SLAVE_USB3_1] = &slv_qhs_usb3_1, 1711 [SLAVE_USB3_2] = &slv_qhs_usb3_2, 1712 [SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg, 1713 [SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg, 1714 [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc, 1715 }; 1716 1717 static struct qcom_icc_node * const dc_noc_nodes[] = { 1718 [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc, 1719 [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc, 1720 [SLAVE_LLCC_CFG] = &slv_qhs_llcc, 1721 }; 1722 1723 static struct qcom_icc_node * const gem_noc_nodes[] = { 1724 [MASTER_AMPSS_M0] = &mas_acm_apps, 1725 [MASTER_GPU_TCU] = &mas_acm_gpu_tcu, 1726 [MASTER_SYS_TCU] = &mas_acm_sys_tcu, 1727 [MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg, 1728 [MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc, 1729 [MASTER_GRAPHICS_3D] = &mas_qnm_gpu, 1730 [MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf, 1731 [MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf, 1732 [MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie, 1733 [MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc, 1734 [MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf, 1735 [MASTER_ECC] = &mas_qxm_ecc, 1736 [SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg, 1737 [SLAVE_ECC] = &slv_qns_ecc, 1738 [SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc, 1739 [SLAVE_LLCC] = &slv_qns_llcc, 1740 [SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc, 1741 [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, 1742 }; 1743 1744 static struct qcom_icc_node * const mc_virt_nodes[] = { 1745 [MASTER_LLCC] = &mas_llcc_mc, 1746 [SLAVE_EBI_CH0] = &slv_ebi, 1747 }; 1748 1749 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1750 [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg, 1751 [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0, 1752 [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1, 1753 [MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf, 1754 [MASTER_MDP_PORT0] = &mas_qxm_mdp0, 1755 [MASTER_MDP_PORT1] = &mas_qxm_mdp1, 1756 [MASTER_ROTATOR] = &mas_qxm_rot, 1757 [MASTER_VIDEO_P0] = &mas_qxm_venus0, 1758 [MASTER_VIDEO_P1] = &mas_qxm_venus1, 1759 [MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9, 1760 [SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc, 1761 [SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf, 1762 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, 1763 }; 1764 1765 static struct qcom_icc_node * const system_noc_nodes[] = { 1766 [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg, 1767 [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc, 1768 [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc, 1769 [MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc, 1770 [MASTER_PIMEM] = &mas_qxm_pimem, 1771 [MASTER_GIC] = &mas_xm_gic, 1772 [SLAVE_APPSS] = &slv_qhs_apss, 1773 [SNOC_CNOC_SLV] = &slv_qns_cnoc, 1774 [SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc, 1775 [SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf, 1776 [SLAVE_OCIMEM] = &slv_qxs_imem, 1777 [SLAVE_PIMEM] = &slv_qxs_pimem, 1778 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc, 1779 [SLAVE_QDSS_STM] = &slv_xs_qdss_stm, 1780 [SLAVE_TCU] = &slv_xs_sys_tcu_cfg, 1781 }; 1782 1783 static const struct qcom_icc_desc sc8180x_aggre1_noc = { 1784 .nodes = aggre1_noc_nodes, 1785 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1786 .bcms = aggre1_noc_bcms, 1787 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1788 }; 1789 1790 static const struct qcom_icc_desc sc8180x_aggre2_noc = { 1791 .nodes = aggre2_noc_nodes, 1792 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1793 .bcms = aggre2_noc_bcms, 1794 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1795 }; 1796 1797 static const struct qcom_icc_desc sc8180x_camnoc_virt = { 1798 .nodes = camnoc_virt_nodes, 1799 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1800 .bcms = camnoc_virt_bcms, 1801 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1802 }; 1803 1804 static const struct qcom_icc_desc sc8180x_compute_noc = { 1805 .nodes = compute_noc_nodes, 1806 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1807 .bcms = compute_noc_bcms, 1808 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1809 }; 1810 1811 static const struct qcom_icc_desc sc8180x_config_noc = { 1812 .nodes = config_noc_nodes, 1813 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1814 .bcms = config_noc_bcms, 1815 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1816 }; 1817 1818 static const struct qcom_icc_desc sc8180x_dc_noc = { 1819 .nodes = dc_noc_nodes, 1820 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1821 }; 1822 1823 static const struct qcom_icc_desc sc8180x_gem_noc = { 1824 .nodes = gem_noc_nodes, 1825 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1826 .bcms = gem_noc_bcms, 1827 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1828 }; 1829 1830 static const struct qcom_icc_desc sc8180x_mc_virt = { 1831 .nodes = mc_virt_nodes, 1832 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1833 .bcms = mc_virt_bcms, 1834 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1835 }; 1836 1837 static const struct qcom_icc_desc sc8180x_mmss_noc = { 1838 .nodes = mmss_noc_nodes, 1839 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1840 .bcms = mmss_noc_bcms, 1841 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1842 }; 1843 1844 static const struct qcom_icc_desc sc8180x_system_noc = { 1845 .nodes = system_noc_nodes, 1846 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1847 .bcms = system_noc_bcms, 1848 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1849 }; 1850 1851 static struct qcom_icc_bcm * const qup_virt_bcms[] = { 1852 &bcm_qup0, 1853 }; 1854 1855 static struct qcom_icc_node * const qup_virt_nodes[] = { 1856 [MASTER_QUP_CORE_0] = &mas_qup_core_0, 1857 [MASTER_QUP_CORE_1] = &mas_qup_core_1, 1858 [MASTER_QUP_CORE_2] = &mas_qup_core_2, 1859 [SLAVE_QUP_CORE_0] = &slv_qup_core_0, 1860 [SLAVE_QUP_CORE_1] = &slv_qup_core_1, 1861 [SLAVE_QUP_CORE_2] = &slv_qup_core_2, 1862 }; 1863 1864 static const struct qcom_icc_desc sc8180x_qup_virt = { 1865 .nodes = qup_virt_nodes, 1866 .num_nodes = ARRAY_SIZE(qup_virt_nodes), 1867 .bcms = qup_virt_bcms, 1868 .num_bcms = ARRAY_SIZE(qup_virt_bcms), 1869 }; 1870 1871 static const struct of_device_id qnoc_of_match[] = { 1872 { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc }, 1873 { .compatible = "qcom,sc8180x-aggre2-noc", .data = &sc8180x_aggre2_noc }, 1874 { .compatible = "qcom,sc8180x-camnoc-virt", .data = &sc8180x_camnoc_virt }, 1875 { .compatible = "qcom,sc8180x-compute-noc", .data = &sc8180x_compute_noc, }, 1876 { .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc }, 1877 { .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc }, 1878 { .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc }, 1879 { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt }, 1880 { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc }, 1881 { .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt }, 1882 { .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc }, 1883 { } 1884 }; 1885 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1886 1887 static struct platform_driver qnoc_driver = { 1888 .probe = qcom_icc_rpmh_probe, 1889 .remove = qcom_icc_rpmh_remove, 1890 .driver = { 1891 .name = "qnoc-sc8180x", 1892 .of_match_table = qnoc_of_match, 1893 .sync_state = icc_sync_state, 1894 }, 1895 }; 1896 module_platform_driver(qnoc_driver); 1897 1898 MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver"); 1899 MODULE_LICENSE("GPL v2"); 1900