1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver 4 * 5 * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com> 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 17 #include <dt-bindings/interconnect/qcom,msm8996.h> 18 19 #include "icc-rpm.h" 20 #include "msm8996.h" 21 22 static const char * const mm_intf_clocks[] = { 23 "iface" 24 }; 25 26 static const char * const a0noc_intf_clocks[] = { 27 "aggre0_snoc_axi", 28 "aggre0_cnoc_ahb", 29 "aggre0_noc_mpu_cfg" 30 }; 31 32 static const char * const a2noc_intf_clocks[] = { 33 "aggre2_ufs_axi", 34 "ufs_axi" 35 }; 36 37 static const u16 mas_a0noc_common_links[] = { 38 MSM8996_SLAVE_A0NOC_SNOC 39 }; 40 41 static struct qcom_icc_node mas_pcie_0 = { 42 .name = "mas_pcie_0", 43 .id = MSM8996_MASTER_PCIE_0, 44 .buswidth = 8, 45 .mas_rpm_id = 65, 46 .slv_rpm_id = -1, 47 .qos.ap_owned = true, 48 .qos.qos_mode = NOC_QOS_MODE_FIXED, 49 .qos.areq_prio = 1, 50 .qos.prio_level = 1, 51 .qos.qos_port = 0, 52 .num_links = ARRAY_SIZE(mas_a0noc_common_links), 53 .links = mas_a0noc_common_links 54 }; 55 56 static struct qcom_icc_node mas_pcie_1 = { 57 .name = "mas_pcie_1", 58 .id = MSM8996_MASTER_PCIE_1, 59 .buswidth = 8, 60 .mas_rpm_id = 66, 61 .slv_rpm_id = -1, 62 .qos.ap_owned = true, 63 .qos.qos_mode = NOC_QOS_MODE_FIXED, 64 .qos.areq_prio = 1, 65 .qos.prio_level = 1, 66 .qos.qos_port = 1, 67 .num_links = ARRAY_SIZE(mas_a0noc_common_links), 68 .links = mas_a0noc_common_links 69 }; 70 71 static struct qcom_icc_node mas_pcie_2 = { 72 .name = "mas_pcie_2", 73 .id = MSM8996_MASTER_PCIE_2, 74 .buswidth = 8, 75 .mas_rpm_id = 119, 76 .slv_rpm_id = -1, 77 .qos.ap_owned = true, 78 .qos.qos_mode = NOC_QOS_MODE_FIXED, 79 .qos.areq_prio = 1, 80 .qos.prio_level = 1, 81 .qos.qos_port = 2, 82 .num_links = ARRAY_SIZE(mas_a0noc_common_links), 83 .links = mas_a0noc_common_links 84 }; 85 86 static const u16 mas_a1noc_common_links[] = { 87 MSM8996_SLAVE_A1NOC_SNOC 88 }; 89 90 static struct qcom_icc_node mas_cnoc_a1noc = { 91 .name = "mas_cnoc_a1noc", 92 .id = MSM8996_MASTER_CNOC_A1NOC, 93 .buswidth = 8, 94 .mas_rpm_id = 116, 95 .slv_rpm_id = -1, 96 .qos.ap_owned = true, 97 .qos.qos_mode = NOC_QOS_MODE_INVALID, 98 .num_links = ARRAY_SIZE(mas_a1noc_common_links), 99 .links = mas_a1noc_common_links 100 }; 101 102 static struct qcom_icc_node mas_crypto_c0 = { 103 .name = "mas_crypto_c0", 104 .id = MSM8996_MASTER_CRYPTO_CORE0, 105 .buswidth = 8, 106 .mas_rpm_id = 23, 107 .slv_rpm_id = -1, 108 .qos.ap_owned = true, 109 .qos.qos_mode = NOC_QOS_MODE_FIXED, 110 .qos.areq_prio = 1, 111 .qos.prio_level = 1, 112 .qos.qos_port = 0, 113 .num_links = ARRAY_SIZE(mas_a1noc_common_links), 114 .links = mas_a1noc_common_links 115 }; 116 117 static struct qcom_icc_node mas_pnoc_a1noc = { 118 .name = "mas_pnoc_a1noc", 119 .id = MSM8996_MASTER_PNOC_A1NOC, 120 .buswidth = 8, 121 .mas_rpm_id = 117, 122 .slv_rpm_id = -1, 123 .qos.ap_owned = false, 124 .qos.qos_mode = NOC_QOS_MODE_FIXED, 125 .qos.areq_prio = 0, 126 .qos.prio_level = 0, 127 .qos.qos_port = 1, 128 .num_links = ARRAY_SIZE(mas_a1noc_common_links), 129 .links = mas_a1noc_common_links 130 }; 131 132 static const u16 mas_a2noc_common_links[] = { 133 MSM8996_SLAVE_A2NOC_SNOC 134 }; 135 136 static struct qcom_icc_node mas_usb3 = { 137 .name = "mas_usb3", 138 .id = MSM8996_MASTER_USB3, 139 .buswidth = 8, 140 .mas_rpm_id = 32, 141 .slv_rpm_id = -1, 142 .qos.ap_owned = true, 143 .qos.qos_mode = NOC_QOS_MODE_FIXED, 144 .qos.areq_prio = 1, 145 .qos.prio_level = 1, 146 .qos.qos_port = 3, 147 .num_links = ARRAY_SIZE(mas_a2noc_common_links), 148 .links = mas_a2noc_common_links 149 }; 150 151 static struct qcom_icc_node mas_ipa = { 152 .name = "mas_ipa", 153 .id = MSM8996_MASTER_IPA, 154 .buswidth = 8, 155 .mas_rpm_id = 59, 156 .slv_rpm_id = -1, 157 .qos.ap_owned = true, 158 .qos.qos_mode = NOC_QOS_MODE_FIXED, 159 .qos.areq_prio = 0, 160 .qos.prio_level = 0, 161 .qos.qos_port = -1, 162 .num_links = ARRAY_SIZE(mas_a2noc_common_links), 163 .links = mas_a2noc_common_links 164 }; 165 166 static struct qcom_icc_node mas_ufs = { 167 .name = "mas_ufs", 168 .id = MSM8996_MASTER_UFS, 169 .buswidth = 8, 170 .mas_rpm_id = 68, 171 .slv_rpm_id = -1, 172 .qos.ap_owned = true, 173 .qos.qos_mode = NOC_QOS_MODE_FIXED, 174 .qos.areq_prio = 1, 175 .qos.prio_level = 1, 176 .qos.qos_port = 2, 177 .num_links = ARRAY_SIZE(mas_a2noc_common_links), 178 .links = mas_a2noc_common_links 179 }; 180 181 static const u16 mas_apps_proc_links[] = { 182 MSM8996_SLAVE_BIMC_SNOC_1, 183 MSM8996_SLAVE_EBI_CH0, 184 MSM8996_SLAVE_BIMC_SNOC_0 185 }; 186 187 static struct qcom_icc_node mas_apps_proc = { 188 .name = "mas_apps_proc", 189 .id = MSM8996_MASTER_AMPSS_M0, 190 .buswidth = 8, 191 .mas_rpm_id = 0, 192 .slv_rpm_id = -1, 193 .qos.ap_owned = true, 194 .qos.qos_mode = NOC_QOS_MODE_FIXED, 195 .qos.areq_prio = 0, 196 .qos.prio_level = 0, 197 .qos.qos_port = 0, 198 .num_links = ARRAY_SIZE(mas_apps_proc_links), 199 .links = mas_apps_proc_links 200 }; 201 202 static const u16 mas_oxili_common_links[] = { 203 MSM8996_SLAVE_BIMC_SNOC_1, 204 MSM8996_SLAVE_HMSS_L3, 205 MSM8996_SLAVE_EBI_CH0, 206 MSM8996_SLAVE_BIMC_SNOC_0 207 }; 208 209 static struct qcom_icc_node mas_oxili = { 210 .name = "mas_oxili", 211 .id = MSM8996_MASTER_GRAPHICS_3D, 212 .buswidth = 8, 213 .mas_rpm_id = 6, 214 .slv_rpm_id = -1, 215 .qos.ap_owned = true, 216 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 217 .qos.areq_prio = 0, 218 .qos.prio_level = 0, 219 .qos.qos_port = 1, 220 .num_links = ARRAY_SIZE(mas_oxili_common_links), 221 .links = mas_oxili_common_links 222 }; 223 224 static struct qcom_icc_node mas_mnoc_bimc = { 225 .name = "mas_mnoc_bimc", 226 .id = MSM8996_MASTER_MNOC_BIMC, 227 .buswidth = 8, 228 .mas_rpm_id = 2, 229 .slv_rpm_id = -1, 230 .qos.ap_owned = true, 231 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 232 .qos.areq_prio = 0, 233 .qos.prio_level = 0, 234 .qos.qos_port = 2, 235 .num_links = ARRAY_SIZE(mas_oxili_common_links), 236 .links = mas_oxili_common_links 237 }; 238 239 static const u16 mas_snoc_bimc_links[] = { 240 MSM8996_SLAVE_HMSS_L3, 241 MSM8996_SLAVE_EBI_CH0 242 }; 243 244 static struct qcom_icc_node mas_snoc_bimc = { 245 .name = "mas_snoc_bimc", 246 .id = MSM8996_MASTER_SNOC_BIMC, 247 .buswidth = 8, 248 .mas_rpm_id = 3, 249 .slv_rpm_id = -1, 250 .qos.ap_owned = false, 251 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 252 .qos.areq_prio = 0, 253 .qos.prio_level = 0, 254 .qos.qos_port = -1, 255 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 256 .links = mas_snoc_bimc_links 257 }; 258 259 static const u16 mas_snoc_cnoc_links[] = { 260 MSM8996_SLAVE_CLK_CTL, 261 MSM8996_SLAVE_RBCPR_CX, 262 MSM8996_SLAVE_A2NOC_SMMU_CFG, 263 MSM8996_SLAVE_A0NOC_MPU_CFG, 264 MSM8996_SLAVE_MESSAGE_RAM, 265 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 266 MSM8996_SLAVE_PCIE_0_CFG, 267 MSM8996_SLAVE_TLMM, 268 MSM8996_SLAVE_MPM, 269 MSM8996_SLAVE_A0NOC_SMMU_CFG, 270 MSM8996_SLAVE_EBI1_PHY_CFG, 271 MSM8996_SLAVE_BIMC_CFG, 272 MSM8996_SLAVE_PIMEM_CFG, 273 MSM8996_SLAVE_RBCPR_MX, 274 MSM8996_SLAVE_PRNG, 275 MSM8996_SLAVE_PCIE20_AHB2PHY, 276 MSM8996_SLAVE_A2NOC_MPU_CFG, 277 MSM8996_SLAVE_QDSS_CFG, 278 MSM8996_SLAVE_A2NOC_CFG, 279 MSM8996_SLAVE_A0NOC_CFG, 280 MSM8996_SLAVE_UFS_CFG, 281 MSM8996_SLAVE_CRYPTO_0_CFG, 282 MSM8996_SLAVE_PCIE_1_CFG, 283 MSM8996_SLAVE_SNOC_CFG, 284 MSM8996_SLAVE_SNOC_MPU_CFG, 285 MSM8996_SLAVE_A1NOC_MPU_CFG, 286 MSM8996_SLAVE_A1NOC_SMMU_CFG, 287 MSM8996_SLAVE_PCIE_2_CFG, 288 MSM8996_SLAVE_CNOC_MNOC_CFG, 289 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 290 MSM8996_SLAVE_PMIC_ARB, 291 MSM8996_SLAVE_IMEM_CFG, 292 MSM8996_SLAVE_A1NOC_CFG, 293 MSM8996_SLAVE_SSC_CFG, 294 MSM8996_SLAVE_TCSR, 295 MSM8996_SLAVE_LPASS_SMMU_CFG, 296 MSM8996_SLAVE_DCC_CFG 297 }; 298 299 static struct qcom_icc_node mas_snoc_cnoc = { 300 .name = "mas_snoc_cnoc", 301 .id = MSM8996_MASTER_SNOC_CNOC, 302 .buswidth = 8, 303 .mas_rpm_id = 52, 304 .slv_rpm_id = -1, 305 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 306 .links = mas_snoc_cnoc_links 307 }; 308 309 static const u16 mas_qdss_dap_links[] = { 310 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 311 MSM8996_SLAVE_RBCPR_CX, 312 MSM8996_SLAVE_A2NOC_SMMU_CFG, 313 MSM8996_SLAVE_A0NOC_MPU_CFG, 314 MSM8996_SLAVE_MESSAGE_RAM, 315 MSM8996_SLAVE_PCIE_0_CFG, 316 MSM8996_SLAVE_TLMM, 317 MSM8996_SLAVE_MPM, 318 MSM8996_SLAVE_A0NOC_SMMU_CFG, 319 MSM8996_SLAVE_EBI1_PHY_CFG, 320 MSM8996_SLAVE_BIMC_CFG, 321 MSM8996_SLAVE_PIMEM_CFG, 322 MSM8996_SLAVE_RBCPR_MX, 323 MSM8996_SLAVE_CLK_CTL, 324 MSM8996_SLAVE_PRNG, 325 MSM8996_SLAVE_PCIE20_AHB2PHY, 326 MSM8996_SLAVE_A2NOC_MPU_CFG, 327 MSM8996_SLAVE_QDSS_CFG, 328 MSM8996_SLAVE_A2NOC_CFG, 329 MSM8996_SLAVE_A0NOC_CFG, 330 MSM8996_SLAVE_UFS_CFG, 331 MSM8996_SLAVE_CRYPTO_0_CFG, 332 MSM8996_SLAVE_CNOC_A1NOC, 333 MSM8996_SLAVE_PCIE_1_CFG, 334 MSM8996_SLAVE_SNOC_CFG, 335 MSM8996_SLAVE_SNOC_MPU_CFG, 336 MSM8996_SLAVE_A1NOC_MPU_CFG, 337 MSM8996_SLAVE_A1NOC_SMMU_CFG, 338 MSM8996_SLAVE_PCIE_2_CFG, 339 MSM8996_SLAVE_CNOC_MNOC_CFG, 340 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 341 MSM8996_SLAVE_PMIC_ARB, 342 MSM8996_SLAVE_IMEM_CFG, 343 MSM8996_SLAVE_A1NOC_CFG, 344 MSM8996_SLAVE_SSC_CFG, 345 MSM8996_SLAVE_TCSR, 346 MSM8996_SLAVE_LPASS_SMMU_CFG, 347 MSM8996_SLAVE_DCC_CFG 348 }; 349 350 static struct qcom_icc_node mas_qdss_dap = { 351 .name = "mas_qdss_dap", 352 .id = MSM8996_MASTER_QDSS_DAP, 353 .buswidth = 8, 354 .mas_rpm_id = 49, 355 .slv_rpm_id = -1, 356 .qos.ap_owned = true, 357 .qos.qos_mode = NOC_QOS_MODE_INVALID, 358 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 359 .links = mas_qdss_dap_links 360 }; 361 362 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { 363 MSM8996_SLAVE_MMAGIC_CFG, 364 MSM8996_SLAVE_DSA_MPU_CFG, 365 MSM8996_SLAVE_MMSS_CLK_CFG, 366 MSM8996_SLAVE_CAMERA_THROTTLE_CFG, 367 MSM8996_SLAVE_VENUS_CFG, 368 MSM8996_SLAVE_SMMU_VFE_CFG, 369 MSM8996_SLAVE_MISC_CFG, 370 MSM8996_SLAVE_SMMU_CPP_CFG, 371 MSM8996_SLAVE_GRAPHICS_3D_CFG, 372 MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, 373 MSM8996_SLAVE_VENUS_THROTTLE_CFG, 374 MSM8996_SLAVE_CAMERA_CFG, 375 MSM8996_SLAVE_DISPLAY_CFG, 376 MSM8996_SLAVE_CPR_CFG, 377 MSM8996_SLAVE_SMMU_ROTATOR_CFG, 378 MSM8996_SLAVE_DSA_CFG, 379 MSM8996_SLAVE_SMMU_VENUS_CFG, 380 MSM8996_SLAVE_VMEM_CFG, 381 MSM8996_SLAVE_SMMU_JPEG_CFG, 382 MSM8996_SLAVE_SMMU_MDP_CFG, 383 MSM8996_SLAVE_MNOC_MPU_CFG 384 }; 385 386 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { 387 .name = "mas_cnoc_mnoc_mmss_cfg", 388 .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG, 389 .buswidth = 8, 390 .mas_rpm_id = 4, 391 .slv_rpm_id = -1, 392 .qos.ap_owned = true, 393 .qos.qos_mode = NOC_QOS_MODE_INVALID, 394 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), 395 .links = mas_cnoc_mnoc_mmss_cfg_links 396 }; 397 398 static const u16 mas_cnoc_mnoc_cfg_links[] = { 399 MSM8996_SLAVE_SERVICE_MNOC 400 }; 401 402 static struct qcom_icc_node mas_cnoc_mnoc_cfg = { 403 .name = "mas_cnoc_mnoc_cfg", 404 .id = MSM8996_MASTER_CNOC_MNOC_CFG, 405 .buswidth = 8, 406 .mas_rpm_id = 5, 407 .slv_rpm_id = -1, 408 .qos.ap_owned = true, 409 .qos.qos_mode = NOC_QOS_MODE_INVALID, 410 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), 411 .links = mas_cnoc_mnoc_cfg_links 412 }; 413 414 static const u16 mas_mnoc_bimc_common_links[] = { 415 MSM8996_SLAVE_MNOC_BIMC 416 }; 417 418 static struct qcom_icc_node mas_cpp = { 419 .name = "mas_cpp", 420 .id = MSM8996_MASTER_CPP, 421 .buswidth = 32, 422 .mas_rpm_id = 115, 423 .slv_rpm_id = -1, 424 .qos.ap_owned = true, 425 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 426 .qos.areq_prio = 0, 427 .qos.prio_level = 0, 428 .qos.qos_port = 5, 429 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 430 .links = mas_mnoc_bimc_common_links 431 }; 432 433 static struct qcom_icc_node mas_jpeg = { 434 .name = "mas_jpeg", 435 .id = MSM8996_MASTER_JPEG, 436 .buswidth = 32, 437 .mas_rpm_id = 7, 438 .slv_rpm_id = -1, 439 .qos.ap_owned = true, 440 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 441 .qos.areq_prio = 0, 442 .qos.prio_level = 0, 443 .qos.qos_port = 7, 444 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 445 .links = mas_mnoc_bimc_common_links 446 }; 447 448 static struct qcom_icc_node mas_mdp_p0 = { 449 .name = "mas_mdp_p0", 450 .id = MSM8996_MASTER_MDP_PORT0, 451 .buswidth = 32, 452 .mas_rpm_id = 8, 453 .slv_rpm_id = -1, 454 .qos.ap_owned = true, 455 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 456 .qos.areq_prio = 0, 457 .qos.prio_level = 0, 458 .qos.qos_port = 1, 459 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 460 .links = mas_mnoc_bimc_common_links 461 }; 462 463 static struct qcom_icc_node mas_mdp_p1 = { 464 .name = "mas_mdp_p1", 465 .id = MSM8996_MASTER_MDP_PORT1, 466 .buswidth = 32, 467 .mas_rpm_id = 61, 468 .slv_rpm_id = -1, 469 .qos.ap_owned = true, 470 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 471 .qos.areq_prio = 0, 472 .qos.prio_level = 0, 473 .qos.qos_port = 2, 474 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 475 .links = mas_mnoc_bimc_common_links 476 }; 477 478 static struct qcom_icc_node mas_rotator = { 479 .name = "mas_rotator", 480 .id = MSM8996_MASTER_ROTATOR, 481 .buswidth = 32, 482 .mas_rpm_id = 120, 483 .slv_rpm_id = -1, 484 .qos.ap_owned = true, 485 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 486 .qos.areq_prio = 0, 487 .qos.prio_level = 0, 488 .qos.qos_port = 0, 489 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 490 .links = mas_mnoc_bimc_common_links 491 }; 492 493 static struct qcom_icc_node mas_venus = { 494 .name = "mas_venus", 495 .id = MSM8996_MASTER_VIDEO_P0, 496 .buswidth = 32, 497 .mas_rpm_id = 9, 498 .slv_rpm_id = -1, 499 .qos.ap_owned = true, 500 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 501 .qos.areq_prio = 0, 502 .qos.prio_level = 0, 503 .qos.qos_port = 3, 504 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 505 .links = mas_mnoc_bimc_common_links 506 }; 507 508 static struct qcom_icc_node mas_vfe = { 509 .name = "mas_vfe", 510 .id = MSM8996_MASTER_VFE, 511 .buswidth = 32, 512 .mas_rpm_id = 11, 513 .slv_rpm_id = -1, 514 .qos.ap_owned = true, 515 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 516 .qos.areq_prio = 0, 517 .qos.prio_level = 0, 518 .qos.qos_port = 6, 519 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 520 .links = mas_mnoc_bimc_common_links 521 }; 522 523 static const u16 mas_vmem_common_links[] = { 524 MSM8996_SLAVE_VMEM 525 }; 526 527 static struct qcom_icc_node mas_snoc_vmem = { 528 .name = "mas_snoc_vmem", 529 .id = MSM8996_MASTER_SNOC_VMEM, 530 .buswidth = 32, 531 .mas_rpm_id = 114, 532 .slv_rpm_id = -1, 533 .qos.ap_owned = true, 534 .qos.qos_mode = NOC_QOS_MODE_INVALID, 535 .num_links = ARRAY_SIZE(mas_vmem_common_links), 536 .links = mas_vmem_common_links 537 }; 538 539 static struct qcom_icc_node mas_venus_vmem = { 540 .name = "mas_venus_vmem", 541 .id = MSM8996_MASTER_VIDEO_P0_OCMEM, 542 .buswidth = 32, 543 .mas_rpm_id = 121, 544 .slv_rpm_id = -1, 545 .qos.ap_owned = true, 546 .qos.qos_mode = NOC_QOS_MODE_INVALID, 547 .num_links = ARRAY_SIZE(mas_vmem_common_links), 548 .links = mas_vmem_common_links 549 }; 550 551 static const u16 mas_snoc_pnoc_links[] = { 552 MSM8996_SLAVE_BLSP_1, 553 MSM8996_SLAVE_BLSP_2, 554 MSM8996_SLAVE_SDCC_1, 555 MSM8996_SLAVE_SDCC_2, 556 MSM8996_SLAVE_SDCC_4, 557 MSM8996_SLAVE_TSIF, 558 MSM8996_SLAVE_PDM, 559 MSM8996_SLAVE_AHB2PHY 560 }; 561 562 static struct qcom_icc_node mas_snoc_pnoc = { 563 .name = "mas_snoc_pnoc", 564 .id = MSM8996_MASTER_SNOC_PNOC, 565 .buswidth = 8, 566 .mas_rpm_id = 44, 567 .slv_rpm_id = -1, 568 .num_links = ARRAY_SIZE(mas_snoc_pnoc_links), 569 .links = mas_snoc_pnoc_links 570 }; 571 572 static const u16 mas_pnoc_a1noc_common_links[] = { 573 MSM8996_SLAVE_PNOC_A1NOC 574 }; 575 576 static struct qcom_icc_node mas_sdcc_1 = { 577 .name = "mas_sdcc_1", 578 .id = MSM8996_MASTER_SDCC_1, 579 .buswidth = 8, 580 .mas_rpm_id = 33, 581 .slv_rpm_id = -1, 582 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 583 .links = mas_pnoc_a1noc_common_links 584 }; 585 586 static struct qcom_icc_node mas_sdcc_2 = { 587 .name = "mas_sdcc_2", 588 .id = MSM8996_MASTER_SDCC_2, 589 .buswidth = 8, 590 .mas_rpm_id = 35, 591 .slv_rpm_id = -1, 592 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 593 .links = mas_pnoc_a1noc_common_links 594 }; 595 596 static struct qcom_icc_node mas_sdcc_4 = { 597 .name = "mas_sdcc_4", 598 .id = MSM8996_MASTER_SDCC_4, 599 .buswidth = 8, 600 .mas_rpm_id = 36, 601 .slv_rpm_id = -1, 602 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 603 .links = mas_pnoc_a1noc_common_links 604 }; 605 606 static struct qcom_icc_node mas_usb_hs = { 607 .name = "mas_usb_hs", 608 .id = MSM8996_MASTER_USB_HS, 609 .buswidth = 8, 610 .mas_rpm_id = 42, 611 .slv_rpm_id = -1, 612 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 613 .links = mas_pnoc_a1noc_common_links 614 }; 615 616 static struct qcom_icc_node mas_blsp_1 = { 617 .name = "mas_blsp_1", 618 .id = MSM8996_MASTER_BLSP_1, 619 .buswidth = 4, 620 .mas_rpm_id = 41, 621 .slv_rpm_id = -1, 622 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 623 .links = mas_pnoc_a1noc_common_links 624 }; 625 626 static struct qcom_icc_node mas_blsp_2 = { 627 .name = "mas_blsp_2", 628 .id = MSM8996_MASTER_BLSP_2, 629 .buswidth = 4, 630 .mas_rpm_id = 39, 631 .slv_rpm_id = -1, 632 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 633 .links = mas_pnoc_a1noc_common_links 634 }; 635 636 static struct qcom_icc_node mas_tsif = { 637 .name = "mas_tsif", 638 .id = MSM8996_MASTER_TSIF, 639 .buswidth = 4, 640 .mas_rpm_id = 37, 641 .slv_rpm_id = -1, 642 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 643 .links = mas_pnoc_a1noc_common_links 644 }; 645 646 static const u16 mas_hmss_links[] = { 647 MSM8996_SLAVE_PIMEM, 648 MSM8996_SLAVE_OCIMEM, 649 MSM8996_SLAVE_SNOC_BIMC 650 }; 651 652 static struct qcom_icc_node mas_hmss = { 653 .name = "mas_hmss", 654 .id = MSM8996_MASTER_HMSS, 655 .buswidth = 8, 656 .mas_rpm_id = 118, 657 .slv_rpm_id = -1, 658 .qos.ap_owned = true, 659 .qos.qos_mode = NOC_QOS_MODE_FIXED, 660 .qos.areq_prio = 1, 661 .qos.prio_level = 1, 662 .qos.qos_port = 4, 663 .num_links = ARRAY_SIZE(mas_hmss_links), 664 .links = mas_hmss_links 665 }; 666 667 static const u16 mas_qdss_common_links[] = { 668 MSM8996_SLAVE_PIMEM, 669 MSM8996_SLAVE_USB3, 670 MSM8996_SLAVE_OCIMEM, 671 MSM8996_SLAVE_SNOC_BIMC, 672 MSM8996_SLAVE_SNOC_PNOC 673 }; 674 675 static struct qcom_icc_node mas_qdss_bam = { 676 .name = "mas_qdss_bam", 677 .id = MSM8996_MASTER_QDSS_BAM, 678 .buswidth = 16, 679 .mas_rpm_id = 19, 680 .slv_rpm_id = -1, 681 .qos.ap_owned = true, 682 .qos.qos_mode = NOC_QOS_MODE_FIXED, 683 .qos.areq_prio = 1, 684 .qos.prio_level = 1, 685 .qos.qos_port = 2, 686 .num_links = ARRAY_SIZE(mas_qdss_common_links), 687 .links = mas_qdss_common_links 688 }; 689 690 static const u16 mas_snoc_cfg_links[] = { 691 MSM8996_SLAVE_SERVICE_SNOC 692 }; 693 694 static struct qcom_icc_node mas_snoc_cfg = { 695 .name = "mas_snoc_cfg", 696 .id = MSM8996_MASTER_SNOC_CFG, 697 .buswidth = 16, 698 .mas_rpm_id = 20, 699 .slv_rpm_id = -1, 700 .qos.ap_owned = true, 701 .qos.qos_mode = NOC_QOS_MODE_INVALID, 702 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 703 .links = mas_snoc_cfg_links 704 }; 705 706 static const u16 mas_bimc_snoc_0_links[] = { 707 MSM8996_SLAVE_SNOC_VMEM, 708 MSM8996_SLAVE_USB3, 709 MSM8996_SLAVE_PIMEM, 710 MSM8996_SLAVE_LPASS, 711 MSM8996_SLAVE_APPSS, 712 MSM8996_SLAVE_SNOC_CNOC, 713 MSM8996_SLAVE_SNOC_PNOC, 714 MSM8996_SLAVE_OCIMEM, 715 MSM8996_SLAVE_QDSS_STM 716 }; 717 718 static struct qcom_icc_node mas_bimc_snoc_0 = { 719 .name = "mas_bimc_snoc_0", 720 .id = MSM8996_MASTER_BIMC_SNOC_0, 721 .buswidth = 16, 722 .mas_rpm_id = 21, 723 .slv_rpm_id = -1, 724 .qos.ap_owned = true, 725 .qos.qos_mode = NOC_QOS_MODE_INVALID, 726 .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links), 727 .links = mas_bimc_snoc_0_links 728 }; 729 730 static const u16 mas_bimc_snoc_1_links[] = { 731 MSM8996_SLAVE_PCIE_2, 732 MSM8996_SLAVE_PCIE_1, 733 MSM8996_SLAVE_PCIE_0 734 }; 735 736 static struct qcom_icc_node mas_bimc_snoc_1 = { 737 .name = "mas_bimc_snoc_1", 738 .id = MSM8996_MASTER_BIMC_SNOC_1, 739 .buswidth = 16, 740 .mas_rpm_id = 109, 741 .slv_rpm_id = -1, 742 .qos.ap_owned = true, 743 .qos.qos_mode = NOC_QOS_MODE_INVALID, 744 .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links), 745 .links = mas_bimc_snoc_1_links 746 }; 747 748 static const u16 mas_a0noc_snoc_links[] = { 749 MSM8996_SLAVE_SNOC_PNOC, 750 MSM8996_SLAVE_OCIMEM, 751 MSM8996_SLAVE_APPSS, 752 MSM8996_SLAVE_SNOC_BIMC, 753 MSM8996_SLAVE_PIMEM 754 }; 755 756 static struct qcom_icc_node mas_a0noc_snoc = { 757 .name = "mas_a0noc_snoc", 758 .id = MSM8996_MASTER_A0NOC_SNOC, 759 .buswidth = 16, 760 .mas_rpm_id = 110, 761 .slv_rpm_id = -1, 762 .qos.ap_owned = true, 763 .qos.qos_mode = NOC_QOS_MODE_INVALID, 764 .num_links = ARRAY_SIZE(mas_a0noc_snoc_links), 765 .links = mas_a0noc_snoc_links 766 }; 767 768 static const u16 mas_a1noc_snoc_links[] = { 769 MSM8996_SLAVE_SNOC_VMEM, 770 MSM8996_SLAVE_USB3, 771 MSM8996_SLAVE_PCIE_0, 772 MSM8996_SLAVE_PIMEM, 773 MSM8996_SLAVE_PCIE_2, 774 MSM8996_SLAVE_LPASS, 775 MSM8996_SLAVE_PCIE_1, 776 MSM8996_SLAVE_APPSS, 777 MSM8996_SLAVE_SNOC_BIMC, 778 MSM8996_SLAVE_SNOC_CNOC, 779 MSM8996_SLAVE_SNOC_PNOC, 780 MSM8996_SLAVE_OCIMEM, 781 MSM8996_SLAVE_QDSS_STM 782 }; 783 784 static struct qcom_icc_node mas_a1noc_snoc = { 785 .name = "mas_a1noc_snoc", 786 .id = MSM8996_MASTER_A1NOC_SNOC, 787 .buswidth = 16, 788 .mas_rpm_id = 111, 789 .slv_rpm_id = -1, 790 .num_links = ARRAY_SIZE(mas_a1noc_snoc_links), 791 .links = mas_a1noc_snoc_links 792 }; 793 794 static const u16 mas_a2noc_snoc_links[] = { 795 MSM8996_SLAVE_SNOC_VMEM, 796 MSM8996_SLAVE_USB3, 797 MSM8996_SLAVE_PCIE_1, 798 MSM8996_SLAVE_PIMEM, 799 MSM8996_SLAVE_PCIE_2, 800 MSM8996_SLAVE_QDSS_STM, 801 MSM8996_SLAVE_LPASS, 802 MSM8996_SLAVE_SNOC_BIMC, 803 MSM8996_SLAVE_SNOC_CNOC, 804 MSM8996_SLAVE_SNOC_PNOC, 805 MSM8996_SLAVE_OCIMEM, 806 MSM8996_SLAVE_PCIE_0 807 }; 808 809 static struct qcom_icc_node mas_a2noc_snoc = { 810 .name = "mas_a2noc_snoc", 811 .id = MSM8996_MASTER_A2NOC_SNOC, 812 .buswidth = 16, 813 .mas_rpm_id = 112, 814 .slv_rpm_id = -1, 815 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), 816 .links = mas_a2noc_snoc_links 817 }; 818 819 static struct qcom_icc_node mas_qdss_etr = { 820 .name = "mas_qdss_etr", 821 .id = MSM8996_MASTER_QDSS_ETR, 822 .buswidth = 16, 823 .mas_rpm_id = 31, 824 .slv_rpm_id = -1, 825 .qos.ap_owned = true, 826 .qos.qos_mode = NOC_QOS_MODE_FIXED, 827 .qos.areq_prio = 1, 828 .qos.prio_level = 1, 829 .qos.qos_port = 3, 830 .num_links = ARRAY_SIZE(mas_qdss_common_links), 831 .links = mas_qdss_common_links 832 }; 833 834 static const u16 slv_a0noc_snoc_links[] = { 835 MSM8996_MASTER_A0NOC_SNOC 836 }; 837 838 static struct qcom_icc_node slv_a0noc_snoc = { 839 .name = "slv_a0noc_snoc", 840 .id = MSM8996_SLAVE_A0NOC_SNOC, 841 .buswidth = 8, 842 .mas_rpm_id = -1, 843 .slv_rpm_id = 141, 844 .qos.ap_owned = true, 845 .qos.qos_mode = NOC_QOS_MODE_INVALID, 846 .num_links = ARRAY_SIZE(slv_a0noc_snoc_links), 847 .links = slv_a0noc_snoc_links 848 }; 849 850 static const u16 slv_a1noc_snoc_links[] = { 851 MSM8996_MASTER_A1NOC_SNOC 852 }; 853 854 static struct qcom_icc_node slv_a1noc_snoc = { 855 .name = "slv_a1noc_snoc", 856 .id = MSM8996_SLAVE_A1NOC_SNOC, 857 .buswidth = 8, 858 .mas_rpm_id = -1, 859 .slv_rpm_id = 142, 860 .num_links = ARRAY_SIZE(slv_a1noc_snoc_links), 861 .links = slv_a1noc_snoc_links 862 }; 863 864 static const u16 slv_a2noc_snoc_links[] = { 865 MSM8996_MASTER_A2NOC_SNOC 866 }; 867 868 static struct qcom_icc_node slv_a2noc_snoc = { 869 .name = "slv_a2noc_snoc", 870 .id = MSM8996_SLAVE_A2NOC_SNOC, 871 .buswidth = 8, 872 .mas_rpm_id = -1, 873 .slv_rpm_id = 143, 874 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), 875 .links = slv_a2noc_snoc_links 876 }; 877 878 static struct qcom_icc_node slv_ebi = { 879 .name = "slv_ebi", 880 .id = MSM8996_SLAVE_EBI_CH0, 881 .buswidth = 8, 882 .mas_rpm_id = -1, 883 .slv_rpm_id = 0 884 }; 885 886 static struct qcom_icc_node slv_hmss_l3 = { 887 .name = "slv_hmss_l3", 888 .id = MSM8996_SLAVE_HMSS_L3, 889 .buswidth = 8, 890 .mas_rpm_id = -1, 891 .slv_rpm_id = 160 892 }; 893 894 static const u16 slv_bimc_snoc_0_links[] = { 895 MSM8996_MASTER_BIMC_SNOC_0 896 }; 897 898 static struct qcom_icc_node slv_bimc_snoc_0 = { 899 .name = "slv_bimc_snoc_0", 900 .id = MSM8996_SLAVE_BIMC_SNOC_0, 901 .buswidth = 8, 902 .mas_rpm_id = -1, 903 .slv_rpm_id = 2, 904 .qos.ap_owned = true, 905 .qos.qos_mode = NOC_QOS_MODE_INVALID, 906 .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links), 907 .links = slv_bimc_snoc_0_links 908 }; 909 910 static const u16 slv_bimc_snoc_1_links[] = { 911 MSM8996_MASTER_BIMC_SNOC_1 912 }; 913 914 static struct qcom_icc_node slv_bimc_snoc_1 = { 915 .name = "slv_bimc_snoc_1", 916 .id = MSM8996_SLAVE_BIMC_SNOC_1, 917 .buswidth = 8, 918 .mas_rpm_id = -1, 919 .slv_rpm_id = 138, 920 .qos.ap_owned = true, 921 .qos.qos_mode = NOC_QOS_MODE_INVALID, 922 .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links), 923 .links = slv_bimc_snoc_1_links 924 }; 925 926 static const u16 slv_cnoc_a1noc_links[] = { 927 MSM8996_MASTER_CNOC_A1NOC 928 }; 929 930 static struct qcom_icc_node slv_cnoc_a1noc = { 931 .name = "slv_cnoc_a1noc", 932 .id = MSM8996_SLAVE_CNOC_A1NOC, 933 .buswidth = 4, 934 .mas_rpm_id = -1, 935 .slv_rpm_id = 75, 936 .qos.ap_owned = true, 937 .qos.qos_mode = NOC_QOS_MODE_INVALID, 938 .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links), 939 .links = slv_cnoc_a1noc_links 940 }; 941 942 static struct qcom_icc_node slv_clk_ctl = { 943 .name = "slv_clk_ctl", 944 .id = MSM8996_SLAVE_CLK_CTL, 945 .buswidth = 4, 946 .mas_rpm_id = -1, 947 .slv_rpm_id = 47 948 }; 949 950 static struct qcom_icc_node slv_tcsr = { 951 .name = "slv_tcsr", 952 .id = MSM8996_SLAVE_TCSR, 953 .buswidth = 4, 954 .mas_rpm_id = -1, 955 .slv_rpm_id = 50 956 }; 957 958 static struct qcom_icc_node slv_tlmm = { 959 .name = "slv_tlmm", 960 .id = MSM8996_SLAVE_TLMM, 961 .buswidth = 4, 962 .mas_rpm_id = -1, 963 .slv_rpm_id = 51 964 }; 965 966 static struct qcom_icc_node slv_crypto0_cfg = { 967 .name = "slv_crypto0_cfg", 968 .id = MSM8996_SLAVE_CRYPTO_0_CFG, 969 .buswidth = 4, 970 .mas_rpm_id = -1, 971 .slv_rpm_id = 52, 972 .qos.ap_owned = true, 973 .qos.qos_mode = NOC_QOS_MODE_INVALID 974 }; 975 976 static struct qcom_icc_node slv_mpm = { 977 .name = "slv_mpm", 978 .id = MSM8996_SLAVE_MPM, 979 .buswidth = 4, 980 .mas_rpm_id = -1, 981 .slv_rpm_id = 62, 982 .qos.ap_owned = true, 983 .qos.qos_mode = NOC_QOS_MODE_INVALID 984 }; 985 986 static struct qcom_icc_node slv_pimem_cfg = { 987 .name = "slv_pimem_cfg", 988 .id = MSM8996_SLAVE_PIMEM_CFG, 989 .buswidth = 4, 990 .mas_rpm_id = -1, 991 .slv_rpm_id = 167, 992 .qos.ap_owned = true, 993 .qos.qos_mode = NOC_QOS_MODE_INVALID 994 }; 995 996 static struct qcom_icc_node slv_imem_cfg = { 997 .name = "slv_imem_cfg", 998 .id = MSM8996_SLAVE_IMEM_CFG, 999 .buswidth = 4, 1000 .mas_rpm_id = -1, 1001 .slv_rpm_id = 54, 1002 .qos.ap_owned = true, 1003 .qos.qos_mode = NOC_QOS_MODE_INVALID 1004 }; 1005 1006 static struct qcom_icc_node slv_message_ram = { 1007 .name = "slv_message_ram", 1008 .id = MSM8996_SLAVE_MESSAGE_RAM, 1009 .buswidth = 4, 1010 .mas_rpm_id = -1, 1011 .slv_rpm_id = 55 1012 }; 1013 1014 static struct qcom_icc_node slv_bimc_cfg = { 1015 .name = "slv_bimc_cfg", 1016 .id = MSM8996_SLAVE_BIMC_CFG, 1017 .buswidth = 4, 1018 .mas_rpm_id = -1, 1019 .slv_rpm_id = 56, 1020 .qos.ap_owned = true, 1021 .qos.qos_mode = NOC_QOS_MODE_INVALID 1022 }; 1023 1024 static struct qcom_icc_node slv_pmic_arb = { 1025 .name = "slv_pmic_arb", 1026 .id = MSM8996_SLAVE_PMIC_ARB, 1027 .buswidth = 4, 1028 .mas_rpm_id = -1, 1029 .slv_rpm_id = 59 1030 }; 1031 1032 static struct qcom_icc_node slv_prng = { 1033 .name = "slv_prng", 1034 .id = MSM8996_SLAVE_PRNG, 1035 .buswidth = 4, 1036 .mas_rpm_id = -1, 1037 .slv_rpm_id = 127, 1038 .qos.ap_owned = true, 1039 .qos.qos_mode = NOC_QOS_MODE_INVALID 1040 }; 1041 1042 static struct qcom_icc_node slv_dcc_cfg = { 1043 .name = "slv_dcc_cfg", 1044 .id = MSM8996_SLAVE_DCC_CFG, 1045 .buswidth = 4, 1046 .mas_rpm_id = -1, 1047 .slv_rpm_id = 155, 1048 .qos.ap_owned = true, 1049 .qos.qos_mode = NOC_QOS_MODE_INVALID 1050 }; 1051 1052 static struct qcom_icc_node slv_rbcpr_mx = { 1053 .name = "slv_rbcpr_mx", 1054 .id = MSM8996_SLAVE_RBCPR_MX, 1055 .buswidth = 4, 1056 .mas_rpm_id = -1, 1057 .slv_rpm_id = 170, 1058 .qos.ap_owned = true, 1059 .qos.qos_mode = NOC_QOS_MODE_INVALID 1060 }; 1061 1062 static struct qcom_icc_node slv_qdss_cfg = { 1063 .name = "slv_qdss_cfg", 1064 .id = MSM8996_SLAVE_QDSS_CFG, 1065 .buswidth = 4, 1066 .mas_rpm_id = -1, 1067 .slv_rpm_id = 63, 1068 .qos.ap_owned = true, 1069 .qos.qos_mode = NOC_QOS_MODE_INVALID 1070 }; 1071 1072 static struct qcom_icc_node slv_rbcpr_cx = { 1073 .name = "slv_rbcpr_cx", 1074 .id = MSM8996_SLAVE_RBCPR_CX, 1075 .buswidth = 4, 1076 .mas_rpm_id = -1, 1077 .slv_rpm_id = 169, 1078 .qos.ap_owned = true, 1079 .qos.qos_mode = NOC_QOS_MODE_INVALID 1080 }; 1081 1082 static struct qcom_icc_node slv_cpu_apu_cfg = { 1083 .name = "slv_cpu_apu_cfg", 1084 .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 1085 .buswidth = 4, 1086 .mas_rpm_id = -1, 1087 .slv_rpm_id = 168, 1088 .qos.ap_owned = true, 1089 .qos.qos_mode = NOC_QOS_MODE_INVALID 1090 }; 1091 1092 static const u16 slv_cnoc_mnoc_cfg_links[] = { 1093 MSM8996_MASTER_CNOC_MNOC_CFG 1094 }; 1095 1096 static struct qcom_icc_node slv_cnoc_mnoc_cfg = { 1097 .name = "slv_cnoc_mnoc_cfg", 1098 .id = MSM8996_SLAVE_CNOC_MNOC_CFG, 1099 .buswidth = 4, 1100 .mas_rpm_id = -1, 1101 .slv_rpm_id = 66, 1102 .qos.ap_owned = true, 1103 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1104 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), 1105 .links = slv_cnoc_mnoc_cfg_links 1106 }; 1107 1108 static struct qcom_icc_node slv_snoc_cfg = { 1109 .name = "slv_snoc_cfg", 1110 .id = MSM8996_SLAVE_SNOC_CFG, 1111 .buswidth = 4, 1112 .mas_rpm_id = -1, 1113 .slv_rpm_id = 70, 1114 .qos.ap_owned = true, 1115 .qos.qos_mode = NOC_QOS_MODE_INVALID 1116 }; 1117 1118 static struct qcom_icc_node slv_snoc_mpu_cfg = { 1119 .name = "slv_snoc_mpu_cfg", 1120 .id = MSM8996_SLAVE_SNOC_MPU_CFG, 1121 .buswidth = 4, 1122 .mas_rpm_id = -1, 1123 .slv_rpm_id = 67, 1124 .qos.ap_owned = true, 1125 .qos.qos_mode = NOC_QOS_MODE_INVALID 1126 }; 1127 1128 static struct qcom_icc_node slv_ebi1_phy_cfg = { 1129 .name = "slv_ebi1_phy_cfg", 1130 .id = MSM8996_SLAVE_EBI1_PHY_CFG, 1131 .buswidth = 4, 1132 .mas_rpm_id = -1, 1133 .slv_rpm_id = 73, 1134 .qos.ap_owned = true, 1135 .qos.qos_mode = NOC_QOS_MODE_INVALID 1136 }; 1137 1138 static struct qcom_icc_node slv_a0noc_cfg = { 1139 .name = "slv_a0noc_cfg", 1140 .id = MSM8996_SLAVE_A0NOC_CFG, 1141 .buswidth = 4, 1142 .mas_rpm_id = -1, 1143 .slv_rpm_id = 144, 1144 .qos.ap_owned = true, 1145 .qos.qos_mode = NOC_QOS_MODE_INVALID 1146 }; 1147 1148 static struct qcom_icc_node slv_pcie_1_cfg = { 1149 .name = "slv_pcie_1_cfg", 1150 .id = MSM8996_SLAVE_PCIE_1_CFG, 1151 .buswidth = 4, 1152 .mas_rpm_id = -1, 1153 .slv_rpm_id = 89, 1154 .qos.ap_owned = true, 1155 .qos.qos_mode = NOC_QOS_MODE_INVALID 1156 }; 1157 1158 static struct qcom_icc_node slv_pcie_2_cfg = { 1159 .name = "slv_pcie_2_cfg", 1160 .id = MSM8996_SLAVE_PCIE_2_CFG, 1161 .buswidth = 4, 1162 .mas_rpm_id = -1, 1163 .slv_rpm_id = 165, 1164 .qos.ap_owned = true, 1165 .qos.qos_mode = NOC_QOS_MODE_INVALID 1166 }; 1167 1168 static struct qcom_icc_node slv_pcie_0_cfg = { 1169 .name = "slv_pcie_0_cfg", 1170 .id = MSM8996_SLAVE_PCIE_0_CFG, 1171 .buswidth = 4, 1172 .mas_rpm_id = -1, 1173 .slv_rpm_id = 88, 1174 .qos.ap_owned = true, 1175 .qos.qos_mode = NOC_QOS_MODE_INVALID 1176 }; 1177 1178 static struct qcom_icc_node slv_pcie20_ahb2phy = { 1179 .name = "slv_pcie20_ahb2phy", 1180 .id = MSM8996_SLAVE_PCIE20_AHB2PHY, 1181 .buswidth = 4, 1182 .mas_rpm_id = -1, 1183 .slv_rpm_id = 163, 1184 .qos.ap_owned = true, 1185 .qos.qos_mode = NOC_QOS_MODE_INVALID 1186 }; 1187 1188 static struct qcom_icc_node slv_a0noc_mpu_cfg = { 1189 .name = "slv_a0noc_mpu_cfg", 1190 .id = MSM8996_SLAVE_A0NOC_MPU_CFG, 1191 .buswidth = 4, 1192 .mas_rpm_id = -1, 1193 .slv_rpm_id = 145, 1194 .qos.ap_owned = true, 1195 .qos.qos_mode = NOC_QOS_MODE_INVALID 1196 }; 1197 1198 static struct qcom_icc_node slv_ufs_cfg = { 1199 .name = "slv_ufs_cfg", 1200 .id = MSM8996_SLAVE_UFS_CFG, 1201 .buswidth = 4, 1202 .mas_rpm_id = -1, 1203 .slv_rpm_id = 92, 1204 .qos.ap_owned = true, 1205 .qos.qos_mode = NOC_QOS_MODE_INVALID 1206 }; 1207 1208 static struct qcom_icc_node slv_a1noc_cfg = { 1209 .name = "slv_a1noc_cfg", 1210 .id = MSM8996_SLAVE_A1NOC_CFG, 1211 .buswidth = 4, 1212 .mas_rpm_id = -1, 1213 .slv_rpm_id = 147, 1214 .qos.ap_owned = true, 1215 .qos.qos_mode = NOC_QOS_MODE_INVALID 1216 }; 1217 1218 static struct qcom_icc_node slv_a1noc_mpu_cfg = { 1219 .name = "slv_a1noc_mpu_cfg", 1220 .id = MSM8996_SLAVE_A1NOC_MPU_CFG, 1221 .buswidth = 4, 1222 .mas_rpm_id = -1, 1223 .slv_rpm_id = 148, 1224 .qos.ap_owned = true, 1225 .qos.qos_mode = NOC_QOS_MODE_INVALID 1226 }; 1227 1228 static struct qcom_icc_node slv_a2noc_cfg = { 1229 .name = "slv_a2noc_cfg", 1230 .id = MSM8996_SLAVE_A2NOC_CFG, 1231 .buswidth = 4, 1232 .mas_rpm_id = -1, 1233 .slv_rpm_id = 150, 1234 .qos.ap_owned = true, 1235 .qos.qos_mode = NOC_QOS_MODE_INVALID 1236 }; 1237 1238 static struct qcom_icc_node slv_a2noc_mpu_cfg = { 1239 .name = "slv_a2noc_mpu_cfg", 1240 .id = MSM8996_SLAVE_A2NOC_MPU_CFG, 1241 .buswidth = 4, 1242 .mas_rpm_id = -1, 1243 .slv_rpm_id = 151, 1244 .qos.ap_owned = true, 1245 .qos.qos_mode = NOC_QOS_MODE_INVALID 1246 }; 1247 1248 static struct qcom_icc_node slv_ssc_cfg = { 1249 .name = "slv_ssc_cfg", 1250 .id = MSM8996_SLAVE_SSC_CFG, 1251 .buswidth = 4, 1252 .mas_rpm_id = -1, 1253 .slv_rpm_id = 177, 1254 .qos.ap_owned = true, 1255 .qos.qos_mode = NOC_QOS_MODE_INVALID 1256 }; 1257 1258 static struct qcom_icc_node slv_a0noc_smmu_cfg = { 1259 .name = "slv_a0noc_smmu_cfg", 1260 .id = MSM8996_SLAVE_A0NOC_SMMU_CFG, 1261 .buswidth = 8, 1262 .mas_rpm_id = -1, 1263 .slv_rpm_id = 146, 1264 .qos.ap_owned = true, 1265 .qos.qos_mode = NOC_QOS_MODE_INVALID 1266 }; 1267 1268 static struct qcom_icc_node slv_a1noc_smmu_cfg = { 1269 .name = "slv_a1noc_smmu_cfg", 1270 .id = MSM8996_SLAVE_A1NOC_SMMU_CFG, 1271 .buswidth = 8, 1272 .mas_rpm_id = -1, 1273 .slv_rpm_id = 149, 1274 .qos.ap_owned = true, 1275 .qos.qos_mode = NOC_QOS_MODE_INVALID 1276 }; 1277 1278 static struct qcom_icc_node slv_a2noc_smmu_cfg = { 1279 .name = "slv_a2noc_smmu_cfg", 1280 .id = MSM8996_SLAVE_A2NOC_SMMU_CFG, 1281 .buswidth = 8, 1282 .mas_rpm_id = -1, 1283 .slv_rpm_id = 152, 1284 .qos.ap_owned = true, 1285 .qos.qos_mode = NOC_QOS_MODE_INVALID 1286 }; 1287 1288 static struct qcom_icc_node slv_lpass_smmu_cfg = { 1289 .name = "slv_lpass_smmu_cfg", 1290 .id = MSM8996_SLAVE_LPASS_SMMU_CFG, 1291 .buswidth = 8, 1292 .mas_rpm_id = -1, 1293 .slv_rpm_id = 161, 1294 .qos.ap_owned = true, 1295 .qos.qos_mode = NOC_QOS_MODE_INVALID 1296 }; 1297 1298 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { 1299 MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 1300 }; 1301 1302 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { 1303 .name = "slv_cnoc_mnoc_mmss_cfg", 1304 .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 1305 .buswidth = 8, 1306 .mas_rpm_id = -1, 1307 .slv_rpm_id = 58, 1308 .qos.ap_owned = true, 1309 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1310 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), 1311 .links = slv_cnoc_mnoc_mmss_cfg_links 1312 }; 1313 1314 static struct qcom_icc_node slv_mmagic_cfg = { 1315 .name = "slv_mmagic_cfg", 1316 .id = MSM8996_SLAVE_MMAGIC_CFG, 1317 .buswidth = 8, 1318 .mas_rpm_id = -1, 1319 .slv_rpm_id = 162, 1320 .qos.ap_owned = true, 1321 .qos.qos_mode = NOC_QOS_MODE_INVALID 1322 }; 1323 1324 static struct qcom_icc_node slv_cpr_cfg = { 1325 .name = "slv_cpr_cfg", 1326 .id = MSM8996_SLAVE_CPR_CFG, 1327 .buswidth = 8, 1328 .mas_rpm_id = -1, 1329 .slv_rpm_id = 6, 1330 .qos.ap_owned = true, 1331 .qos.qos_mode = NOC_QOS_MODE_INVALID 1332 }; 1333 1334 static struct qcom_icc_node slv_misc_cfg = { 1335 .name = "slv_misc_cfg", 1336 .id = MSM8996_SLAVE_MISC_CFG, 1337 .buswidth = 8, 1338 .mas_rpm_id = -1, 1339 .slv_rpm_id = 8, 1340 .qos.ap_owned = true, 1341 .qos.qos_mode = NOC_QOS_MODE_INVALID 1342 }; 1343 1344 static struct qcom_icc_node slv_venus_throttle_cfg = { 1345 .name = "slv_venus_throttle_cfg", 1346 .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG, 1347 .buswidth = 8, 1348 .mas_rpm_id = -1, 1349 .slv_rpm_id = 178, 1350 .qos.ap_owned = true, 1351 .qos.qos_mode = NOC_QOS_MODE_INVALID 1352 }; 1353 1354 static struct qcom_icc_node slv_venus_cfg = { 1355 .name = "slv_venus_cfg", 1356 .id = MSM8996_SLAVE_VENUS_CFG, 1357 .buswidth = 8, 1358 .mas_rpm_id = -1, 1359 .slv_rpm_id = 10, 1360 .qos.ap_owned = true, 1361 .qos.qos_mode = NOC_QOS_MODE_INVALID 1362 }; 1363 1364 static struct qcom_icc_node slv_vmem_cfg = { 1365 .name = "slv_vmem_cfg", 1366 .id = MSM8996_SLAVE_VMEM_CFG, 1367 .buswidth = 8, 1368 .mas_rpm_id = -1, 1369 .slv_rpm_id = 180, 1370 .qos.ap_owned = true, 1371 .qos.qos_mode = NOC_QOS_MODE_INVALID 1372 }; 1373 1374 static struct qcom_icc_node slv_dsa_cfg = { 1375 .name = "slv_dsa_cfg", 1376 .id = MSM8996_SLAVE_DSA_CFG, 1377 .buswidth = 8, 1378 .mas_rpm_id = -1, 1379 .slv_rpm_id = 157, 1380 .qos.ap_owned = true, 1381 .qos.qos_mode = NOC_QOS_MODE_INVALID 1382 }; 1383 1384 static struct qcom_icc_node slv_mnoc_clocks_cfg = { 1385 .name = "slv_mnoc_clocks_cfg", 1386 .id = MSM8996_SLAVE_MMSS_CLK_CFG, 1387 .buswidth = 8, 1388 .mas_rpm_id = -1, 1389 .slv_rpm_id = 12, 1390 .qos.ap_owned = true, 1391 .qos.qos_mode = NOC_QOS_MODE_INVALID 1392 }; 1393 1394 static struct qcom_icc_node slv_dsa_mpu_cfg = { 1395 .name = "slv_dsa_mpu_cfg", 1396 .id = MSM8996_SLAVE_DSA_MPU_CFG, 1397 .buswidth = 8, 1398 .mas_rpm_id = -1, 1399 .slv_rpm_id = 158, 1400 .qos.ap_owned = true, 1401 .qos.qos_mode = NOC_QOS_MODE_INVALID 1402 }; 1403 1404 static struct qcom_icc_node slv_mnoc_mpu_cfg = { 1405 .name = "slv_mnoc_mpu_cfg", 1406 .id = MSM8996_SLAVE_MNOC_MPU_CFG, 1407 .buswidth = 8, 1408 .mas_rpm_id = -1, 1409 .slv_rpm_id = 14, 1410 .qos.ap_owned = true, 1411 .qos.qos_mode = NOC_QOS_MODE_INVALID 1412 }; 1413 1414 static struct qcom_icc_node slv_display_cfg = { 1415 .name = "slv_display_cfg", 1416 .id = MSM8996_SLAVE_DISPLAY_CFG, 1417 .buswidth = 8, 1418 .mas_rpm_id = -1, 1419 .slv_rpm_id = 4, 1420 .qos.ap_owned = true, 1421 .qos.qos_mode = NOC_QOS_MODE_INVALID 1422 }; 1423 1424 static struct qcom_icc_node slv_display_throttle_cfg = { 1425 .name = "slv_display_throttle_cfg", 1426 .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, 1427 .buswidth = 8, 1428 .mas_rpm_id = -1, 1429 .slv_rpm_id = 156, 1430 .qos.ap_owned = true, 1431 .qos.qos_mode = NOC_QOS_MODE_INVALID 1432 }; 1433 1434 static struct qcom_icc_node slv_camera_cfg = { 1435 .name = "slv_camera_cfg", 1436 .id = MSM8996_SLAVE_CAMERA_CFG, 1437 .buswidth = 8, 1438 .mas_rpm_id = -1, 1439 .slv_rpm_id = 3, 1440 .qos.ap_owned = true, 1441 .qos.qos_mode = NOC_QOS_MODE_INVALID 1442 }; 1443 1444 static struct qcom_icc_node slv_camera_throttle_cfg = { 1445 .name = "slv_camera_throttle_cfg", 1446 .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG, 1447 .buswidth = 8, 1448 .mas_rpm_id = -1, 1449 .slv_rpm_id = 154, 1450 .qos.ap_owned = true, 1451 .qos.qos_mode = NOC_QOS_MODE_INVALID 1452 }; 1453 1454 static struct qcom_icc_node slv_oxili_cfg = { 1455 .name = "slv_oxili_cfg", 1456 .id = MSM8996_SLAVE_GRAPHICS_3D_CFG, 1457 .buswidth = 8, 1458 .mas_rpm_id = -1, 1459 .slv_rpm_id = 11, 1460 .qos.ap_owned = true, 1461 .qos.qos_mode = NOC_QOS_MODE_INVALID 1462 }; 1463 1464 static struct qcom_icc_node slv_smmu_mdp_cfg = { 1465 .name = "slv_smmu_mdp_cfg", 1466 .id = MSM8996_SLAVE_SMMU_MDP_CFG, 1467 .buswidth = 8, 1468 .mas_rpm_id = -1, 1469 .slv_rpm_id = 173, 1470 .qos.ap_owned = true, 1471 .qos.qos_mode = NOC_QOS_MODE_INVALID 1472 }; 1473 1474 static struct qcom_icc_node slv_smmu_rot_cfg = { 1475 .name = "slv_smmu_rot_cfg", 1476 .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG, 1477 .buswidth = 8, 1478 .mas_rpm_id = -1, 1479 .slv_rpm_id = 174, 1480 .qos.ap_owned = true, 1481 .qos.qos_mode = NOC_QOS_MODE_INVALID 1482 }; 1483 1484 static struct qcom_icc_node slv_smmu_venus_cfg = { 1485 .name = "slv_smmu_venus_cfg", 1486 .id = MSM8996_SLAVE_SMMU_VENUS_CFG, 1487 .buswidth = 8, 1488 .mas_rpm_id = -1, 1489 .slv_rpm_id = 175, 1490 .qos.ap_owned = true, 1491 .qos.qos_mode = NOC_QOS_MODE_INVALID 1492 }; 1493 1494 static struct qcom_icc_node slv_smmu_cpp_cfg = { 1495 .name = "slv_smmu_cpp_cfg", 1496 .id = MSM8996_SLAVE_SMMU_CPP_CFG, 1497 .buswidth = 8, 1498 .mas_rpm_id = -1, 1499 .slv_rpm_id = 171, 1500 .qos.ap_owned = true, 1501 .qos.qos_mode = NOC_QOS_MODE_INVALID 1502 }; 1503 1504 static struct qcom_icc_node slv_smmu_jpeg_cfg = { 1505 .name = "slv_smmu_jpeg_cfg", 1506 .id = MSM8996_SLAVE_SMMU_JPEG_CFG, 1507 .buswidth = 8, 1508 .mas_rpm_id = -1, 1509 .slv_rpm_id = 172, 1510 .qos.ap_owned = true, 1511 .qos.qos_mode = NOC_QOS_MODE_INVALID 1512 }; 1513 1514 static struct qcom_icc_node slv_smmu_vfe_cfg = { 1515 .name = "slv_smmu_vfe_cfg", 1516 .id = MSM8996_SLAVE_SMMU_VFE_CFG, 1517 .buswidth = 8, 1518 .mas_rpm_id = -1, 1519 .slv_rpm_id = 176, 1520 .qos.ap_owned = true, 1521 .qos.qos_mode = NOC_QOS_MODE_INVALID 1522 }; 1523 1524 static const u16 slv_mnoc_bimc_links[] = { 1525 MSM8996_MASTER_MNOC_BIMC 1526 }; 1527 1528 static struct qcom_icc_node slv_mnoc_bimc = { 1529 .name = "slv_mnoc_bimc", 1530 .id = MSM8996_SLAVE_MNOC_BIMC, 1531 .buswidth = 32, 1532 .mas_rpm_id = -1, 1533 .slv_rpm_id = 16, 1534 .qos.ap_owned = true, 1535 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1536 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), 1537 .links = slv_mnoc_bimc_links 1538 }; 1539 1540 static struct qcom_icc_node slv_vmem = { 1541 .name = "slv_vmem", 1542 .id = MSM8996_SLAVE_VMEM, 1543 .buswidth = 32, 1544 .mas_rpm_id = -1, 1545 .slv_rpm_id = 179, 1546 .qos.ap_owned = true, 1547 .qos.qos_mode = NOC_QOS_MODE_INVALID 1548 }; 1549 1550 static struct qcom_icc_node slv_srvc_mnoc = { 1551 .name = "slv_srvc_mnoc", 1552 .id = MSM8996_SLAVE_SERVICE_MNOC, 1553 .buswidth = 8, 1554 .mas_rpm_id = -1, 1555 .slv_rpm_id = 17, 1556 .qos.ap_owned = true, 1557 .qos.qos_mode = NOC_QOS_MODE_INVALID 1558 }; 1559 1560 static const u16 slv_pnoc_a1noc_links[] = { 1561 MSM8996_MASTER_PNOC_A1NOC 1562 }; 1563 1564 static struct qcom_icc_node slv_pnoc_a1noc = { 1565 .name = "slv_pnoc_a1noc", 1566 .id = MSM8996_SLAVE_PNOC_A1NOC, 1567 .buswidth = 8, 1568 .mas_rpm_id = -1, 1569 .slv_rpm_id = 139, 1570 .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links), 1571 .links = slv_pnoc_a1noc_links 1572 }; 1573 1574 static struct qcom_icc_node slv_usb_hs = { 1575 .name = "slv_usb_hs", 1576 .id = MSM8996_SLAVE_USB_HS, 1577 .buswidth = 4, 1578 .mas_rpm_id = -1, 1579 .slv_rpm_id = 40 1580 }; 1581 1582 static struct qcom_icc_node slv_sdcc_2 = { 1583 .name = "slv_sdcc_2", 1584 .id = MSM8996_SLAVE_SDCC_2, 1585 .buswidth = 4, 1586 .mas_rpm_id = -1, 1587 .slv_rpm_id = 33 1588 }; 1589 1590 static struct qcom_icc_node slv_sdcc_4 = { 1591 .name = "slv_sdcc_4", 1592 .id = MSM8996_SLAVE_SDCC_4, 1593 .buswidth = 4, 1594 .mas_rpm_id = -1, 1595 .slv_rpm_id = 34 1596 }; 1597 1598 static struct qcom_icc_node slv_tsif = { 1599 .name = "slv_tsif", 1600 .id = MSM8996_SLAVE_TSIF, 1601 .buswidth = 4, 1602 .mas_rpm_id = -1, 1603 .slv_rpm_id = 35 1604 }; 1605 1606 static struct qcom_icc_node slv_blsp_2 = { 1607 .name = "slv_blsp_2", 1608 .id = MSM8996_SLAVE_BLSP_2, 1609 .buswidth = 4, 1610 .mas_rpm_id = -1, 1611 .slv_rpm_id = 37 1612 }; 1613 1614 static struct qcom_icc_node slv_sdcc_1 = { 1615 .name = "slv_sdcc_1", 1616 .id = MSM8996_SLAVE_SDCC_1, 1617 .buswidth = 4, 1618 .mas_rpm_id = -1, 1619 .slv_rpm_id = 31 1620 }; 1621 1622 static struct qcom_icc_node slv_blsp_1 = { 1623 .name = "slv_blsp_1", 1624 .id = MSM8996_SLAVE_BLSP_1, 1625 .buswidth = 4, 1626 .mas_rpm_id = -1, 1627 .slv_rpm_id = 39 1628 }; 1629 1630 static struct qcom_icc_node slv_pdm = { 1631 .name = "slv_pdm", 1632 .id = MSM8996_SLAVE_PDM, 1633 .buswidth = 4, 1634 .mas_rpm_id = -1, 1635 .slv_rpm_id = 41 1636 }; 1637 1638 static struct qcom_icc_node slv_ahb2phy = { 1639 .name = "slv_ahb2phy", 1640 .id = MSM8996_SLAVE_AHB2PHY, 1641 .buswidth = 4, 1642 .mas_rpm_id = -1, 1643 .slv_rpm_id = 153, 1644 .qos.ap_owned = true, 1645 .qos.qos_mode = NOC_QOS_MODE_INVALID 1646 }; 1647 1648 static struct qcom_icc_node slv_hmss = { 1649 .name = "slv_hmss", 1650 .id = MSM8996_SLAVE_APPSS, 1651 .buswidth = 16, 1652 .mas_rpm_id = -1, 1653 .slv_rpm_id = 20, 1654 .qos.ap_owned = true, 1655 .qos.qos_mode = NOC_QOS_MODE_INVALID 1656 }; 1657 1658 static struct qcom_icc_node slv_lpass = { 1659 .name = "slv_lpass", 1660 .id = MSM8996_SLAVE_LPASS, 1661 .buswidth = 16, 1662 .mas_rpm_id = -1, 1663 .slv_rpm_id = 21, 1664 .qos.ap_owned = true, 1665 .qos.qos_mode = NOC_QOS_MODE_INVALID 1666 }; 1667 1668 static struct qcom_icc_node slv_usb3 = { 1669 .name = "slv_usb3", 1670 .id = MSM8996_SLAVE_USB3, 1671 .buswidth = 16, 1672 .mas_rpm_id = -1, 1673 .slv_rpm_id = 22, 1674 .qos.ap_owned = true, 1675 .qos.qos_mode = NOC_QOS_MODE_INVALID 1676 }; 1677 1678 static const u16 slv_snoc_bimc_links[] = { 1679 MSM8996_MASTER_SNOC_BIMC 1680 }; 1681 1682 static struct qcom_icc_node slv_snoc_bimc = { 1683 .name = "slv_snoc_bimc", 1684 .id = MSM8996_SLAVE_SNOC_BIMC, 1685 .buswidth = 32, 1686 .mas_rpm_id = -1, 1687 .slv_rpm_id = 24, 1688 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1689 .links = slv_snoc_bimc_links 1690 }; 1691 1692 static const u16 slv_snoc_cnoc_links[] = { 1693 MSM8996_MASTER_SNOC_CNOC 1694 }; 1695 1696 static struct qcom_icc_node slv_snoc_cnoc = { 1697 .name = "slv_snoc_cnoc", 1698 .id = MSM8996_SLAVE_SNOC_CNOC, 1699 .buswidth = 16, 1700 .mas_rpm_id = -1, 1701 .slv_rpm_id = 25, 1702 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1703 .links = slv_snoc_cnoc_links 1704 }; 1705 1706 static struct qcom_icc_node slv_imem = { 1707 .name = "slv_imem", 1708 .id = MSM8996_SLAVE_OCIMEM, 1709 .buswidth = 16, 1710 .mas_rpm_id = -1, 1711 .slv_rpm_id = 26 1712 }; 1713 1714 static struct qcom_icc_node slv_pimem = { 1715 .name = "slv_pimem", 1716 .id = MSM8996_SLAVE_PIMEM, 1717 .buswidth = 16, 1718 .mas_rpm_id = -1, 1719 .slv_rpm_id = 166 1720 }; 1721 1722 static const u16 slv_snoc_vmem_links[] = { 1723 MSM8996_MASTER_SNOC_VMEM 1724 }; 1725 1726 static struct qcom_icc_node slv_snoc_vmem = { 1727 .name = "slv_snoc_vmem", 1728 .id = MSM8996_SLAVE_SNOC_VMEM, 1729 .buswidth = 16, 1730 .mas_rpm_id = -1, 1731 .slv_rpm_id = 140, 1732 .qos.ap_owned = true, 1733 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1734 .num_links = ARRAY_SIZE(slv_snoc_vmem_links), 1735 .links = slv_snoc_vmem_links 1736 }; 1737 1738 static const u16 slv_snoc_pnoc_links[] = { 1739 MSM8996_MASTER_SNOC_PNOC 1740 }; 1741 1742 static struct qcom_icc_node slv_snoc_pnoc = { 1743 .name = "slv_snoc_pnoc", 1744 .id = MSM8996_SLAVE_SNOC_PNOC, 1745 .buswidth = 16, 1746 .mas_rpm_id = -1, 1747 .slv_rpm_id = 28, 1748 .num_links = ARRAY_SIZE(slv_snoc_pnoc_links), 1749 .links = slv_snoc_pnoc_links 1750 }; 1751 1752 static struct qcom_icc_node slv_qdss_stm = { 1753 .name = "slv_qdss_stm", 1754 .id = MSM8996_SLAVE_QDSS_STM, 1755 .buswidth = 16, 1756 .mas_rpm_id = -1, 1757 .slv_rpm_id = 30 1758 }; 1759 1760 static struct qcom_icc_node slv_pcie_0 = { 1761 .name = "slv_pcie_0", 1762 .id = MSM8996_SLAVE_PCIE_0, 1763 .buswidth = 16, 1764 .mas_rpm_id = -1, 1765 .slv_rpm_id = 84, 1766 .qos.ap_owned = true, 1767 .qos.qos_mode = NOC_QOS_MODE_INVALID 1768 }; 1769 1770 static struct qcom_icc_node slv_pcie_1 = { 1771 .name = "slv_pcie_1", 1772 .id = MSM8996_SLAVE_PCIE_1, 1773 .buswidth = 16, 1774 .mas_rpm_id = -1, 1775 .slv_rpm_id = 85, 1776 .qos.ap_owned = true, 1777 .qos.qos_mode = NOC_QOS_MODE_INVALID 1778 }; 1779 1780 static struct qcom_icc_node slv_pcie_2 = { 1781 .name = "slv_pcie_2", 1782 .id = MSM8996_SLAVE_PCIE_2, 1783 .buswidth = 16, 1784 .mas_rpm_id = -1, 1785 .slv_rpm_id = 164, 1786 .qos.ap_owned = true, 1787 .qos.qos_mode = NOC_QOS_MODE_INVALID 1788 }; 1789 1790 static struct qcom_icc_node slv_srvc_snoc = { 1791 .name = "slv_srvc_snoc", 1792 .id = MSM8996_SLAVE_SERVICE_SNOC, 1793 .buswidth = 16, 1794 .mas_rpm_id = -1, 1795 .slv_rpm_id = 29, 1796 .qos.ap_owned = true, 1797 .qos.qos_mode = NOC_QOS_MODE_INVALID 1798 }; 1799 1800 static struct qcom_icc_node * const a0noc_nodes[] = { 1801 [MASTER_PCIE_0] = &mas_pcie_0, 1802 [MASTER_PCIE_1] = &mas_pcie_1, 1803 [MASTER_PCIE_2] = &mas_pcie_2 1804 }; 1805 1806 static const struct regmap_config msm8996_a0noc_regmap_config = { 1807 .reg_bits = 32, 1808 .reg_stride = 4, 1809 .val_bits = 32, 1810 .max_register = 0x6000, 1811 .fast_io = true 1812 }; 1813 1814 static const struct qcom_icc_desc msm8996_a0noc = { 1815 .type = QCOM_ICC_NOC, 1816 .nodes = a0noc_nodes, 1817 .num_nodes = ARRAY_SIZE(a0noc_nodes), 1818 .intf_clocks = a0noc_intf_clocks, 1819 .num_intf_clocks = ARRAY_SIZE(a0noc_intf_clocks), 1820 .regmap_cfg = &msm8996_a0noc_regmap_config 1821 }; 1822 1823 static struct qcom_icc_node * const a1noc_nodes[] = { 1824 [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc, 1825 [MASTER_CRYPTO_CORE0] = &mas_crypto_c0, 1826 [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc 1827 }; 1828 1829 static const struct regmap_config msm8996_a1noc_regmap_config = { 1830 .reg_bits = 32, 1831 .reg_stride = 4, 1832 .val_bits = 32, 1833 .max_register = 0x5000, 1834 .fast_io = true 1835 }; 1836 1837 static const struct qcom_icc_desc msm8996_a1noc = { 1838 .type = QCOM_ICC_NOC, 1839 .nodes = a1noc_nodes, 1840 .num_nodes = ARRAY_SIZE(a1noc_nodes), 1841 .bus_clk_desc = &aggre1_branch_clk, 1842 .regmap_cfg = &msm8996_a1noc_regmap_config 1843 }; 1844 1845 static struct qcom_icc_node * const a2noc_nodes[] = { 1846 [MASTER_USB3] = &mas_usb3, 1847 [MASTER_IPA] = &mas_ipa, 1848 [MASTER_UFS] = &mas_ufs 1849 }; 1850 1851 static const struct regmap_config msm8996_a2noc_regmap_config = { 1852 .reg_bits = 32, 1853 .reg_stride = 4, 1854 .val_bits = 32, 1855 .max_register = 0x7000, 1856 .fast_io = true 1857 }; 1858 1859 static const struct qcom_icc_desc msm8996_a2noc = { 1860 .type = QCOM_ICC_NOC, 1861 .nodes = a2noc_nodes, 1862 .num_nodes = ARRAY_SIZE(a2noc_nodes), 1863 .bus_clk_desc = &aggre2_branch_clk, 1864 .intf_clocks = a2noc_intf_clocks, 1865 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks), 1866 .regmap_cfg = &msm8996_a2noc_regmap_config 1867 }; 1868 1869 static struct qcom_icc_node * const bimc_nodes[] = { 1870 [MASTER_AMPSS_M0] = &mas_apps_proc, 1871 [MASTER_GRAPHICS_3D] = &mas_oxili, 1872 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, 1873 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1874 [SLAVE_EBI_CH0] = &slv_ebi, 1875 [SLAVE_HMSS_L3] = &slv_hmss_l3, 1876 [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0, 1877 [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1 1878 }; 1879 1880 static const struct regmap_config msm8996_bimc_regmap_config = { 1881 .reg_bits = 32, 1882 .reg_stride = 4, 1883 .val_bits = 32, 1884 .max_register = 0x5a000, 1885 .fast_io = true 1886 }; 1887 1888 static const struct qcom_icc_desc msm8996_bimc = { 1889 .type = QCOM_ICC_BIMC, 1890 .nodes = bimc_nodes, 1891 .num_nodes = ARRAY_SIZE(bimc_nodes), 1892 .bus_clk_desc = &bimc_clk, 1893 .regmap_cfg = &msm8996_bimc_regmap_config 1894 }; 1895 1896 static struct qcom_icc_node * const cnoc_nodes[] = { 1897 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1898 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1899 [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc, 1900 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1901 [SLAVE_TCSR] = &slv_tcsr, 1902 [SLAVE_TLMM] = &slv_tlmm, 1903 [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg, 1904 [SLAVE_MPM] = &slv_mpm, 1905 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1906 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1907 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1908 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1909 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1910 [SLAVE_PRNG] = &slv_prng, 1911 [SLAVE_DCC_CFG] = &slv_dcc_cfg, 1912 [SLAVE_RBCPR_MX] = &slv_rbcpr_mx, 1913 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1914 [SLAVE_RBCPR_CX] = &slv_rbcpr_cx, 1915 [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg, 1916 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, 1917 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1918 [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, 1919 [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, 1920 [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg, 1921 [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg, 1922 [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg, 1923 [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg, 1924 [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy, 1925 [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg, 1926 [SLAVE_UFS_CFG] = &slv_ufs_cfg, 1927 [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg, 1928 [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg, 1929 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, 1930 [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg, 1931 [SLAVE_SSC_CFG] = &slv_ssc_cfg, 1932 [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg, 1933 [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg, 1934 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, 1935 [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg, 1936 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg 1937 }; 1938 1939 static const struct regmap_config msm8996_cnoc_regmap_config = { 1940 .reg_bits = 32, 1941 .reg_stride = 4, 1942 .val_bits = 32, 1943 .max_register = 0x1000, 1944 .fast_io = true 1945 }; 1946 1947 static const struct qcom_icc_desc msm8996_cnoc = { 1948 .type = QCOM_ICC_NOC, 1949 .nodes = cnoc_nodes, 1950 .num_nodes = ARRAY_SIZE(cnoc_nodes), 1951 .bus_clk_desc = &bus_2_clk, 1952 .regmap_cfg = &msm8996_cnoc_regmap_config 1953 }; 1954 1955 static struct qcom_icc_node * const mnoc_nodes[] = { 1956 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, 1957 [MASTER_CPP] = &mas_cpp, 1958 [MASTER_JPEG] = &mas_jpeg, 1959 [MASTER_MDP_PORT0] = &mas_mdp_p0, 1960 [MASTER_MDP_PORT1] = &mas_mdp_p1, 1961 [MASTER_ROTATOR] = &mas_rotator, 1962 [MASTER_VIDEO_P0] = &mas_venus, 1963 [MASTER_VFE] = &mas_vfe, 1964 [MASTER_SNOC_VMEM] = &mas_snoc_vmem, 1965 [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem, 1966 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, 1967 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, 1968 [SLAVE_VMEM] = &slv_vmem, 1969 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, 1970 [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg, 1971 [SLAVE_CPR_CFG] = &slv_cpr_cfg, 1972 [SLAVE_MISC_CFG] = &slv_misc_cfg, 1973 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1974 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1975 [SLAVE_VMEM_CFG] = &slv_vmem_cfg, 1976 [SLAVE_DSA_CFG] = &slv_dsa_cfg, 1977 [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg, 1978 [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg, 1979 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, 1980 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1981 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1982 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1983 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, 1984 [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg, 1985 [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg, 1986 [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg, 1987 [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg, 1988 [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg, 1989 [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg, 1990 [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg 1991 }; 1992 1993 static const struct regmap_config msm8996_mnoc_regmap_config = { 1994 .reg_bits = 32, 1995 .reg_stride = 4, 1996 .val_bits = 32, 1997 .max_register = 0x1c000, 1998 .fast_io = true 1999 }; 2000 2001 static const struct qcom_icc_desc msm8996_mnoc = { 2002 .type = QCOM_ICC_NOC, 2003 .nodes = mnoc_nodes, 2004 .num_nodes = ARRAY_SIZE(mnoc_nodes), 2005 .bus_clk_desc = &mmaxi_0_clk, 2006 .intf_clocks = mm_intf_clocks, 2007 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), 2008 .regmap_cfg = &msm8996_mnoc_regmap_config 2009 }; 2010 2011 static struct qcom_icc_node * const pnoc_nodes[] = { 2012 [MASTER_SNOC_PNOC] = &mas_snoc_pnoc, 2013 [MASTER_SDCC_1] = &mas_sdcc_1, 2014 [MASTER_SDCC_2] = &mas_sdcc_2, 2015 [MASTER_SDCC_4] = &mas_sdcc_4, 2016 [MASTER_USB_HS] = &mas_usb_hs, 2017 [MASTER_BLSP_1] = &mas_blsp_1, 2018 [MASTER_BLSP_2] = &mas_blsp_2, 2019 [MASTER_TSIF] = &mas_tsif, 2020 [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc, 2021 [SLAVE_USB_HS] = &slv_usb_hs, 2022 [SLAVE_SDCC_2] = &slv_sdcc_2, 2023 [SLAVE_SDCC_4] = &slv_sdcc_4, 2024 [SLAVE_TSIF] = &slv_tsif, 2025 [SLAVE_BLSP_2] = &slv_blsp_2, 2026 [SLAVE_SDCC_1] = &slv_sdcc_1, 2027 [SLAVE_BLSP_1] = &slv_blsp_1, 2028 [SLAVE_PDM] = &slv_pdm, 2029 [SLAVE_AHB2PHY] = &slv_ahb2phy 2030 }; 2031 2032 static const struct regmap_config msm8996_pnoc_regmap_config = { 2033 .reg_bits = 32, 2034 .reg_stride = 4, 2035 .val_bits = 32, 2036 .max_register = 0x3000, 2037 .fast_io = true 2038 }; 2039 2040 static const struct qcom_icc_desc msm8996_pnoc = { 2041 .type = QCOM_ICC_NOC, 2042 .nodes = pnoc_nodes, 2043 .num_nodes = ARRAY_SIZE(pnoc_nodes), 2044 .bus_clk_desc = &bus_0_clk, 2045 .regmap_cfg = &msm8996_pnoc_regmap_config 2046 }; 2047 2048 static struct qcom_icc_node * const snoc_nodes[] = { 2049 [MASTER_HMSS] = &mas_hmss, 2050 [MASTER_QDSS_BAM] = &mas_qdss_bam, 2051 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 2052 [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0, 2053 [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1, 2054 [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc, 2055 [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc, 2056 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, 2057 [MASTER_QDSS_ETR] = &mas_qdss_etr, 2058 [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc, 2059 [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc, 2060 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, 2061 [SLAVE_HMSS] = &slv_hmss, 2062 [SLAVE_LPASS] = &slv_lpass, 2063 [SLAVE_USB3] = &slv_usb3, 2064 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 2065 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 2066 [SLAVE_IMEM] = &slv_imem, 2067 [SLAVE_PIMEM] = &slv_pimem, 2068 [SLAVE_SNOC_VMEM] = &slv_snoc_vmem, 2069 [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc, 2070 [SLAVE_QDSS_STM] = &slv_qdss_stm, 2071 [SLAVE_PCIE_0] = &slv_pcie_0, 2072 [SLAVE_PCIE_1] = &slv_pcie_1, 2073 [SLAVE_PCIE_2] = &slv_pcie_2, 2074 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc 2075 }; 2076 2077 static const struct regmap_config msm8996_snoc_regmap_config = { 2078 .reg_bits = 32, 2079 .reg_stride = 4, 2080 .val_bits = 32, 2081 .max_register = 0x20000, 2082 .fast_io = true 2083 }; 2084 2085 static const struct qcom_icc_desc msm8996_snoc = { 2086 .type = QCOM_ICC_NOC, 2087 .nodes = snoc_nodes, 2088 .num_nodes = ARRAY_SIZE(snoc_nodes), 2089 .bus_clk_desc = &bus_1_clk, 2090 .regmap_cfg = &msm8996_snoc_regmap_config 2091 }; 2092 2093 static const struct of_device_id qnoc_of_match[] = { 2094 { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc}, 2095 { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc}, 2096 { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc}, 2097 { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc}, 2098 { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc}, 2099 { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc}, 2100 { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc}, 2101 { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc}, 2102 { } 2103 }; 2104 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2105 2106 static struct platform_driver qnoc_driver = { 2107 .probe = qnoc_probe, 2108 .remove = qnoc_remove, 2109 .driver = { 2110 .name = "qnoc-msm8996", 2111 .of_match_table = qnoc_of_match, 2112 .sync_state = icc_sync_state, 2113 } 2114 }; 2115 static int __init qnoc_driver_init(void) 2116 { 2117 return platform_driver_register(&qnoc_driver); 2118 } 2119 core_initcall(qnoc_driver_init); 2120 2121 static void __exit qnoc_driver_exit(void) 2122 { 2123 platform_driver_unregister(&qnoc_driver); 2124 } 2125 module_exit(qnoc_driver_exit); 2126 2127 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); 2128 MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver"); 2129 MODULE_LICENSE("GPL v2"); 2130