1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Brian Masney <masneyb@onstation.org> 4 * 5 * Based on MSM bus code from downstream MSM kernel sources. 6 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. 7 * 8 * Based on qcs404.c 9 * Copyright (C) 2019 Linaro Ltd 10 * 11 * Here's a rough representation that shows the various buses that form the 12 * Network On Chip (NOC) for the msm8974: 13 * 14 * Multimedia Subsystem (MMSS) 15 * |----------+-----------------------------------+-----------| 16 * | | 17 * | | 18 * Config | Bus Interface | Memory Controller 19 * |------------+-+-----------| |------------+-+-----------| 20 * | | 21 * | | 22 * | System | 23 * |--------------+-+---------------------------------+-+-------------| 24 * | | 25 * | | 26 * Peripheral | On Chip | Memory (OCMEM) 27 * |------------+-------------| |------------+-------------| 28 */ 29 30 #include <dt-bindings/interconnect/qcom,msm8974.h> 31 #include <linux/clk.h> 32 #include <linux/device.h> 33 #include <linux/interconnect-provider.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/of_device.h> 37 #include <linux/of_platform.h> 38 #include <linux/platform_device.h> 39 #include <linux/slab.h> 40 41 #include "smd-rpm.h" 42 43 enum { 44 MSM8974_BIMC_MAS_AMPSS_M0 = 1, 45 MSM8974_BIMC_MAS_AMPSS_M1, 46 MSM8974_BIMC_MAS_MSS_PROC, 47 MSM8974_BIMC_TO_MNOC, 48 MSM8974_BIMC_TO_SNOC, 49 MSM8974_BIMC_SLV_EBI_CH0, 50 MSM8974_BIMC_SLV_AMPSS_L2, 51 MSM8974_CNOC_MAS_RPM_INST, 52 MSM8974_CNOC_MAS_RPM_DATA, 53 MSM8974_CNOC_MAS_RPM_SYS, 54 MSM8974_CNOC_MAS_DEHR, 55 MSM8974_CNOC_MAS_QDSS_DAP, 56 MSM8974_CNOC_MAS_SPDM, 57 MSM8974_CNOC_MAS_TIC, 58 MSM8974_CNOC_SLV_CLK_CTL, 59 MSM8974_CNOC_SLV_CNOC_MSS, 60 MSM8974_CNOC_SLV_SECURITY, 61 MSM8974_CNOC_SLV_TCSR, 62 MSM8974_CNOC_SLV_TLMM, 63 MSM8974_CNOC_SLV_CRYPTO_0_CFG, 64 MSM8974_CNOC_SLV_CRYPTO_1_CFG, 65 MSM8974_CNOC_SLV_IMEM_CFG, 66 MSM8974_CNOC_SLV_MESSAGE_RAM, 67 MSM8974_CNOC_SLV_BIMC_CFG, 68 MSM8974_CNOC_SLV_BOOT_ROM, 69 MSM8974_CNOC_SLV_PMIC_ARB, 70 MSM8974_CNOC_SLV_SPDM_WRAPPER, 71 MSM8974_CNOC_SLV_DEHR_CFG, 72 MSM8974_CNOC_SLV_MPM, 73 MSM8974_CNOC_SLV_QDSS_CFG, 74 MSM8974_CNOC_SLV_RBCPR_CFG, 75 MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 76 MSM8974_CNOC_TO_SNOC, 77 MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 78 MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 79 MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 80 MSM8974_CNOC_SLV_PNOC_CFG, 81 MSM8974_CNOC_SLV_SNOC_MPU_CFG, 82 MSM8974_CNOC_SLV_SNOC_CFG, 83 MSM8974_CNOC_SLV_EBI1_DLL_CFG, 84 MSM8974_CNOC_SLV_PHY_APU_CFG, 85 MSM8974_CNOC_SLV_EBI1_PHY_CFG, 86 MSM8974_CNOC_SLV_RPM, 87 MSM8974_CNOC_SLV_SERVICE_CNOC, 88 MSM8974_MNOC_MAS_GRAPHICS_3D, 89 MSM8974_MNOC_MAS_JPEG, 90 MSM8974_MNOC_MAS_MDP_PORT0, 91 MSM8974_MNOC_MAS_VIDEO_P0, 92 MSM8974_MNOC_MAS_VIDEO_P1, 93 MSM8974_MNOC_MAS_VFE, 94 MSM8974_MNOC_TO_CNOC, 95 MSM8974_MNOC_TO_BIMC, 96 MSM8974_MNOC_SLV_CAMERA_CFG, 97 MSM8974_MNOC_SLV_DISPLAY_CFG, 98 MSM8974_MNOC_SLV_OCMEM_CFG, 99 MSM8974_MNOC_SLV_CPR_CFG, 100 MSM8974_MNOC_SLV_CPR_XPU_CFG, 101 MSM8974_MNOC_SLV_MISC_CFG, 102 MSM8974_MNOC_SLV_MISC_XPU_CFG, 103 MSM8974_MNOC_SLV_VENUS_CFG, 104 MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 105 MSM8974_MNOC_SLV_MMSS_CLK_CFG, 106 MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 107 MSM8974_MNOC_SLV_MNOC_MPU_CFG, 108 MSM8974_MNOC_SLV_ONOC_MPU_CFG, 109 MSM8974_MNOC_SLV_SERVICE_MNOC, 110 MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 111 MSM8974_OCMEM_MAS_JPEG_OCMEM, 112 MSM8974_OCMEM_MAS_MDP_OCMEM, 113 MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 114 MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 115 MSM8974_OCMEM_MAS_VFE_OCMEM, 116 MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 117 MSM8974_OCMEM_SLV_SERVICE_ONOC, 118 MSM8974_OCMEM_VNOC_TO_SNOC, 119 MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 120 MSM8974_OCMEM_VNOC_MAS_GFX3D, 121 MSM8974_OCMEM_SLV_OCMEM, 122 MSM8974_PNOC_MAS_PNOC_CFG, 123 MSM8974_PNOC_MAS_SDCC_1, 124 MSM8974_PNOC_MAS_SDCC_3, 125 MSM8974_PNOC_MAS_SDCC_4, 126 MSM8974_PNOC_MAS_SDCC_2, 127 MSM8974_PNOC_MAS_TSIF, 128 MSM8974_PNOC_MAS_BAM_DMA, 129 MSM8974_PNOC_MAS_BLSP_2, 130 MSM8974_PNOC_MAS_USB_HSIC, 131 MSM8974_PNOC_MAS_BLSP_1, 132 MSM8974_PNOC_MAS_USB_HS, 133 MSM8974_PNOC_TO_SNOC, 134 MSM8974_PNOC_SLV_SDCC_1, 135 MSM8974_PNOC_SLV_SDCC_3, 136 MSM8974_PNOC_SLV_SDCC_2, 137 MSM8974_PNOC_SLV_SDCC_4, 138 MSM8974_PNOC_SLV_TSIF, 139 MSM8974_PNOC_SLV_BAM_DMA, 140 MSM8974_PNOC_SLV_BLSP_2, 141 MSM8974_PNOC_SLV_USB_HSIC, 142 MSM8974_PNOC_SLV_BLSP_1, 143 MSM8974_PNOC_SLV_USB_HS, 144 MSM8974_PNOC_SLV_PDM, 145 MSM8974_PNOC_SLV_PERIPH_APU_CFG, 146 MSM8974_PNOC_SLV_PNOC_MPU_CFG, 147 MSM8974_PNOC_SLV_PRNG, 148 MSM8974_PNOC_SLV_SERVICE_PNOC, 149 MSM8974_SNOC_MAS_LPASS_AHB, 150 MSM8974_SNOC_MAS_QDSS_BAM, 151 MSM8974_SNOC_MAS_SNOC_CFG, 152 MSM8974_SNOC_TO_BIMC, 153 MSM8974_SNOC_TO_CNOC, 154 MSM8974_SNOC_TO_PNOC, 155 MSM8974_SNOC_TO_OCMEM_VNOC, 156 MSM8974_SNOC_MAS_CRYPTO_CORE0, 157 MSM8974_SNOC_MAS_CRYPTO_CORE1, 158 MSM8974_SNOC_MAS_LPASS_PROC, 159 MSM8974_SNOC_MAS_MSS, 160 MSM8974_SNOC_MAS_MSS_NAV, 161 MSM8974_SNOC_MAS_OCMEM_DMA, 162 MSM8974_SNOC_MAS_WCSS, 163 MSM8974_SNOC_MAS_QDSS_ETR, 164 MSM8974_SNOC_MAS_USB3, 165 MSM8974_SNOC_SLV_AMPSS, 166 MSM8974_SNOC_SLV_LPASS, 167 MSM8974_SNOC_SLV_USB3, 168 MSM8974_SNOC_SLV_WCSS, 169 MSM8974_SNOC_SLV_OCIMEM, 170 MSM8974_SNOC_SLV_SNOC_OCMEM, 171 MSM8974_SNOC_SLV_SERVICE_SNOC, 172 MSM8974_SNOC_SLV_QDSS_STM, 173 }; 174 175 #define RPM_BUS_MASTER_REQ 0x73616d62 176 #define RPM_BUS_SLAVE_REQ 0x766c7362 177 178 #define to_msm8974_icc_provider(_provider) \ 179 container_of(_provider, struct msm8974_icc_provider, provider) 180 181 static const struct clk_bulk_data msm8974_icc_bus_clocks[] = { 182 { .id = "bus" }, 183 { .id = "bus_a" }, 184 }; 185 186 /** 187 * struct msm8974_icc_provider - Qualcomm specific interconnect provider 188 * @provider: generic interconnect provider 189 * @bus_clks: the clk_bulk_data table of bus clocks 190 * @num_clks: the total number of clk_bulk_data entries 191 */ 192 struct msm8974_icc_provider { 193 struct icc_provider provider; 194 struct clk_bulk_data *bus_clks; 195 int num_clks; 196 }; 197 198 #define MSM8974_ICC_MAX_LINKS 3 199 200 /** 201 * struct msm8974_icc_node - Qualcomm specific interconnect nodes 202 * @name: the node name used in debugfs 203 * @id: a unique node identifier 204 * @links: an array of nodes where we can go next while traversing 205 * @num_links: the total number of @links 206 * @buswidth: width of the interconnect between a node and the bus (bytes) 207 * @mas_rpm_id: RPM ID for devices that are bus masters 208 * @slv_rpm_id: RPM ID for devices that are bus slaves 209 * @rate: current bus clock rate in Hz 210 */ 211 struct msm8974_icc_node { 212 unsigned char *name; 213 u16 id; 214 u16 links[MSM8974_ICC_MAX_LINKS]; 215 u16 num_links; 216 u16 buswidth; 217 int mas_rpm_id; 218 int slv_rpm_id; 219 u64 rate; 220 }; 221 222 struct msm8974_icc_desc { 223 struct msm8974_icc_node * const *nodes; 224 size_t num_nodes; 225 }; 226 227 #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ 228 ...) \ 229 static struct msm8974_icc_node _name = { \ 230 .name = #_name, \ 231 .id = _id, \ 232 .buswidth = _buswidth, \ 233 .mas_rpm_id = _mas_rpm_id, \ 234 .slv_rpm_id = _slv_rpm_id, \ 235 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ 236 .links = { __VA_ARGS__ }, \ 237 } 238 239 DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1); 240 DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1); 241 DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1); 242 DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SLV_EBI_CH0); 243 DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0); 244 DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0); 245 DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1); 246 247 static struct msm8974_icc_node * const msm8974_bimc_nodes[] = { 248 [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0, 249 [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1, 250 [BIMC_MAS_MSS_PROC] = &mas_mss_proc, 251 [BIMC_TO_MNOC] = &bimc_to_mnoc, 252 [BIMC_TO_SNOC] = &bimc_to_snoc, 253 [BIMC_SLV_EBI_CH0] = &slv_ebi_ch0, 254 [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2, 255 }; 256 257 static const struct msm8974_icc_desc msm8974_bimc = { 258 .nodes = msm8974_bimc_nodes, 259 .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes), 260 }; 261 262 DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1); 263 DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1); 264 DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1); 265 DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1); 266 DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1); 267 DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1); 268 DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1); 269 DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47); 270 DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48); 271 DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49); 272 DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50); 273 DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51); 274 DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52); 275 DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53); 276 DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54); 277 DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55); 278 DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56); 279 DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57); 280 DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59); 281 DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60); 282 DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61); 283 DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62); 284 DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63); 285 DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64); 286 DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 8, -1, 65); 287 DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75); 288 DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68); 289 DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 8, -1, 58); 290 DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66); 291 DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69); 292 DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67); 293 DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70); 294 DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71); 295 DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72); 296 DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73); 297 DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74); 298 DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76); 299 300 static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = { 301 [CNOC_MAS_RPM_INST] = &mas_rpm_inst, 302 [CNOC_MAS_RPM_DATA] = &mas_rpm_data, 303 [CNOC_MAS_RPM_SYS] = &mas_rpm_sys, 304 [CNOC_MAS_DEHR] = &mas_dehr, 305 [CNOC_MAS_QDSS_DAP] = &mas_qdss_dap, 306 [CNOC_MAS_SPDM] = &mas_spdm, 307 [CNOC_MAS_TIC] = &mas_tic, 308 [CNOC_SLV_CLK_CTL] = &slv_clk_ctl, 309 [CNOC_SLV_CNOC_MSS] = &slv_cnoc_mss, 310 [CNOC_SLV_SECURITY] = &slv_security, 311 [CNOC_SLV_TCSR] = &slv_tcsr, 312 [CNOC_SLV_TLMM] = &slv_tlmm, 313 [CNOC_SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 314 [CNOC_SLV_CRYPTO_1_CFG] = &slv_crypto_1_cfg, 315 [CNOC_SLV_IMEM_CFG] = &slv_imem_cfg, 316 [CNOC_SLV_MESSAGE_RAM] = &slv_message_ram, 317 [CNOC_SLV_BIMC_CFG] = &slv_bimc_cfg, 318 [CNOC_SLV_BOOT_ROM] = &slv_boot_rom, 319 [CNOC_SLV_PMIC_ARB] = &slv_pmic_arb, 320 [CNOC_SLV_SPDM_WRAPPER] = &slv_spdm_wrapper, 321 [CNOC_SLV_DEHR_CFG] = &slv_dehr_cfg, 322 [CNOC_SLV_MPM] = &slv_mpm, 323 [CNOC_SLV_QDSS_CFG] = &slv_qdss_cfg, 324 [CNOC_SLV_RBCPR_CFG] = &slv_rbcpr_cfg, 325 [CNOC_SLV_RBCPR_QDSS_APU_CFG] = &slv_rbcpr_qdss_apu_cfg, 326 [CNOC_TO_SNOC] = &cnoc_to_snoc, 327 [CNOC_SLV_CNOC_ONOC_CFG] = &slv_cnoc_onoc_cfg, 328 [CNOC_SLV_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg, 329 [CNOC_SLV_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, 330 [CNOC_SLV_PNOC_CFG] = &slv_pnoc_cfg, 331 [CNOC_SLV_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, 332 [CNOC_SLV_SNOC_CFG] = &slv_snoc_cfg, 333 [CNOC_SLV_EBI1_DLL_CFG] = &slv_ebi1_dll_cfg, 334 [CNOC_SLV_PHY_APU_CFG] = &slv_phy_apu_cfg, 335 [CNOC_SLV_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, 336 [CNOC_SLV_RPM] = &slv_rpm, 337 [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc, 338 }; 339 340 static const struct msm8974_icc_desc msm8974_cnoc = { 341 .nodes = msm8974_cnoc_nodes, 342 .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes), 343 }; 344 345 DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM8974_MNOC_TO_BIMC); 346 DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_BIMC); 347 DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974_MNOC_TO_BIMC); 348 DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1); 349 DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1); 350 DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BIMC); 351 DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1); 352 DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_TO_MNOC); 353 DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3); 354 DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4); 355 DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5); 356 DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6); 357 DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7); 358 DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8); 359 DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9); 360 DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10); 361 DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1, 11); 362 DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12); 363 DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, -1, 13); 364 DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14); 365 DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15); 366 DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17); 367 368 static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = { 369 [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d, 370 [MNOC_MAS_JPEG] = &mas_jpeg, 371 [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0, 372 [MNOC_MAS_VIDEO_P0] = &mas_video_p0, 373 [MNOC_MAS_VIDEO_P1] = &mas_video_p1, 374 [MNOC_MAS_VFE] = &mas_vfe, 375 [MNOC_TO_CNOC] = &mnoc_to_cnoc, 376 [MNOC_TO_BIMC] = &mnoc_to_bimc, 377 [MNOC_SLV_CAMERA_CFG] = &slv_camera_cfg, 378 [MNOC_SLV_DISPLAY_CFG] = &slv_display_cfg, 379 [MNOC_SLV_OCMEM_CFG] = &slv_ocmem_cfg, 380 [MNOC_SLV_CPR_CFG] = &slv_cpr_cfg, 381 [MNOC_SLV_CPR_XPU_CFG] = &slv_cpr_xpu_cfg, 382 [MNOC_SLV_MISC_CFG] = &slv_misc_cfg, 383 [MNOC_SLV_MISC_XPU_CFG] = &slv_misc_xpu_cfg, 384 [MNOC_SLV_VENUS_CFG] = &slv_venus_cfg, 385 [MNOC_SLV_GRAPHICS_3D_CFG] = &slv_graphics_3d_cfg, 386 [MNOC_SLV_MMSS_CLK_CFG] = &slv_mmss_clk_cfg, 387 [MNOC_SLV_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg, 388 [MNOC_SLV_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, 389 [MNOC_SLV_ONOC_MPU_CFG] = &slv_onoc_mpu_cfg, 390 [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc, 391 }; 392 393 static const struct msm8974_icc_desc msm8974_mnoc = { 394 .nodes = msm8974_mnoc_nodes, 395 .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes), 396 }; 397 398 DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16, 54, 78, MSM8974_OCMEM_SLV_OCMEM); 399 DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1); 400 DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1); 401 DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15, -1); 402 DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16, -1); 403 DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1); 404 DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -1); 405 DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19); 406 DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18); 407 408 /* Virtual NoC is needed for connection to OCMEM */ 409 DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC); 410 DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80); 411 DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); 412 413 static struct msm8974_icc_node * const msm8974_onoc_nodes[] = { 414 [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc, 415 [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem, 416 [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem, 417 [OCMEM_MAS_VIDEO_P0_OCMEM] = &mas_video_p0_ocmem, 418 [OCMEM_MAS_VIDEO_P1_OCMEM] = &mas_video_p1_ocmem, 419 [OCMEM_MAS_VFE_OCMEM] = &mas_vfe_ocmem, 420 [OCMEM_MAS_CNOC_ONOC_CFG] = &mas_cnoc_onoc_cfg, 421 [OCMEM_SLV_SERVICE_ONOC] = &slv_service_onoc, 422 [OCMEM_VNOC_TO_SNOC] = &ocmem_vnoc_to_snoc, 423 [OCMEM_VNOC_TO_OCMEM_NOC] = &ocmem_vnoc_to_onoc, 424 [OCMEM_VNOC_MAS_GFX3D] = &mas_v_ocmem_gfx3d, 425 [OCMEM_SLV_OCMEM] = &slv_ocmem, 426 }; 427 428 static const struct msm8974_icc_desc msm8974_onoc = { 429 .nodes = msm8974_onoc_nodes, 430 .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes), 431 }; 432 433 DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1); 434 DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_TO_SNOC); 435 DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_TO_SNOC); 436 DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_TO_SNOC); 437 DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_TO_SNOC); 438 DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_SNOC); 439 DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1); 440 DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_TO_SNOC); 441 DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_PNOC_TO_SNOC); 442 DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_TO_SNOC); 443 DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_TO_SNOC); 444 DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_TO_PNOC, MSM8974_PNOC_SLV_PRNG); 445 DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31); 446 DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32); 447 DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33); 448 DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34); 449 DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35); 450 DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36); 451 DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37); 452 DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38); 453 DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39); 454 DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40); 455 DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41); 456 DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 42); 457 DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43); 458 DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC); 459 DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46); 460 461 static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = { 462 [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg, 463 [PNOC_MAS_SDCC_1] = &mas_sdcc_1, 464 [PNOC_MAS_SDCC_3] = &mas_sdcc_3, 465 [PNOC_MAS_SDCC_4] = &mas_sdcc_4, 466 [PNOC_MAS_SDCC_2] = &mas_sdcc_2, 467 [PNOC_MAS_TSIF] = &mas_tsif, 468 [PNOC_MAS_BAM_DMA] = &mas_bam_dma, 469 [PNOC_MAS_BLSP_2] = &mas_blsp_2, 470 [PNOC_MAS_USB_HSIC] = &mas_usb_hsic, 471 [PNOC_MAS_BLSP_1] = &mas_blsp_1, 472 [PNOC_MAS_USB_HS] = &mas_usb_hs, 473 [PNOC_TO_SNOC] = &pnoc_to_snoc, 474 [PNOC_SLV_SDCC_1] = &slv_sdcc_1, 475 [PNOC_SLV_SDCC_3] = &slv_sdcc_3, 476 [PNOC_SLV_SDCC_2] = &slv_sdcc_2, 477 [PNOC_SLV_SDCC_4] = &slv_sdcc_4, 478 [PNOC_SLV_TSIF] = &slv_tsif, 479 [PNOC_SLV_BAM_DMA] = &slv_bam_dma, 480 [PNOC_SLV_BLSP_2] = &slv_blsp_2, 481 [PNOC_SLV_USB_HSIC] = &slv_usb_hsic, 482 [PNOC_SLV_BLSP_1] = &slv_blsp_1, 483 [PNOC_SLV_USB_HS] = &slv_usb_hs, 484 [PNOC_SLV_PDM] = &slv_pdm, 485 [PNOC_SLV_PERIPH_APU_CFG] = &slv_periph_apu_cfg, 486 [PNOC_SLV_PNOC_MPU_CFG] = &slv_pnoc_mpu_cfg, 487 [PNOC_SLV_PRNG] = &slv_prng, 488 [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc, 489 }; 490 491 static const struct msm8974_icc_desc msm8974_pnoc = { 492 .nodes = msm8974_pnoc_nodes, 493 .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes), 494 }; 495 496 DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1); 497 DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1); 498 DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1); 499 DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_TO_SNOC); 500 DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25); 501 DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_TO_SNOC); 502 DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC); 503 DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, MSM8974_SNOC_TO_BIMC); 504 DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1); 505 DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM8974_SNOC_TO_OCMEM_VNOC); 506 DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1); 507 DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1); 508 DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1); 509 DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1); 510 DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1); 511 DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_BIMC); 512 DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20); 513 DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21); 514 DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22); 515 DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23); 516 DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26); 517 DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27); 518 DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29); 519 DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30); 520 521 static struct msm8974_icc_node * const msm8974_snoc_nodes[] = { 522 [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb, 523 [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam, 524 [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg, 525 [SNOC_TO_BIMC] = &snoc_to_bimc, 526 [SNOC_TO_CNOC] = &snoc_to_cnoc, 527 [SNOC_TO_PNOC] = &snoc_to_pnoc, 528 [SNOC_TO_OCMEM_VNOC] = &snoc_to_ocmem_vnoc, 529 [SNOC_MAS_CRYPTO_CORE0] = &mas_crypto_core0, 530 [SNOC_MAS_CRYPTO_CORE1] = &mas_crypto_core1, 531 [SNOC_MAS_LPASS_PROC] = &mas_lpass_proc, 532 [SNOC_MAS_MSS] = &mas_mss, 533 [SNOC_MAS_MSS_NAV] = &mas_mss_nav, 534 [SNOC_MAS_OCMEM_DMA] = &mas_ocmem_dma, 535 [SNOC_MAS_WCSS] = &mas_wcss, 536 [SNOC_MAS_QDSS_ETR] = &mas_qdss_etr, 537 [SNOC_MAS_USB3] = &mas_usb3, 538 [SNOC_SLV_AMPSS] = &slv_ampss, 539 [SNOC_SLV_LPASS] = &slv_lpass, 540 [SNOC_SLV_USB3] = &slv_usb3, 541 [SNOC_SLV_WCSS] = &slv_wcss, 542 [SNOC_SLV_OCIMEM] = &slv_ocimem, 543 [SNOC_SLV_SNOC_OCMEM] = &slv_snoc_ocmem, 544 [SNOC_SLV_SERVICE_SNOC] = &slv_service_snoc, 545 [SNOC_SLV_QDSS_STM] = &slv_qdss_stm, 546 }; 547 548 static const struct msm8974_icc_desc msm8974_snoc = { 549 .nodes = msm8974_snoc_nodes, 550 .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes), 551 }; 552 553 static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type, 554 char *name, int id, u64 val) 555 { 556 int ret; 557 558 if (id == -1) 559 return; 560 561 /* 562 * Setting the bandwidth requests for some nodes fails and this same 563 * behavior occurs on the downstream MSM 3.4 kernel sources based on 564 * errors like this in that kernel: 565 * 566 * msm_rpm_get_error_from_ack(): RPM NACK Unsupported resource 567 * AXI: msm_bus_rpm_req(): RPM: Ack failed 568 * AXI: msm_bus_rpm_commit_arb(): RPM: Req fail: mas:32, bw:240000000 569 * 570 * Since there's no publicly available documentation for this hardware, 571 * and the bandwidth for some nodes in the path can be set properly, 572 * let's not return an error. 573 */ 574 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id, 575 val); 576 if (ret) 577 dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n", 578 name, id, ret); 579 } 580 581 static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst) 582 { 583 struct msm8974_icc_node *src_qn, *dst_qn; 584 struct msm8974_icc_provider *qp; 585 u64 sum_bw, max_peak_bw, rate; 586 u32 agg_avg = 0, agg_peak = 0; 587 struct icc_provider *provider; 588 struct icc_node *n; 589 int ret, i; 590 591 src_qn = src->data; 592 dst_qn = dst->data; 593 provider = src->provider; 594 qp = to_msm8974_icc_provider(provider); 595 596 list_for_each_entry(n, &provider->nodes, node_list) 597 provider->aggregate(n, 0, n->avg_bw, n->peak_bw, 598 &agg_avg, &agg_peak); 599 600 sum_bw = icc_units_to_bps(agg_avg); 601 max_peak_bw = icc_units_to_bps(agg_peak); 602 603 /* Set bandwidth on source node */ 604 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ, 605 src_qn->name, src_qn->mas_rpm_id, sum_bw); 606 607 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ, 608 src_qn->name, src_qn->slv_rpm_id, sum_bw); 609 610 /* Set bandwidth on destination node */ 611 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ, 612 dst_qn->name, dst_qn->mas_rpm_id, sum_bw); 613 614 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ, 615 dst_qn->name, dst_qn->slv_rpm_id, sum_bw); 616 617 rate = max(sum_bw, max_peak_bw); 618 619 do_div(rate, src_qn->buswidth); 620 621 rate = min_t(u32, rate, INT_MAX); 622 623 if (src_qn->rate == rate) 624 return 0; 625 626 for (i = 0; i < qp->num_clks; i++) { 627 ret = clk_set_rate(qp->bus_clks[i].clk, rate); 628 if (ret) { 629 dev_err(provider->dev, "%s clk_set_rate error: %d\n", 630 qp->bus_clks[i].id, ret); 631 ret = 0; 632 } 633 } 634 635 src_qn->rate = rate; 636 637 return 0; 638 } 639 640 static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak) 641 { 642 *avg = 0; 643 *peak = 0; 644 645 return 0; 646 } 647 648 static int msm8974_icc_probe(struct platform_device *pdev) 649 { 650 const struct msm8974_icc_desc *desc; 651 struct msm8974_icc_node * const *qnodes; 652 struct msm8974_icc_provider *qp; 653 struct device *dev = &pdev->dev; 654 struct icc_onecell_data *data; 655 struct icc_provider *provider; 656 struct icc_node *node; 657 size_t num_nodes, i; 658 int ret; 659 660 /* wait for the RPM proxy */ 661 if (!qcom_icc_rpm_smd_available()) 662 return -EPROBE_DEFER; 663 664 desc = of_device_get_match_data(dev); 665 if (!desc) 666 return -EINVAL; 667 668 qnodes = desc->nodes; 669 num_nodes = desc->num_nodes; 670 671 qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); 672 if (!qp) 673 return -ENOMEM; 674 675 data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), 676 GFP_KERNEL); 677 if (!data) 678 return -ENOMEM; 679 680 qp->bus_clks = devm_kmemdup(dev, msm8974_icc_bus_clocks, 681 sizeof(msm8974_icc_bus_clocks), GFP_KERNEL); 682 if (!qp->bus_clks) 683 return -ENOMEM; 684 685 qp->num_clks = ARRAY_SIZE(msm8974_icc_bus_clocks); 686 ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); 687 if (ret) 688 return ret; 689 690 ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); 691 if (ret) 692 return ret; 693 694 provider = &qp->provider; 695 INIT_LIST_HEAD(&provider->nodes); 696 provider->dev = dev; 697 provider->set = msm8974_icc_set; 698 provider->aggregate = icc_std_aggregate; 699 provider->xlate = of_icc_xlate_onecell; 700 provider->data = data; 701 provider->get_bw = msm8974_get_bw; 702 703 ret = icc_provider_add(provider); 704 if (ret) { 705 dev_err(dev, "error adding interconnect provider: %d\n", ret); 706 goto err_disable_clks; 707 } 708 709 for (i = 0; i < num_nodes; i++) { 710 size_t j; 711 712 node = icc_node_create(qnodes[i]->id); 713 if (IS_ERR(node)) { 714 ret = PTR_ERR(node); 715 goto err_del_icc; 716 } 717 718 node->name = qnodes[i]->name; 719 node->data = qnodes[i]; 720 icc_node_add(node, provider); 721 722 dev_dbg(dev, "registered node %s\n", node->name); 723 724 /* populate links */ 725 for (j = 0; j < qnodes[i]->num_links; j++) 726 icc_link_create(node, qnodes[i]->links[j]); 727 728 data->nodes[i] = node; 729 } 730 data->num_nodes = num_nodes; 731 732 platform_set_drvdata(pdev, qp); 733 734 return 0; 735 736 err_del_icc: 737 icc_nodes_remove(provider); 738 icc_provider_del(provider); 739 740 err_disable_clks: 741 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); 742 743 return ret; 744 } 745 746 static int msm8974_icc_remove(struct platform_device *pdev) 747 { 748 struct msm8974_icc_provider *qp = platform_get_drvdata(pdev); 749 750 icc_nodes_remove(&qp->provider); 751 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); 752 icc_provider_del(&qp->provider); 753 754 return 0; 755 } 756 757 static const struct of_device_id msm8974_noc_of_match[] = { 758 { .compatible = "qcom,msm8974-bimc", .data = &msm8974_bimc}, 759 { .compatible = "qcom,msm8974-cnoc", .data = &msm8974_cnoc}, 760 { .compatible = "qcom,msm8974-mmssnoc", .data = &msm8974_mnoc}, 761 { .compatible = "qcom,msm8974-ocmemnoc", .data = &msm8974_onoc}, 762 { .compatible = "qcom,msm8974-pnoc", .data = &msm8974_pnoc}, 763 { .compatible = "qcom,msm8974-snoc", .data = &msm8974_snoc}, 764 { }, 765 }; 766 MODULE_DEVICE_TABLE(of, msm8974_noc_of_match); 767 768 static struct platform_driver msm8974_noc_driver = { 769 .probe = msm8974_icc_probe, 770 .remove = msm8974_icc_remove, 771 .driver = { 772 .name = "qnoc-msm8974", 773 .of_match_table = msm8974_noc_of_match, 774 .sync_state = icc_sync_state, 775 }, 776 }; 777 module_platform_driver(msm8974_noc_driver); 778 MODULE_DESCRIPTION("Qualcomm MSM8974 NoC driver"); 779 MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>"); 780 MODULE_LICENSE("GPL v2"); 781