1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Linaro Ltd 4 */ 5 6 #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 7 #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 8 9 #include <linux/soc/qcom/smd-rpm.h> 10 11 #include <dt-bindings/interconnect/qcom,rpm-icc.h> 12 #include <linux/clk.h> 13 #include <linux/interconnect-provider.h> 14 #include <linux/platform_device.h> 15 16 #define RPM_BUS_MASTER_REQ 0x73616d62 17 #define RPM_BUS_SLAVE_REQ 0x766c7362 18 19 #define to_qcom_provider(_provider) \ 20 container_of(_provider, struct qcom_icc_provider, provider) 21 22 enum qcom_icc_type { 23 QCOM_ICC_NOC, 24 QCOM_ICC_BIMC, 25 QCOM_ICC_QNOC, 26 }; 27 28 /** 29 * struct rpm_clk_resource - RPM bus clock resource 30 * @resource_type: RPM resource type of the clock resource 31 * @clock_id: index of the clock resource of a specific resource type 32 * @branch: whether the resource represents a branch clock 33 */ 34 struct rpm_clk_resource { 35 u32 resource_type; 36 u32 clock_id; 37 bool branch; 38 }; 39 40 /** 41 * struct qcom_icc_provider - Qualcomm specific interconnect provider 42 * @provider: generic interconnect provider 43 * @num_intf_clks: the total number of intf_clks clk_bulk_data entries 44 * @type: the ICC provider type 45 * @regmap: regmap for QoS registers read/write access 46 * @qos_offset: offset to QoS registers 47 * @bus_clk_rate: bus clock rate in Hz 48 * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks 49 * @bus_clk: a pointer to a HLOS-owned bus clock 50 * @intf_clks: a clk_bulk_data array of interface clocks 51 * @keep_alive: whether to always keep a minimum vote on the bus clocks 52 * @is_on: whether the bus is powered on 53 */ 54 struct qcom_icc_provider { 55 struct icc_provider provider; 56 int num_intf_clks; 57 enum qcom_icc_type type; 58 struct regmap *regmap; 59 unsigned int qos_offset; 60 u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; 61 const struct rpm_clk_resource *bus_clk_desc; 62 struct clk *bus_clk; 63 struct clk_bulk_data *intf_clks; 64 bool keep_alive; 65 bool is_on; 66 }; 67 68 /** 69 * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters 70 * @areq_prio: node requests priority 71 * @prio_level: priority level for bus communication 72 * @limit_commands: activate/deactivate limiter mode during runtime 73 * @ap_owned: indicates if the node is owned by the AP or by the RPM 74 * @qos_mode: default qos mode for this node 75 * @qos_port: qos port number for finding qos registers of this node 76 * @urg_fwd_en: enable urgent forwarding 77 */ 78 struct qcom_icc_qos { 79 u32 areq_prio; 80 u32 prio_level; 81 bool limit_commands; 82 bool ap_owned; 83 int qos_mode; 84 int qos_port; 85 bool urg_fwd_en; 86 }; 87 88 /** 89 * struct qcom_icc_node - Qualcomm specific interconnect nodes 90 * @name: the node name used in debugfs 91 * @id: a unique node identifier 92 * @links: an array of nodes where we can go next while traversing 93 * @num_links: the total number of @links 94 * @channels: number of channels at this node (e.g. DDR channels) 95 * @buswidth: width of the interconnect between a node and the bus (bytes) 96 * @sum_avg: current sum aggregate value of all avg bw requests 97 * @max_peak: current max aggregate value of all peak bw requests 98 * @mas_rpm_id: RPM id for devices that are bus masters 99 * @slv_rpm_id: RPM id for devices that are bus slaves 100 * @qos: NoC QoS setting parameters 101 */ 102 struct qcom_icc_node { 103 unsigned char *name; 104 u16 id; 105 const u16 *links; 106 u16 num_links; 107 u16 channels; 108 u16 buswidth; 109 u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; 110 u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; 111 int mas_rpm_id; 112 int slv_rpm_id; 113 struct qcom_icc_qos qos; 114 }; 115 116 struct qcom_icc_desc { 117 struct qcom_icc_node * const *nodes; 118 size_t num_nodes; 119 const struct rpm_clk_resource *bus_clk_desc; 120 const char * const *intf_clocks; 121 size_t num_intf_clocks; 122 bool keep_alive; 123 enum qcom_icc_type type; 124 const struct regmap_config *regmap_cfg; 125 unsigned int qos_offset; 126 }; 127 128 /* Valid for all bus types */ 129 enum qos_mode { 130 NOC_QOS_MODE_INVALID = 0, 131 NOC_QOS_MODE_FIXED, 132 NOC_QOS_MODE_BYPASS, 133 }; 134 135 extern const struct rpm_clk_resource aggre1_clk; 136 extern const struct rpm_clk_resource aggre2_clk; 137 extern const struct rpm_clk_resource bimc_clk; 138 extern const struct rpm_clk_resource bus_0_clk; 139 extern const struct rpm_clk_resource bus_1_clk; 140 extern const struct rpm_clk_resource bus_2_clk; 141 extern const struct rpm_clk_resource mmaxi_0_clk; 142 extern const struct rpm_clk_resource mmaxi_1_clk; 143 extern const struct rpm_clk_resource qup_clk; 144 145 extern const struct rpm_clk_resource aggre1_branch_clk; 146 extern const struct rpm_clk_resource aggre2_branch_clk; 147 148 int qnoc_probe(struct platform_device *pdev); 149 int qnoc_remove(struct platform_device *pdev); 150 151 bool qcom_icc_rpm_smd_available(void); 152 int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); 153 int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 rate); 154 155 #endif 156