162feb14eSJun Nie /* SPDX-License-Identifier: GPL-2.0 */ 262feb14eSJun Nie /* 362feb14eSJun Nie * Copyright (C) 2020 Linaro Ltd 462feb14eSJun Nie */ 562feb14eSJun Nie 662feb14eSJun Nie #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 762feb14eSJun Nie #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 862feb14eSJun Nie 9*dcbce7b0SLeo Yan #include <dt-bindings/interconnect/qcom,icc.h> 10*dcbce7b0SLeo Yan 1162feb14eSJun Nie #define RPM_BUS_MASTER_REQ 0x73616d62 1262feb14eSJun Nie #define RPM_BUS_SLAVE_REQ 0x766c7362 1362feb14eSJun Nie 1462feb14eSJun Nie #define to_qcom_provider(_provider) \ 1562feb14eSJun Nie container_of(_provider, struct qcom_icc_provider, provider) 1662feb14eSJun Nie 17e9d54c26SShawn Guo enum qcom_icc_type { 18e9d54c26SShawn Guo QCOM_ICC_NOC, 19e9d54c26SShawn Guo QCOM_ICC_BIMC, 2008c59040SShawn Guo QCOM_ICC_QNOC, 21e9d54c26SShawn Guo }; 22e9d54c26SShawn Guo 2362feb14eSJun Nie /** 2462feb14eSJun Nie * struct qcom_icc_provider - Qualcomm specific interconnect provider 2562feb14eSJun Nie * @provider: generic interconnect provider 2662feb14eSJun Nie * @bus_clks: the clk_bulk_data table of bus clocks 2762feb14eSJun Nie * @num_clks: the total number of clk_bulk_data entries 28e9d54c26SShawn Guo * @type: the ICC provider type 290788f4d5SDmitry Baryshkov * @qos_offset: offset to QoS registers 302b6c7d64SDmitry Baryshkov * @regmap: regmap for QoS registers read/write access 3165fac3b3SLeo Yan * @bus_clk_rate: bus clock rate in Hz 3262feb14eSJun Nie */ 3362feb14eSJun Nie struct qcom_icc_provider { 3462feb14eSJun Nie struct icc_provider provider; 3562feb14eSJun Nie int num_clks; 36e9d54c26SShawn Guo enum qcom_icc_type type; 372b6c7d64SDmitry Baryshkov struct regmap *regmap; 380788f4d5SDmitry Baryshkov unsigned int qos_offset; 3997f7d384SLeo Yan u64 *bus_clk_rate; 4063e8ab61SDmitry Baryshkov struct clk_bulk_data bus_clks[]; 4162feb14eSJun Nie }; 4262feb14eSJun Nie 4362feb14eSJun Nie /** 442b6c7d64SDmitry Baryshkov * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters 452b6c7d64SDmitry Baryshkov * @areq_prio: node requests priority 462b6c7d64SDmitry Baryshkov * @prio_level: priority level for bus communication 472b6c7d64SDmitry Baryshkov * @limit_commands: activate/deactivate limiter mode during runtime 482b6c7d64SDmitry Baryshkov * @ap_owned: indicates if the node is owned by the AP or by the RPM 492b6c7d64SDmitry Baryshkov * @qos_mode: default qos mode for this node 502b6c7d64SDmitry Baryshkov * @qos_port: qos port number for finding qos registers of this node 5108c59040SShawn Guo * @urg_fwd_en: enable urgent forwarding 522b6c7d64SDmitry Baryshkov */ 532b6c7d64SDmitry Baryshkov struct qcom_icc_qos { 542b6c7d64SDmitry Baryshkov u32 areq_prio; 552b6c7d64SDmitry Baryshkov u32 prio_level; 562b6c7d64SDmitry Baryshkov bool limit_commands; 572b6c7d64SDmitry Baryshkov bool ap_owned; 582b6c7d64SDmitry Baryshkov int qos_mode; 592b6c7d64SDmitry Baryshkov int qos_port; 6008c59040SShawn Guo bool urg_fwd_en; 612b6c7d64SDmitry Baryshkov }; 622b6c7d64SDmitry Baryshkov 632b6c7d64SDmitry Baryshkov /** 6462feb14eSJun Nie * struct qcom_icc_node - Qualcomm specific interconnect nodes 6562feb14eSJun Nie * @name: the node name used in debugfs 6662feb14eSJun Nie * @id: a unique node identifier 6762feb14eSJun Nie * @links: an array of nodes where we can go next while traversing 6862feb14eSJun Nie * @num_links: the total number of @links 6962feb14eSJun Nie * @buswidth: width of the interconnect between a node and the bus (bytes) 70*dcbce7b0SLeo Yan * @sum_avg: current sum aggregate value of all avg bw requests 71*dcbce7b0SLeo Yan * @max_peak: current max aggregate value of all peak bw requests 7262feb14eSJun Nie * @mas_rpm_id: RPM id for devices that are bus masters 7362feb14eSJun Nie * @slv_rpm_id: RPM id for devices that are bus slaves 742b6c7d64SDmitry Baryshkov * @qos: NoC QoS setting parameters 7562feb14eSJun Nie */ 7662feb14eSJun Nie struct qcom_icc_node { 7762feb14eSJun Nie unsigned char *name; 7862feb14eSJun Nie u16 id; 792b6c7d64SDmitry Baryshkov const u16 *links; 8062feb14eSJun Nie u16 num_links; 8162feb14eSJun Nie u16 buswidth; 82*dcbce7b0SLeo Yan u64 sum_avg[QCOM_ICC_NUM_BUCKETS]; 83*dcbce7b0SLeo Yan u64 max_peak[QCOM_ICC_NUM_BUCKETS]; 8462feb14eSJun Nie int mas_rpm_id; 8562feb14eSJun Nie int slv_rpm_id; 862b6c7d64SDmitry Baryshkov struct qcom_icc_qos qos; 8762feb14eSJun Nie }; 8862feb14eSJun Nie 8962feb14eSJun Nie struct qcom_icc_desc { 902ccf33c0SKrzysztof Kozlowski struct qcom_icc_node * const *nodes; 9162feb14eSJun Nie size_t num_nodes; 922b6c7d64SDmitry Baryshkov const char * const *clocks; 932b6c7d64SDmitry Baryshkov size_t num_clocks; 947de109c0SYassine Oudjana bool has_bus_pd; 95e9d54c26SShawn Guo enum qcom_icc_type type; 962b6c7d64SDmitry Baryshkov const struct regmap_config *regmap_cfg; 970788f4d5SDmitry Baryshkov unsigned int qos_offset; 9862feb14eSJun Nie }; 9962feb14eSJun Nie 1002b6c7d64SDmitry Baryshkov /* Valid for both NoC and BIMC */ 1012b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_INVALID -1 1022b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_FIXED 0x0 1032b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_BYPASS 0x2 10462feb14eSJun Nie 10563e8ab61SDmitry Baryshkov int qnoc_probe(struct platform_device *pdev); 10662feb14eSJun Nie int qnoc_remove(struct platform_device *pdev); 10762feb14eSJun Nie 10862feb14eSJun Nie #endif 109