162feb14eSJun Nie /* SPDX-License-Identifier: GPL-2.0 */ 262feb14eSJun Nie /* 362feb14eSJun Nie * Copyright (C) 2020 Linaro Ltd 462feb14eSJun Nie */ 562feb14eSJun Nie 662feb14eSJun Nie #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 762feb14eSJun Nie #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 862feb14eSJun Nie 919ced2aeSKonrad Dybcio #include <linux/soc/qcom/smd-rpm.h> 1019ced2aeSKonrad Dybcio 11dcbce7b0SLeo Yan #include <dt-bindings/interconnect/qcom,icc.h> 1240cdeed6SKonrad Dybcio #include <linux/clk.h> 1340cdeed6SKonrad Dybcio #include <linux/interconnect-provider.h> 1440cdeed6SKonrad Dybcio #include <linux/platform_device.h> 15dcbce7b0SLeo Yan 1662feb14eSJun Nie #define RPM_BUS_MASTER_REQ 0x73616d62 1762feb14eSJun Nie #define RPM_BUS_SLAVE_REQ 0x766c7362 1862feb14eSJun Nie 1962feb14eSJun Nie #define to_qcom_provider(_provider) \ 2062feb14eSJun Nie container_of(_provider, struct qcom_icc_provider, provider) 2162feb14eSJun Nie 22e9d54c26SShawn Guo enum qcom_icc_type { 23e9d54c26SShawn Guo QCOM_ICC_NOC, 24e9d54c26SShawn Guo QCOM_ICC_BIMC, 2508c59040SShawn Guo QCOM_ICC_QNOC, 26e9d54c26SShawn Guo }; 27e9d54c26SShawn Guo 28a927eb09SKonrad Dybcio /** 29a927eb09SKonrad Dybcio * struct rpm_clk_resource - RPM bus clock resource 30a927eb09SKonrad Dybcio * @resource_type: RPM resource type of the clock resource 31a927eb09SKonrad Dybcio * @clock_id: index of the clock resource of a specific resource type 32a927eb09SKonrad Dybcio * @branch: whether the resource represents a branch clock 33a927eb09SKonrad Dybcio */ 34a927eb09SKonrad Dybcio struct rpm_clk_resource { 35a927eb09SKonrad Dybcio u32 resource_type; 36a927eb09SKonrad Dybcio u32 clock_id; 37a927eb09SKonrad Dybcio bool branch; 38a927eb09SKonrad Dybcio }; 39a927eb09SKonrad Dybcio 402e2113c8SKonrad Dybcio #define NUM_BUS_CLKS 2 412e2113c8SKonrad Dybcio 4262feb14eSJun Nie /** 4362feb14eSJun Nie * struct qcom_icc_provider - Qualcomm specific interconnect provider 4462feb14eSJun Nie * @provider: generic interconnect provider 45a867cf9bSKonrad Dybcio * @num_bus_clks: the total number of bus_clks clk_bulk_data entries (0 or 2) 462e2113c8SKonrad Dybcio * @num_intf_clks: the total number of intf_clks clk_bulk_data entries 47e9d54c26SShawn Guo * @type: the ICC provider type 482b6c7d64SDmitry Baryshkov * @regmap: regmap for QoS registers read/write access 4982a4b285SKonrad Dybcio * @qos_offset: offset to QoS registers 5065fac3b3SLeo Yan * @bus_clk_rate: bus clock rate in Hz 5182a4b285SKonrad Dybcio * @bus_clks: the clk_bulk_data table of bus clocks 522e2113c8SKonrad Dybcio * @intf_clks: a clk_bulk_data array of interface clocks 53b979049cSKonrad Dybcio * @keep_alive: whether to always keep a minimum vote on the bus clocks 542e2113c8SKonrad Dybcio * @is_on: whether the bus is powered on 5562feb14eSJun Nie */ 5662feb14eSJun Nie struct qcom_icc_provider { 5762feb14eSJun Nie struct icc_provider provider; 581a12928eSKonrad Dybcio int num_bus_clks; 592e2113c8SKonrad Dybcio int num_intf_clks; 60e9d54c26SShawn Guo enum qcom_icc_type type; 612b6c7d64SDmitry Baryshkov struct regmap *regmap; 620788f4d5SDmitry Baryshkov unsigned int qos_offset; 632e2113c8SKonrad Dybcio u64 bus_clk_rate[NUM_BUS_CLKS]; 642e2113c8SKonrad Dybcio struct clk_bulk_data bus_clks[NUM_BUS_CLKS]; 65a927eb09SKonrad Dybcio const struct rpm_clk_resource *bus_clk_desc; 662e2113c8SKonrad Dybcio struct clk_bulk_data *intf_clks; 67b979049cSKonrad Dybcio bool keep_alive; 682e2113c8SKonrad Dybcio bool is_on; 6962feb14eSJun Nie }; 7062feb14eSJun Nie 7162feb14eSJun Nie /** 722b6c7d64SDmitry Baryshkov * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters 732b6c7d64SDmitry Baryshkov * @areq_prio: node requests priority 742b6c7d64SDmitry Baryshkov * @prio_level: priority level for bus communication 752b6c7d64SDmitry Baryshkov * @limit_commands: activate/deactivate limiter mode during runtime 762b6c7d64SDmitry Baryshkov * @ap_owned: indicates if the node is owned by the AP or by the RPM 772b6c7d64SDmitry Baryshkov * @qos_mode: default qos mode for this node 782b6c7d64SDmitry Baryshkov * @qos_port: qos port number for finding qos registers of this node 7908c59040SShawn Guo * @urg_fwd_en: enable urgent forwarding 802b6c7d64SDmitry Baryshkov */ 812b6c7d64SDmitry Baryshkov struct qcom_icc_qos { 822b6c7d64SDmitry Baryshkov u32 areq_prio; 832b6c7d64SDmitry Baryshkov u32 prio_level; 842b6c7d64SDmitry Baryshkov bool limit_commands; 852b6c7d64SDmitry Baryshkov bool ap_owned; 862b6c7d64SDmitry Baryshkov int qos_mode; 872b6c7d64SDmitry Baryshkov int qos_port; 8808c59040SShawn Guo bool urg_fwd_en; 892b6c7d64SDmitry Baryshkov }; 902b6c7d64SDmitry Baryshkov 912b6c7d64SDmitry Baryshkov /** 9262feb14eSJun Nie * struct qcom_icc_node - Qualcomm specific interconnect nodes 9362feb14eSJun Nie * @name: the node name used in debugfs 9462feb14eSJun Nie * @id: a unique node identifier 9562feb14eSJun Nie * @links: an array of nodes where we can go next while traversing 9662feb14eSJun Nie * @num_links: the total number of @links 9702819953SKonrad Dybcio * @channels: number of channels at this node (e.g. DDR channels) 9862feb14eSJun Nie * @buswidth: width of the interconnect between a node and the bus (bytes) 99dcbce7b0SLeo Yan * @sum_avg: current sum aggregate value of all avg bw requests 100dcbce7b0SLeo Yan * @max_peak: current max aggregate value of all peak bw requests 10162feb14eSJun Nie * @mas_rpm_id: RPM id for devices that are bus masters 10262feb14eSJun Nie * @slv_rpm_id: RPM id for devices that are bus slaves 1032b6c7d64SDmitry Baryshkov * @qos: NoC QoS setting parameters 10462feb14eSJun Nie */ 10562feb14eSJun Nie struct qcom_icc_node { 10662feb14eSJun Nie unsigned char *name; 10762feb14eSJun Nie u16 id; 1082b6c7d64SDmitry Baryshkov const u16 *links; 10962feb14eSJun Nie u16 num_links; 11002819953SKonrad Dybcio u16 channels; 11162feb14eSJun Nie u16 buswidth; 112dcbce7b0SLeo Yan u64 sum_avg[QCOM_ICC_NUM_BUCKETS]; 113dcbce7b0SLeo Yan u64 max_peak[QCOM_ICC_NUM_BUCKETS]; 11462feb14eSJun Nie int mas_rpm_id; 11562feb14eSJun Nie int slv_rpm_id; 1162b6c7d64SDmitry Baryshkov struct qcom_icc_qos qos; 11762feb14eSJun Nie }; 11862feb14eSJun Nie 11962feb14eSJun Nie struct qcom_icc_desc { 1202ccf33c0SKrzysztof Kozlowski struct qcom_icc_node * const *nodes; 12162feb14eSJun Nie size_t num_nodes; 1226643b532SKonrad Dybcio const char * const *bus_clocks; 123a927eb09SKonrad Dybcio const struct rpm_clk_resource *bus_clk_desc; 1242e2113c8SKonrad Dybcio const char * const *intf_clocks; 1252e2113c8SKonrad Dybcio size_t num_intf_clocks; 126b979049cSKonrad Dybcio bool keep_alive; 127a867cf9bSKonrad Dybcio bool no_clk_scaling; 128e9d54c26SShawn Guo enum qcom_icc_type type; 1292b6c7d64SDmitry Baryshkov const struct regmap_config *regmap_cfg; 1300788f4d5SDmitry Baryshkov unsigned int qos_offset; 13162feb14eSJun Nie }; 13262feb14eSJun Nie 1331d779317SKonrad Dybcio /* Valid for all bus types */ 1341d779317SKonrad Dybcio enum qos_mode { 1351d779317SKonrad Dybcio NOC_QOS_MODE_INVALID = 0, 1361d779317SKonrad Dybcio NOC_QOS_MODE_FIXED, 1371d779317SKonrad Dybcio NOC_QOS_MODE_BYPASS, 1381d779317SKonrad Dybcio }; 13962feb14eSJun Nie 140*918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre1_clk; 141*918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre2_clk; 142*918b8604SKonrad Dybcio extern const struct rpm_clk_resource bimc_clk; 143*918b8604SKonrad Dybcio extern const struct rpm_clk_resource bus_0_clk; 144*918b8604SKonrad Dybcio extern const struct rpm_clk_resource bus_1_clk; 145*918b8604SKonrad Dybcio extern const struct rpm_clk_resource bus_2_clk; 146*918b8604SKonrad Dybcio extern const struct rpm_clk_resource mmaxi_0_clk; 147*918b8604SKonrad Dybcio extern const struct rpm_clk_resource mmaxi_1_clk; 148*918b8604SKonrad Dybcio extern const struct rpm_clk_resource qup_clk; 149*918b8604SKonrad Dybcio 150*918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre1_branch_clk; 151*918b8604SKonrad Dybcio extern const struct rpm_clk_resource aggre2_branch_clk; 152*918b8604SKonrad Dybcio 15363e8ab61SDmitry Baryshkov int qnoc_probe(struct platform_device *pdev); 15462feb14eSJun Nie int qnoc_remove(struct platform_device *pdev); 15562feb14eSJun Nie 15619ced2aeSKonrad Dybcio bool qcom_icc_rpm_smd_available(void); 15719ced2aeSKonrad Dybcio int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); 158a927eb09SKonrad Dybcio int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 rate); 15919ced2aeSKonrad Dybcio 16062feb14eSJun Nie #endif 161