162feb14eSJun Nie /* SPDX-License-Identifier: GPL-2.0 */
262feb14eSJun Nie /*
362feb14eSJun Nie  * Copyright (C) 2020 Linaro Ltd
462feb14eSJun Nie  */
562feb14eSJun Nie 
662feb14eSJun Nie #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
762feb14eSJun Nie #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
862feb14eSJun Nie 
962feb14eSJun Nie #define RPM_BUS_MASTER_REQ	0x73616d62
1062feb14eSJun Nie #define RPM_BUS_SLAVE_REQ	0x766c7362
1162feb14eSJun Nie 
1262feb14eSJun Nie #define to_qcom_provider(_provider) \
1362feb14eSJun Nie 	container_of(_provider, struct qcom_icc_provider, provider)
1462feb14eSJun Nie 
15e9d54c26SShawn Guo enum qcom_icc_type {
16e9d54c26SShawn Guo 	QCOM_ICC_NOC,
17e9d54c26SShawn Guo 	QCOM_ICC_BIMC,
1808c59040SShawn Guo 	QCOM_ICC_QNOC,
19e9d54c26SShawn Guo };
20e9d54c26SShawn Guo 
2162feb14eSJun Nie /**
2262feb14eSJun Nie  * struct qcom_icc_provider - Qualcomm specific interconnect provider
2362feb14eSJun Nie  * @provider: generic interconnect provider
2462feb14eSJun Nie  * @bus_clks: the clk_bulk_data table of bus clocks
2562feb14eSJun Nie  * @num_clks: the total number of clk_bulk_data entries
26e9d54c26SShawn Guo  * @type: the ICC provider type
270788f4d5SDmitry Baryshkov  * @qos_offset: offset to QoS registers
282b6c7d64SDmitry Baryshkov  * @regmap: regmap for QoS registers read/write access
29*65fac3b3SLeo Yan  * @bus_clk_rate: bus clock rate in Hz
3062feb14eSJun Nie  */
3162feb14eSJun Nie struct qcom_icc_provider {
3262feb14eSJun Nie 	struct icc_provider provider;
3362feb14eSJun Nie 	int num_clks;
34e9d54c26SShawn Guo 	enum qcom_icc_type type;
352b6c7d64SDmitry Baryshkov 	struct regmap *regmap;
360788f4d5SDmitry Baryshkov 	unsigned int qos_offset;
37*65fac3b3SLeo Yan 	u64 bus_clk_rate;
3863e8ab61SDmitry Baryshkov 	struct clk_bulk_data bus_clks[];
3962feb14eSJun Nie };
4062feb14eSJun Nie 
4162feb14eSJun Nie /**
422b6c7d64SDmitry Baryshkov  * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
432b6c7d64SDmitry Baryshkov  * @areq_prio: node requests priority
442b6c7d64SDmitry Baryshkov  * @prio_level: priority level for bus communication
452b6c7d64SDmitry Baryshkov  * @limit_commands: activate/deactivate limiter mode during runtime
462b6c7d64SDmitry Baryshkov  * @ap_owned: indicates if the node is owned by the AP or by the RPM
472b6c7d64SDmitry Baryshkov  * @qos_mode: default qos mode for this node
482b6c7d64SDmitry Baryshkov  * @qos_port: qos port number for finding qos registers of this node
4908c59040SShawn Guo  * @urg_fwd_en: enable urgent forwarding
502b6c7d64SDmitry Baryshkov  */
512b6c7d64SDmitry Baryshkov struct qcom_icc_qos {
522b6c7d64SDmitry Baryshkov 	u32 areq_prio;
532b6c7d64SDmitry Baryshkov 	u32 prio_level;
542b6c7d64SDmitry Baryshkov 	bool limit_commands;
552b6c7d64SDmitry Baryshkov 	bool ap_owned;
562b6c7d64SDmitry Baryshkov 	int qos_mode;
572b6c7d64SDmitry Baryshkov 	int qos_port;
5808c59040SShawn Guo 	bool urg_fwd_en;
592b6c7d64SDmitry Baryshkov };
602b6c7d64SDmitry Baryshkov 
612b6c7d64SDmitry Baryshkov /**
6262feb14eSJun Nie  * struct qcom_icc_node - Qualcomm specific interconnect nodes
6362feb14eSJun Nie  * @name: the node name used in debugfs
6462feb14eSJun Nie  * @id: a unique node identifier
6562feb14eSJun Nie  * @links: an array of nodes where we can go next while traversing
6662feb14eSJun Nie  * @num_links: the total number of @links
6762feb14eSJun Nie  * @buswidth: width of the interconnect between a node and the bus (bytes)
6862feb14eSJun Nie  * @mas_rpm_id:	RPM id for devices that are bus masters
6962feb14eSJun Nie  * @slv_rpm_id:	RPM id for devices that are bus slaves
702b6c7d64SDmitry Baryshkov  * @qos: NoC QoS setting parameters
7162feb14eSJun Nie  */
7262feb14eSJun Nie struct qcom_icc_node {
7362feb14eSJun Nie 	unsigned char *name;
7462feb14eSJun Nie 	u16 id;
752b6c7d64SDmitry Baryshkov 	const u16 *links;
7662feb14eSJun Nie 	u16 num_links;
7762feb14eSJun Nie 	u16 buswidth;
7862feb14eSJun Nie 	int mas_rpm_id;
7962feb14eSJun Nie 	int slv_rpm_id;
802b6c7d64SDmitry Baryshkov 	struct qcom_icc_qos qos;
8162feb14eSJun Nie };
8262feb14eSJun Nie 
8362feb14eSJun Nie struct qcom_icc_desc {
8462feb14eSJun Nie 	struct qcom_icc_node **nodes;
8562feb14eSJun Nie 	size_t num_nodes;
862b6c7d64SDmitry Baryshkov 	const char * const *clocks;
872b6c7d64SDmitry Baryshkov 	size_t num_clocks;
887de109c0SYassine Oudjana 	bool has_bus_pd;
89e9d54c26SShawn Guo 	enum qcom_icc_type type;
902b6c7d64SDmitry Baryshkov 	const struct regmap_config *regmap_cfg;
910788f4d5SDmitry Baryshkov 	unsigned int qos_offset;
9262feb14eSJun Nie };
9362feb14eSJun Nie 
942b6c7d64SDmitry Baryshkov /* Valid for both NoC and BIMC */
952b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_INVALID		-1
962b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_FIXED		0x0
972b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_BYPASS		0x2
9862feb14eSJun Nie 
9963e8ab61SDmitry Baryshkov int qnoc_probe(struct platform_device *pdev);
10062feb14eSJun Nie int qnoc_remove(struct platform_device *pdev);
10162feb14eSJun Nie 
10262feb14eSJun Nie #endif
103