162feb14eSJun Nie /* SPDX-License-Identifier: GPL-2.0 */ 262feb14eSJun Nie /* 362feb14eSJun Nie * Copyright (C) 2020 Linaro Ltd 462feb14eSJun Nie */ 562feb14eSJun Nie 662feb14eSJun Nie #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 762feb14eSJun Nie #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 862feb14eSJun Nie 962feb14eSJun Nie #define RPM_BUS_MASTER_REQ 0x73616d62 1062feb14eSJun Nie #define RPM_BUS_SLAVE_REQ 0x766c7362 1162feb14eSJun Nie 1262feb14eSJun Nie #define to_qcom_provider(_provider) \ 1362feb14eSJun Nie container_of(_provider, struct qcom_icc_provider, provider) 1462feb14eSJun Nie 1562feb14eSJun Nie /** 1662feb14eSJun Nie * struct qcom_icc_provider - Qualcomm specific interconnect provider 1762feb14eSJun Nie * @provider: generic interconnect provider 1862feb14eSJun Nie * @bus_clks: the clk_bulk_data table of bus clocks 1962feb14eSJun Nie * @num_clks: the total number of clk_bulk_data entries 20*2b6c7d64SDmitry Baryshkov * @is_bimc_node: indicates whether to use bimc specific setting 21*2b6c7d64SDmitry Baryshkov * @regmap: regmap for QoS registers read/write access 2262feb14eSJun Nie */ 2362feb14eSJun Nie struct qcom_icc_provider { 2462feb14eSJun Nie struct icc_provider provider; 2562feb14eSJun Nie int num_clks; 26*2b6c7d64SDmitry Baryshkov bool is_bimc_node; 27*2b6c7d64SDmitry Baryshkov struct regmap *regmap; 2863e8ab61SDmitry Baryshkov struct clk_bulk_data bus_clks[]; 2962feb14eSJun Nie }; 3062feb14eSJun Nie 3162feb14eSJun Nie /** 32*2b6c7d64SDmitry Baryshkov * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters 33*2b6c7d64SDmitry Baryshkov * @areq_prio: node requests priority 34*2b6c7d64SDmitry Baryshkov * @prio_level: priority level for bus communication 35*2b6c7d64SDmitry Baryshkov * @limit_commands: activate/deactivate limiter mode during runtime 36*2b6c7d64SDmitry Baryshkov * @ap_owned: indicates if the node is owned by the AP or by the RPM 37*2b6c7d64SDmitry Baryshkov * @qos_mode: default qos mode for this node 38*2b6c7d64SDmitry Baryshkov * @qos_port: qos port number for finding qos registers of this node 39*2b6c7d64SDmitry Baryshkov */ 40*2b6c7d64SDmitry Baryshkov struct qcom_icc_qos { 41*2b6c7d64SDmitry Baryshkov u32 areq_prio; 42*2b6c7d64SDmitry Baryshkov u32 prio_level; 43*2b6c7d64SDmitry Baryshkov bool limit_commands; 44*2b6c7d64SDmitry Baryshkov bool ap_owned; 45*2b6c7d64SDmitry Baryshkov int qos_mode; 46*2b6c7d64SDmitry Baryshkov int qos_port; 47*2b6c7d64SDmitry Baryshkov }; 48*2b6c7d64SDmitry Baryshkov 49*2b6c7d64SDmitry Baryshkov /** 5062feb14eSJun Nie * struct qcom_icc_node - Qualcomm specific interconnect nodes 5162feb14eSJun Nie * @name: the node name used in debugfs 5262feb14eSJun Nie * @id: a unique node identifier 5362feb14eSJun Nie * @links: an array of nodes where we can go next while traversing 5462feb14eSJun Nie * @num_links: the total number of @links 5562feb14eSJun Nie * @buswidth: width of the interconnect between a node and the bus (bytes) 5662feb14eSJun Nie * @mas_rpm_id: RPM id for devices that are bus masters 5762feb14eSJun Nie * @slv_rpm_id: RPM id for devices that are bus slaves 58*2b6c7d64SDmitry Baryshkov * @qos: NoC QoS setting parameters 5962feb14eSJun Nie * @rate: current bus clock rate in Hz 6062feb14eSJun Nie */ 6162feb14eSJun Nie struct qcom_icc_node { 6262feb14eSJun Nie unsigned char *name; 6362feb14eSJun Nie u16 id; 64*2b6c7d64SDmitry Baryshkov const u16 *links; 6562feb14eSJun Nie u16 num_links; 6662feb14eSJun Nie u16 buswidth; 6762feb14eSJun Nie int mas_rpm_id; 6862feb14eSJun Nie int slv_rpm_id; 69*2b6c7d64SDmitry Baryshkov struct qcom_icc_qos qos; 7062feb14eSJun Nie u64 rate; 7162feb14eSJun Nie }; 7262feb14eSJun Nie 7362feb14eSJun Nie struct qcom_icc_desc { 7462feb14eSJun Nie struct qcom_icc_node **nodes; 7562feb14eSJun Nie size_t num_nodes; 76*2b6c7d64SDmitry Baryshkov const char * const *clocks; 77*2b6c7d64SDmitry Baryshkov size_t num_clocks; 78*2b6c7d64SDmitry Baryshkov bool is_bimc_node; 79*2b6c7d64SDmitry Baryshkov const struct regmap_config *regmap_cfg; 8062feb14eSJun Nie }; 8162feb14eSJun Nie 8262feb14eSJun Nie #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ 8362feb14eSJun Nie ...) \ 84*2b6c7d64SDmitry Baryshkov static const u16 _name ## _links[] = { __VA_ARGS__ }; \ 85*2b6c7d64SDmitry Baryshkov \ 8662feb14eSJun Nie static struct qcom_icc_node _name = { \ 8762feb14eSJun Nie .name = #_name, \ 8862feb14eSJun Nie .id = _id, \ 8962feb14eSJun Nie .buswidth = _buswidth, \ 9062feb14eSJun Nie .mas_rpm_id = _mas_rpm_id, \ 9162feb14eSJun Nie .slv_rpm_id = _slv_rpm_id, \ 92*2b6c7d64SDmitry Baryshkov .num_links = ARRAY_SIZE(_name ## _links), \ 93*2b6c7d64SDmitry Baryshkov .links = _name ## _links, \ 9462feb14eSJun Nie } 9562feb14eSJun Nie 96*2b6c7d64SDmitry Baryshkov /* Valid for both NoC and BIMC */ 97*2b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_INVALID -1 98*2b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_FIXED 0x0 99*2b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_BYPASS 0x2 10062feb14eSJun Nie 10163e8ab61SDmitry Baryshkov int qnoc_probe(struct platform_device *pdev); 10262feb14eSJun Nie int qnoc_remove(struct platform_device *pdev); 10362feb14eSJun Nie 10462feb14eSJun Nie #endif 105