162feb14eSJun Nie /* SPDX-License-Identifier: GPL-2.0 */ 262feb14eSJun Nie /* 362feb14eSJun Nie * Copyright (C) 2020 Linaro Ltd 462feb14eSJun Nie */ 562feb14eSJun Nie 662feb14eSJun Nie #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 762feb14eSJun Nie #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H 862feb14eSJun Nie 962feb14eSJun Nie #define RPM_BUS_MASTER_REQ 0x73616d62 1062feb14eSJun Nie #define RPM_BUS_SLAVE_REQ 0x766c7362 1162feb14eSJun Nie 1262feb14eSJun Nie #define to_qcom_provider(_provider) \ 1362feb14eSJun Nie container_of(_provider, struct qcom_icc_provider, provider) 1462feb14eSJun Nie 15e9d54c26SShawn Guo enum qcom_icc_type { 16e9d54c26SShawn Guo QCOM_ICC_NOC, 17e9d54c26SShawn Guo QCOM_ICC_BIMC, 18*08c59040SShawn Guo QCOM_ICC_QNOC, 19e9d54c26SShawn Guo }; 20e9d54c26SShawn Guo 2162feb14eSJun Nie /** 2262feb14eSJun Nie * struct qcom_icc_provider - Qualcomm specific interconnect provider 2362feb14eSJun Nie * @provider: generic interconnect provider 2462feb14eSJun Nie * @bus_clks: the clk_bulk_data table of bus clocks 2562feb14eSJun Nie * @num_clks: the total number of clk_bulk_data entries 26e9d54c26SShawn Guo * @type: the ICC provider type 270788f4d5SDmitry Baryshkov * @qos_offset: offset to QoS registers 282b6c7d64SDmitry Baryshkov * @regmap: regmap for QoS registers read/write access 2962feb14eSJun Nie */ 3062feb14eSJun Nie struct qcom_icc_provider { 3162feb14eSJun Nie struct icc_provider provider; 3262feb14eSJun Nie int num_clks; 33e9d54c26SShawn Guo enum qcom_icc_type type; 342b6c7d64SDmitry Baryshkov struct regmap *regmap; 350788f4d5SDmitry Baryshkov unsigned int qos_offset; 3663e8ab61SDmitry Baryshkov struct clk_bulk_data bus_clks[]; 3762feb14eSJun Nie }; 3862feb14eSJun Nie 3962feb14eSJun Nie /** 402b6c7d64SDmitry Baryshkov * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters 412b6c7d64SDmitry Baryshkov * @areq_prio: node requests priority 422b6c7d64SDmitry Baryshkov * @prio_level: priority level for bus communication 432b6c7d64SDmitry Baryshkov * @limit_commands: activate/deactivate limiter mode during runtime 442b6c7d64SDmitry Baryshkov * @ap_owned: indicates if the node is owned by the AP or by the RPM 452b6c7d64SDmitry Baryshkov * @qos_mode: default qos mode for this node 462b6c7d64SDmitry Baryshkov * @qos_port: qos port number for finding qos registers of this node 47*08c59040SShawn Guo * @urg_fwd_en: enable urgent forwarding 482b6c7d64SDmitry Baryshkov */ 492b6c7d64SDmitry Baryshkov struct qcom_icc_qos { 502b6c7d64SDmitry Baryshkov u32 areq_prio; 512b6c7d64SDmitry Baryshkov u32 prio_level; 522b6c7d64SDmitry Baryshkov bool limit_commands; 532b6c7d64SDmitry Baryshkov bool ap_owned; 542b6c7d64SDmitry Baryshkov int qos_mode; 552b6c7d64SDmitry Baryshkov int qos_port; 56*08c59040SShawn Guo bool urg_fwd_en; 572b6c7d64SDmitry Baryshkov }; 582b6c7d64SDmitry Baryshkov 592b6c7d64SDmitry Baryshkov /** 6062feb14eSJun Nie * struct qcom_icc_node - Qualcomm specific interconnect nodes 6162feb14eSJun Nie * @name: the node name used in debugfs 6262feb14eSJun Nie * @id: a unique node identifier 6362feb14eSJun Nie * @links: an array of nodes where we can go next while traversing 6462feb14eSJun Nie * @num_links: the total number of @links 6562feb14eSJun Nie * @buswidth: width of the interconnect between a node and the bus (bytes) 6662feb14eSJun Nie * @mas_rpm_id: RPM id for devices that are bus masters 6762feb14eSJun Nie * @slv_rpm_id: RPM id for devices that are bus slaves 682b6c7d64SDmitry Baryshkov * @qos: NoC QoS setting parameters 6962feb14eSJun Nie * @rate: current bus clock rate in Hz 7062feb14eSJun Nie */ 7162feb14eSJun Nie struct qcom_icc_node { 7262feb14eSJun Nie unsigned char *name; 7362feb14eSJun Nie u16 id; 742b6c7d64SDmitry Baryshkov const u16 *links; 7562feb14eSJun Nie u16 num_links; 7662feb14eSJun Nie u16 buswidth; 7762feb14eSJun Nie int mas_rpm_id; 7862feb14eSJun Nie int slv_rpm_id; 792b6c7d64SDmitry Baryshkov struct qcom_icc_qos qos; 8062feb14eSJun Nie u64 rate; 8162feb14eSJun Nie }; 8262feb14eSJun Nie 8362feb14eSJun Nie struct qcom_icc_desc { 8462feb14eSJun Nie struct qcom_icc_node **nodes; 8562feb14eSJun Nie size_t num_nodes; 862b6c7d64SDmitry Baryshkov const char * const *clocks; 872b6c7d64SDmitry Baryshkov size_t num_clocks; 887de109c0SYassine Oudjana bool has_bus_pd; 89e9d54c26SShawn Guo enum qcom_icc_type type; 902b6c7d64SDmitry Baryshkov const struct regmap_config *regmap_cfg; 910788f4d5SDmitry Baryshkov unsigned int qos_offset; 9262feb14eSJun Nie }; 9362feb14eSJun Nie 942b6c7d64SDmitry Baryshkov /* Valid for both NoC and BIMC */ 952b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_INVALID -1 962b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_FIXED 0x0 972b6c7d64SDmitry Baryshkov #define NOC_QOS_MODE_BYPASS 0x2 9862feb14eSJun Nie 9963e8ab61SDmitry Baryshkov int qnoc_probe(struct platform_device *pdev); 10062feb14eSJun Nie int qnoc_remove(struct platform_device *pdev); 10162feb14eSJun Nie 10262feb14eSJun Nie #endif 103