1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Interconnect framework driver for i.MX8MP SoC
4  *
5  * Copyright 2022 NXP
6  * Peng Fan <peng.fan@nxp.com>
7  */
8 
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 
13 #include "imx.h"
14 
15 static const struct imx_icc_node_adj_desc imx8mp_noc_adj = {
16 	.bw_mul = 1,
17 	.bw_div = 16,
18 	.main_noc = true,
19 };
20 
21 static struct imx_icc_noc_setting noc_setting_nodes[] = {
22 	[IMX8MP_ICM_MLMIX] = {
23 		.reg = 0x180,
24 		.mode = IMX_NOC_MODE_FIXED,
25 		.prio_level = 3,
26 	},
27 	[IMX8MP_ICM_DSP] = {
28 		.reg = 0x200,
29 		.mode = IMX_NOC_MODE_FIXED,
30 		.prio_level = 3,
31 	},
32 	[IMX8MP_ICM_SDMA2PER] = {
33 		.reg = 0x280,
34 		.mode = IMX_NOC_MODE_FIXED,
35 		.prio_level = 4,
36 	},
37 	[IMX8MP_ICM_SDMA2BURST] = {
38 		.reg = 0x300,
39 		.mode = IMX_NOC_MODE_FIXED,
40 		.prio_level = 4,
41 	},
42 	[IMX8MP_ICM_SDMA3PER] = {
43 		.reg = 0x380,
44 		.mode = IMX_NOC_MODE_FIXED,
45 		.prio_level = 4,
46 	},
47 	[IMX8MP_ICM_SDMA3BURST] = {
48 		.reg = 0x400,
49 		.mode = IMX_NOC_MODE_FIXED,
50 		.prio_level = 4,
51 	},
52 	[IMX8MP_ICM_EDMA] = {
53 		.reg = 0x480,
54 		.mode = IMX_NOC_MODE_FIXED,
55 		.prio_level = 4,
56 	},
57 	[IMX8MP_ICM_GPU3D] = {
58 		.reg = 0x500,
59 		.mode = IMX_NOC_MODE_FIXED,
60 		.prio_level = 3,
61 	},
62 	[IMX8MP_ICM_GPU2D] = {
63 		.reg = 0x580,
64 		.mode = IMX_NOC_MODE_FIXED,
65 		.prio_level = 3,
66 	},
67 	[IMX8MP_ICM_HRV] = {
68 		.reg = 0x600,
69 		.mode = IMX_NOC_MODE_FIXED,
70 		.prio_level = 2,
71 		.ext_control = 1,
72 	},
73 	[IMX8MP_ICM_LCDIF_HDMI] = {
74 		.reg = 0x680,
75 		.mode = IMX_NOC_MODE_FIXED,
76 		.prio_level = 2,
77 		.ext_control = 1,
78 	},
79 	[IMX8MP_ICM_HDCP] = {
80 		.reg = 0x700,
81 		.mode = IMX_NOC_MODE_FIXED,
82 		.prio_level = 5,
83 	},
84 	[IMX8MP_ICM_NOC_PCIE] = {
85 		.reg = 0x780,
86 		.mode = IMX_NOC_MODE_FIXED,
87 		.prio_level = 3,
88 	},
89 	[IMX8MP_ICM_USB1] = {
90 		.reg = 0x800,
91 		.mode = IMX_NOC_MODE_FIXED,
92 		.prio_level = 3,
93 	},
94 	[IMX8MP_ICM_USB2] = {
95 		.reg = 0x880,
96 		.mode = IMX_NOC_MODE_FIXED,
97 		.prio_level = 3,
98 	},
99 	[IMX8MP_ICM_PCIE] = {
100 		.reg = 0x900,
101 		.mode = IMX_NOC_MODE_FIXED,
102 		.prio_level = 3,
103 	},
104 	[IMX8MP_ICM_LCDIF_RD] = {
105 		.reg = 0x980,
106 		.mode = IMX_NOC_MODE_FIXED,
107 		.prio_level = 2,
108 		.ext_control = 1,
109 	},
110 	[IMX8MP_ICM_LCDIF_WR] = {
111 		.reg = 0xa00,
112 		.mode = IMX_NOC_MODE_FIXED,
113 		.prio_level = 2,
114 		.ext_control = 1,
115 	},
116 	[IMX8MP_ICM_ISI0] = {
117 		.reg = 0xa80,
118 		.mode = IMX_NOC_MODE_FIXED,
119 		.prio_level = 2,
120 		.ext_control = 1,
121 	},
122 	[IMX8MP_ICM_ISI1] = {
123 		.reg = 0xb00,
124 		.mode = IMX_NOC_MODE_FIXED,
125 		.prio_level = 2,
126 		.ext_control = 1,
127 	},
128 	[IMX8MP_ICM_ISI2] = {
129 		.reg = 0xb80,
130 		.mode = IMX_NOC_MODE_FIXED,
131 		.prio_level = 2,
132 		.ext_control = 1,
133 	},
134 	[IMX8MP_ICM_ISP0] = {
135 		.reg = 0xc00,
136 		.mode = IMX_NOC_MODE_FIXED,
137 		.prio_level = 7,
138 	},
139 	[IMX8MP_ICM_ISP1] = {
140 		.reg = 0xc80,
141 		.mode = IMX_NOC_MODE_FIXED,
142 		.prio_level = 7,
143 	},
144 	[IMX8MP_ICM_DWE] = {
145 		.reg = 0xd00,
146 		.mode = IMX_NOC_MODE_FIXED,
147 		.prio_level = 7,
148 	},
149 	[IMX8MP_ICM_VPU_G1] = {
150 		.reg = 0xd80,
151 		.mode = IMX_NOC_MODE_FIXED,
152 		.prio_level = 3,
153 	},
154 	[IMX8MP_ICM_VPU_G2] = {
155 		.reg = 0xe00,
156 		.mode = IMX_NOC_MODE_FIXED,
157 		.prio_level = 3,
158 	},
159 	[IMX8MP_ICM_VPU_H1] = {
160 		.reg = 0xe80,
161 		.mode = IMX_NOC_MODE_FIXED,
162 		.prio_level = 3,
163 	},
164 	[IMX8MP_ICN_MEDIA] = {
165 		.mode = IMX_NOC_MODE_UNCONFIGURED,
166 	},
167 	[IMX8MP_ICN_VIDEO] = {
168 		.mode = IMX_NOC_MODE_UNCONFIGURED,
169 	},
170 	[IMX8MP_ICN_AUDIO] = {
171 		.mode = IMX_NOC_MODE_UNCONFIGURED,
172 	},
173 	[IMX8MP_ICN_HDMI] = {
174 		.mode = IMX_NOC_MODE_UNCONFIGURED,
175 	},
176 	[IMX8MP_ICN_GPU] = {
177 		.mode = IMX_NOC_MODE_UNCONFIGURED,
178 	},
179 	[IMX8MP_ICN_HSIO] = {
180 		.mode = IMX_NOC_MODE_UNCONFIGURED,
181 	},
182 };
183 
184 /* Describe bus masters, slaves and connections between them */
185 static struct imx_icc_node_desc nodes[] = {
186 	DEFINE_BUS_INTERCONNECT("NOC", IMX8MP_ICN_NOC, &imx8mp_noc_adj,
187 				IMX8MP_ICS_DRAM, IMX8MP_ICN_MAIN),
188 
189 	DEFINE_BUS_SLAVE("OCRAM", IMX8MP_ICS_OCRAM, NULL),
190 	DEFINE_BUS_SLAVE("DRAM", IMX8MP_ICS_DRAM, NULL),
191 	DEFINE_BUS_MASTER("A53", IMX8MP_ICM_A53, IMX8MP_ICN_NOC),
192 	DEFINE_BUS_MASTER("SUPERMIX", IMX8MP_ICM_SUPERMIX, IMX8MP_ICN_NOC),
193 	DEFINE_BUS_MASTER("GIC", IMX8MP_ICM_GIC, IMX8MP_ICN_NOC),
194 	DEFINE_BUS_MASTER("MLMIX", IMX8MP_ICM_MLMIX, IMX8MP_ICN_NOC),
195 
196 	DEFINE_BUS_INTERCONNECT("NOC_AUDIO", IMX8MP_ICN_AUDIO, NULL, IMX8MP_ICN_NOC),
197 	DEFINE_BUS_MASTER("DSP", IMX8MP_ICM_DSP, IMX8MP_ICN_AUDIO),
198 	DEFINE_BUS_MASTER("SDMA2PER", IMX8MP_ICM_SDMA2PER, IMX8MP_ICN_AUDIO),
199 	DEFINE_BUS_MASTER("SDMA2BURST", IMX8MP_ICM_SDMA2BURST, IMX8MP_ICN_AUDIO),
200 	DEFINE_BUS_MASTER("SDMA3PER", IMX8MP_ICM_SDMA3PER, IMX8MP_ICN_AUDIO),
201 	DEFINE_BUS_MASTER("SDMA3BURST", IMX8MP_ICM_SDMA3BURST, IMX8MP_ICN_AUDIO),
202 	DEFINE_BUS_MASTER("EDMA", IMX8MP_ICM_EDMA, IMX8MP_ICN_AUDIO),
203 
204 	DEFINE_BUS_INTERCONNECT("NOC_GPU", IMX8MP_ICN_GPU, NULL, IMX8MP_ICN_NOC),
205 	DEFINE_BUS_MASTER("GPU 2D", IMX8MP_ICM_GPU2D, IMX8MP_ICN_GPU),
206 	DEFINE_BUS_MASTER("GPU 3D", IMX8MP_ICM_GPU3D, IMX8MP_ICN_GPU),
207 
208 	DEFINE_BUS_INTERCONNECT("NOC_HDMI", IMX8MP_ICN_HDMI, NULL, IMX8MP_ICN_NOC),
209 	DEFINE_BUS_MASTER("HRV", IMX8MP_ICM_HRV, IMX8MP_ICN_HDMI),
210 	DEFINE_BUS_MASTER("LCDIF_HDMI", IMX8MP_ICM_LCDIF_HDMI, IMX8MP_ICN_HDMI),
211 	DEFINE_BUS_MASTER("HDCP", IMX8MP_ICM_HDCP, IMX8MP_ICN_HDMI),
212 
213 	DEFINE_BUS_INTERCONNECT("NOC_HSIO", IMX8MP_ICN_HSIO, NULL, IMX8MP_ICN_NOC),
214 	DEFINE_BUS_MASTER("NOC_PCIE", IMX8MP_ICM_NOC_PCIE, IMX8MP_ICN_HSIO),
215 	DEFINE_BUS_MASTER("USB1", IMX8MP_ICM_USB1, IMX8MP_ICN_HSIO),
216 	DEFINE_BUS_MASTER("USB2", IMX8MP_ICM_USB2, IMX8MP_ICN_HSIO),
217 	DEFINE_BUS_MASTER("PCIE", IMX8MP_ICM_PCIE, IMX8MP_ICN_HSIO),
218 
219 	DEFINE_BUS_INTERCONNECT("NOC_MEDIA", IMX8MP_ICN_MEDIA, NULL, IMX8MP_ICN_NOC),
220 	DEFINE_BUS_MASTER("LCDIF_RD", IMX8MP_ICM_LCDIF_RD, IMX8MP_ICN_MEDIA),
221 	DEFINE_BUS_MASTER("LCDIF_WR", IMX8MP_ICM_LCDIF_WR, IMX8MP_ICN_MEDIA),
222 	DEFINE_BUS_MASTER("ISI0", IMX8MP_ICM_ISI0, IMX8MP_ICN_MEDIA),
223 	DEFINE_BUS_MASTER("ISI1", IMX8MP_ICM_ISI1, IMX8MP_ICN_MEDIA),
224 	DEFINE_BUS_MASTER("ISI2", IMX8MP_ICM_ISI2, IMX8MP_ICN_MEDIA),
225 	DEFINE_BUS_MASTER("ISP0", IMX8MP_ICM_ISP0, IMX8MP_ICN_MEDIA),
226 	DEFINE_BUS_MASTER("ISP1", IMX8MP_ICM_ISP1, IMX8MP_ICN_MEDIA),
227 	DEFINE_BUS_MASTER("DWE", IMX8MP_ICM_DWE, IMX8MP_ICN_MEDIA),
228 
229 	DEFINE_BUS_INTERCONNECT("NOC_VIDEO", IMX8MP_ICN_VIDEO, NULL, IMX8MP_ICN_NOC),
230 	DEFINE_BUS_MASTER("VPU G1", IMX8MP_ICM_VPU_G1, IMX8MP_ICN_VIDEO),
231 	DEFINE_BUS_MASTER("VPU G2", IMX8MP_ICM_VPU_G2, IMX8MP_ICN_VIDEO),
232 	DEFINE_BUS_MASTER("VPU H1", IMX8MP_ICM_VPU_H1, IMX8MP_ICN_VIDEO),
233 	DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MP_ICN_MAIN, NULL,
234 				IMX8MP_ICN_NOC, IMX8MP_ICS_OCRAM),
235 };
236 
237 static int imx8mp_icc_probe(struct platform_device *pdev)
238 {
239 	return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes);
240 }
241 
242 static int imx8mp_icc_remove(struct platform_device *pdev)
243 {
244 	imx_icc_unregister(pdev);
245 
246 	return 0;
247 }
248 
249 static struct platform_driver imx8mp_icc_driver = {
250 	.probe = imx8mp_icc_probe,
251 	.remove = imx8mp_icc_remove,
252 	.driver = {
253 		.name = "imx8mp-interconnect",
254 	},
255 };
256 
257 module_platform_driver(imx8mp_icc_driver);
258 MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
259 MODULE_LICENSE("GPL");
260 MODULE_ALIAS("platform:imx8mp-interconnect");
261