1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Interconnect framework driver for i.MX SoC 4 * 5 * Copyright (c) 2019, BayLibre 6 * Copyright (c) 2019-2020, NXP 7 * Author: Alexandre Bailon <abailon@baylibre.com> 8 * Author: Leonard Crestez <leonard.crestez@nxp.com> 9 */ 10 #ifndef __DRIVERS_INTERCONNECT_IMX_H 11 #define __DRIVERS_INTERCONNECT_IMX_H 12 13 #include <linux/interconnect-provider.h> 14 #include <linux/kernel.h> 15 16 #define IMX_ICC_MAX_LINKS 4 17 18 /* 19 * High throughput priority level in Regulator mode 20 * Read Priority in Fixed/Limiter mode 21 */ 22 #define PRIORITY0_SHIFT 0 23 /* 24 * Low throughput priority level in Regulator mode 25 * Write Priority in Fixed/Limiter mode 26 */ 27 #define PRIORITY1_SHIFT 8 28 #define PRIORITY_MASK 0x7 29 30 #define PRIORITY_COMP_MARK BIT(31) /* Must set */ 31 32 #define IMX_NOC_MODE_FIXED 0 33 #define IMX_NOC_MODE_LIMITER 1 34 #define IMX_NOC_MODE_BYPASS 2 35 #define IMX_NOC_MODE_REGULATOR 3 36 #define IMX_NOC_MODE_UNCONFIGURED 0xFF 37 38 #define IMX_NOC_PRIO_REG 0x8 39 #define IMX_NOC_MODE_REG 0xC 40 #define IMX_NOC_BANDWIDTH_REG 0x10 41 #define IMX_NOC_SATURATION 0x14 42 #define IMX_NOC_EXT_CTL_REG 0x18 43 44 struct imx_icc_provider { 45 void __iomem *noc_base; 46 struct icc_provider provider; 47 }; 48 49 /* 50 * struct imx_icc_node_adj - Describe a dynamic adjustable node 51 */ 52 struct imx_icc_node_adj_desc { 53 unsigned int bw_mul, bw_div; 54 const char *phandle_name; 55 bool main_noc; 56 }; 57 58 /* 59 * struct imx_icc_node - Describe an interconnect node 60 * @name: name of the node 61 * @id: an unique id to identify the node 62 * @links: an array of slaves' node id 63 * @num_links: number of id defined in links 64 */ 65 struct imx_icc_node_desc { 66 const char *name; 67 u16 id; 68 u16 links[IMX_ICC_MAX_LINKS]; 69 u16 num_links; 70 const struct imx_icc_node_adj_desc *adj; 71 }; 72 73 /* 74 * struct imx_icc_noc_setting - Describe an interconnect node setting 75 * @reg: register offset inside the NoC 76 * @prio_level: priority level 77 * @mode: functional mode 78 * @ext_control: external input control 79 */ 80 struct imx_icc_noc_setting { 81 u32 reg; 82 u32 prio_level; 83 u32 mode; 84 u32 ext_control; 85 }; 86 87 #define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \ 88 { \ 89 .id = _id, \ 90 .name = _name, \ 91 .adj = _adj, \ 92 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ 93 .links = { __VA_ARGS__ }, \ 94 } 95 96 #define DEFINE_BUS_MASTER(_name, _id, _dest_id) \ 97 DEFINE_BUS_INTERCONNECT(_name, _id, NULL, _dest_id) 98 99 #define DEFINE_BUS_SLAVE(_name, _id, _adj) \ 100 DEFINE_BUS_INTERCONNECT(_name, _id, _adj) 101 102 int imx_icc_register(struct platform_device *pdev, 103 struct imx_icc_node_desc *nodes, 104 int nodes_count, 105 struct imx_icc_noc_setting *noc_settings); 106 int imx_icc_unregister(struct platform_device *pdev); 107 108 #endif /* __DRIVERS_INTERCONNECT_IMX_H */ 109