1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Azoteq IQS7210A/7211A/E Trackpad/Touchscreen Controller
4  *
5  * Copyright (C) 2023 Jeff LaBundy <jeff@labundy.com>
6  */
7 
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/input.h>
15 #include <linux/input/mt.h>
16 #include <linux/input/touchscreen.h>
17 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/property.h>
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
26 
27 #define IQS7211_PROD_NUM			0x00
28 
29 #define IQS7211_EVENT_MASK_ALL			GENMASK(14, 8)
30 #define IQS7211_EVENT_MASK_ALP			BIT(13)
31 #define IQS7211_EVENT_MASK_BTN			BIT(12)
32 #define IQS7211_EVENT_MASK_ATI			BIT(11)
33 #define IQS7211_EVENT_MASK_MOVE			BIT(10)
34 #define IQS7211_EVENT_MASK_GSTR			BIT(9)
35 #define IQS7211_EVENT_MODE			BIT(8)
36 
37 #define IQS7211_COMMS_ERROR			0xEEEE
38 #define IQS7211_COMMS_RETRY_MS			50
39 #define IQS7211_COMMS_SLEEP_US			100
40 #define IQS7211_COMMS_TIMEOUT_US		(100 * USEC_PER_MSEC)
41 #define IQS7211_RESET_TIMEOUT_MS		150
42 #define IQS7211_START_TIMEOUT_US		(1 * USEC_PER_SEC)
43 
44 #define IQS7211_NUM_RETRIES			5
45 #define IQS7211_NUM_CRX				8
46 #define IQS7211_MAX_CTX				13
47 
48 #define IQS7211_MAX_CONTACTS			2
49 #define IQS7211_MAX_CYCLES			21
50 
51 /*
52  * The following delay is used during instances that must wait for the open-
53  * drain RDY pin to settle. Its value is calculated as 5*R*C, where R and C
54  * represent typical datasheet values of 4.7k and 100 nF, respectively.
55  */
56 #define iqs7211_irq_wait()			usleep_range(2500, 2600)
57 
58 enum iqs7211_dev_id {
59 	IQS7210A,
60 	IQS7211A,
61 	IQS7211E,
62 };
63 
64 enum iqs7211_comms_mode {
65 	IQS7211_COMMS_MODE_WAIT,
66 	IQS7211_COMMS_MODE_FREE,
67 	IQS7211_COMMS_MODE_FORCE,
68 };
69 
70 struct iqs7211_reg_field_desc {
71 	struct list_head list;
72 	u8 addr;
73 	u16 mask;
74 	u16 val;
75 };
76 
77 enum iqs7211_reg_key_id {
78 	IQS7211_REG_KEY_NONE,
79 	IQS7211_REG_KEY_PROX,
80 	IQS7211_REG_KEY_TOUCH,
81 	IQS7211_REG_KEY_TAP,
82 	IQS7211_REG_KEY_HOLD,
83 	IQS7211_REG_KEY_PALM,
84 	IQS7211_REG_KEY_AXIAL_X,
85 	IQS7211_REG_KEY_AXIAL_Y,
86 	IQS7211_REG_KEY_RESERVED
87 };
88 
89 enum iqs7211_reg_grp_id {
90 	IQS7211_REG_GRP_TP,
91 	IQS7211_REG_GRP_BTN,
92 	IQS7211_REG_GRP_ALP,
93 	IQS7211_REG_GRP_SYS,
94 	IQS7211_NUM_REG_GRPS
95 };
96 
97 static const char * const iqs7211_reg_grp_names[IQS7211_NUM_REG_GRPS] = {
98 	[IQS7211_REG_GRP_TP] = "trackpad",
99 	[IQS7211_REG_GRP_BTN] = "button",
100 	[IQS7211_REG_GRP_ALP] = "alp",
101 };
102 
103 static const u16 iqs7211_reg_grp_masks[IQS7211_NUM_REG_GRPS] = {
104 	[IQS7211_REG_GRP_TP] = IQS7211_EVENT_MASK_GSTR,
105 	[IQS7211_REG_GRP_BTN] = IQS7211_EVENT_MASK_BTN,
106 	[IQS7211_REG_GRP_ALP] = IQS7211_EVENT_MASK_ALP,
107 };
108 
109 struct iqs7211_event_desc {
110 	const char *name;
111 	u16 mask;
112 	u16 enable;
113 	enum iqs7211_reg_grp_id reg_grp;
114 	enum iqs7211_reg_key_id reg_key;
115 };
116 
117 static const struct iqs7211_event_desc iqs7210a_kp_events[] = {
118 	{
119 		.mask = BIT(10),
120 		.enable = BIT(13) | BIT(12),
121 		.reg_grp = IQS7211_REG_GRP_ALP,
122 	},
123 	{
124 		.name = "event-prox",
125 		.mask = BIT(2),
126 		.enable = BIT(5) | BIT(4),
127 		.reg_grp = IQS7211_REG_GRP_BTN,
128 		.reg_key = IQS7211_REG_KEY_PROX,
129 	},
130 	{
131 		.name = "event-touch",
132 		.mask = BIT(3),
133 		.enable = BIT(5) | BIT(4),
134 		.reg_grp = IQS7211_REG_GRP_BTN,
135 		.reg_key = IQS7211_REG_KEY_TOUCH,
136 	},
137 	{
138 		.name = "event-tap",
139 		.mask = BIT(0),
140 		.enable = BIT(0),
141 		.reg_grp = IQS7211_REG_GRP_TP,
142 		.reg_key = IQS7211_REG_KEY_TAP,
143 	},
144 	{
145 		.name = "event-hold",
146 		.mask = BIT(1),
147 		.enable = BIT(1),
148 		.reg_grp = IQS7211_REG_GRP_TP,
149 		.reg_key = IQS7211_REG_KEY_HOLD,
150 	},
151 	{
152 		.name = "event-swipe-x-neg",
153 		.mask = BIT(2),
154 		.enable = BIT(2),
155 		.reg_grp = IQS7211_REG_GRP_TP,
156 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
157 	},
158 	{
159 		.name = "event-swipe-x-pos",
160 		.mask = BIT(3),
161 		.enable = BIT(3),
162 		.reg_grp = IQS7211_REG_GRP_TP,
163 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
164 	},
165 	{
166 		.name = "event-swipe-y-pos",
167 		.mask = BIT(4),
168 		.enable = BIT(4),
169 		.reg_grp = IQS7211_REG_GRP_TP,
170 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
171 	},
172 	{
173 		.name = "event-swipe-y-neg",
174 		.mask = BIT(5),
175 		.enable = BIT(5),
176 		.reg_grp = IQS7211_REG_GRP_TP,
177 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
178 	},
179 };
180 
181 static const struct iqs7211_event_desc iqs7211a_kp_events[] = {
182 	{
183 		.mask = BIT(14),
184 		.reg_grp = IQS7211_REG_GRP_ALP,
185 	},
186 	{
187 		.name = "event-tap",
188 		.mask = BIT(0),
189 		.enable = BIT(0),
190 		.reg_grp = IQS7211_REG_GRP_TP,
191 		.reg_key = IQS7211_REG_KEY_TAP,
192 	},
193 	{
194 		.name = "event-hold",
195 		.mask = BIT(1),
196 		.enable = BIT(1),
197 		.reg_grp = IQS7211_REG_GRP_TP,
198 		.reg_key = IQS7211_REG_KEY_HOLD,
199 	},
200 	{
201 		.name = "event-swipe-x-neg",
202 		.mask = BIT(2),
203 		.enable = BIT(2),
204 		.reg_grp = IQS7211_REG_GRP_TP,
205 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
206 	},
207 	{
208 		.name = "event-swipe-x-pos",
209 		.mask = BIT(3),
210 		.enable = BIT(3),
211 		.reg_grp = IQS7211_REG_GRP_TP,
212 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
213 	},
214 	{
215 		.name = "event-swipe-y-pos",
216 		.mask = BIT(4),
217 		.enable = BIT(4),
218 		.reg_grp = IQS7211_REG_GRP_TP,
219 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
220 	},
221 	{
222 		.name = "event-swipe-y-neg",
223 		.mask = BIT(5),
224 		.enable = BIT(5),
225 		.reg_grp = IQS7211_REG_GRP_TP,
226 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
227 	},
228 };
229 
230 static const struct iqs7211_event_desc iqs7211e_kp_events[] = {
231 	{
232 		.mask = BIT(14),
233 		.reg_grp = IQS7211_REG_GRP_ALP,
234 	},
235 	{
236 		.name = "event-tap",
237 		.mask = BIT(0),
238 		.enable = BIT(0),
239 		.reg_grp = IQS7211_REG_GRP_TP,
240 		.reg_key = IQS7211_REG_KEY_TAP,
241 	},
242 	{
243 		.name = "event-tap-double",
244 		.mask = BIT(1),
245 		.enable = BIT(1),
246 		.reg_grp = IQS7211_REG_GRP_TP,
247 		.reg_key = IQS7211_REG_KEY_TAP,
248 	},
249 	{
250 		.name = "event-tap-triple",
251 		.mask = BIT(2),
252 		.enable = BIT(2),
253 		.reg_grp = IQS7211_REG_GRP_TP,
254 		.reg_key = IQS7211_REG_KEY_TAP,
255 	},
256 	{
257 		.name = "event-hold",
258 		.mask = BIT(3),
259 		.enable = BIT(3),
260 		.reg_grp = IQS7211_REG_GRP_TP,
261 		.reg_key = IQS7211_REG_KEY_HOLD,
262 	},
263 	{
264 		.name = "event-palm",
265 		.mask = BIT(4),
266 		.enable = BIT(4),
267 		.reg_grp = IQS7211_REG_GRP_TP,
268 		.reg_key = IQS7211_REG_KEY_PALM,
269 	},
270 	{
271 		.name = "event-swipe-x-pos",
272 		.mask = BIT(8),
273 		.enable = BIT(8),
274 		.reg_grp = IQS7211_REG_GRP_TP,
275 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
276 	},
277 	{
278 		.name = "event-swipe-x-neg",
279 		.mask = BIT(9),
280 		.enable = BIT(9),
281 		.reg_grp = IQS7211_REG_GRP_TP,
282 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
283 	},
284 	{
285 		.name = "event-swipe-y-pos",
286 		.mask = BIT(10),
287 		.enable = BIT(10),
288 		.reg_grp = IQS7211_REG_GRP_TP,
289 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
290 	},
291 	{
292 		.name = "event-swipe-y-neg",
293 		.mask = BIT(11),
294 		.enable = BIT(11),
295 		.reg_grp = IQS7211_REG_GRP_TP,
296 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
297 	},
298 	{
299 		.name = "event-swipe-x-pos-hold",
300 		.mask = BIT(12),
301 		.enable = BIT(12),
302 		.reg_grp = IQS7211_REG_GRP_TP,
303 		.reg_key = IQS7211_REG_KEY_HOLD,
304 	},
305 	{
306 		.name = "event-swipe-x-neg-hold",
307 		.mask = BIT(13),
308 		.enable = BIT(13),
309 		.reg_grp = IQS7211_REG_GRP_TP,
310 		.reg_key = IQS7211_REG_KEY_HOLD,
311 	},
312 	{
313 		.name = "event-swipe-y-pos-hold",
314 		.mask = BIT(14),
315 		.enable = BIT(14),
316 		.reg_grp = IQS7211_REG_GRP_TP,
317 		.reg_key = IQS7211_REG_KEY_HOLD,
318 	},
319 	{
320 		.name = "event-swipe-y-neg-hold",
321 		.mask = BIT(15),
322 		.enable = BIT(15),
323 		.reg_grp = IQS7211_REG_GRP_TP,
324 		.reg_key = IQS7211_REG_KEY_HOLD,
325 	},
326 };
327 
328 struct iqs7211_dev_desc {
329 	const char *tp_name;
330 	const char *kp_name;
331 	u16 prod_num;
332 	u16 show_reset;
333 	u16 ati_error[IQS7211_NUM_REG_GRPS];
334 	u16 ati_start[IQS7211_NUM_REG_GRPS];
335 	u16 suspend;
336 	u16 ack_reset;
337 	u16 comms_end;
338 	u16 comms_req;
339 	int charge_shift;
340 	int info_offs;
341 	int gesture_offs;
342 	int contact_offs;
343 	u8 sys_stat;
344 	u8 sys_ctrl;
345 	u8 alp_config;
346 	u8 tp_config;
347 	u8 exp_file;
348 	u8 kp_enable[IQS7211_NUM_REG_GRPS];
349 	u8 gesture_angle;
350 	u8 rx_tx_map;
351 	u8 cycle_alloc[2];
352 	u8 cycle_limit[2];
353 	const struct iqs7211_event_desc *kp_events;
354 	int num_kp_events;
355 	int min_crx_alp;
356 	int num_ctx;
357 };
358 
359 static const struct iqs7211_dev_desc iqs7211_devs[] = {
360 	[IQS7210A] = {
361 		.tp_name = "iqs7210a_trackpad",
362 		.kp_name = "iqs7210a_keys",
363 		.prod_num = 944,
364 		.show_reset = BIT(15),
365 		.ati_error = {
366 			[IQS7211_REG_GRP_TP] = BIT(12),
367 			[IQS7211_REG_GRP_BTN] = BIT(0),
368 			[IQS7211_REG_GRP_ALP] = BIT(8),
369 		},
370 		.ati_start = {
371 			[IQS7211_REG_GRP_TP] = BIT(13),
372 			[IQS7211_REG_GRP_BTN] = BIT(1),
373 			[IQS7211_REG_GRP_ALP] = BIT(9),
374 		},
375 		.suspend = BIT(11),
376 		.ack_reset = BIT(7),
377 		.comms_end = BIT(2),
378 		.comms_req = BIT(1),
379 		.charge_shift = 4,
380 		.info_offs = 0,
381 		.gesture_offs = 1,
382 		.contact_offs = 4,
383 		.sys_stat = 0x0A,
384 		.sys_ctrl = 0x35,
385 		.alp_config = 0x39,
386 		.tp_config = 0x4E,
387 		.exp_file = 0x57,
388 		.kp_enable = {
389 			[IQS7211_REG_GRP_TP] = 0x58,
390 			[IQS7211_REG_GRP_BTN] = 0x37,
391 			[IQS7211_REG_GRP_ALP] = 0x37,
392 		},
393 		.gesture_angle = 0x5F,
394 		.rx_tx_map = 0x60,
395 		.cycle_alloc = { 0x66, 0x75, },
396 		.cycle_limit = { 10, 6, },
397 		.kp_events = iqs7210a_kp_events,
398 		.num_kp_events = ARRAY_SIZE(iqs7210a_kp_events),
399 		.min_crx_alp = 4,
400 		.num_ctx = IQS7211_MAX_CTX - 1,
401 	},
402 	[IQS7211A] = {
403 		.tp_name = "iqs7211a_trackpad",
404 		.kp_name = "iqs7211a_keys",
405 		.prod_num = 763,
406 		.show_reset = BIT(7),
407 		.ati_error = {
408 			[IQS7211_REG_GRP_TP] = BIT(3),
409 			[IQS7211_REG_GRP_ALP] = BIT(5),
410 		},
411 		.ati_start = {
412 			[IQS7211_REG_GRP_TP] = BIT(5),
413 			[IQS7211_REG_GRP_ALP] = BIT(6),
414 		},
415 		.ack_reset = BIT(7),
416 		.comms_req = BIT(4),
417 		.charge_shift = 0,
418 		.info_offs = 0,
419 		.gesture_offs = 1,
420 		.contact_offs = 4,
421 		.sys_stat = 0x10,
422 		.sys_ctrl = 0x50,
423 		.tp_config = 0x60,
424 		.alp_config = 0x72,
425 		.exp_file = 0x74,
426 		.kp_enable = {
427 			[IQS7211_REG_GRP_TP] = 0x80,
428 		},
429 		.gesture_angle = 0x87,
430 		.rx_tx_map = 0x90,
431 		.cycle_alloc = { 0xA0, 0xB0, },
432 		.cycle_limit = { 10, 8, },
433 		.kp_events = iqs7211a_kp_events,
434 		.num_kp_events = ARRAY_SIZE(iqs7211a_kp_events),
435 		.num_ctx = IQS7211_MAX_CTX - 1,
436 	},
437 	[IQS7211E] = {
438 		.tp_name = "iqs7211e_trackpad",
439 		.kp_name = "iqs7211e_keys",
440 		.prod_num = 1112,
441 		.show_reset = BIT(7),
442 		.ati_error = {
443 			[IQS7211_REG_GRP_TP] = BIT(3),
444 			[IQS7211_REG_GRP_ALP] = BIT(5),
445 		},
446 		.ati_start = {
447 			[IQS7211_REG_GRP_TP] = BIT(5),
448 			[IQS7211_REG_GRP_ALP] = BIT(6),
449 		},
450 		.suspend = BIT(11),
451 		.ack_reset = BIT(7),
452 		.comms_end = BIT(6),
453 		.comms_req = BIT(4),
454 		.charge_shift = 0,
455 		.info_offs = 1,
456 		.gesture_offs = 0,
457 		.contact_offs = 2,
458 		.sys_stat = 0x0E,
459 		.sys_ctrl = 0x33,
460 		.tp_config = 0x41,
461 		.alp_config = 0x36,
462 		.exp_file = 0x4A,
463 		.kp_enable = {
464 			[IQS7211_REG_GRP_TP] = 0x4B,
465 		},
466 		.gesture_angle = 0x55,
467 		.rx_tx_map = 0x56,
468 		.cycle_alloc = { 0x5D, 0x6C, },
469 		.cycle_limit = { 10, 11, },
470 		.kp_events = iqs7211e_kp_events,
471 		.num_kp_events = ARRAY_SIZE(iqs7211e_kp_events),
472 		.num_ctx = IQS7211_MAX_CTX,
473 	},
474 };
475 
476 struct iqs7211_prop_desc {
477 	const char *name;
478 	enum iqs7211_reg_key_id reg_key;
479 	u8 reg_addr[IQS7211_NUM_REG_GRPS][ARRAY_SIZE(iqs7211_devs)];
480 	int reg_shift;
481 	int reg_width;
482 	int val_pitch;
483 	int val_min;
484 	int val_max;
485 	const char *label;
486 };
487 
488 static const struct iqs7211_prop_desc iqs7211_props[] = {
489 	{
490 		.name = "azoteq,ati-frac-div-fine",
491 		.reg_addr = {
492 			[IQS7211_REG_GRP_TP] = {
493 				[IQS7210A] = 0x1E,
494 				[IQS7211A] = 0x30,
495 				[IQS7211E] = 0x21,
496 			},
497 			[IQS7211_REG_GRP_BTN] = {
498 				[IQS7210A] = 0x22,
499 			},
500 			[IQS7211_REG_GRP_ALP] = {
501 				[IQS7210A] = 0x23,
502 				[IQS7211A] = 0x36,
503 				[IQS7211E] = 0x25,
504 			},
505 		},
506 		.reg_shift = 9,
507 		.reg_width = 5,
508 		.label = "ATI fine fractional divider",
509 	},
510 	{
511 		.name = "azoteq,ati-frac-mult-coarse",
512 		.reg_addr = {
513 			[IQS7211_REG_GRP_TP] = {
514 				[IQS7210A] = 0x1E,
515 				[IQS7211A] = 0x30,
516 				[IQS7211E] = 0x21,
517 			},
518 			[IQS7211_REG_GRP_BTN] = {
519 				[IQS7210A] = 0x22,
520 			},
521 			[IQS7211_REG_GRP_ALP] = {
522 				[IQS7210A] = 0x23,
523 				[IQS7211A] = 0x36,
524 				[IQS7211E] = 0x25,
525 			},
526 		},
527 		.reg_shift = 5,
528 		.reg_width = 4,
529 		.label = "ATI coarse fractional multiplier",
530 	},
531 	{
532 		.name = "azoteq,ati-frac-div-coarse",
533 		.reg_addr = {
534 			[IQS7211_REG_GRP_TP] = {
535 				[IQS7210A] = 0x1E,
536 				[IQS7211A] = 0x30,
537 				[IQS7211E] = 0x21,
538 			},
539 			[IQS7211_REG_GRP_BTN] = {
540 				[IQS7210A] = 0x22,
541 			},
542 			[IQS7211_REG_GRP_ALP] = {
543 				[IQS7210A] = 0x23,
544 				[IQS7211A] = 0x36,
545 				[IQS7211E] = 0x25,
546 			},
547 		},
548 		.reg_shift = 0,
549 		.reg_width = 5,
550 		.label = "ATI coarse fractional divider",
551 	},
552 	{
553 		.name = "azoteq,ati-comp-div",
554 		.reg_addr = {
555 			[IQS7211_REG_GRP_TP] = {
556 				[IQS7210A] = 0x1F,
557 				[IQS7211E] = 0x22,
558 			},
559 			[IQS7211_REG_GRP_BTN] = {
560 				[IQS7210A] = 0x24,
561 			},
562 			[IQS7211_REG_GRP_ALP] = {
563 				[IQS7211E] = 0x26,
564 			},
565 		},
566 		.reg_shift = 0,
567 		.reg_width = 8,
568 		.val_max = 31,
569 		.label = "ATI compensation divider",
570 	},
571 	{
572 		.name = "azoteq,ati-comp-div",
573 		.reg_addr = {
574 			[IQS7211_REG_GRP_ALP] = {
575 				[IQS7210A] = 0x24,
576 			},
577 		},
578 		.reg_shift = 8,
579 		.reg_width = 8,
580 		.val_max = 31,
581 		.label = "ATI compensation divider",
582 	},
583 	{
584 		.name = "azoteq,ati-comp-div",
585 		.reg_addr = {
586 			[IQS7211_REG_GRP_TP] = {
587 				[IQS7211A] = 0x31,
588 			},
589 			[IQS7211_REG_GRP_ALP] = {
590 				[IQS7211A] = 0x37,
591 			},
592 		},
593 		.val_max = 31,
594 		.label = "ATI compensation divider",
595 	},
596 	{
597 		.name = "azoteq,ati-target",
598 		.reg_addr = {
599 			[IQS7211_REG_GRP_TP] = {
600 				[IQS7210A] = 0x20,
601 				[IQS7211A] = 0x32,
602 				[IQS7211E] = 0x23,
603 			},
604 			[IQS7211_REG_GRP_BTN] = {
605 				[IQS7210A] = 0x27,
606 			},
607 			[IQS7211_REG_GRP_ALP] = {
608 				[IQS7210A] = 0x28,
609 				[IQS7211A] = 0x38,
610 				[IQS7211E] = 0x27,
611 			},
612 		},
613 		.label = "ATI target",
614 	},
615 	{
616 		.name = "azoteq,ati-base",
617 		.reg_addr[IQS7211_REG_GRP_ALP] = {
618 			[IQS7210A] = 0x26,
619 		},
620 		.reg_shift = 8,
621 		.reg_width = 8,
622 		.val_pitch = 8,
623 		.label = "ATI base",
624 	},
625 	{
626 		.name = "azoteq,ati-base",
627 		.reg_addr[IQS7211_REG_GRP_BTN] = {
628 			[IQS7210A] = 0x26,
629 		},
630 		.reg_shift = 0,
631 		.reg_width = 8,
632 		.val_pitch = 8,
633 		.label = "ATI base",
634 	},
635 	{
636 		.name = "azoteq,rate-active-ms",
637 		.reg_addr[IQS7211_REG_GRP_SYS] = {
638 			[IQS7210A] = 0x29,
639 			[IQS7211A] = 0x40,
640 			[IQS7211E] = 0x28,
641 		},
642 		.label = "active mode report rate",
643 	},
644 	{
645 		.name = "azoteq,rate-touch-ms",
646 		.reg_addr[IQS7211_REG_GRP_SYS] = {
647 			[IQS7210A] = 0x2A,
648 			[IQS7211A] = 0x41,
649 			[IQS7211E] = 0x29,
650 		},
651 		.label = "idle-touch mode report rate",
652 	},
653 	{
654 		.name = "azoteq,rate-idle-ms",
655 		.reg_addr[IQS7211_REG_GRP_SYS] = {
656 			[IQS7210A] = 0x2B,
657 			[IQS7211A] = 0x42,
658 			[IQS7211E] = 0x2A,
659 		},
660 		.label = "idle mode report rate",
661 	},
662 	{
663 		.name = "azoteq,rate-lp1-ms",
664 		.reg_addr[IQS7211_REG_GRP_SYS] = {
665 			[IQS7210A] = 0x2C,
666 			[IQS7211A] = 0x43,
667 			[IQS7211E] = 0x2B,
668 		},
669 		.label = "low-power mode 1 report rate",
670 	},
671 	{
672 		.name = "azoteq,rate-lp2-ms",
673 		.reg_addr[IQS7211_REG_GRP_SYS] = {
674 			[IQS7210A] = 0x2D,
675 			[IQS7211A] = 0x44,
676 			[IQS7211E] = 0x2C,
677 		},
678 		.label = "low-power mode 2 report rate",
679 	},
680 	{
681 		.name = "azoteq,timeout-active-ms",
682 		.reg_addr[IQS7211_REG_GRP_SYS] = {
683 			[IQS7210A] = 0x2E,
684 			[IQS7211A] = 0x45,
685 			[IQS7211E] = 0x2D,
686 		},
687 		.val_pitch = 1000,
688 		.label = "active mode timeout",
689 	},
690 	{
691 		.name = "azoteq,timeout-touch-ms",
692 		.reg_addr[IQS7211_REG_GRP_SYS] = {
693 			[IQS7210A] = 0x2F,
694 			[IQS7211A] = 0x46,
695 			[IQS7211E] = 0x2E,
696 		},
697 		.val_pitch = 1000,
698 		.label = "idle-touch mode timeout",
699 	},
700 	{
701 		.name = "azoteq,timeout-idle-ms",
702 		.reg_addr[IQS7211_REG_GRP_SYS] = {
703 			[IQS7210A] = 0x30,
704 			[IQS7211A] = 0x47,
705 			[IQS7211E] = 0x2F,
706 		},
707 		.val_pitch = 1000,
708 		.label = "idle mode timeout",
709 	},
710 	{
711 		.name = "azoteq,timeout-lp1-ms",
712 		.reg_addr[IQS7211_REG_GRP_SYS] = {
713 			[IQS7210A] = 0x31,
714 			[IQS7211A] = 0x48,
715 			[IQS7211E] = 0x30,
716 		},
717 		.val_pitch = 1000,
718 		.label = "low-power mode 1 timeout",
719 	},
720 	{
721 		.name = "azoteq,timeout-lp2-ms",
722 		.reg_addr[IQS7211_REG_GRP_SYS] = {
723 			[IQS7210A] = 0x32,
724 			[IQS7211E] = 0x31,
725 		},
726 		.reg_shift = 8,
727 		.reg_width = 8,
728 		.val_pitch = 1000,
729 		.val_max = 60000,
730 		.label = "trackpad reference value update rate",
731 	},
732 	{
733 		.name = "azoteq,timeout-lp2-ms",
734 		.reg_addr[IQS7211_REG_GRP_SYS] = {
735 			[IQS7211A] = 0x49,
736 		},
737 		.val_pitch = 1000,
738 		.val_max = 60000,
739 		.label = "trackpad reference value update rate",
740 	},
741 	{
742 		.name = "azoteq,timeout-ati-ms",
743 		.reg_addr[IQS7211_REG_GRP_SYS] = {
744 			[IQS7210A] = 0x32,
745 			[IQS7211E] = 0x31,
746 		},
747 		.reg_width = 8,
748 		.val_pitch = 1000,
749 		.val_max = 60000,
750 		.label = "ATI error timeout",
751 	},
752 	{
753 		.name = "azoteq,timeout-ati-ms",
754 		.reg_addr[IQS7211_REG_GRP_SYS] = {
755 			[IQS7211A] = 0x35,
756 		},
757 		.val_pitch = 1000,
758 		.val_max = 60000,
759 		.label = "ATI error timeout",
760 	},
761 	{
762 		.name = "azoteq,timeout-comms-ms",
763 		.reg_addr[IQS7211_REG_GRP_SYS] = {
764 			[IQS7210A] = 0x33,
765 			[IQS7211A] = 0x4A,
766 			[IQS7211E] = 0x32,
767 		},
768 		.label = "communication timeout",
769 	},
770 	{
771 		.name = "azoteq,timeout-press-ms",
772 		.reg_addr[IQS7211_REG_GRP_SYS] = {
773 			[IQS7210A] = 0x34,
774 		},
775 		.reg_width = 8,
776 		.val_pitch = 1000,
777 		.val_max = 60000,
778 		.label = "press timeout",
779 	},
780 	{
781 		.name = "azoteq,ati-mode",
782 		.reg_addr[IQS7211_REG_GRP_ALP] = {
783 			[IQS7210A] = 0x37,
784 		},
785 		.reg_shift = 15,
786 		.reg_width = 1,
787 		.label = "ATI mode",
788 	},
789 	{
790 		.name = "azoteq,ati-mode",
791 		.reg_addr[IQS7211_REG_GRP_BTN] = {
792 			[IQS7210A] = 0x37,
793 		},
794 		.reg_shift = 7,
795 		.reg_width = 1,
796 		.label = "ATI mode",
797 	},
798 	{
799 		.name = "azoteq,sense-mode",
800 		.reg_addr[IQS7211_REG_GRP_ALP] = {
801 			[IQS7210A] = 0x37,
802 			[IQS7211A] = 0x72,
803 			[IQS7211E] = 0x36,
804 		},
805 		.reg_shift = 8,
806 		.reg_width = 1,
807 		.label = "sensing mode",
808 	},
809 	{
810 		.name = "azoteq,sense-mode",
811 		.reg_addr[IQS7211_REG_GRP_BTN] = {
812 			[IQS7210A] = 0x37,
813 		},
814 		.reg_shift = 0,
815 		.reg_width = 2,
816 		.val_max = 2,
817 		.label = "sensing mode",
818 	},
819 	{
820 		.name = "azoteq,fosc-freq",
821 		.reg_addr[IQS7211_REG_GRP_SYS] = {
822 			[IQS7210A] = 0x38,
823 			[IQS7211A] = 0x52,
824 			[IQS7211E] = 0x35,
825 		},
826 		.reg_shift = 4,
827 		.reg_width = 1,
828 		.label = "core clock frequency selection",
829 	},
830 	{
831 		.name = "azoteq,fosc-trim",
832 		.reg_addr[IQS7211_REG_GRP_SYS] = {
833 			[IQS7210A] = 0x38,
834 			[IQS7211A] = 0x52,
835 			[IQS7211E] = 0x35,
836 		},
837 		.reg_shift = 0,
838 		.reg_width = 4,
839 		.label = "core clock frequency trim",
840 	},
841 	{
842 		.name = "azoteq,touch-exit",
843 		.reg_addr = {
844 			[IQS7211_REG_GRP_TP] = {
845 				[IQS7210A] = 0x3B,
846 				[IQS7211A] = 0x53,
847 				[IQS7211E] = 0x38,
848 			},
849 			[IQS7211_REG_GRP_BTN] = {
850 				[IQS7210A] = 0x3E,
851 			},
852 		},
853 		.reg_shift = 8,
854 		.reg_width = 8,
855 		.label = "touch exit factor",
856 	},
857 	{
858 		.name = "azoteq,touch-enter",
859 		.reg_addr = {
860 			[IQS7211_REG_GRP_TP] = {
861 				[IQS7210A] = 0x3B,
862 				[IQS7211A] = 0x53,
863 				[IQS7211E] = 0x38,
864 			},
865 			[IQS7211_REG_GRP_BTN] = {
866 				[IQS7210A] = 0x3E,
867 			},
868 		},
869 		.reg_shift = 0,
870 		.reg_width = 8,
871 		.label = "touch entrance factor",
872 	},
873 	{
874 		.name = "azoteq,thresh",
875 		.reg_addr = {
876 			[IQS7211_REG_GRP_BTN] = {
877 				[IQS7210A] = 0x3C,
878 			},
879 			[IQS7211_REG_GRP_ALP] = {
880 				[IQS7210A] = 0x3D,
881 				[IQS7211A] = 0x54,
882 				[IQS7211E] = 0x39,
883 			},
884 		},
885 		.label = "threshold",
886 	},
887 	{
888 		.name = "azoteq,debounce-exit",
889 		.reg_addr = {
890 			[IQS7211_REG_GRP_BTN] = {
891 				[IQS7210A] = 0x3F,
892 			},
893 			[IQS7211_REG_GRP_ALP] = {
894 				[IQS7210A] = 0x40,
895 				[IQS7211A] = 0x56,
896 				[IQS7211E] = 0x3A,
897 			},
898 		},
899 		.reg_shift = 8,
900 		.reg_width = 8,
901 		.label = "debounce exit factor",
902 	},
903 	{
904 		.name = "azoteq,debounce-enter",
905 		.reg_addr = {
906 			[IQS7211_REG_GRP_BTN] = {
907 				[IQS7210A] = 0x3F,
908 			},
909 			[IQS7211_REG_GRP_ALP] = {
910 				[IQS7210A] = 0x40,
911 				[IQS7211A] = 0x56,
912 				[IQS7211E] = 0x3A,
913 			},
914 		},
915 		.reg_shift = 0,
916 		.reg_width = 8,
917 		.label = "debounce entrance factor",
918 	},
919 	{
920 		.name = "azoteq,conv-frac",
921 		.reg_addr = {
922 			[IQS7211_REG_GRP_TP] = {
923 				[IQS7210A] = 0x48,
924 				[IQS7211A] = 0x58,
925 				[IQS7211E] = 0x3D,
926 			},
927 			[IQS7211_REG_GRP_BTN] = {
928 				[IQS7210A] = 0x49,
929 			},
930 			[IQS7211_REG_GRP_ALP] = {
931 				[IQS7210A] = 0x4A,
932 				[IQS7211A] = 0x59,
933 				[IQS7211E] = 0x3E,
934 			},
935 		},
936 		.reg_shift = 8,
937 		.reg_width = 8,
938 		.label = "conversion frequency fractional divider",
939 	},
940 	{
941 		.name = "azoteq,conv-period",
942 		.reg_addr = {
943 			[IQS7211_REG_GRP_TP] = {
944 				[IQS7210A] = 0x48,
945 				[IQS7211A] = 0x58,
946 				[IQS7211E] = 0x3D,
947 			},
948 			[IQS7211_REG_GRP_BTN] = {
949 				[IQS7210A] = 0x49,
950 			},
951 			[IQS7211_REG_GRP_ALP] = {
952 				[IQS7210A] = 0x4A,
953 				[IQS7211A] = 0x59,
954 				[IQS7211E] = 0x3E,
955 			},
956 		},
957 		.reg_shift = 0,
958 		.reg_width = 8,
959 		.label = "conversion period",
960 	},
961 	{
962 		.name = "azoteq,thresh",
963 		.reg_addr[IQS7211_REG_GRP_TP] = {
964 			[IQS7210A] = 0x55,
965 			[IQS7211A] = 0x67,
966 			[IQS7211E] = 0x48,
967 		},
968 		.reg_shift = 0,
969 		.reg_width = 8,
970 		.label = "threshold",
971 	},
972 	{
973 		.name = "azoteq,contact-split",
974 		.reg_addr[IQS7211_REG_GRP_SYS] = {
975 			[IQS7210A] = 0x55,
976 			[IQS7211A] = 0x67,
977 			[IQS7211E] = 0x48,
978 		},
979 		.reg_shift = 8,
980 		.reg_width = 8,
981 		.label = "contact split factor",
982 	},
983 	{
984 		.name = "azoteq,trim-x",
985 		.reg_addr[IQS7211_REG_GRP_SYS] = {
986 			[IQS7210A] = 0x56,
987 			[IQS7211E] = 0x49,
988 		},
989 		.reg_shift = 0,
990 		.reg_width = 8,
991 		.label = "horizontal trim width",
992 	},
993 	{
994 		.name = "azoteq,trim-x",
995 		.reg_addr[IQS7211_REG_GRP_SYS] = {
996 			[IQS7211A] = 0x68,
997 		},
998 		.label = "horizontal trim width",
999 	},
1000 	{
1001 		.name = "azoteq,trim-y",
1002 		.reg_addr[IQS7211_REG_GRP_SYS] = {
1003 			[IQS7210A] = 0x56,
1004 			[IQS7211E] = 0x49,
1005 		},
1006 		.reg_shift = 8,
1007 		.reg_width = 8,
1008 		.label = "vertical trim height",
1009 	},
1010 	{
1011 		.name = "azoteq,trim-y",
1012 		.reg_addr[IQS7211_REG_GRP_SYS] = {
1013 			[IQS7211A] = 0x69,
1014 		},
1015 		.label = "vertical trim height",
1016 	},
1017 	{
1018 		.name = "azoteq,gesture-max-ms",
1019 		.reg_key = IQS7211_REG_KEY_TAP,
1020 		.reg_addr[IQS7211_REG_GRP_TP] = {
1021 			[IQS7210A] = 0x59,
1022 			[IQS7211A] = 0x81,
1023 			[IQS7211E] = 0x4C,
1024 		},
1025 		.label = "maximum gesture time",
1026 	},
1027 	{
1028 		.name = "azoteq,gesture-mid-ms",
1029 		.reg_key = IQS7211_REG_KEY_TAP,
1030 		.reg_addr[IQS7211_REG_GRP_TP] = {
1031 			[IQS7211E] = 0x4D,
1032 		},
1033 		.label = "repeated gesture time",
1034 	},
1035 	{
1036 		.name = "azoteq,gesture-dist",
1037 		.reg_key = IQS7211_REG_KEY_TAP,
1038 		.reg_addr[IQS7211_REG_GRP_TP] = {
1039 			[IQS7210A] = 0x5A,
1040 			[IQS7211A] = 0x82,
1041 			[IQS7211E] = 0x4E,
1042 		},
1043 		.label = "gesture distance",
1044 	},
1045 	{
1046 		.name = "azoteq,gesture-dist",
1047 		.reg_key = IQS7211_REG_KEY_HOLD,
1048 		.reg_addr[IQS7211_REG_GRP_TP] = {
1049 			[IQS7210A] = 0x5A,
1050 			[IQS7211A] = 0x82,
1051 			[IQS7211E] = 0x4E,
1052 		},
1053 		.label = "gesture distance",
1054 	},
1055 	{
1056 		.name = "azoteq,gesture-min-ms",
1057 		.reg_key = IQS7211_REG_KEY_HOLD,
1058 		.reg_addr[IQS7211_REG_GRP_TP] = {
1059 			[IQS7210A] = 0x5B,
1060 			[IQS7211A] = 0x83,
1061 			[IQS7211E] = 0x4F,
1062 		},
1063 		.label = "minimum gesture time",
1064 	},
1065 	{
1066 		.name = "azoteq,gesture-max-ms",
1067 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
1068 		.reg_addr[IQS7211_REG_GRP_TP] = {
1069 			[IQS7210A] = 0x5C,
1070 			[IQS7211A] = 0x84,
1071 			[IQS7211E] = 0x50,
1072 		},
1073 		.label = "maximum gesture time",
1074 	},
1075 	{
1076 		.name = "azoteq,gesture-max-ms",
1077 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
1078 		.reg_addr[IQS7211_REG_GRP_TP] = {
1079 			[IQS7210A] = 0x5C,
1080 			[IQS7211A] = 0x84,
1081 			[IQS7211E] = 0x50,
1082 		},
1083 		.label = "maximum gesture time",
1084 	},
1085 	{
1086 		.name = "azoteq,gesture-dist",
1087 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
1088 		.reg_addr[IQS7211_REG_GRP_TP] = {
1089 			[IQS7210A] = 0x5D,
1090 			[IQS7211A] = 0x85,
1091 			[IQS7211E] = 0x51,
1092 		},
1093 		.label = "gesture distance",
1094 	},
1095 	{
1096 		.name = "azoteq,gesture-dist",
1097 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
1098 		.reg_addr[IQS7211_REG_GRP_TP] = {
1099 			[IQS7210A] = 0x5E,
1100 			[IQS7211A] = 0x86,
1101 			[IQS7211E] = 0x52,
1102 		},
1103 		.label = "gesture distance",
1104 	},
1105 	{
1106 		.name = "azoteq,gesture-dist-rep",
1107 		.reg_key = IQS7211_REG_KEY_AXIAL_X,
1108 		.reg_addr[IQS7211_REG_GRP_TP] = {
1109 			[IQS7211E] = 0x53,
1110 		},
1111 		.label = "repeated gesture distance",
1112 	},
1113 	{
1114 		.name = "azoteq,gesture-dist-rep",
1115 		.reg_key = IQS7211_REG_KEY_AXIAL_Y,
1116 		.reg_addr[IQS7211_REG_GRP_TP] = {
1117 			[IQS7211E] = 0x54,
1118 		},
1119 		.label = "repeated gesture distance",
1120 	},
1121 	{
1122 		.name = "azoteq,thresh",
1123 		.reg_key = IQS7211_REG_KEY_PALM,
1124 		.reg_addr[IQS7211_REG_GRP_TP] = {
1125 			[IQS7211E] = 0x55,
1126 		},
1127 		.reg_shift = 8,
1128 		.reg_width = 8,
1129 		.val_max = 42,
1130 		.label = "threshold",
1131 	},
1132 };
1133 
1134 static const u8 iqs7211_gesture_angle[] = {
1135 	0x00, 0x01, 0x02, 0x03,
1136 	0x04, 0x06, 0x07, 0x08,
1137 	0x09, 0x0A, 0x0B, 0x0C,
1138 	0x0E, 0x0F, 0x10, 0x11,
1139 	0x12, 0x14, 0x15, 0x16,
1140 	0x17, 0x19, 0x1A, 0x1B,
1141 	0x1C, 0x1E, 0x1F, 0x21,
1142 	0x22, 0x23, 0x25, 0x26,
1143 	0x28, 0x2A, 0x2B, 0x2D,
1144 	0x2E, 0x30, 0x32, 0x34,
1145 	0x36, 0x38, 0x3A, 0x3C,
1146 	0x3E, 0x40, 0x42, 0x45,
1147 	0x47, 0x4A, 0x4C, 0x4F,
1148 	0x52, 0x55, 0x58, 0x5B,
1149 	0x5F, 0x63, 0x66, 0x6B,
1150 	0x6F, 0x73, 0x78, 0x7E,
1151 	0x83, 0x89, 0x90, 0x97,
1152 	0x9E, 0xA7, 0xB0, 0xBA,
1153 	0xC5, 0xD1, 0xDF, 0xEF,
1154 };
1155 
1156 struct iqs7211_ver_info {
1157 	__le16 prod_num;
1158 	__le16 major;
1159 	__le16 minor;
1160 	__le32 patch;
1161 } __packed;
1162 
1163 struct iqs7211_touch_data {
1164 	__le16 abs_x;
1165 	__le16 abs_y;
1166 	__le16 pressure;
1167 	__le16 area;
1168 } __packed;
1169 
1170 struct iqs7211_tp_config {
1171 	u8 tp_settings;
1172 	u8 total_rx;
1173 	u8 total_tx;
1174 	u8 num_contacts;
1175 	__le16 max_x;
1176 	__le16 max_y;
1177 } __packed;
1178 
1179 struct iqs7211_private {
1180 	const struct iqs7211_dev_desc *dev_desc;
1181 	struct gpio_desc *reset_gpio;
1182 	struct gpio_desc *irq_gpio;
1183 	struct i2c_client *client;
1184 	struct input_dev *tp_idev;
1185 	struct input_dev *kp_idev;
1186 	struct iqs7211_ver_info ver_info;
1187 	struct iqs7211_tp_config tp_config;
1188 	struct touchscreen_properties prop;
1189 	struct list_head reg_field_head;
1190 	enum iqs7211_comms_mode comms_init;
1191 	enum iqs7211_comms_mode comms_mode;
1192 	unsigned int num_contacts;
1193 	unsigned int kp_code[ARRAY_SIZE(iqs7211e_kp_events)];
1194 	u8 rx_tx_map[IQS7211_MAX_CTX + 1];
1195 	u8 cycle_alloc[2][33];
1196 	u8 exp_file[2];
1197 	u16 event_mask;
1198 	u16 ati_start;
1199 	u16 gesture_cache;
1200 };
1201 
1202 static int iqs7211_irq_poll(struct iqs7211_private *iqs7211, u64 timeout_us)
1203 {
1204 	int error, val;
1205 
1206 	error = readx_poll_timeout(gpiod_get_value_cansleep, iqs7211->irq_gpio,
1207 				   val, val, IQS7211_COMMS_SLEEP_US, timeout_us);
1208 
1209 	return val < 0 ? val : error;
1210 }
1211 
1212 static int iqs7211_hard_reset(struct iqs7211_private *iqs7211)
1213 {
1214 	if (!iqs7211->reset_gpio)
1215 		return 0;
1216 
1217 	gpiod_set_value_cansleep(iqs7211->reset_gpio, 1);
1218 
1219 	/*
1220 	 * The following delay ensures the shared RDY/MCLR pin is sampled in
1221 	 * between periodic assertions by the device and assumes the default
1222 	 * communication timeout has not been overwritten in OTP memory.
1223 	 */
1224 	if (iqs7211->reset_gpio == iqs7211->irq_gpio)
1225 		msleep(IQS7211_RESET_TIMEOUT_MS);
1226 	else
1227 		usleep_range(1000, 1100);
1228 
1229 	gpiod_set_value_cansleep(iqs7211->reset_gpio, 0);
1230 	if (iqs7211->reset_gpio == iqs7211->irq_gpio)
1231 		iqs7211_irq_wait();
1232 
1233 	return iqs7211_irq_poll(iqs7211, IQS7211_START_TIMEOUT_US);
1234 }
1235 
1236 static int iqs7211_force_comms(struct iqs7211_private *iqs7211)
1237 {
1238 	u8 msg_buf[] = { 0xFF, };
1239 	int ret;
1240 
1241 	switch (iqs7211->comms_mode) {
1242 	case IQS7211_COMMS_MODE_WAIT:
1243 		return iqs7211_irq_poll(iqs7211, IQS7211_START_TIMEOUT_US);
1244 
1245 	case IQS7211_COMMS_MODE_FREE:
1246 		return 0;
1247 
1248 	case IQS7211_COMMS_MODE_FORCE:
1249 		break;
1250 
1251 	default:
1252 		return -EINVAL;
1253 	}
1254 
1255 	/*
1256 	 * The device cannot communicate until it asserts its interrupt (RDY)
1257 	 * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1258 	 * ever all write data is ignored, and all read data returns 0xEE.
1259 	 *
1260 	 * Unsolicited communication must be preceded by a special force com-
1261 	 * munication command, after which the device eventually asserts its
1262 	 * RDY pin and agrees to communicate.
1263 	 *
1264 	 * Regardless of whether communication is forced or the result of an
1265 	 * interrupt, the device automatically deasserts its RDY pin once it
1266 	 * detects an I2C stop condition, or a timeout expires.
1267 	 */
1268 	ret = gpiod_get_value_cansleep(iqs7211->irq_gpio);
1269 	if (ret < 0)
1270 		return ret;
1271 	else if (ret > 0)
1272 		return 0;
1273 
1274 	ret = i2c_master_send(iqs7211->client, msg_buf, sizeof(msg_buf));
1275 	if (ret < (int)sizeof(msg_buf)) {
1276 		if (ret >= 0)
1277 			ret = -EIO;
1278 
1279 		msleep(IQS7211_COMMS_RETRY_MS);
1280 		return ret;
1281 	}
1282 
1283 	iqs7211_irq_wait();
1284 
1285 	return iqs7211_irq_poll(iqs7211, IQS7211_COMMS_TIMEOUT_US);
1286 }
1287 
1288 static int iqs7211_read_burst(struct iqs7211_private *iqs7211,
1289 			      u8 reg, void *val, u16 val_len)
1290 {
1291 	int ret, i;
1292 	struct i2c_client *client = iqs7211->client;
1293 	struct i2c_msg msg[] = {
1294 		{
1295 			.addr = client->addr,
1296 			.flags = 0,
1297 			.len = sizeof(reg),
1298 			.buf = &reg,
1299 		},
1300 		{
1301 			.addr = client->addr,
1302 			.flags = I2C_M_RD,
1303 			.len = val_len,
1304 			.buf = (u8 *)val,
1305 		},
1306 	};
1307 
1308 	/*
1309 	 * The following loop protects against an edge case in which the RDY
1310 	 * pin is automatically deasserted just as the read is initiated. In
1311 	 * that case, the read must be retried using forced communication.
1312 	 */
1313 	for (i = 0; i < IQS7211_NUM_RETRIES; i++) {
1314 		ret = iqs7211_force_comms(iqs7211);
1315 		if (ret < 0)
1316 			continue;
1317 
1318 		ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1319 		if (ret < (int)ARRAY_SIZE(msg)) {
1320 			if (ret >= 0)
1321 				ret = -EIO;
1322 
1323 			msleep(IQS7211_COMMS_RETRY_MS);
1324 			continue;
1325 		}
1326 
1327 		if (get_unaligned_le16(msg[1].buf) == IQS7211_COMMS_ERROR) {
1328 			ret = -ENODATA;
1329 			continue;
1330 		}
1331 
1332 		ret = 0;
1333 		break;
1334 	}
1335 
1336 	iqs7211_irq_wait();
1337 
1338 	if (ret < 0)
1339 		dev_err(&client->dev,
1340 			"Failed to read from address 0x%02X: %d\n", reg, ret);
1341 
1342 	return ret;
1343 }
1344 
1345 static int iqs7211_read_word(struct iqs7211_private *iqs7211, u8 reg, u16 *val)
1346 {
1347 	__le16 val_buf;
1348 	int error;
1349 
1350 	error = iqs7211_read_burst(iqs7211, reg, &val_buf, sizeof(val_buf));
1351 	if (error)
1352 		return error;
1353 
1354 	*val = le16_to_cpu(val_buf);
1355 
1356 	return 0;
1357 }
1358 
1359 static int iqs7211_write_burst(struct iqs7211_private *iqs7211,
1360 			       u8 reg, const void *val, u16 val_len)
1361 {
1362 	int msg_len = sizeof(reg) + val_len;
1363 	int ret, i;
1364 	struct i2c_client *client = iqs7211->client;
1365 	u8 *msg_buf;
1366 
1367 	msg_buf = kzalloc(msg_len, GFP_KERNEL);
1368 	if (!msg_buf)
1369 		return -ENOMEM;
1370 
1371 	*msg_buf = reg;
1372 	memcpy(msg_buf + sizeof(reg), val, val_len);
1373 
1374 	/*
1375 	 * The following loop protects against an edge case in which the RDY
1376 	 * pin is automatically asserted just before the force communication
1377 	 * command is sent.
1378 	 *
1379 	 * In that case, the subsequent I2C stop condition tricks the device
1380 	 * into preemptively deasserting the RDY pin and the command must be
1381 	 * sent again.
1382 	 */
1383 	for (i = 0; i < IQS7211_NUM_RETRIES; i++) {
1384 		ret = iqs7211_force_comms(iqs7211);
1385 		if (ret < 0)
1386 			continue;
1387 
1388 		ret = i2c_master_send(client, msg_buf, msg_len);
1389 		if (ret < msg_len) {
1390 			if (ret >= 0)
1391 				ret = -EIO;
1392 
1393 			msleep(IQS7211_COMMS_RETRY_MS);
1394 			continue;
1395 		}
1396 
1397 		ret = 0;
1398 		break;
1399 	}
1400 
1401 	kfree(msg_buf);
1402 
1403 	iqs7211_irq_wait();
1404 
1405 	if (ret < 0)
1406 		dev_err(&client->dev,
1407 			"Failed to write to address 0x%02X: %d\n", reg, ret);
1408 
1409 	return ret;
1410 }
1411 
1412 static int iqs7211_write_word(struct iqs7211_private *iqs7211, u8 reg, u16 val)
1413 {
1414 	__le16 val_buf = cpu_to_le16(val);
1415 
1416 	return iqs7211_write_burst(iqs7211, reg, &val_buf, sizeof(val_buf));
1417 }
1418 
1419 static int iqs7211_start_comms(struct iqs7211_private *iqs7211)
1420 {
1421 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
1422 	struct i2c_client *client = iqs7211->client;
1423 	bool forced_comms;
1424 	unsigned int val;
1425 	u16 comms_setup;
1426 	int error;
1427 
1428 	/*
1429 	 * Until forced communication can be enabled, the host must wait for a
1430 	 * communication window each time it intends to elicit a response from
1431 	 * the device.
1432 	 *
1433 	 * Forced communication is not necessary, however, if the host adapter
1434 	 * can support clock stretching. In that case, the device freely clock
1435 	 * stretches until all pending conversions are complete.
1436 	 */
1437 	forced_comms = device_property_present(&client->dev,
1438 					       "azoteq,forced-comms");
1439 
1440 	error = device_property_read_u32(&client->dev,
1441 					 "azoteq,forced-comms-default", &val);
1442 	if (error == -EINVAL) {
1443 		iqs7211->comms_init = IQS7211_COMMS_MODE_WAIT;
1444 	} else if (error) {
1445 		dev_err(&client->dev,
1446 			"Failed to read default communication mode: %d\n",
1447 			error);
1448 		return error;
1449 	} else if (val) {
1450 		iqs7211->comms_init = forced_comms ? IQS7211_COMMS_MODE_FORCE
1451 						   : IQS7211_COMMS_MODE_WAIT;
1452 	} else {
1453 		iqs7211->comms_init = forced_comms ? IQS7211_COMMS_MODE_WAIT
1454 						   : IQS7211_COMMS_MODE_FREE;
1455 	}
1456 
1457 	iqs7211->comms_mode = iqs7211->comms_init;
1458 
1459 	error = iqs7211_hard_reset(iqs7211);
1460 	if (error) {
1461 		dev_err(&client->dev, "Failed to reset device: %d\n", error);
1462 		return error;
1463 	}
1464 
1465 	error = iqs7211_read_burst(iqs7211, IQS7211_PROD_NUM,
1466 				   &iqs7211->ver_info,
1467 				   sizeof(iqs7211->ver_info));
1468 	if (error)
1469 		return error;
1470 
1471 	if (le16_to_cpu(iqs7211->ver_info.prod_num) != dev_desc->prod_num) {
1472 		dev_err(&client->dev, "Invalid product number: %u\n",
1473 			le16_to_cpu(iqs7211->ver_info.prod_num));
1474 		return -EINVAL;
1475 	}
1476 
1477 	error = iqs7211_read_word(iqs7211, dev_desc->sys_ctrl + 1,
1478 				  &comms_setup);
1479 	if (error)
1480 		return error;
1481 
1482 	if (forced_comms)
1483 		comms_setup |= dev_desc->comms_req;
1484 	else
1485 		comms_setup &= ~dev_desc->comms_req;
1486 
1487 	error = iqs7211_write_word(iqs7211, dev_desc->sys_ctrl + 1,
1488 				   comms_setup | dev_desc->comms_end);
1489 	if (error)
1490 		return error;
1491 
1492 	if (forced_comms)
1493 		iqs7211->comms_mode = IQS7211_COMMS_MODE_FORCE;
1494 	else
1495 		iqs7211->comms_mode = IQS7211_COMMS_MODE_FREE;
1496 
1497 	error = iqs7211_read_burst(iqs7211, dev_desc->exp_file,
1498 				   iqs7211->exp_file,
1499 				   sizeof(iqs7211->exp_file));
1500 	if (error)
1501 		return error;
1502 
1503 	error = iqs7211_read_burst(iqs7211, dev_desc->tp_config,
1504 				   &iqs7211->tp_config,
1505 				   sizeof(iqs7211->tp_config));
1506 	if (error)
1507 		return error;
1508 
1509 	error = iqs7211_write_word(iqs7211, dev_desc->sys_ctrl + 1,
1510 				   comms_setup);
1511 	if (error)
1512 		return error;
1513 
1514 	iqs7211->event_mask = comms_setup & ~IQS7211_EVENT_MASK_ALL;
1515 	iqs7211->event_mask |= (IQS7211_EVENT_MASK_ATI | IQS7211_EVENT_MODE);
1516 
1517 	return 0;
1518 }
1519 
1520 static int iqs7211_init_device(struct iqs7211_private *iqs7211)
1521 {
1522 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
1523 	struct iqs7211_reg_field_desc *reg_field;
1524 	__le16 sys_ctrl[] = {
1525 		cpu_to_le16(dev_desc->ack_reset),
1526 		cpu_to_le16(iqs7211->event_mask),
1527 	};
1528 	int error, i;
1529 
1530 	/*
1531 	 * Acknowledge reset before writing any registers in case the device
1532 	 * suffers a spurious reset during initialization. The communication
1533 	 * mode is configured at this time as well.
1534 	 */
1535 	error = iqs7211_write_burst(iqs7211, dev_desc->sys_ctrl, sys_ctrl,
1536 				    sizeof(sys_ctrl));
1537 	if (error)
1538 		return error;
1539 
1540 	if (iqs7211->event_mask & dev_desc->comms_req)
1541 		iqs7211->comms_mode = IQS7211_COMMS_MODE_FORCE;
1542 	else
1543 		iqs7211->comms_mode = IQS7211_COMMS_MODE_FREE;
1544 
1545 	/*
1546 	 * Take advantage of the stop-bit disable function, if available, to
1547 	 * save the trouble of having to reopen a communication window after
1548 	 * each read or write.
1549 	 */
1550 	error = iqs7211_write_word(iqs7211, dev_desc->sys_ctrl + 1,
1551 				   iqs7211->event_mask | dev_desc->comms_end);
1552 	if (error)
1553 		return error;
1554 
1555 	list_for_each_entry(reg_field, &iqs7211->reg_field_head, list) {
1556 		u16 new_val = reg_field->val;
1557 
1558 		if (reg_field->mask < U16_MAX) {
1559 			u16 old_val;
1560 
1561 			error = iqs7211_read_word(iqs7211, reg_field->addr,
1562 						  &old_val);
1563 			if (error)
1564 				return error;
1565 
1566 			new_val = old_val & ~reg_field->mask;
1567 			new_val |= reg_field->val;
1568 
1569 			if (new_val == old_val)
1570 				continue;
1571 		}
1572 
1573 		error = iqs7211_write_word(iqs7211, reg_field->addr, new_val);
1574 		if (error)
1575 			return error;
1576 	}
1577 
1578 	error = iqs7211_write_burst(iqs7211, dev_desc->tp_config,
1579 				    &iqs7211->tp_config,
1580 				    sizeof(iqs7211->tp_config));
1581 	if (error)
1582 		return error;
1583 
1584 	if (**iqs7211->cycle_alloc) {
1585 		error = iqs7211_write_burst(iqs7211, dev_desc->rx_tx_map,
1586 					    &iqs7211->rx_tx_map,
1587 					    dev_desc->num_ctx);
1588 		if (error)
1589 			return error;
1590 
1591 		for (i = 0; i < sizeof(dev_desc->cycle_limit); i++) {
1592 			error = iqs7211_write_burst(iqs7211,
1593 						    dev_desc->cycle_alloc[i],
1594 						    iqs7211->cycle_alloc[i],
1595 						    dev_desc->cycle_limit[i] * 3);
1596 			if (error)
1597 				return error;
1598 		}
1599 	}
1600 
1601 	*sys_ctrl = cpu_to_le16(iqs7211->ati_start);
1602 
1603 	return iqs7211_write_burst(iqs7211, dev_desc->sys_ctrl, sys_ctrl,
1604 				   sizeof(sys_ctrl));
1605 }
1606 
1607 static int iqs7211_add_field(struct iqs7211_private *iqs7211,
1608 			     struct iqs7211_reg_field_desc new_field)
1609 {
1610 	struct i2c_client *client = iqs7211->client;
1611 	struct iqs7211_reg_field_desc *reg_field;
1612 
1613 	if (!new_field.addr)
1614 		return 0;
1615 
1616 	list_for_each_entry(reg_field, &iqs7211->reg_field_head, list) {
1617 		if (reg_field->addr != new_field.addr)
1618 			continue;
1619 
1620 		reg_field->mask |= new_field.mask;
1621 		reg_field->val |= new_field.val;
1622 		return 0;
1623 	}
1624 
1625 	reg_field = devm_kzalloc(&client->dev, sizeof(*reg_field), GFP_KERNEL);
1626 	if (!reg_field)
1627 		return -ENOMEM;
1628 
1629 	reg_field->addr = new_field.addr;
1630 	reg_field->mask = new_field.mask;
1631 	reg_field->val = new_field.val;
1632 
1633 	list_add(&reg_field->list, &iqs7211->reg_field_head);
1634 
1635 	return 0;
1636 }
1637 
1638 static int iqs7211_parse_props(struct iqs7211_private *iqs7211,
1639 			       struct fwnode_handle *reg_grp_node,
1640 			       enum iqs7211_reg_grp_id reg_grp,
1641 			       enum iqs7211_reg_key_id reg_key)
1642 {
1643 	struct i2c_client *client = iqs7211->client;
1644 	int i;
1645 
1646 	for (i = 0; i < ARRAY_SIZE(iqs7211_props); i++) {
1647 		const char *name = iqs7211_props[i].name;
1648 		u8 reg_addr = iqs7211_props[i].reg_addr[reg_grp]
1649 						       [iqs7211->dev_desc -
1650 							iqs7211_devs];
1651 		int reg_shift = iqs7211_props[i].reg_shift;
1652 		int reg_width = iqs7211_props[i].reg_width ? : 16;
1653 		int val_pitch = iqs7211_props[i].val_pitch ? : 1;
1654 		int val_min = iqs7211_props[i].val_min;
1655 		int val_max = iqs7211_props[i].val_max;
1656 		const char *label = iqs7211_props[i].label ? : name;
1657 		struct iqs7211_reg_field_desc reg_field;
1658 		unsigned int val;
1659 		int error;
1660 
1661 		if (iqs7211_props[i].reg_key != reg_key)
1662 			continue;
1663 
1664 		if (!reg_addr)
1665 			continue;
1666 
1667 		error = fwnode_property_read_u32(reg_grp_node, name, &val);
1668 		if (error == -EINVAL) {
1669 			continue;
1670 		} else if (error) {
1671 			dev_err(&client->dev, "Failed to read %s %s: %d\n",
1672 				fwnode_get_name(reg_grp_node), label, error);
1673 			return error;
1674 		}
1675 
1676 		if (!val_max)
1677 			val_max = GENMASK(reg_width - 1, 0) * val_pitch;
1678 
1679 		if (val < val_min || val > val_max) {
1680 			dev_err(&client->dev, "Invalid %s: %u\n", label, val);
1681 			return -EINVAL;
1682 		}
1683 
1684 		reg_field.addr = reg_addr;
1685 		reg_field.mask = GENMASK(reg_shift + reg_width - 1, reg_shift);
1686 		reg_field.val = val / val_pitch << reg_shift;
1687 
1688 		error = iqs7211_add_field(iqs7211, reg_field);
1689 		if (error)
1690 			return error;
1691 	}
1692 
1693 	return 0;
1694 }
1695 
1696 static int iqs7211_parse_event(struct iqs7211_private *iqs7211,
1697 			       struct fwnode_handle *event_node,
1698 			       enum iqs7211_reg_grp_id reg_grp,
1699 			       enum iqs7211_reg_key_id reg_key,
1700 			       unsigned int *event_code)
1701 {
1702 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
1703 	struct i2c_client *client = iqs7211->client;
1704 	struct iqs7211_reg_field_desc reg_field;
1705 	unsigned int val;
1706 	int error;
1707 
1708 	error = iqs7211_parse_props(iqs7211, event_node, reg_grp, reg_key);
1709 	if (error)
1710 		return error;
1711 
1712 	if (reg_key == IQS7211_REG_KEY_AXIAL_X ||
1713 	    reg_key == IQS7211_REG_KEY_AXIAL_Y) {
1714 		error = fwnode_property_read_u32(event_node,
1715 						 "azoteq,gesture-angle", &val);
1716 		if (!error) {
1717 			if (val >= ARRAY_SIZE(iqs7211_gesture_angle)) {
1718 				dev_err(&client->dev,
1719 					"Invalid %s gesture angle: %u\n",
1720 					fwnode_get_name(event_node), val);
1721 				return -EINVAL;
1722 			}
1723 
1724 			reg_field.addr = dev_desc->gesture_angle;
1725 			reg_field.mask = U8_MAX;
1726 			reg_field.val = iqs7211_gesture_angle[val];
1727 
1728 			error = iqs7211_add_field(iqs7211, reg_field);
1729 			if (error)
1730 				return error;
1731 		} else if (error != -EINVAL) {
1732 			dev_err(&client->dev,
1733 				"Failed to read %s gesture angle: %d\n",
1734 				fwnode_get_name(event_node), error);
1735 			return error;
1736 		}
1737 	}
1738 
1739 	error = fwnode_property_read_u32(event_node, "linux,code", event_code);
1740 	if (error == -EINVAL)
1741 		error = 0;
1742 	else if (error)
1743 		dev_err(&client->dev, "Failed to read %s code: %d\n",
1744 			fwnode_get_name(event_node), error);
1745 
1746 	return error;
1747 }
1748 
1749 static int iqs7211_parse_cycles(struct iqs7211_private *iqs7211,
1750 				struct fwnode_handle *tp_node)
1751 {
1752 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
1753 	struct i2c_client *client = iqs7211->client;
1754 	int num_cycles = dev_desc->cycle_limit[0] + dev_desc->cycle_limit[1];
1755 	int error, count, i, j, k, cycle_start;
1756 	unsigned int cycle_alloc[IQS7211_MAX_CYCLES][2];
1757 	u8 total_rx = iqs7211->tp_config.total_rx;
1758 	u8 total_tx = iqs7211->tp_config.total_tx;
1759 
1760 	for (i = 0; i < IQS7211_MAX_CYCLES * 2; i++)
1761 		*(cycle_alloc[0] + i) = U8_MAX;
1762 
1763 	count = fwnode_property_count_u32(tp_node, "azoteq,channel-select");
1764 	if (count == -EINVAL) {
1765 		/*
1766 		 * Assign each sensing cycle's slots (0 and 1) to a channel,
1767 		 * defined as the intersection between two CRx and CTx pins.
1768 		 * A channel assignment of 255 means the slot is unused.
1769 		 */
1770 		for (i = 0, cycle_start = 0; i < total_tx; i++) {
1771 			int cycle_stop = 0;
1772 
1773 			for (j = 0; j < total_rx; j++) {
1774 				/*
1775 				 * Channels formed by CRx0-3 and CRx4-7 are
1776 				 * bound to slots 0 and 1, respectively.
1777 				 */
1778 				int slot = iqs7211->rx_tx_map[j] < 4 ? 0 : 1;
1779 				int chan = i * total_rx + j;
1780 
1781 				for (k = cycle_start; k < num_cycles; k++) {
1782 					if (cycle_alloc[k][slot] < U8_MAX)
1783 						continue;
1784 
1785 					cycle_alloc[k][slot] = chan;
1786 					break;
1787 				}
1788 
1789 				if (k < num_cycles) {
1790 					cycle_stop = max(k, cycle_stop);
1791 					continue;
1792 				}
1793 
1794 				dev_err(&client->dev,
1795 					"Insufficient number of cycles\n");
1796 				return -EINVAL;
1797 			}
1798 
1799 			/*
1800 			 * Sensing cycles cannot straddle more than one CTx
1801 			 * pin. As such, the next row's starting cycle must
1802 			 * be greater than the previous row's highest cycle.
1803 			 */
1804 			cycle_start = cycle_stop + 1;
1805 		}
1806 	} else if (count < 0) {
1807 		dev_err(&client->dev, "Failed to count channels: %d\n", count);
1808 		return count;
1809 	} else if (count > num_cycles * 2) {
1810 		dev_err(&client->dev, "Insufficient number of cycles\n");
1811 		return -EINVAL;
1812 	} else if (count > 0) {
1813 		error = fwnode_property_read_u32_array(tp_node,
1814 						       "azoteq,channel-select",
1815 						       cycle_alloc[0], count);
1816 		if (error) {
1817 			dev_err(&client->dev, "Failed to read channels: %d\n",
1818 				error);
1819 			return error;
1820 		}
1821 
1822 		for (i = 0; i < count; i++) {
1823 			int chan = *(cycle_alloc[0] + i);
1824 
1825 			if (chan == U8_MAX)
1826 				continue;
1827 
1828 			if (chan >= total_rx * total_tx) {
1829 				dev_err(&client->dev, "Invalid channel: %d\n",
1830 					chan);
1831 				return -EINVAL;
1832 			}
1833 
1834 			for (j = 0; j < count; j++) {
1835 				if (j == i || *(cycle_alloc[0] + j) != chan)
1836 					continue;
1837 
1838 				dev_err(&client->dev, "Duplicate channel: %d\n",
1839 					chan);
1840 				return -EINVAL;
1841 			}
1842 		}
1843 	}
1844 
1845 	/*
1846 	 * Once the raw channel assignments have been derived, they must be
1847 	 * packed according to the device's register map.
1848 	 */
1849 	for (i = 0, cycle_start = 0; i < sizeof(dev_desc->cycle_limit); i++) {
1850 		int offs = 0;
1851 
1852 		for (j = cycle_start;
1853 		     j < cycle_start + dev_desc->cycle_limit[i]; j++) {
1854 			iqs7211->cycle_alloc[i][offs++] = 0x05;
1855 			iqs7211->cycle_alloc[i][offs++] = cycle_alloc[j][0];
1856 			iqs7211->cycle_alloc[i][offs++] = cycle_alloc[j][1];
1857 		}
1858 
1859 		cycle_start += dev_desc->cycle_limit[i];
1860 	}
1861 
1862 	return 0;
1863 }
1864 
1865 static int iqs7211_parse_tp(struct iqs7211_private *iqs7211,
1866 			    struct fwnode_handle *tp_node)
1867 {
1868 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
1869 	struct i2c_client *client = iqs7211->client;
1870 	unsigned int pins[IQS7211_MAX_CTX];
1871 	int error, count, i, j;
1872 
1873 	count = fwnode_property_count_u32(tp_node, "azoteq,rx-enable");
1874 	if (count == -EINVAL) {
1875 		return 0;
1876 	} else if (count < 0) {
1877 		dev_err(&client->dev, "Failed to count CRx pins: %d\n", count);
1878 		return count;
1879 	} else if (count > IQS7211_NUM_CRX) {
1880 		dev_err(&client->dev, "Invalid number of CRx pins\n");
1881 		return -EINVAL;
1882 	}
1883 
1884 	error = fwnode_property_read_u32_array(tp_node, "azoteq,rx-enable",
1885 					       pins, count);
1886 	if (error) {
1887 		dev_err(&client->dev, "Failed to read CRx pins: %d\n", error);
1888 		return error;
1889 	}
1890 
1891 	for (i = 0; i < count; i++) {
1892 		if (pins[i] >= IQS7211_NUM_CRX) {
1893 			dev_err(&client->dev, "Invalid CRx pin: %u\n", pins[i]);
1894 			return -EINVAL;
1895 		}
1896 
1897 		iqs7211->rx_tx_map[i] = pins[i];
1898 	}
1899 
1900 	iqs7211->tp_config.total_rx = count;
1901 
1902 	count = fwnode_property_count_u32(tp_node, "azoteq,tx-enable");
1903 	if (count < 0) {
1904 		dev_err(&client->dev, "Failed to count CTx pins: %d\n", count);
1905 		return count;
1906 	} else if (count > dev_desc->num_ctx) {
1907 		dev_err(&client->dev, "Invalid number of CTx pins\n");
1908 		return -EINVAL;
1909 	}
1910 
1911 	error = fwnode_property_read_u32_array(tp_node, "azoteq,tx-enable",
1912 					       pins, count);
1913 	if (error) {
1914 		dev_err(&client->dev, "Failed to read CTx pins: %d\n", error);
1915 		return error;
1916 	}
1917 
1918 	for (i = 0; i < count; i++) {
1919 		if (pins[i] >= dev_desc->num_ctx) {
1920 			dev_err(&client->dev, "Invalid CTx pin: %u\n", pins[i]);
1921 			return -EINVAL;
1922 		}
1923 
1924 		for (j = 0; j < iqs7211->tp_config.total_rx; j++) {
1925 			if (iqs7211->rx_tx_map[j] != pins[i])
1926 				continue;
1927 
1928 			dev_err(&client->dev, "Conflicting CTx pin: %u\n",
1929 				pins[i]);
1930 			return -EINVAL;
1931 		}
1932 
1933 		iqs7211->rx_tx_map[iqs7211->tp_config.total_rx + i] = pins[i];
1934 	}
1935 
1936 	iqs7211->tp_config.total_tx = count;
1937 
1938 	return iqs7211_parse_cycles(iqs7211, tp_node);
1939 }
1940 
1941 static int iqs7211_parse_alp(struct iqs7211_private *iqs7211,
1942 			     struct fwnode_handle *alp_node)
1943 {
1944 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
1945 	struct i2c_client *client = iqs7211->client;
1946 	struct iqs7211_reg_field_desc reg_field;
1947 	int error, count, i;
1948 
1949 	count = fwnode_property_count_u32(alp_node, "azoteq,rx-enable");
1950 	if (count < 0 && count != -EINVAL) {
1951 		dev_err(&client->dev, "Failed to count CRx pins: %d\n", count);
1952 		return count;
1953 	} else if (count > IQS7211_NUM_CRX) {
1954 		dev_err(&client->dev, "Invalid number of CRx pins\n");
1955 		return -EINVAL;
1956 	} else if (count >= 0) {
1957 		unsigned int pins[IQS7211_NUM_CRX];
1958 
1959 		error = fwnode_property_read_u32_array(alp_node,
1960 						       "azoteq,rx-enable",
1961 						       pins, count);
1962 		if (error) {
1963 			dev_err(&client->dev, "Failed to read CRx pins: %d\n",
1964 				error);
1965 			return error;
1966 		}
1967 
1968 		reg_field.addr = dev_desc->alp_config;
1969 		reg_field.mask = GENMASK(IQS7211_NUM_CRX - 1, 0);
1970 		reg_field.val = 0;
1971 
1972 		for (i = 0; i < count; i++) {
1973 			if (pins[i] < dev_desc->min_crx_alp ||
1974 			    pins[i] >= IQS7211_NUM_CRX) {
1975 				dev_err(&client->dev, "Invalid CRx pin: %u\n",
1976 					pins[i]);
1977 				return -EINVAL;
1978 			}
1979 
1980 			reg_field.val |= BIT(pins[i]);
1981 		}
1982 
1983 		error = iqs7211_add_field(iqs7211, reg_field);
1984 		if (error)
1985 			return error;
1986 	}
1987 
1988 	count = fwnode_property_count_u32(alp_node, "azoteq,tx-enable");
1989 	if (count < 0 && count != -EINVAL) {
1990 		dev_err(&client->dev, "Failed to count CTx pins: %d\n", count);
1991 		return count;
1992 	} else if (count > dev_desc->num_ctx) {
1993 		dev_err(&client->dev, "Invalid number of CTx pins\n");
1994 		return -EINVAL;
1995 	} else if (count >= 0) {
1996 		unsigned int pins[IQS7211_MAX_CTX];
1997 
1998 		error = fwnode_property_read_u32_array(alp_node,
1999 						       "azoteq,tx-enable",
2000 						       pins, count);
2001 		if (error) {
2002 			dev_err(&client->dev, "Failed to read CTx pins: %d\n",
2003 				error);
2004 			return error;
2005 		}
2006 
2007 		reg_field.addr = dev_desc->alp_config + 1;
2008 		reg_field.mask = GENMASK(dev_desc->num_ctx - 1, 0);
2009 		reg_field.val = 0;
2010 
2011 		for (i = 0; i < count; i++) {
2012 			if (pins[i] >= dev_desc->num_ctx) {
2013 				dev_err(&client->dev, "Invalid CTx pin: %u\n",
2014 					pins[i]);
2015 				return -EINVAL;
2016 			}
2017 
2018 			reg_field.val |= BIT(pins[i]);
2019 		}
2020 
2021 		error = iqs7211_add_field(iqs7211, reg_field);
2022 		if (error)
2023 			return error;
2024 	}
2025 
2026 	return 0;
2027 }
2028 
2029 static int (*iqs7211_parse_extra[IQS7211_NUM_REG_GRPS])
2030 				(struct iqs7211_private *iqs7211,
2031 				 struct fwnode_handle *reg_grp_node) = {
2032 	[IQS7211_REG_GRP_TP] = iqs7211_parse_tp,
2033 	[IQS7211_REG_GRP_ALP] = iqs7211_parse_alp,
2034 };
2035 
2036 static int iqs7211_parse_reg_grp(struct iqs7211_private *iqs7211,
2037 				 struct fwnode_handle *reg_grp_node,
2038 				 enum iqs7211_reg_grp_id reg_grp)
2039 {
2040 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
2041 	struct iqs7211_reg_field_desc reg_field;
2042 	int error, i;
2043 
2044 	error = iqs7211_parse_props(iqs7211, reg_grp_node, reg_grp,
2045 				    IQS7211_REG_KEY_NONE);
2046 	if (error)
2047 		return error;
2048 
2049 	if (iqs7211_parse_extra[reg_grp]) {
2050 		error = iqs7211_parse_extra[reg_grp](iqs7211, reg_grp_node);
2051 		if (error)
2052 			return error;
2053 	}
2054 
2055 	iqs7211->ati_start |= dev_desc->ati_start[reg_grp];
2056 
2057 	reg_field.addr = dev_desc->kp_enable[reg_grp];
2058 	reg_field.mask = 0;
2059 	reg_field.val = 0;
2060 
2061 	for (i = 0; i < dev_desc->num_kp_events; i++) {
2062 		const char *event_name = dev_desc->kp_events[i].name;
2063 		struct fwnode_handle *event_node;
2064 
2065 		if (dev_desc->kp_events[i].reg_grp != reg_grp)
2066 			continue;
2067 
2068 		reg_field.mask |= dev_desc->kp_events[i].enable;
2069 
2070 		if (event_name)
2071 			event_node = fwnode_get_named_child_node(reg_grp_node,
2072 								 event_name);
2073 		else
2074 			event_node = fwnode_handle_get(reg_grp_node);
2075 
2076 		if (!event_node)
2077 			continue;
2078 
2079 		error = iqs7211_parse_event(iqs7211, event_node,
2080 					    dev_desc->kp_events[i].reg_grp,
2081 					    dev_desc->kp_events[i].reg_key,
2082 					    &iqs7211->kp_code[i]);
2083 		fwnode_handle_put(event_node);
2084 		if (error)
2085 			return error;
2086 
2087 		reg_field.val |= dev_desc->kp_events[i].enable;
2088 
2089 		iqs7211->event_mask |= iqs7211_reg_grp_masks[reg_grp];
2090 	}
2091 
2092 	return iqs7211_add_field(iqs7211, reg_field);
2093 }
2094 
2095 static int iqs7211_register_kp(struct iqs7211_private *iqs7211)
2096 {
2097 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
2098 	struct input_dev *kp_idev = iqs7211->kp_idev;
2099 	struct i2c_client *client = iqs7211->client;
2100 	int error, i;
2101 
2102 	for (i = 0; i < dev_desc->num_kp_events; i++)
2103 		if (iqs7211->kp_code[i])
2104 			break;
2105 
2106 	if (i == dev_desc->num_kp_events)
2107 		return 0;
2108 
2109 	kp_idev = devm_input_allocate_device(&client->dev);
2110 	if (!kp_idev)
2111 		return -ENOMEM;
2112 
2113 	iqs7211->kp_idev = kp_idev;
2114 
2115 	kp_idev->name = dev_desc->kp_name;
2116 	kp_idev->id.bustype = BUS_I2C;
2117 
2118 	for (i = 0; i < dev_desc->num_kp_events; i++)
2119 		if (iqs7211->kp_code[i])
2120 			input_set_capability(iqs7211->kp_idev, EV_KEY,
2121 					     iqs7211->kp_code[i]);
2122 
2123 	error = input_register_device(kp_idev);
2124 	if (error)
2125 		dev_err(&client->dev, "Failed to register %s: %d\n",
2126 			kp_idev->name, error);
2127 
2128 	return error;
2129 }
2130 
2131 static int iqs7211_register_tp(struct iqs7211_private *iqs7211)
2132 {
2133 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
2134 	struct touchscreen_properties *prop = &iqs7211->prop;
2135 	struct input_dev *tp_idev = iqs7211->tp_idev;
2136 	struct i2c_client *client = iqs7211->client;
2137 	int error;
2138 
2139 	error = device_property_read_u32(&client->dev, "azoteq,num-contacts",
2140 					 &iqs7211->num_contacts);
2141 	if (error == -EINVAL) {
2142 		return 0;
2143 	} else if (error) {
2144 		dev_err(&client->dev, "Failed to read number of contacts: %d\n",
2145 			error);
2146 		return error;
2147 	} else if (iqs7211->num_contacts > IQS7211_MAX_CONTACTS) {
2148 		dev_err(&client->dev, "Invalid number of contacts: %u\n",
2149 			iqs7211->num_contacts);
2150 		return -EINVAL;
2151 	}
2152 
2153 	iqs7211->tp_config.num_contacts = iqs7211->num_contacts ? : 1;
2154 
2155 	if (!iqs7211->num_contacts)
2156 		return 0;
2157 
2158 	iqs7211->event_mask |= IQS7211_EVENT_MASK_MOVE;
2159 
2160 	tp_idev = devm_input_allocate_device(&client->dev);
2161 	if (!tp_idev)
2162 		return -ENOMEM;
2163 
2164 	iqs7211->tp_idev = tp_idev;
2165 
2166 	tp_idev->name = dev_desc->tp_name;
2167 	tp_idev->id.bustype = BUS_I2C;
2168 
2169 	input_set_abs_params(tp_idev, ABS_MT_POSITION_X,
2170 			     0, le16_to_cpu(iqs7211->tp_config.max_x), 0, 0);
2171 
2172 	input_set_abs_params(tp_idev, ABS_MT_POSITION_Y,
2173 			     0, le16_to_cpu(iqs7211->tp_config.max_y), 0, 0);
2174 
2175 	input_set_abs_params(tp_idev, ABS_MT_PRESSURE, 0, U16_MAX, 0, 0);
2176 
2177 	touchscreen_parse_properties(tp_idev, true, prop);
2178 
2179 	/*
2180 	 * The device reserves 0xFFFF for coordinates that correspond to slots
2181 	 * which are not in a state of touch.
2182 	 */
2183 	if (prop->max_x >= U16_MAX || prop->max_y >= U16_MAX) {
2184 		dev_err(&client->dev, "Invalid trackpad size: %u*%u\n",
2185 			prop->max_x, prop->max_y);
2186 		return -EINVAL;
2187 	}
2188 
2189 	iqs7211->tp_config.max_x = cpu_to_le16(prop->max_x);
2190 	iqs7211->tp_config.max_y = cpu_to_le16(prop->max_y);
2191 
2192 	error = input_mt_init_slots(tp_idev, iqs7211->num_contacts,
2193 				    INPUT_MT_DIRECT);
2194 	if (error) {
2195 		dev_err(&client->dev, "Failed to initialize slots: %d\n",
2196 			error);
2197 		return error;
2198 	}
2199 
2200 	error = input_register_device(tp_idev);
2201 	if (error)
2202 		dev_err(&client->dev, "Failed to register %s: %d\n",
2203 			tp_idev->name, error);
2204 
2205 	return error;
2206 }
2207 
2208 static int iqs7211_report(struct iqs7211_private *iqs7211)
2209 {
2210 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
2211 	struct i2c_client *client = iqs7211->client;
2212 	struct iqs7211_touch_data *touch_data;
2213 	u16 info_flags, charge_mode, gesture_flags;
2214 	__le16 status[12];
2215 	int error, i;
2216 
2217 	error = iqs7211_read_burst(iqs7211, dev_desc->sys_stat, status,
2218 				   dev_desc->contact_offs * sizeof(__le16) +
2219 				   iqs7211->num_contacts * sizeof(*touch_data));
2220 	if (error)
2221 		return error;
2222 
2223 	info_flags = le16_to_cpu(status[dev_desc->info_offs]);
2224 
2225 	if (info_flags & dev_desc->show_reset) {
2226 		dev_err(&client->dev, "Unexpected device reset\n");
2227 
2228 		/*
2229 		 * The device may or may not expect forced communication after
2230 		 * it exits hardware reset, so the corresponding state machine
2231 		 * must be reset as well.
2232 		 */
2233 		iqs7211->comms_mode = iqs7211->comms_init;
2234 
2235 		return iqs7211_init_device(iqs7211);
2236 	}
2237 
2238 	for (i = 0; i < ARRAY_SIZE(dev_desc->ati_error); i++) {
2239 		if (!(info_flags & dev_desc->ati_error[i]))
2240 			continue;
2241 
2242 		dev_err(&client->dev, "Unexpected %s ATI error\n",
2243 			iqs7211_reg_grp_names[i]);
2244 		return 0;
2245 	}
2246 
2247 	for (i = 0; i < iqs7211->num_contacts; i++) {
2248 		u16 pressure;
2249 
2250 		touch_data = (struct iqs7211_touch_data *)
2251 			     &status[dev_desc->contact_offs] + i;
2252 		pressure = le16_to_cpu(touch_data->pressure);
2253 
2254 		input_mt_slot(iqs7211->tp_idev, i);
2255 		if (input_mt_report_slot_state(iqs7211->tp_idev, MT_TOOL_FINGER,
2256 					       pressure != 0)) {
2257 			touchscreen_report_pos(iqs7211->tp_idev, &iqs7211->prop,
2258 					       le16_to_cpu(touch_data->abs_x),
2259 					       le16_to_cpu(touch_data->abs_y),
2260 					       true);
2261 			input_report_abs(iqs7211->tp_idev, ABS_MT_PRESSURE,
2262 					 pressure);
2263 		}
2264 	}
2265 
2266 	if (iqs7211->num_contacts) {
2267 		input_mt_sync_frame(iqs7211->tp_idev);
2268 		input_sync(iqs7211->tp_idev);
2269 	}
2270 
2271 	if (!iqs7211->kp_idev)
2272 		return 0;
2273 
2274 	charge_mode = info_flags & GENMASK(dev_desc->charge_shift + 2,
2275 					   dev_desc->charge_shift);
2276 	charge_mode >>= dev_desc->charge_shift;
2277 
2278 	/*
2279 	 * A charging mode higher than 2 (idle mode) indicates the device last
2280 	 * operated in low-power mode and intends to express an ALP event.
2281 	 */
2282 	if (info_flags & dev_desc->kp_events->mask && charge_mode > 2) {
2283 		input_report_key(iqs7211->kp_idev, *iqs7211->kp_code, 1);
2284 		input_sync(iqs7211->kp_idev);
2285 
2286 		input_report_key(iqs7211->kp_idev, *iqs7211->kp_code, 0);
2287 	}
2288 
2289 	for (i = 0; i < dev_desc->num_kp_events; i++) {
2290 		if (dev_desc->kp_events[i].reg_grp != IQS7211_REG_GRP_BTN)
2291 			continue;
2292 
2293 		input_report_key(iqs7211->kp_idev, iqs7211->kp_code[i],
2294 				 info_flags & dev_desc->kp_events[i].mask);
2295 	}
2296 
2297 	gesture_flags = le16_to_cpu(status[dev_desc->gesture_offs]);
2298 
2299 	for (i = 0; i < dev_desc->num_kp_events; i++) {
2300 		enum iqs7211_reg_key_id reg_key = dev_desc->kp_events[i].reg_key;
2301 		u16 mask = dev_desc->kp_events[i].mask;
2302 
2303 		if (dev_desc->kp_events[i].reg_grp != IQS7211_REG_GRP_TP)
2304 			continue;
2305 
2306 		if ((gesture_flags ^ iqs7211->gesture_cache) & mask)
2307 			input_report_key(iqs7211->kp_idev, iqs7211->kp_code[i],
2308 					 gesture_flags & mask);
2309 
2310 		iqs7211->gesture_cache &= ~mask;
2311 
2312 		/*
2313 		 * Hold and palm gestures persist while the contact remains in
2314 		 * place; all others are momentary and hence are followed by a
2315 		 * complementary release event.
2316 		 */
2317 		if (reg_key == IQS7211_REG_KEY_HOLD ||
2318 		    reg_key == IQS7211_REG_KEY_PALM) {
2319 			iqs7211->gesture_cache |= gesture_flags & mask;
2320 			gesture_flags &= ~mask;
2321 		}
2322 	}
2323 
2324 	if (gesture_flags) {
2325 		input_sync(iqs7211->kp_idev);
2326 
2327 		for (i = 0; i < dev_desc->num_kp_events; i++)
2328 			if (dev_desc->kp_events[i].reg_grp == IQS7211_REG_GRP_TP &&
2329 			    gesture_flags & dev_desc->kp_events[i].mask)
2330 				input_report_key(iqs7211->kp_idev,
2331 						 iqs7211->kp_code[i], 0);
2332 	}
2333 
2334 	input_sync(iqs7211->kp_idev);
2335 
2336 	return 0;
2337 }
2338 
2339 static irqreturn_t iqs7211_irq(int irq, void *context)
2340 {
2341 	struct iqs7211_private *iqs7211 = context;
2342 
2343 	return iqs7211_report(iqs7211) ? IRQ_NONE : IRQ_HANDLED;
2344 }
2345 
2346 static int iqs7211_suspend(struct device *dev)
2347 {
2348 	struct iqs7211_private *iqs7211 = dev_get_drvdata(dev);
2349 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
2350 	int error;
2351 
2352 	if (!dev_desc->suspend || device_may_wakeup(dev))
2353 		return 0;
2354 
2355 	/*
2356 	 * I2C communication prompts the device to assert its RDY pin if it is
2357 	 * not already asserted. As such, the interrupt must be disabled so as
2358 	 * to prevent reentrant interrupts.
2359 	 */
2360 	disable_irq(gpiod_to_irq(iqs7211->irq_gpio));
2361 
2362 	error = iqs7211_write_word(iqs7211, dev_desc->sys_ctrl,
2363 				   dev_desc->suspend);
2364 
2365 	enable_irq(gpiod_to_irq(iqs7211->irq_gpio));
2366 
2367 	return error;
2368 }
2369 
2370 static int iqs7211_resume(struct device *dev)
2371 {
2372 	struct iqs7211_private *iqs7211 = dev_get_drvdata(dev);
2373 	const struct iqs7211_dev_desc *dev_desc = iqs7211->dev_desc;
2374 	__le16 sys_ctrl[] = {
2375 		0,
2376 		cpu_to_le16(iqs7211->event_mask),
2377 	};
2378 	int error;
2379 
2380 	if (!dev_desc->suspend || device_may_wakeup(dev))
2381 		return 0;
2382 
2383 	disable_irq(gpiod_to_irq(iqs7211->irq_gpio));
2384 
2385 	/*
2386 	 * Forced communication, if in use, must be explicitly enabled as part
2387 	 * of the wake-up command.
2388 	 */
2389 	error = iqs7211_write_burst(iqs7211, dev_desc->sys_ctrl, sys_ctrl,
2390 				    sizeof(sys_ctrl));
2391 
2392 	enable_irq(gpiod_to_irq(iqs7211->irq_gpio));
2393 
2394 	return error;
2395 }
2396 
2397 static DEFINE_SIMPLE_DEV_PM_OPS(iqs7211_pm, iqs7211_suspend, iqs7211_resume);
2398 
2399 static ssize_t fw_info_show(struct device *dev,
2400 			    struct device_attribute *attr, char *buf)
2401 {
2402 	struct iqs7211_private *iqs7211 = dev_get_drvdata(dev);
2403 
2404 	return scnprintf(buf, PAGE_SIZE, "%u.%u.%u.%u:%u.%u\n",
2405 			 le16_to_cpu(iqs7211->ver_info.prod_num),
2406 			 le32_to_cpu(iqs7211->ver_info.patch),
2407 			 le16_to_cpu(iqs7211->ver_info.major),
2408 			 le16_to_cpu(iqs7211->ver_info.minor),
2409 			 iqs7211->exp_file[1], iqs7211->exp_file[0]);
2410 }
2411 
2412 static DEVICE_ATTR_RO(fw_info);
2413 
2414 static struct attribute *iqs7211_attrs[] = {
2415 	&dev_attr_fw_info.attr,
2416 	NULL
2417 };
2418 ATTRIBUTE_GROUPS(iqs7211);
2419 
2420 static const struct of_device_id iqs7211_of_match[] = {
2421 	{
2422 		.compatible = "azoteq,iqs7210a",
2423 		.data = &iqs7211_devs[IQS7210A],
2424 	},
2425 	{
2426 		.compatible = "azoteq,iqs7211a",
2427 		.data = &iqs7211_devs[IQS7211A],
2428 	},
2429 	{
2430 		.compatible = "azoteq,iqs7211e",
2431 		.data = &iqs7211_devs[IQS7211E],
2432 	},
2433 	{ }
2434 };
2435 MODULE_DEVICE_TABLE(of, iqs7211_of_match);
2436 
2437 static int iqs7211_probe(struct i2c_client *client)
2438 {
2439 	struct iqs7211_private *iqs7211;
2440 	enum iqs7211_reg_grp_id reg_grp;
2441 	unsigned long irq_flags;
2442 	bool shared_irq;
2443 	int error, irq;
2444 
2445 	iqs7211 = devm_kzalloc(&client->dev, sizeof(*iqs7211), GFP_KERNEL);
2446 	if (!iqs7211)
2447 		return -ENOMEM;
2448 
2449 	i2c_set_clientdata(client, iqs7211);
2450 	iqs7211->client = client;
2451 
2452 	INIT_LIST_HEAD(&iqs7211->reg_field_head);
2453 
2454 	iqs7211->dev_desc = device_get_match_data(&client->dev);
2455 	if (!iqs7211->dev_desc)
2456 		return -ENODEV;
2457 
2458 	shared_irq = iqs7211->dev_desc->num_ctx == IQS7211_MAX_CTX;
2459 
2460 	/*
2461 	 * The RDY pin behaves as an interrupt, but must also be polled ahead
2462 	 * of unsolicited I2C communication. As such, it is first opened as a
2463 	 * GPIO and then passed to gpiod_to_irq() to register the interrupt.
2464 	 *
2465 	 * If an extra CTx pin is present, the RDY and MCLR pins are combined
2466 	 * into a single bidirectional pin. In that case, the platform's GPIO
2467 	 * must be configured as an open-drain output.
2468 	 */
2469 	iqs7211->irq_gpio = devm_gpiod_get(&client->dev, "irq",
2470 					   shared_irq ? GPIOD_OUT_LOW
2471 						      : GPIOD_IN);
2472 	if (IS_ERR(iqs7211->irq_gpio)) {
2473 		error = PTR_ERR(iqs7211->irq_gpio);
2474 		dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
2475 			error);
2476 		return error;
2477 	}
2478 
2479 	if (shared_irq) {
2480 		iqs7211->reset_gpio = iqs7211->irq_gpio;
2481 	} else {
2482 		iqs7211->reset_gpio = devm_gpiod_get_optional(&client->dev,
2483 							      "reset",
2484 							      GPIOD_OUT_HIGH);
2485 		if (IS_ERR(iqs7211->reset_gpio)) {
2486 			error = PTR_ERR(iqs7211->reset_gpio);
2487 			dev_err(&client->dev,
2488 				"Failed to request reset GPIO: %d\n", error);
2489 			return error;
2490 		}
2491 	}
2492 
2493 	error = iqs7211_start_comms(iqs7211);
2494 	if (error)
2495 		return error;
2496 
2497 	for (reg_grp = 0; reg_grp < IQS7211_NUM_REG_GRPS; reg_grp++) {
2498 		const char *reg_grp_name = iqs7211_reg_grp_names[reg_grp];
2499 		struct fwnode_handle *reg_grp_node;
2500 
2501 		if (reg_grp_name)
2502 			reg_grp_node = device_get_named_child_node(&client->dev,
2503 								   reg_grp_name);
2504 		else
2505 			reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev));
2506 
2507 		if (!reg_grp_node)
2508 			continue;
2509 
2510 		error = iqs7211_parse_reg_grp(iqs7211, reg_grp_node, reg_grp);
2511 		fwnode_handle_put(reg_grp_node);
2512 		if (error)
2513 			return error;
2514 	}
2515 
2516 	error = iqs7211_register_kp(iqs7211);
2517 	if (error)
2518 		return error;
2519 
2520 	error = iqs7211_register_tp(iqs7211);
2521 	if (error)
2522 		return error;
2523 
2524 	error = iqs7211_init_device(iqs7211);
2525 	if (error)
2526 		return error;
2527 
2528 	irq = gpiod_to_irq(iqs7211->irq_gpio);
2529 	if (irq < 0)
2530 		return irq;
2531 
2532 	irq_flags = gpiod_is_active_low(iqs7211->irq_gpio) ? IRQF_TRIGGER_LOW
2533 							   : IRQF_TRIGGER_HIGH;
2534 	irq_flags |= IRQF_ONESHOT;
2535 
2536 	error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7211_irq,
2537 					  irq_flags, client->name, iqs7211);
2538 	if (error)
2539 		dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
2540 
2541 	return error;
2542 }
2543 
2544 static struct i2c_driver iqs7211_i2c_driver = {
2545 	.probe = iqs7211_probe,
2546 	.driver = {
2547 		.name = "iqs7211",
2548 		.of_match_table = iqs7211_of_match,
2549 		.dev_groups = iqs7211_groups,
2550 		.pm = pm_sleep_ptr(&iqs7211_pm),
2551 	},
2552 };
2553 module_i2c_driver(iqs7211_i2c_driver);
2554 
2555 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
2556 MODULE_DESCRIPTION("Azoteq IQS7210A/7211A/E Trackpad/Touchscreen Controller");
2557 MODULE_LICENSE("GPL");
2558