1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2012-2017 Hideep, Inc.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/firmware.h>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/i2c.h>
12 #include <linux/acpi.h>
13 #include <linux/interrupt.h>
14 #include <linux/regmap.h>
15 #include <linux/sysfs.h>
16 #include <linux/input.h>
17 #include <linux/input/mt.h>
18 #include <linux/input/touchscreen.h>
19 #include <linux/regulator/consumer.h>
20 #include <asm/unaligned.h>
21 
22 #define HIDEEP_TS_NAME			"HiDeep Touchscreen"
23 #define HIDEEP_I2C_NAME			"hideep_ts"
24 
25 #define HIDEEP_MT_MAX			10
26 #define HIDEEP_KEY_MAX			3
27 
28 /* count(2) + touch data(100) + key data(6) */
29 #define HIDEEP_MAX_EVENT		108UL
30 
31 #define HIDEEP_TOUCH_EVENT_INDEX	2
32 #define HIDEEP_KEY_EVENT_INDEX		102
33 
34 /* Touch & key event */
35 #define HIDEEP_EVENT_ADDR		0x240
36 
37 /* command list */
38 #define HIDEEP_RESET_CMD		0x9800
39 
40 /* event bit */
41 #define HIDEEP_MT_RELEASED		BIT(4)
42 #define HIDEEP_KEY_PRESSED		BIT(7)
43 #define HIDEEP_KEY_FIRST_PRESSED	BIT(8)
44 #define HIDEEP_KEY_PRESSED_MASK		(HIDEEP_KEY_PRESSED | \
45 					 HIDEEP_KEY_FIRST_PRESSED)
46 
47 #define HIDEEP_KEY_IDX_MASK		0x0f
48 
49 /* For NVM */
50 #define HIDEEP_YRAM_BASE		0x40000000
51 #define HIDEEP_PERIPHERAL_BASE		0x50000000
52 #define HIDEEP_ESI_BASE			(HIDEEP_PERIPHERAL_BASE + 0x00000000)
53 #define HIDEEP_FLASH_BASE		(HIDEEP_PERIPHERAL_BASE + 0x01000000)
54 #define HIDEEP_SYSCON_BASE		(HIDEEP_PERIPHERAL_BASE + 0x02000000)
55 
56 #define HIDEEP_SYSCON_MOD_CON		(HIDEEP_SYSCON_BASE + 0x0000)
57 #define HIDEEP_SYSCON_SPC_CON		(HIDEEP_SYSCON_BASE + 0x0004)
58 #define HIDEEP_SYSCON_CLK_CON		(HIDEEP_SYSCON_BASE + 0x0008)
59 #define HIDEEP_SYSCON_CLK_ENA		(HIDEEP_SYSCON_BASE + 0x000C)
60 #define HIDEEP_SYSCON_RST_CON		(HIDEEP_SYSCON_BASE + 0x0010)
61 #define HIDEEP_SYSCON_WDT_CON		(HIDEEP_SYSCON_BASE + 0x0014)
62 #define HIDEEP_SYSCON_WDT_CNT		(HIDEEP_SYSCON_BASE + 0x0018)
63 #define HIDEEP_SYSCON_PWR_CON		(HIDEEP_SYSCON_BASE + 0x0020)
64 #define HIDEEP_SYSCON_PGM_ID		(HIDEEP_SYSCON_BASE + 0x00F4)
65 
66 #define HIDEEP_FLASH_CON		(HIDEEP_FLASH_BASE + 0x0000)
67 #define HIDEEP_FLASH_STA		(HIDEEP_FLASH_BASE + 0x0004)
68 #define HIDEEP_FLASH_CFG		(HIDEEP_FLASH_BASE + 0x0008)
69 #define HIDEEP_FLASH_TIM		(HIDEEP_FLASH_BASE + 0x000C)
70 #define HIDEEP_FLASH_CACHE_CFG		(HIDEEP_FLASH_BASE + 0x0010)
71 #define HIDEEP_FLASH_PIO_SIG		(HIDEEP_FLASH_BASE + 0x400000)
72 
73 #define HIDEEP_ESI_TX_INVALID		(HIDEEP_ESI_BASE + 0x0008)
74 
75 #define HIDEEP_PERASE			0x00040000
76 #define HIDEEP_WRONLY			0x00100000
77 
78 #define HIDEEP_NVM_MASK_OFS		0x0000000C
79 #define HIDEEP_NVM_DEFAULT_PAGE		0
80 #define HIDEEP_NVM_SFR_WPAGE		1
81 #define HIDEEP_NVM_SFR_RPAGE		2
82 
83 #define HIDEEP_PIO_SIG			0x00400000
84 #define HIDEEP_PROT_MODE		0x03400000
85 
86 #define HIDEEP_NVM_PAGE_SIZE		128
87 
88 #define HIDEEP_DWZ_INFO			0x000002C0
89 
90 struct hideep_event {
91 	__le16 x;
92 	__le16 y;
93 	__le16 z;
94 	u8 w;
95 	u8 flag;
96 	u8 type;
97 	u8 index;
98 };
99 
100 struct dwz_info {
101 	__be32 code_start;
102 	u8 code_crc[12];
103 
104 	__be32 c_code_start;
105 	__be16 gen_ver;
106 	__be16 c_code_len;
107 
108 	__be32 vr_start;
109 	__be16 rsv0;
110 	__be16 vr_len;
111 
112 	__be32 ft_start;
113 	__be16 vr_version;
114 	__be16 ft_len;
115 
116 	__be16 core_ver;
117 	__be16 boot_ver;
118 
119 	__be16 release_ver;
120 	__be16 custom_ver;
121 
122 	u8 factory_id;
123 	u8 panel_type;
124 	u8 model_name[6];
125 
126 	__be16 extra_option;
127 	__be16 product_code;
128 
129 	__be16 vendor_id;
130 	__be16 product_id;
131 };
132 
133 struct pgm_packet {
134 	struct {
135 		u8 unused[3];
136 		u8 len;
137 		__be32 addr;
138 	} header;
139 	__be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
140 };
141 
142 #define HIDEEP_XFER_BUF_SIZE	sizeof(struct pgm_packet)
143 
144 struct hideep_ts {
145 	struct i2c_client *client;
146 	struct input_dev *input_dev;
147 	struct regmap *reg;
148 
149 	struct touchscreen_properties prop;
150 
151 	struct gpio_desc *reset_gpio;
152 
153 	struct regulator *vcc_vdd;
154 	struct regulator *vcc_vid;
155 
156 	struct mutex dev_mutex;
157 
158 	u32 tch_count;
159 	u32 lpm_count;
160 
161 	/*
162 	 * Data buffer to read packet from the device (contacts and key
163 	 * states). We align it on double-word boundary to keep word-sized
164 	 * fields in contact data and double-word-sized fields in program
165 	 * packet aligned.
166 	 */
167 	u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
168 
169 	int key_num;
170 	u32 key_codes[HIDEEP_KEY_MAX];
171 
172 	struct dwz_info dwz_info;
173 
174 	unsigned int fw_size;
175 	u32 nvm_mask;
176 };
177 
178 static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
179 			    const __be32 *data, size_t count)
180 {
181 	struct pgm_packet *packet = (void *)ts->xfer_buf;
182 	size_t len = count * sizeof(*data);
183 	struct i2c_msg msg = {
184 		.addr	= ts->client->addr,
185 		.len	= len + sizeof(packet->header.len) +
186 				sizeof(packet->header.addr),
187 		.buf	= &packet->header.len,
188 	};
189 	int ret;
190 
191 	if (len > HIDEEP_NVM_PAGE_SIZE)
192 		return -EINVAL;
193 
194 	packet->header.len = 0x80 | (count - 1);
195 	packet->header.addr = cpu_to_be32(addr);
196 	memcpy(packet->payload, data, len);
197 
198 	ret = i2c_transfer(ts->client->adapter, &msg, 1);
199 	if (ret != 1)
200 		return ret < 0 ? ret : -EIO;
201 
202 	return 0;
203 }
204 
205 static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
206 			    __be32 *data, size_t count)
207 {
208 	struct pgm_packet *packet = (void *)ts->xfer_buf;
209 	size_t len = count * sizeof(*data);
210 	struct i2c_msg msg[] = {
211 		{
212 			.addr	= ts->client->addr,
213 			.len	= sizeof(packet->header.len) +
214 					sizeof(packet->header.addr),
215 			.buf	= &packet->header.len,
216 		},
217 		{
218 			.addr	= ts->client->addr,
219 			.flags	= I2C_M_RD,
220 			.len	= len,
221 			.buf	= (u8 *)data,
222 		},
223 	};
224 	int ret;
225 
226 	if (len > HIDEEP_NVM_PAGE_SIZE)
227 		return -EINVAL;
228 
229 	packet->header.len = count - 1;
230 	packet->header.addr = cpu_to_be32(addr);
231 
232 	ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
233 	if (ret != ARRAY_SIZE(msg))
234 		return ret < 0 ? ret : -EIO;
235 
236 	return 0;
237 }
238 
239 static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
240 {
241 	__be32 data;
242 	int error;
243 
244 	error = hideep_pgm_r_mem(ts, addr, &data, 1);
245 	if (error) {
246 		dev_err(&ts->client->dev,
247 			"read of register %#08x failed: %d\n",
248 			addr, error);
249 		return error;
250 	}
251 
252 	*val = be32_to_cpu(data);
253 	return 0;
254 }
255 
256 static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
257 {
258 	__be32 data = cpu_to_be32(val);
259 	int error;
260 
261 	error = hideep_pgm_w_mem(ts, addr, &data, 1);
262 	if (error) {
263 		dev_err(&ts->client->dev,
264 			"write to register %#08x (%#08x) failed: %d\n",
265 			addr, val, error);
266 		return error;
267 	}
268 
269 	return 0;
270 }
271 
272 #define SW_RESET_IN_PGM(clk)					\
273 {								\
274 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk));	\
275 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03);	\
276 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01);	\
277 }
278 
279 #define SET_FLASH_PIO(ce)					\
280 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON,			\
281 			 0x01 | ((ce) << 1))
282 
283 #define SET_PIO_SIG(x, y)					\
284 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
285 
286 #define SET_FLASH_HWCONTROL()					\
287 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
288 
289 #define NVM_W_SFR(x, y)						\
290 {								\
291 	SET_FLASH_PIO(1);					\
292 	SET_PIO_SIG(x, y);					\
293 	SET_FLASH_PIO(0);					\
294 }
295 
296 static void hideep_pgm_set(struct hideep_ts *ts)
297 {
298 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
299 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
300 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
301 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
302 	hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
303 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
304 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
305 }
306 
307 static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
308 {
309 	u16 p1 = 0xAF39;
310 	u16 p2 = 0xDF9D;
311 	int error;
312 
313 	error = regmap_bulk_write(ts->reg, p1, &p2, 1);
314 	if (error) {
315 		dev_err(&ts->client->dev,
316 			"%s: regmap_bulk_write() failed with %d\n",
317 			__func__, error);
318 		return error;
319 	}
320 
321 	usleep_range(1000, 1100);
322 
323 	/* flush invalid Tx load register */
324 	error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
325 	if (error)
326 		return error;
327 
328 	error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
329 	if (error)
330 		return error;
331 
332 	return 0;
333 }
334 
335 static int hideep_enter_pgm(struct hideep_ts *ts)
336 {
337 	int retry_count = 10;
338 	u32 pattern;
339 	int error;
340 
341 	while (retry_count--) {
342 		error = hideep_pgm_get_pattern(ts, &pattern);
343 		if (error) {
344 			dev_err(&ts->client->dev,
345 				"hideep_pgm_get_pattern failed: %d\n", error);
346 		} else if (pattern != 0x39AF9DDF) {
347 			dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
348 				__func__, pattern);
349 		} else {
350 			dev_dbg(&ts->client->dev, "found magic code");
351 
352 			hideep_pgm_set(ts);
353 			usleep_range(1000, 1100);
354 
355 			return 0;
356 		}
357 	}
358 
359 	dev_err(&ts->client->dev, "failed to  enter pgm mode\n");
360 	SW_RESET_IN_PGM(1000);
361 	return -EIO;
362 }
363 
364 static int hideep_nvm_unlock(struct hideep_ts *ts)
365 {
366 	u32 unmask_code;
367 	int error;
368 
369 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
370 	error = hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
371 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
372 	if (error)
373 		return error;
374 
375 	/* make it unprotected code */
376 	unmask_code &= ~HIDEEP_PROT_MODE;
377 
378 	/* compare unmask code */
379 	if (unmask_code != ts->nvm_mask)
380 		dev_warn(&ts->client->dev,
381 			 "read mask code different %#08x vs %#08x",
382 			 unmask_code, ts->nvm_mask);
383 
384 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
385 	SET_FLASH_PIO(0);
386 
387 	NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
388 	SET_FLASH_HWCONTROL();
389 	hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
390 
391 	return 0;
392 }
393 
394 static int hideep_check_status(struct hideep_ts *ts)
395 {
396 	int time_out = 100;
397 	int status;
398 	int error;
399 
400 	while (time_out--) {
401 		error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
402 		if (!error && status)
403 			return 0;
404 
405 		usleep_range(1000, 1100);
406 	}
407 
408 	return -ETIMEDOUT;
409 }
410 
411 static int hideep_program_page(struct hideep_ts *ts, u32 addr,
412 			       const __be32 *ucode, size_t xfer_count)
413 {
414 	u32 val;
415 	int error;
416 
417 	error = hideep_check_status(ts);
418 	if (error)
419 		return -EBUSY;
420 
421 	addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
422 
423 	SET_FLASH_PIO(0);
424 	SET_FLASH_PIO(1);
425 
426 	/* erase page */
427 	SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
428 
429 	SET_FLASH_PIO(0);
430 
431 	error = hideep_check_status(ts);
432 	if (error)
433 		return -EBUSY;
434 
435 	/* write page */
436 	SET_FLASH_PIO(1);
437 
438 	val = be32_to_cpu(ucode[0]);
439 	SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
440 
441 	hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
442 			 ucode, xfer_count);
443 
444 	val = be32_to_cpu(ucode[xfer_count - 1]);
445 	SET_PIO_SIG(124, val);
446 
447 	SET_FLASH_PIO(0);
448 
449 	usleep_range(1000, 1100);
450 
451 	error = hideep_check_status(ts);
452 	if (error)
453 		return -EBUSY;
454 
455 	SET_FLASH_HWCONTROL();
456 
457 	return 0;
458 }
459 
460 static int hideep_program_nvm(struct hideep_ts *ts,
461 			      const __be32 *ucode, size_t ucode_len)
462 {
463 	struct pgm_packet *packet_r = (void *)ts->xfer_buf;
464 	__be32 *current_ucode = packet_r->payload;
465 	size_t xfer_len;
466 	size_t xfer_count;
467 	u32 addr = 0;
468 	int error;
469 
470        error = hideep_nvm_unlock(ts);
471        if (error)
472                return error;
473 
474 	while (ucode_len > 0) {
475 		xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
476 		xfer_count = xfer_len / sizeof(*ucode);
477 
478 		error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
479 					 current_ucode, xfer_count);
480 		if (error) {
481 			dev_err(&ts->client->dev,
482 				"%s: failed to read page at offset %#08x: %d\n",
483 				__func__, addr, error);
484 			return error;
485 		}
486 
487 		/* See if the page needs updating */
488 		if (memcmp(ucode, current_ucode, xfer_len)) {
489 			error = hideep_program_page(ts, addr,
490 						    ucode, xfer_count);
491 			if (error) {
492 				dev_err(&ts->client->dev,
493 					"%s: iwrite failure @%#08x: %d\n",
494 					__func__, addr, error);
495 				return error;
496 			}
497 
498 			usleep_range(1000, 1100);
499 		}
500 
501 		ucode += xfer_count;
502 		addr += xfer_len;
503 		ucode_len -= xfer_len;
504 	}
505 
506 	return 0;
507 }
508 
509 static int hideep_verify_nvm(struct hideep_ts *ts,
510 			     const __be32 *ucode, size_t ucode_len)
511 {
512 	struct pgm_packet *packet_r = (void *)ts->xfer_buf;
513 	__be32 *current_ucode = packet_r->payload;
514 	size_t xfer_len;
515 	size_t xfer_count;
516 	u32 addr = 0;
517 	int i;
518 	int error;
519 
520 	while (ucode_len > 0) {
521 		xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
522 		xfer_count = xfer_len / sizeof(*ucode);
523 
524 		error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
525 					 current_ucode, xfer_count);
526 		if (error) {
527 			dev_err(&ts->client->dev,
528 				"%s: failed to read page at offset %#08x: %d\n",
529 				__func__, addr, error);
530 			return error;
531 		}
532 
533 		if (memcmp(ucode, current_ucode, xfer_len)) {
534 			const u8 *ucode_bytes = (const u8 *)ucode;
535 			const u8 *current_bytes = (const u8 *)current_ucode;
536 
537 			for (i = 0; i < xfer_len; i++)
538 				if (ucode_bytes[i] != current_bytes[i])
539 					dev_err(&ts->client->dev,
540 						"%s: mismatch @%#08x: (%#02x vs %#02x)\n",
541 						__func__, addr + i,
542 						ucode_bytes[i],
543 						current_bytes[i]);
544 
545 			return -EIO;
546 		}
547 
548 		ucode += xfer_count;
549 		addr += xfer_len;
550 		ucode_len -= xfer_len;
551 	}
552 
553 	return 0;
554 }
555 
556 static int hideep_load_dwz(struct hideep_ts *ts)
557 {
558 	u16 product_code;
559 	int error;
560 
561 	error = hideep_enter_pgm(ts);
562 	if (error)
563 		return error;
564 
565 	msleep(50);
566 
567 	error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
568 				 (void *)&ts->dwz_info,
569 				 sizeof(ts->dwz_info) / sizeof(__be32));
570 
571 	SW_RESET_IN_PGM(10);
572 	msleep(50);
573 
574 	if (error) {
575 		dev_err(&ts->client->dev,
576 			"failed to fetch DWZ data: %d\n", error);
577 		return error;
578 	}
579 
580 	product_code = be16_to_cpu(ts->dwz_info.product_code);
581 
582 	switch (product_code & 0xF0) {
583 	case 0x40:
584 		dev_dbg(&ts->client->dev, "used crimson IC");
585 		ts->fw_size = 1024 * 48;
586 		ts->nvm_mask = 0x00310000;
587 		break;
588 	case 0x60:
589 		dev_dbg(&ts->client->dev, "used lime IC");
590 		ts->fw_size = 1024 * 64;
591 		ts->nvm_mask = 0x0030027B;
592 		break;
593 	default:
594 		dev_err(&ts->client->dev, "product code is wrong: %#04x",
595 			product_code);
596 		return -EINVAL;
597 	}
598 
599 	dev_dbg(&ts->client->dev, "firmware release version: %#04x",
600 		be16_to_cpu(ts->dwz_info.release_ver));
601 
602 	return 0;
603 }
604 
605 static int hideep_flash_firmware(struct hideep_ts *ts,
606 				 const __be32 *ucode, size_t ucode_len)
607 {
608 	int retry_cnt = 3;
609 	int error;
610 
611 	while (retry_cnt--) {
612 		error = hideep_program_nvm(ts, ucode, ucode_len);
613 		if (!error) {
614 			error = hideep_verify_nvm(ts, ucode, ucode_len);
615 			if (!error)
616 				return 0;
617 		}
618 	}
619 
620 	return error;
621 }
622 
623 static int hideep_update_firmware(struct hideep_ts *ts,
624 				  const __be32 *ucode, size_t ucode_len)
625 {
626 	int error, error2;
627 
628 	dev_dbg(&ts->client->dev, "starting firmware update");
629 
630 	/* enter program mode */
631 	error = hideep_enter_pgm(ts);
632 	if (error)
633 		return error;
634 
635 	error = hideep_flash_firmware(ts, ucode, ucode_len);
636 	if (error)
637 		dev_err(&ts->client->dev,
638 			"firmware update failed: %d\n", error);
639 	else
640 		dev_dbg(&ts->client->dev, "firmware updated successfully\n");
641 
642 	SW_RESET_IN_PGM(1000);
643 
644 	error2 = hideep_load_dwz(ts);
645 	if (error2)
646 		dev_err(&ts->client->dev,
647 			"failed to load dwz after firmware update: %d\n",
648 			error2);
649 
650 	return error ?: error2;
651 }
652 
653 static int hideep_power_on(struct hideep_ts *ts)
654 {
655 	int error = 0;
656 
657 	error = regulator_enable(ts->vcc_vdd);
658 	if (error)
659 		dev_err(&ts->client->dev,
660 			"failed to enable 'vdd' regulator: %d", error);
661 
662 	usleep_range(999, 1000);
663 
664 	error = regulator_enable(ts->vcc_vid);
665 	if (error)
666 		dev_err(&ts->client->dev,
667 			"failed to enable 'vcc_vid' regulator: %d",
668 			error);
669 
670 	msleep(30);
671 
672 	if (ts->reset_gpio) {
673 		gpiod_set_value_cansleep(ts->reset_gpio, 0);
674 	} else {
675 		error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
676 		if (error)
677 			dev_err(&ts->client->dev,
678 				"failed to send 'reset' command: %d\n", error);
679 	}
680 
681 	msleep(50);
682 
683 	return error;
684 }
685 
686 static void hideep_power_off(void *data)
687 {
688 	struct hideep_ts *ts = data;
689 
690 	if (ts->reset_gpio)
691 		gpiod_set_value(ts->reset_gpio, 1);
692 
693 	regulator_disable(ts->vcc_vid);
694 	regulator_disable(ts->vcc_vdd);
695 }
696 
697 #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
698 
699 static void hideep_report_slot(struct input_dev *input,
700 			       const struct hideep_event *event)
701 {
702 	input_mt_slot(input, event->index & 0x0f);
703 	input_mt_report_slot_state(input,
704 				   __GET_MT_TOOL_TYPE(event->type),
705 				   !(event->flag & HIDEEP_MT_RELEASED));
706 	if (!(event->flag & HIDEEP_MT_RELEASED)) {
707 		input_report_abs(input, ABS_MT_POSITION_X,
708 				 le16_to_cpup(&event->x));
709 		input_report_abs(input, ABS_MT_POSITION_Y,
710 				 le16_to_cpup(&event->y));
711 		input_report_abs(input, ABS_MT_PRESSURE,
712 				 le16_to_cpup(&event->z));
713 		input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
714 	}
715 }
716 
717 static void hideep_parse_and_report(struct hideep_ts *ts)
718 {
719 	const struct hideep_event *events =
720 			(void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
721 	const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
722 	int touch_count = ts->xfer_buf[0];
723 	int key_count = ts->xfer_buf[1] & 0x0f;
724 	int lpm_count = ts->xfer_buf[1] & 0xf0;
725 	int i;
726 
727 	/* get touch event count */
728 	dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
729 		touch_count, key_count, lpm_count);
730 
731 	touch_count = min(touch_count, HIDEEP_MT_MAX);
732 	for (i = 0; i < touch_count; i++)
733 		hideep_report_slot(ts->input_dev, events + i);
734 
735 	key_count = min(key_count, HIDEEP_KEY_MAX);
736 	for (i = 0; i < key_count; i++) {
737 		u8 key_data = keys[i * 2];
738 
739 		input_report_key(ts->input_dev,
740 				 ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
741 				 key_data & HIDEEP_KEY_PRESSED_MASK);
742 	}
743 
744 	input_mt_sync_frame(ts->input_dev);
745 	input_sync(ts->input_dev);
746 }
747 
748 static irqreturn_t hideep_irq(int irq, void *handle)
749 {
750 	struct hideep_ts *ts = handle;
751 	int error;
752 
753 	BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
754 
755 	error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
756 				 ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
757 	if (error) {
758 		dev_err(&ts->client->dev, "failed to read events: %d\n", error);
759 		goto out;
760 	}
761 
762 	hideep_parse_and_report(ts);
763 
764 out:
765 	return IRQ_HANDLED;
766 }
767 
768 static int hideep_get_axis_info(struct hideep_ts *ts)
769 {
770 	__le16 val[2];
771 	int error;
772 
773 	error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
774 	if (error)
775 		return error;
776 
777 	ts->prop.max_x = le16_to_cpup(val);
778 	ts->prop.max_y = le16_to_cpup(val + 1);
779 
780 	dev_dbg(&ts->client->dev, "X: %d, Y: %d",
781 		ts->prop.max_x, ts->prop.max_y);
782 
783 	return 0;
784 }
785 
786 static int hideep_init_input(struct hideep_ts *ts)
787 {
788 	struct device *dev = &ts->client->dev;
789 	int i;
790 	int error;
791 
792 	ts->input_dev = devm_input_allocate_device(dev);
793 	if (!ts->input_dev) {
794 		dev_err(dev, "failed to allocate input device\n");
795 		return -ENOMEM;
796 	}
797 
798 	ts->input_dev->name = HIDEEP_TS_NAME;
799 	ts->input_dev->id.bustype = BUS_I2C;
800 	input_set_drvdata(ts->input_dev, ts);
801 
802 	input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
803 	input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
804 	input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
805 	input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
806 	input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
807 			     0, MT_TOOL_MAX, 0, 0);
808 	touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
809 
810 	if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
811 		error = hideep_get_axis_info(ts);
812 		if (error)
813 			return error;
814 	}
815 
816 	error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
817 				    INPUT_MT_DIRECT);
818 	if (error)
819 		return error;
820 
821 	ts->key_num = device_property_count_u32(dev, "linux,keycodes");
822 	if (ts->key_num > HIDEEP_KEY_MAX) {
823 		dev_err(dev, "too many keys defined: %d\n",
824 			ts->key_num);
825 		return -EINVAL;
826 	}
827 
828 	if (ts->key_num <= 0) {
829 		dev_dbg(dev,
830 			"missing or malformed 'linux,keycodes' property\n");
831 	} else {
832 		error = device_property_read_u32_array(dev, "linux,keycodes",
833 						       ts->key_codes,
834 						       ts->key_num);
835 		if (error) {
836 			dev_dbg(dev, "failed to read keymap: %d", error);
837 			return error;
838 		}
839 
840 		if (ts->key_num) {
841 			ts->input_dev->keycode = ts->key_codes;
842 			ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
843 			ts->input_dev->keycodemax = ts->key_num;
844 
845 			for (i = 0; i < ts->key_num; i++)
846 				input_set_capability(ts->input_dev, EV_KEY,
847 					ts->key_codes[i]);
848 		}
849 	}
850 
851 	error = input_register_device(ts->input_dev);
852 	if (error) {
853 		dev_err(dev, "failed to register input device: %d", error);
854 		return error;
855 	}
856 
857 	return 0;
858 }
859 
860 static ssize_t hideep_update_fw(struct device *dev,
861 				struct device_attribute *attr,
862 				const char *buf, size_t count)
863 {
864 	struct i2c_client *client = to_i2c_client(dev);
865 	struct hideep_ts *ts = i2c_get_clientdata(client);
866 	const struct firmware *fw_entry;
867 	char *fw_name;
868 	int mode;
869 	int error;
870 
871 	error = kstrtoint(buf, 0, &mode);
872 	if (error)
873 		return error;
874 
875 	fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin",
876 			    be16_to_cpu(ts->dwz_info.product_id));
877 	if (!fw_name)
878 		return -ENOMEM;
879 
880 	error = request_firmware(&fw_entry, fw_name, dev);
881 	if (error) {
882 		dev_err(dev, "failed to request firmware %s: %d",
883 			fw_name, error);
884 		goto out_free_fw_name;
885 	}
886 
887 	if (fw_entry->size % sizeof(__be32)) {
888 		dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
889 		error = -EINVAL;
890 		goto out_release_fw;
891 	}
892 
893 	if (fw_entry->size > ts->fw_size) {
894 		dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
895 			fw_entry->size, ts->fw_size);
896 		error = -EFBIG;
897 		goto out_release_fw;
898 	}
899 
900 	mutex_lock(&ts->dev_mutex);
901 	disable_irq(client->irq);
902 
903 	error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
904 				       fw_entry->size);
905 
906 	enable_irq(client->irq);
907 	mutex_unlock(&ts->dev_mutex);
908 
909 out_release_fw:
910 	release_firmware(fw_entry);
911 out_free_fw_name:
912 	kfree(fw_name);
913 
914 	return error ?: count;
915 }
916 
917 static ssize_t hideep_fw_version_show(struct device *dev,
918 				      struct device_attribute *attr, char *buf)
919 {
920 	struct i2c_client *client = to_i2c_client(dev);
921 	struct hideep_ts *ts = i2c_get_clientdata(client);
922 	ssize_t len;
923 
924 	mutex_lock(&ts->dev_mutex);
925 	len = scnprintf(buf, PAGE_SIZE, "%04x\n",
926 			be16_to_cpu(ts->dwz_info.release_ver));
927 	mutex_unlock(&ts->dev_mutex);
928 
929 	return len;
930 }
931 
932 static ssize_t hideep_product_id_show(struct device *dev,
933 				      struct device_attribute *attr, char *buf)
934 {
935 	struct i2c_client *client = to_i2c_client(dev);
936 	struct hideep_ts *ts = i2c_get_clientdata(client);
937 	ssize_t len;
938 
939 	mutex_lock(&ts->dev_mutex);
940 	len = scnprintf(buf, PAGE_SIZE, "%04x\n",
941 			be16_to_cpu(ts->dwz_info.product_id));
942 	mutex_unlock(&ts->dev_mutex);
943 
944 	return len;
945 }
946 
947 static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
948 static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
949 static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
950 
951 static struct attribute *hideep_ts_sysfs_entries[] = {
952 	&dev_attr_version.attr,
953 	&dev_attr_product_id.attr,
954 	&dev_attr_update_fw.attr,
955 	NULL,
956 };
957 
958 static const struct attribute_group hideep_ts_attr_group = {
959 	.attrs = hideep_ts_sysfs_entries,
960 };
961 
962 static int __maybe_unused hideep_suspend(struct device *dev)
963 {
964 	struct i2c_client *client = to_i2c_client(dev);
965 	struct hideep_ts *ts = i2c_get_clientdata(client);
966 
967 	disable_irq(client->irq);
968 	hideep_power_off(ts);
969 
970 	return 0;
971 }
972 
973 static int __maybe_unused hideep_resume(struct device *dev)
974 {
975 	struct i2c_client *client = to_i2c_client(dev);
976 	struct hideep_ts *ts = i2c_get_clientdata(client);
977 	int error;
978 
979 	error = hideep_power_on(ts);
980 	if (error) {
981 		dev_err(&client->dev, "power on failed");
982 		return error;
983 	}
984 
985 	enable_irq(client->irq);
986 
987 	return 0;
988 }
989 
990 static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
991 
992 static const struct regmap_config hideep_regmap_config = {
993 	.reg_bits = 16,
994 	.reg_format_endian = REGMAP_ENDIAN_LITTLE,
995 	.val_bits = 16,
996 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
997 	.max_register = 0xffff,
998 };
999 
1000 static int hideep_probe(struct i2c_client *client)
1001 {
1002 	struct hideep_ts *ts;
1003 	int error;
1004 
1005 	/* check i2c bus */
1006 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1007 		dev_err(&client->dev, "check i2c device error");
1008 		return -ENODEV;
1009 	}
1010 
1011 	if (client->irq <= 0) {
1012 		dev_err(&client->dev, "missing irq: %d\n", client->irq);
1013 		return -EINVAL;
1014 	}
1015 
1016 	ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
1017 	if (!ts)
1018 		return -ENOMEM;
1019 
1020 	ts->client = client;
1021 	i2c_set_clientdata(client, ts);
1022 	mutex_init(&ts->dev_mutex);
1023 
1024 	ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
1025 	if (IS_ERR(ts->reg)) {
1026 		error = PTR_ERR(ts->reg);
1027 		dev_err(&client->dev,
1028 			"failed to initialize regmap: %d\n", error);
1029 		return error;
1030 	}
1031 
1032 	ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
1033 	if (IS_ERR(ts->vcc_vdd))
1034 		return PTR_ERR(ts->vcc_vdd);
1035 
1036 	ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
1037 	if (IS_ERR(ts->vcc_vid))
1038 		return PTR_ERR(ts->vcc_vid);
1039 
1040 	ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
1041 						 "reset", GPIOD_OUT_HIGH);
1042 	if (IS_ERR(ts->reset_gpio))
1043 		return PTR_ERR(ts->reset_gpio);
1044 
1045 	error = hideep_power_on(ts);
1046 	if (error) {
1047 		dev_err(&client->dev, "power on failed: %d\n", error);
1048 		return error;
1049 	}
1050 
1051 	error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
1052 	if (error)
1053 		return error;
1054 
1055 	error = hideep_load_dwz(ts);
1056 	if (error) {
1057 		dev_err(&client->dev, "failed to load dwz: %d", error);
1058 		return error;
1059 	}
1060 
1061 	error = hideep_init_input(ts);
1062 	if (error)
1063 		return error;
1064 
1065 	error = devm_request_threaded_irq(&client->dev, client->irq,
1066 					  NULL, hideep_irq, IRQF_ONESHOT,
1067 					  client->name, ts);
1068 	if (error) {
1069 		dev_err(&client->dev, "failed to request irq %d: %d\n",
1070 			client->irq, error);
1071 		return error;
1072 	}
1073 
1074 	error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
1075 	if (error) {
1076 		dev_err(&client->dev,
1077 			"failed to add sysfs attributes: %d\n", error);
1078 		return error;
1079 	}
1080 
1081 	return 0;
1082 }
1083 
1084 static const struct i2c_device_id hideep_i2c_id[] = {
1085 	{ HIDEEP_I2C_NAME, 0 },
1086 	{ }
1087 };
1088 MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
1089 
1090 #ifdef CONFIG_ACPI
1091 static const struct acpi_device_id hideep_acpi_id[] = {
1092 	{ "HIDP0001", 0 },
1093 	{ }
1094 };
1095 MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
1096 #endif
1097 
1098 #ifdef CONFIG_OF
1099 static const struct of_device_id hideep_match_table[] = {
1100 	{ .compatible = "hideep,hideep-ts" },
1101 	{ }
1102 };
1103 MODULE_DEVICE_TABLE(of, hideep_match_table);
1104 #endif
1105 
1106 static struct i2c_driver hideep_driver = {
1107 	.driver = {
1108 		.name			= HIDEEP_I2C_NAME,
1109 		.of_match_table		= of_match_ptr(hideep_match_table),
1110 		.acpi_match_table	= ACPI_PTR(hideep_acpi_id),
1111 		.pm			= &hideep_pm_ops,
1112 	},
1113 	.id_table	= hideep_i2c_id,
1114 	.probe_new	= hideep_probe,
1115 };
1116 
1117 module_i2c_driver(hideep_driver);
1118 
1119 MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
1120 MODULE_AUTHOR("anthony.kim@hideep.com");
1121 MODULE_LICENSE("GPL v2");
1122