xref: /openbmc/linux/drivers/input/serio/sun4i-ps2.c (revision 423997ff) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *	Driver for Allwinner A10 PS2 host controller
4  *
5  *	Author: Vishnu Patekar <vishnupatekar0510@gmail.com>
6  *		Aaron.maoye <leafy.myeh@newbietech.com>
7  */
8 
9 #include <linux/module.h>
10 #include <linux/serio.h>
11 #include <linux/interrupt.h>
12 #include <linux/errno.h>
13 #include <linux/slab.h>
14 #include <linux/io.h>
15 #include <linux/clk.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/platform_device.h>
18 
19 #define DRIVER_NAME		"sun4i-ps2"
20 
21 /* register offset definitions */
22 #define PS2_REG_GCTL		0x00	/* PS2 Module Global Control Reg */
23 #define PS2_REG_DATA		0x04	/* PS2 Module Data Reg		*/
24 #define PS2_REG_LCTL		0x08	/* PS2 Module Line Control Reg */
25 #define PS2_REG_LSTS		0x0C	/* PS2 Module Line Status Reg	*/
26 #define PS2_REG_FCTL		0x10	/* PS2 Module FIFO Control Reg */
27 #define PS2_REG_FSTS		0x14	/* PS2 Module FIFO Status Reg	*/
28 #define PS2_REG_CLKDR		0x18	/* PS2 Module Clock Divider Reg*/
29 
30 /*  PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
31 #define PS2_GCTL_INTFLAG	BIT(4)
32 #define PS2_GCTL_INTEN		BIT(3)
33 #define PS2_GCTL_RESET		BIT(2)
34 #define PS2_GCTL_MASTER		BIT(1)
35 #define PS2_GCTL_BUSEN		BIT(0)
36 
37 /* PS2 LINE CONTROL REGISTER */
38 #define PS2_LCTL_NOACK		BIT(18)
39 #define PS2_LCTL_TXDTOEN	BIT(8)
40 #define PS2_LCTL_STOPERREN	BIT(3)
41 #define PS2_LCTL_ACKERREN	BIT(2)
42 #define PS2_LCTL_PARERREN	BIT(1)
43 #define PS2_LCTL_RXDTOEN	BIT(0)
44 
45 /* PS2 LINE STATUS REGISTER */
46 #define PS2_LSTS_TXTDO		BIT(8)
47 #define PS2_LSTS_STOPERR	BIT(3)
48 #define PS2_LSTS_ACKERR		BIT(2)
49 #define PS2_LSTS_PARERR		BIT(1)
50 #define PS2_LSTS_RXTDO		BIT(0)
51 
52 #define PS2_LINE_ERROR_BIT \
53 	(PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
54 	PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
55 
56 /* PS2 FIFO CONTROL REGISTER */
57 #define PS2_FCTL_TXRST		BIT(17)
58 #define PS2_FCTL_RXRST		BIT(16)
59 #define PS2_FCTL_TXUFIEN	BIT(10)
60 #define PS2_FCTL_TXOFIEN	BIT(9)
61 #define PS2_FCTL_TXRDYIEN	BIT(8)
62 #define PS2_FCTL_RXUFIEN	BIT(2)
63 #define PS2_FCTL_RXOFIEN	BIT(1)
64 #define PS2_FCTL_RXRDYIEN	BIT(0)
65 
66 /* PS2 FIFO STATUS REGISTER */
67 #define PS2_FSTS_TXUF		BIT(10)
68 #define PS2_FSTS_TXOF		BIT(9)
69 #define PS2_FSTS_TXRDY		BIT(8)
70 #define PS2_FSTS_RXUF		BIT(2)
71 #define PS2_FSTS_RXOF		BIT(1)
72 #define PS2_FSTS_RXRDY		BIT(0)
73 
74 #define PS2_FIFO_ERROR_BIT \
75 	(PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
76 
77 #define PS2_SAMPLE_CLK		1000000
78 #define PS2_SCLK		125000
79 
80 struct sun4i_ps2data {
81 	struct serio *serio;
82 	struct device *dev;
83 
84 	/* IO mapping base */
85 	void __iomem	*reg_base;
86 
87 	/* clock management */
88 	struct clk	*clk;
89 
90 	/* irq */
91 	spinlock_t	lock;
92 	int		irq;
93 };
94 
95 static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id)
96 {
97 	struct sun4i_ps2data *drvdata = dev_id;
98 	u32 intr_status;
99 	u32 fifo_status;
100 	unsigned char byte;
101 	unsigned int rxflags = 0;
102 	u32 rval;
103 
104 	spin_lock(&drvdata->lock);
105 
106 	/* Get the PS/2 interrupts and clear them */
107 	intr_status  = readl(drvdata->reg_base + PS2_REG_LSTS);
108 	fifo_status  = readl(drvdata->reg_base + PS2_REG_FSTS);
109 
110 	/* Check line status register */
111 	if (intr_status & PS2_LINE_ERROR_BIT) {
112 		rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0;
113 		rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0;
114 		rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0;
115 
116 		rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR |
117 			PS2_LSTS_PARERR | PS2_LSTS_RXTDO;
118 		writel(rval, drvdata->reg_base + PS2_REG_LSTS);
119 	}
120 
121 	/* Check FIFO status register */
122 	if (fifo_status & PS2_FIFO_ERROR_BIT) {
123 		rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY |
124 			PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY;
125 		writel(rval, drvdata->reg_base + PS2_REG_FSTS);
126 	}
127 
128 	rval = (fifo_status >> 16) & 0x3;
129 	while (rval--) {
130 		byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
131 		serio_interrupt(drvdata->serio, byte, rxflags);
132 	}
133 
134 	writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
135 	writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
136 
137 	spin_unlock(&drvdata->lock);
138 
139 	return IRQ_HANDLED;
140 }
141 
142 static int sun4i_ps2_open(struct serio *serio)
143 {
144 	struct sun4i_ps2data *drvdata = serio->port_data;
145 	u32 src_clk = 0;
146 	u32 clk_scdf;
147 	u32 clk_pcdf;
148 	u32 rval;
149 	unsigned long flags;
150 
151 	/* Set line control and enable interrupt */
152 	rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN
153 		| PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN;
154 	writel(rval, drvdata->reg_base + PS2_REG_LCTL);
155 
156 	/* Reset FIFO */
157 	rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN
158 		| PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN
159 		| PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN;
160 
161 	writel(rval, drvdata->reg_base + PS2_REG_FCTL);
162 
163 	src_clk = clk_get_rate(drvdata->clk);
164 	/* Set clock divider register */
165 	clk_scdf = src_clk / PS2_SAMPLE_CLK - 1;
166 	clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1;
167 	rval = (clk_scdf << 8) | clk_pcdf;
168 	writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
169 
170 	/* Set global control register */
171 	rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER
172 		| PS2_GCTL_BUSEN;
173 
174 	spin_lock_irqsave(&drvdata->lock, flags);
175 	writel(rval, drvdata->reg_base + PS2_REG_GCTL);
176 	spin_unlock_irqrestore(&drvdata->lock, flags);
177 
178 	return 0;
179 }
180 
181 static void sun4i_ps2_close(struct serio *serio)
182 {
183 	struct sun4i_ps2data *drvdata = serio->port_data;
184 	u32 rval;
185 
186 	/* Shut off the interrupt */
187 	rval = readl(drvdata->reg_base + PS2_REG_GCTL);
188 	writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
189 
190 	synchronize_irq(drvdata->irq);
191 }
192 
193 static int sun4i_ps2_write(struct serio *serio, unsigned char val)
194 {
195 	unsigned long expire = jiffies + msecs_to_jiffies(10000);
196 	struct sun4i_ps2data *drvdata = serio->port_data;
197 
198 	do {
199 		if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) {
200 			writel(val, drvdata->reg_base + PS2_REG_DATA);
201 			return 0;
202 		}
203 	} while (time_before(jiffies, expire));
204 
205 	return SERIO_TIMEOUT;
206 }
207 
208 static int sun4i_ps2_probe(struct platform_device *pdev)
209 {
210 	struct resource *res; /* IO mem resources */
211 	struct sun4i_ps2data *drvdata;
212 	struct serio *serio;
213 	struct device *dev = &pdev->dev;
214 	unsigned int irq;
215 	int error;
216 
217 	drvdata = kzalloc(sizeof(struct sun4i_ps2data), GFP_KERNEL);
218 	serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
219 	if (!drvdata || !serio) {
220 		error = -ENOMEM;
221 		goto err_free_mem;
222 	}
223 
224 	spin_lock_init(&drvdata->lock);
225 
226 	/* IO */
227 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
228 	if (!res) {
229 		dev_err(dev, "failed to locate registers\n");
230 		error = -ENXIO;
231 		goto err_free_mem;
232 	}
233 
234 	drvdata->reg_base = ioremap(res->start, resource_size(res));
235 	if (!drvdata->reg_base) {
236 		dev_err(dev, "failed to map registers\n");
237 		error = -ENOMEM;
238 		goto err_free_mem;
239 	}
240 
241 	drvdata->clk = clk_get(dev, NULL);
242 	if (IS_ERR(drvdata->clk)) {
243 		error = PTR_ERR(drvdata->clk);
244 		dev_err(dev, "couldn't get clock %d\n", error);
245 		goto err_ioremap;
246 	}
247 
248 	error = clk_prepare_enable(drvdata->clk);
249 	if (error) {
250 		dev_err(dev, "failed to enable clock %d\n", error);
251 		goto err_clk;
252 	}
253 
254 	serio->id.type = SERIO_8042;
255 	serio->write = sun4i_ps2_write;
256 	serio->open = sun4i_ps2_open;
257 	serio->close = sun4i_ps2_close;
258 	serio->port_data = drvdata;
259 	serio->dev.parent = dev;
260 	strlcpy(serio->name, dev_name(dev), sizeof(serio->name));
261 	strlcpy(serio->phys, dev_name(dev), sizeof(serio->phys));
262 
263 	/* shutoff interrupt */
264 	writel(0, drvdata->reg_base + PS2_REG_GCTL);
265 
266 	/* Get IRQ for the device */
267 	irq = platform_get_irq(pdev, 0);
268 	if (!irq) {
269 		dev_err(dev, "no IRQ found\n");
270 		error = -ENXIO;
271 		goto err_disable_clk;
272 	}
273 
274 	drvdata->irq = irq;
275 	drvdata->serio = serio;
276 	drvdata->dev = dev;
277 
278 	error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0,
279 			    DRIVER_NAME, drvdata);
280 	if (error) {
281 		dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n",
282 			drvdata->irq, error);
283 		goto err_disable_clk;
284 	}
285 
286 	serio_register_port(serio);
287 	platform_set_drvdata(pdev, drvdata);
288 
289 	return 0;	/* success */
290 
291 err_disable_clk:
292 	clk_disable_unprepare(drvdata->clk);
293 err_clk:
294 	clk_put(drvdata->clk);
295 err_ioremap:
296 	iounmap(drvdata->reg_base);
297 err_free_mem:
298 	kfree(serio);
299 	kfree(drvdata);
300 	return error;
301 }
302 
303 static int sun4i_ps2_remove(struct platform_device *pdev)
304 {
305 	struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev);
306 
307 	serio_unregister_port(drvdata->serio);
308 
309 	free_irq(drvdata->irq, drvdata);
310 
311 	clk_disable_unprepare(drvdata->clk);
312 	clk_put(drvdata->clk);
313 
314 	iounmap(drvdata->reg_base);
315 
316 	kfree(drvdata);
317 
318 	return 0;
319 }
320 
321 static const struct of_device_id sun4i_ps2_match[] = {
322 	{ .compatible = "allwinner,sun4i-a10-ps2", },
323 	{ },
324 };
325 
326 MODULE_DEVICE_TABLE(of, sun4i_ps2_match);
327 
328 static struct platform_driver sun4i_ps2_driver = {
329 	.probe		= sun4i_ps2_probe,
330 	.remove		= sun4i_ps2_remove,
331 	.driver = {
332 		.name = DRIVER_NAME,
333 		.of_match_table = sun4i_ps2_match,
334 	},
335 };
336 module_platform_driver(sun4i_ps2_driver);
337 
338 MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
339 MODULE_AUTHOR("Aaron.maoye <leafy.myeh@newbietech.com>");
340 MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver");
341 MODULE_LICENSE("GPL v2");
342