1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/init.h> 19 #include <linux/serio.h> 20 #include <linux/err.h> 21 #include <linux/rcupdate.h> 22 #include <linux/platform_device.h> 23 #include <linux/i8042.h> 24 25 #include <asm/io.h> 26 27 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 28 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 29 MODULE_LICENSE("GPL"); 30 31 static bool i8042_nokbd; 32 module_param_named(nokbd, i8042_nokbd, bool, 0); 33 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 34 35 static bool i8042_noaux; 36 module_param_named(noaux, i8042_noaux, bool, 0); 37 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 38 39 static bool i8042_nomux; 40 module_param_named(nomux, i8042_nomux, bool, 0); 41 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); 42 43 static bool i8042_unlock; 44 module_param_named(unlock, i8042_unlock, bool, 0); 45 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 46 47 static bool i8042_reset; 48 module_param_named(reset, i8042_reset, bool, 0); 49 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 50 51 static bool i8042_direct; 52 module_param_named(direct, i8042_direct, bool, 0); 53 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 54 55 static bool i8042_dumbkbd; 56 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 57 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 58 59 static bool i8042_noloop; 60 module_param_named(noloop, i8042_noloop, bool, 0); 61 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 62 63 static unsigned int i8042_blink_frequency = 500; 64 module_param_named(panicblink, i8042_blink_frequency, uint, 0600); 65 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); 66 67 #ifdef CONFIG_X86 68 static bool i8042_dritek; 69 module_param_named(dritek, i8042_dritek, bool, 0); 70 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 71 #endif 72 73 #ifdef CONFIG_PNP 74 static bool i8042_nopnp; 75 module_param_named(nopnp, i8042_nopnp, bool, 0); 76 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 77 #endif 78 79 #define DEBUG 80 #ifdef DEBUG 81 static bool i8042_debug; 82 module_param_named(debug, i8042_debug, bool, 0600); 83 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 84 #endif 85 86 static bool i8042_bypass_aux_irq_test; 87 88 #include "i8042.h" 89 90 /* 91 * i8042_lock protects serialization between i8042_command and 92 * the interrupt handler. 93 */ 94 static DEFINE_SPINLOCK(i8042_lock); 95 96 /* 97 * Writers to AUX and KBD ports as well as users issuing i8042_command 98 * directly should acquire i8042_mutex (by means of calling 99 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 100 * they do not disturb each other (unfortunately in many i8042 101 * implementations write to one of the ports will immediately abort 102 * command that is being processed by another port). 103 */ 104 static DEFINE_MUTEX(i8042_mutex); 105 106 struct i8042_port { 107 struct serio *serio; 108 int irq; 109 bool exists; 110 signed char mux; 111 }; 112 113 #define I8042_KBD_PORT_NO 0 114 #define I8042_AUX_PORT_NO 1 115 #define I8042_MUX_PORT_NO 2 116 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 117 118 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 119 120 static unsigned char i8042_initial_ctr; 121 static unsigned char i8042_ctr; 122 static bool i8042_mux_present; 123 static bool i8042_kbd_irq_registered; 124 static bool i8042_aux_irq_registered; 125 static unsigned char i8042_suppress_kbd_ack; 126 static struct platform_device *i8042_platform_device; 127 128 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 129 130 void i8042_lock_chip(void) 131 { 132 mutex_lock(&i8042_mutex); 133 } 134 EXPORT_SYMBOL(i8042_lock_chip); 135 136 void i8042_unlock_chip(void) 137 { 138 mutex_unlock(&i8042_mutex); 139 } 140 EXPORT_SYMBOL(i8042_unlock_chip); 141 142 /* 143 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 144 * be ready for reading values from it / writing values to it. 145 * Called always with i8042_lock held. 146 */ 147 148 static int i8042_wait_read(void) 149 { 150 int i = 0; 151 152 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 153 udelay(50); 154 i++; 155 } 156 return -(i == I8042_CTL_TIMEOUT); 157 } 158 159 static int i8042_wait_write(void) 160 { 161 int i = 0; 162 163 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 164 udelay(50); 165 i++; 166 } 167 return -(i == I8042_CTL_TIMEOUT); 168 } 169 170 /* 171 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 172 * of the i8042 down the toilet. 173 */ 174 175 static int i8042_flush(void) 176 { 177 unsigned long flags; 178 unsigned char data, str; 179 int i = 0; 180 181 spin_lock_irqsave(&i8042_lock, flags); 182 183 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 184 udelay(50); 185 data = i8042_read_data(); 186 i++; 187 dbg("%02x <- i8042 (flush, %s)", data, 188 str & I8042_STR_AUXDATA ? "aux" : "kbd"); 189 } 190 191 spin_unlock_irqrestore(&i8042_lock, flags); 192 193 return i; 194 } 195 196 /* 197 * i8042_command() executes a command on the i8042. It also sends the input 198 * parameter(s) of the commands to it, and receives the output value(s). The 199 * parameters are to be stored in the param array, and the output is placed 200 * into the same array. The number of the parameters and output values is 201 * encoded in bits 8-11 of the command number. 202 */ 203 204 static int __i8042_command(unsigned char *param, int command) 205 { 206 int i, error; 207 208 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 209 return -1; 210 211 error = i8042_wait_write(); 212 if (error) 213 return error; 214 215 dbg("%02x -> i8042 (command)", command & 0xff); 216 i8042_write_command(command & 0xff); 217 218 for (i = 0; i < ((command >> 12) & 0xf); i++) { 219 error = i8042_wait_write(); 220 if (error) 221 return error; 222 dbg("%02x -> i8042 (parameter)", param[i]); 223 i8042_write_data(param[i]); 224 } 225 226 for (i = 0; i < ((command >> 8) & 0xf); i++) { 227 error = i8042_wait_read(); 228 if (error) { 229 dbg(" -- i8042 (timeout)"); 230 return error; 231 } 232 233 if (command == I8042_CMD_AUX_LOOP && 234 !(i8042_read_status() & I8042_STR_AUXDATA)) { 235 dbg(" -- i8042 (auxerr)"); 236 return -1; 237 } 238 239 param[i] = i8042_read_data(); 240 dbg("%02x <- i8042 (return)", param[i]); 241 } 242 243 return 0; 244 } 245 246 int i8042_command(unsigned char *param, int command) 247 { 248 unsigned long flags; 249 int retval; 250 251 spin_lock_irqsave(&i8042_lock, flags); 252 retval = __i8042_command(param, command); 253 spin_unlock_irqrestore(&i8042_lock, flags); 254 255 return retval; 256 } 257 EXPORT_SYMBOL(i8042_command); 258 259 /* 260 * i8042_kbd_write() sends a byte out through the keyboard interface. 261 */ 262 263 static int i8042_kbd_write(struct serio *port, unsigned char c) 264 { 265 unsigned long flags; 266 int retval = 0; 267 268 spin_lock_irqsave(&i8042_lock, flags); 269 270 if (!(retval = i8042_wait_write())) { 271 dbg("%02x -> i8042 (kbd-data)", c); 272 i8042_write_data(c); 273 } 274 275 spin_unlock_irqrestore(&i8042_lock, flags); 276 277 return retval; 278 } 279 280 /* 281 * i8042_aux_write() sends a byte out through the aux interface. 282 */ 283 284 static int i8042_aux_write(struct serio *serio, unsigned char c) 285 { 286 struct i8042_port *port = serio->port_data; 287 288 return i8042_command(&c, port->mux == -1 ? 289 I8042_CMD_AUX_SEND : 290 I8042_CMD_MUX_SEND + port->mux); 291 } 292 293 294 /* 295 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 296 * and then re-enabling it. 297 */ 298 299 static void i8042_port_close(struct serio *serio) 300 { 301 int irq_bit; 302 int disable_bit; 303 const char *port_name; 304 305 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 306 irq_bit = I8042_CTR_AUXINT; 307 disable_bit = I8042_CTR_AUXDIS; 308 port_name = "AUX"; 309 } else { 310 irq_bit = I8042_CTR_KBDINT; 311 disable_bit = I8042_CTR_KBDDIS; 312 port_name = "KBD"; 313 } 314 315 i8042_ctr &= ~irq_bit; 316 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 317 printk(KERN_WARNING 318 "i8042.c: Can't write CTR while closing %s port.\n", 319 port_name); 320 321 udelay(50); 322 323 i8042_ctr &= ~disable_bit; 324 i8042_ctr |= irq_bit; 325 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 326 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", 327 port_name); 328 329 /* 330 * See if there is any data appeared while we were messing with 331 * port state. 332 */ 333 i8042_interrupt(0, NULL); 334 } 335 336 /* 337 * i8042_start() is called by serio core when port is about to finish 338 * registering. It will mark port as existing so i8042_interrupt can 339 * start sending data through it. 340 */ 341 static int i8042_start(struct serio *serio) 342 { 343 struct i8042_port *port = serio->port_data; 344 345 port->exists = true; 346 mb(); 347 return 0; 348 } 349 350 /* 351 * i8042_stop() marks serio port as non-existing so i8042_interrupt 352 * will not try to send data to the port that is about to go away. 353 * The function is called by serio core as part of unregister procedure. 354 */ 355 static void i8042_stop(struct serio *serio) 356 { 357 struct i8042_port *port = serio->port_data; 358 359 port->exists = false; 360 361 /* 362 * We synchronize with both AUX and KBD IRQs because there is 363 * a (very unlikely) chance that AUX IRQ is raised for KBD port 364 * and vice versa. 365 */ 366 synchronize_irq(I8042_AUX_IRQ); 367 synchronize_irq(I8042_KBD_IRQ); 368 port->serio = NULL; 369 } 370 371 /* 372 * i8042_interrupt() is the most important function in this driver - 373 * it handles the interrupts from the i8042, and sends incoming bytes 374 * to the upper layers. 375 */ 376 377 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 378 { 379 struct i8042_port *port; 380 unsigned long flags; 381 unsigned char str, data; 382 unsigned int dfl; 383 unsigned int port_no; 384 int ret = 1; 385 386 spin_lock_irqsave(&i8042_lock, flags); 387 str = i8042_read_status(); 388 if (unlikely(~str & I8042_STR_OBF)) { 389 spin_unlock_irqrestore(&i8042_lock, flags); 390 if (irq) dbg("Interrupt %d, without any data", irq); 391 ret = 0; 392 goto out; 393 } 394 data = i8042_read_data(); 395 spin_unlock_irqrestore(&i8042_lock, flags); 396 397 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 398 static unsigned long last_transmit; 399 static unsigned char last_str; 400 401 dfl = 0; 402 if (str & I8042_STR_MUXERR) { 403 dbg("MUX error, status is %02x, data is %02x", str, data); 404 /* 405 * When MUXERR condition is signalled the data register can only contain 406 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 407 * it is not always the case. Some KBCs also report 0xfc when there is 408 * nothing connected to the port while others sometimes get confused which 409 * port the data came from and signal error leaving the data intact. They 410 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 411 * to legacy mode yet, when we see one we'll add proper handling). 412 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 413 * rest assume that the data came from the same serio last byte 414 * was transmitted (if transmission happened not too long ago). 415 */ 416 417 switch (data) { 418 default: 419 if (time_before(jiffies, last_transmit + HZ/10)) { 420 str = last_str; 421 break; 422 } 423 /* fall through - report timeout */ 424 case 0xfc: 425 case 0xfd: 426 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 427 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 428 } 429 } 430 431 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 432 last_str = str; 433 last_transmit = jiffies; 434 } else { 435 436 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 437 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); 438 439 port_no = (str & I8042_STR_AUXDATA) ? 440 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 441 } 442 443 port = &i8042_ports[port_no]; 444 445 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", 446 data, port_no, irq, 447 dfl & SERIO_PARITY ? ", bad parity" : "", 448 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 449 450 if (unlikely(i8042_suppress_kbd_ack)) 451 if (port_no == I8042_KBD_PORT_NO && 452 (data == 0xfa || data == 0xfe)) { 453 i8042_suppress_kbd_ack--; 454 goto out; 455 } 456 457 if (likely(port->exists)) 458 serio_interrupt(port->serio, data, dfl); 459 460 out: 461 return IRQ_RETVAL(ret); 462 } 463 464 /* 465 * i8042_enable_kbd_port enables keyboard port on chip 466 */ 467 468 static int i8042_enable_kbd_port(void) 469 { 470 i8042_ctr &= ~I8042_CTR_KBDDIS; 471 i8042_ctr |= I8042_CTR_KBDINT; 472 473 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 474 i8042_ctr &= ~I8042_CTR_KBDINT; 475 i8042_ctr |= I8042_CTR_KBDDIS; 476 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); 477 return -EIO; 478 } 479 480 return 0; 481 } 482 483 /* 484 * i8042_enable_aux_port enables AUX (mouse) port on chip 485 */ 486 487 static int i8042_enable_aux_port(void) 488 { 489 i8042_ctr &= ~I8042_CTR_AUXDIS; 490 i8042_ctr |= I8042_CTR_AUXINT; 491 492 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 493 i8042_ctr &= ~I8042_CTR_AUXINT; 494 i8042_ctr |= I8042_CTR_AUXDIS; 495 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); 496 return -EIO; 497 } 498 499 return 0; 500 } 501 502 /* 503 * i8042_enable_mux_ports enables 4 individual AUX ports after 504 * the controller has been switched into Multiplexed mode 505 */ 506 507 static int i8042_enable_mux_ports(void) 508 { 509 unsigned char param; 510 int i; 511 512 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 513 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 514 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 515 } 516 517 return i8042_enable_aux_port(); 518 } 519 520 /* 521 * i8042_set_mux_mode checks whether the controller has an 522 * active multiplexor and puts the chip into Multiplexed (true) 523 * or Legacy (false) mode. 524 */ 525 526 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 527 { 528 529 unsigned char param, val; 530 /* 531 * Get rid of bytes in the queue. 532 */ 533 534 i8042_flush(); 535 536 /* 537 * Internal loopback test - send three bytes, they should come back from the 538 * mouse interface, the last should be version. 539 */ 540 541 param = val = 0xf0; 542 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 543 return -1; 544 param = val = multiplex ? 0x56 : 0xf6; 545 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 546 return -1; 547 param = val = multiplex ? 0xa4 : 0xa5; 548 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 549 return -1; 550 551 /* 552 * Workaround for interference with USB Legacy emulation 553 * that causes a v10.12 MUX to be found. 554 */ 555 if (param == 0xac) 556 return -1; 557 558 if (mux_version) 559 *mux_version = param; 560 561 return 0; 562 } 563 564 /* 565 * i8042_check_mux() checks whether the controller supports the PS/2 Active 566 * Multiplexing specification by Synaptics, Phoenix, Insyde and 567 * LCS/Telegraphics. 568 */ 569 570 static int __init i8042_check_mux(void) 571 { 572 unsigned char mux_version; 573 574 if (i8042_set_mux_mode(true, &mux_version)) 575 return -1; 576 577 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", 578 (mux_version >> 4) & 0xf, mux_version & 0xf); 579 580 /* 581 * Disable all muxed ports by disabling AUX. 582 */ 583 i8042_ctr |= I8042_CTR_AUXDIS; 584 i8042_ctr &= ~I8042_CTR_AUXINT; 585 586 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 587 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); 588 return -EIO; 589 } 590 591 i8042_mux_present = true; 592 593 return 0; 594 } 595 596 /* 597 * The following is used to test AUX IRQ delivery. 598 */ 599 static struct completion i8042_aux_irq_delivered __initdata; 600 static bool i8042_irq_being_tested __initdata; 601 602 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 603 { 604 unsigned long flags; 605 unsigned char str, data; 606 int ret = 0; 607 608 spin_lock_irqsave(&i8042_lock, flags); 609 str = i8042_read_status(); 610 if (str & I8042_STR_OBF) { 611 data = i8042_read_data(); 612 if (i8042_irq_being_tested && 613 data == 0xa5 && (str & I8042_STR_AUXDATA)) 614 complete(&i8042_aux_irq_delivered); 615 ret = 1; 616 } 617 spin_unlock_irqrestore(&i8042_lock, flags); 618 619 return IRQ_RETVAL(ret); 620 } 621 622 /* 623 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 624 * verifies success by readinng CTR. Used when testing for presence of AUX 625 * port. 626 */ 627 static int __init i8042_toggle_aux(bool on) 628 { 629 unsigned char param; 630 int i; 631 632 if (i8042_command(¶m, 633 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 634 return -1; 635 636 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 637 for (i = 0; i < 100; i++) { 638 udelay(50); 639 640 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 641 return -1; 642 643 if (!(param & I8042_CTR_AUXDIS) == on) 644 return 0; 645 } 646 647 return -1; 648 } 649 650 /* 651 * i8042_check_aux() applies as much paranoia as it can at detecting 652 * the presence of an AUX interface. 653 */ 654 655 static int __init i8042_check_aux(void) 656 { 657 int retval = -1; 658 bool irq_registered = false; 659 bool aux_loop_broken = false; 660 unsigned long flags; 661 unsigned char param; 662 663 /* 664 * Get rid of bytes in the queue. 665 */ 666 667 i8042_flush(); 668 669 /* 670 * Internal loopback test - filters out AT-type i8042's. Unfortunately 671 * SiS screwed up and their 5597 doesn't support the LOOP command even 672 * though it has an AUX port. 673 */ 674 675 param = 0x5a; 676 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 677 if (retval || param != 0x5a) { 678 679 /* 680 * External connection test - filters out AT-soldered PS/2 i8042's 681 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 682 * 0xfa - no error on some notebooks which ignore the spec 683 * Because it's common for chipsets to return error on perfectly functioning 684 * AUX ports, we test for this only when the LOOP command failed. 685 */ 686 687 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 688 (param && param != 0xfa && param != 0xff)) 689 return -1; 690 691 /* 692 * If AUX_LOOP completed without error but returned unexpected data 693 * mark it as broken 694 */ 695 if (!retval) 696 aux_loop_broken = true; 697 } 698 699 /* 700 * Bit assignment test - filters out PS/2 i8042's in AT mode 701 */ 702 703 if (i8042_toggle_aux(false)) { 704 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 705 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); 706 } 707 708 if (i8042_toggle_aux(true)) 709 return -1; 710 711 /* 712 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 713 * used it for a PCI card or somethig else. 714 */ 715 716 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 717 /* 718 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 719 * is working and hope we are right. 720 */ 721 retval = 0; 722 goto out; 723 } 724 725 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 726 "i8042", i8042_platform_device)) 727 goto out; 728 729 irq_registered = true; 730 731 if (i8042_enable_aux_port()) 732 goto out; 733 734 spin_lock_irqsave(&i8042_lock, flags); 735 736 init_completion(&i8042_aux_irq_delivered); 737 i8042_irq_being_tested = true; 738 739 param = 0xa5; 740 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 741 742 spin_unlock_irqrestore(&i8042_lock, flags); 743 744 if (retval) 745 goto out; 746 747 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 748 msecs_to_jiffies(250)) == 0) { 749 /* 750 * AUX IRQ was never delivered so we need to flush the controller to 751 * get rid of the byte we put there; otherwise keyboard may not work. 752 */ 753 i8042_flush(); 754 retval = -1; 755 } 756 757 out: 758 759 /* 760 * Disable the interface. 761 */ 762 763 i8042_ctr |= I8042_CTR_AUXDIS; 764 i8042_ctr &= ~I8042_CTR_AUXINT; 765 766 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 767 retval = -1; 768 769 if (irq_registered) 770 free_irq(I8042_AUX_IRQ, i8042_platform_device); 771 772 return retval; 773 } 774 775 static int i8042_controller_check(void) 776 { 777 if (i8042_flush() == I8042_BUFFER_SIZE) { 778 printk(KERN_ERR "i8042.c: No controller found.\n"); 779 return -ENODEV; 780 } 781 782 return 0; 783 } 784 785 static int i8042_controller_selftest(void) 786 { 787 unsigned char param; 788 int i = 0; 789 790 if (!i8042_reset) 791 return 0; 792 793 /* 794 * We try this 5 times; on some really fragile systems this does not 795 * take the first time... 796 */ 797 do { 798 799 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 800 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); 801 return -ENODEV; 802 } 803 804 if (param == I8042_RET_CTL_TEST) 805 return 0; 806 807 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", 808 param, I8042_RET_CTL_TEST); 809 msleep(50); 810 } while (i++ < 5); 811 812 #ifdef CONFIG_X86 813 /* 814 * On x86, we don't fail entire i8042 initialization if controller 815 * reset fails in hopes that keyboard port will still be functional 816 * and user will still get a working keyboard. This is especially 817 * important on netbooks. On other arches we trust hardware more. 818 */ 819 printk(KERN_INFO 820 "i8042: giving up on controller selftest, continuing anyway...\n"); 821 return 0; 822 #else 823 return -EIO; 824 #endif 825 } 826 827 /* 828 * i8042_controller init initializes the i8042 controller, and, 829 * most importantly, sets it into non-xlated mode if that's 830 * desired. 831 */ 832 833 static int i8042_controller_init(void) 834 { 835 unsigned long flags; 836 837 /* 838 * Save the CTR for restoral on unload / reboot. 839 */ 840 841 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { 842 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); 843 return -EIO; 844 } 845 846 i8042_initial_ctr = i8042_ctr; 847 848 /* 849 * Disable the keyboard interface and interrupt. 850 */ 851 852 i8042_ctr |= I8042_CTR_KBDDIS; 853 i8042_ctr &= ~I8042_CTR_KBDINT; 854 855 /* 856 * Handle keylock. 857 */ 858 859 spin_lock_irqsave(&i8042_lock, flags); 860 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 861 if (i8042_unlock) 862 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 863 else 864 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); 865 } 866 spin_unlock_irqrestore(&i8042_lock, flags); 867 868 /* 869 * If the chip is configured into nontranslated mode by the BIOS, don't 870 * bother enabling translating and be happy. 871 */ 872 873 if (~i8042_ctr & I8042_CTR_XLATE) 874 i8042_direct = true; 875 876 /* 877 * Set nontranslated mode for the kbd interface if requested by an option. 878 * After this the kbd interface becomes a simple serial in/out, like the aux 879 * interface is. We don't do this by default, since it can confuse notebook 880 * BIOSes. 881 */ 882 883 if (i8042_direct) 884 i8042_ctr &= ~I8042_CTR_XLATE; 885 886 /* 887 * Write CTR back. 888 */ 889 890 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 891 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); 892 return -EIO; 893 } 894 895 return 0; 896 } 897 898 899 /* 900 * Reset the controller and reset CRT to the original value set by BIOS. 901 */ 902 903 static void i8042_controller_reset(void) 904 { 905 i8042_flush(); 906 907 /* 908 * Disable both KBD and AUX interfaces so they don't get in the way 909 */ 910 911 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 912 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 913 914 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 915 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); 916 917 /* 918 * Disable MUX mode if present. 919 */ 920 921 if (i8042_mux_present) 922 i8042_set_mux_mode(false, NULL); 923 924 /* 925 * Reset the controller if requested. 926 */ 927 928 i8042_controller_selftest(); 929 930 /* 931 * Restore the original control register setting. 932 */ 933 934 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 935 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); 936 } 937 938 939 /* 940 * i8042_panic_blink() will flash the keyboard LEDs and is called when 941 * kernel panics. Flashing LEDs is useful for users running X who may 942 * not see the console and will help distingushing panics from "real" 943 * lockups. 944 * 945 * Note that DELAY has a limit of 10ms so we will not get stuck here 946 * waiting for KBC to free up even if KBD interrupt is off 947 */ 948 949 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 950 951 static long i8042_panic_blink(long count) 952 { 953 long delay = 0; 954 static long last_blink; 955 static char led; 956 957 /* 958 * We expect frequency to be about 1/2s. KDB uses about 1s. 959 * Make sure they are different. 960 */ 961 if (!i8042_blink_frequency) 962 return 0; 963 if (count - last_blink < i8042_blink_frequency) 964 return 0; 965 966 led ^= 0x01 | 0x04; 967 while (i8042_read_status() & I8042_STR_IBF) 968 DELAY; 969 dbg("%02x -> i8042 (panic blink)", 0xed); 970 i8042_suppress_kbd_ack = 2; 971 i8042_write_data(0xed); /* set leds */ 972 DELAY; 973 while (i8042_read_status() & I8042_STR_IBF) 974 DELAY; 975 DELAY; 976 dbg("%02x -> i8042 (panic blink)", led); 977 i8042_write_data(led); 978 DELAY; 979 last_blink = count; 980 return delay; 981 } 982 983 #undef DELAY 984 985 #ifdef CONFIG_X86 986 static void i8042_dritek_enable(void) 987 { 988 char param = 0x90; 989 int error; 990 991 error = i8042_command(¶m, 0x1059); 992 if (error) 993 printk(KERN_WARNING 994 "Failed to enable DRITEK extension: %d\n", 995 error); 996 } 997 #endif 998 999 #ifdef CONFIG_PM 1000 1001 /* 1002 * Here we try to restore the original BIOS settings to avoid 1003 * upsetting it. 1004 */ 1005 1006 static int i8042_pm_reset(struct device *dev) 1007 { 1008 i8042_controller_reset(); 1009 1010 return 0; 1011 } 1012 1013 /* 1014 * Here we try to reset everything back to a state we had 1015 * before suspending. 1016 */ 1017 1018 static int i8042_pm_restore(struct device *dev) 1019 { 1020 int error; 1021 1022 error = i8042_controller_check(); 1023 if (error) 1024 return error; 1025 1026 error = i8042_controller_selftest(); 1027 if (error) 1028 return error; 1029 1030 /* 1031 * Restore original CTR value and disable all ports 1032 */ 1033 1034 i8042_ctr = i8042_initial_ctr; 1035 if (i8042_direct) 1036 i8042_ctr &= ~I8042_CTR_XLATE; 1037 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1038 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1039 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1040 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); 1041 msleep(50); 1042 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1043 printk(KERN_ERR "i8042: CTR write retry failed\n"); 1044 return -EIO; 1045 } 1046 } 1047 1048 1049 #ifdef CONFIG_X86 1050 if (i8042_dritek) 1051 i8042_dritek_enable(); 1052 #endif 1053 1054 if (i8042_mux_present) { 1055 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1056 printk(KERN_WARNING 1057 "i8042: failed to resume active multiplexor, " 1058 "mouse won't work.\n"); 1059 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1060 i8042_enable_aux_port(); 1061 1062 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1063 i8042_enable_kbd_port(); 1064 1065 i8042_interrupt(0, NULL); 1066 1067 return 0; 1068 } 1069 1070 static const struct dev_pm_ops i8042_pm_ops = { 1071 .suspend = i8042_pm_reset, 1072 .resume = i8042_pm_restore, 1073 .poweroff = i8042_pm_reset, 1074 .restore = i8042_pm_restore, 1075 }; 1076 1077 #endif /* CONFIG_PM */ 1078 1079 /* 1080 * We need to reset the 8042 back to original mode on system shutdown, 1081 * because otherwise BIOSes will be confused. 1082 */ 1083 1084 static void i8042_shutdown(struct platform_device *dev) 1085 { 1086 i8042_controller_reset(); 1087 } 1088 1089 static int __init i8042_create_kbd_port(void) 1090 { 1091 struct serio *serio; 1092 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1093 1094 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1095 if (!serio) 1096 return -ENOMEM; 1097 1098 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1099 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1100 serio->start = i8042_start; 1101 serio->stop = i8042_stop; 1102 serio->close = i8042_port_close; 1103 serio->port_data = port; 1104 serio->dev.parent = &i8042_platform_device->dev; 1105 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1106 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1107 1108 port->serio = serio; 1109 port->irq = I8042_KBD_IRQ; 1110 1111 return 0; 1112 } 1113 1114 static int __init i8042_create_aux_port(int idx) 1115 { 1116 struct serio *serio; 1117 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1118 struct i8042_port *port = &i8042_ports[port_no]; 1119 1120 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1121 if (!serio) 1122 return -ENOMEM; 1123 1124 serio->id.type = SERIO_8042; 1125 serio->write = i8042_aux_write; 1126 serio->start = i8042_start; 1127 serio->stop = i8042_stop; 1128 serio->port_data = port; 1129 serio->dev.parent = &i8042_platform_device->dev; 1130 if (idx < 0) { 1131 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1132 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1133 serio->close = i8042_port_close; 1134 } else { 1135 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1136 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1137 } 1138 1139 port->serio = serio; 1140 port->mux = idx; 1141 port->irq = I8042_AUX_IRQ; 1142 1143 return 0; 1144 } 1145 1146 static void __init i8042_free_kbd_port(void) 1147 { 1148 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1149 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1150 } 1151 1152 static void __init i8042_free_aux_ports(void) 1153 { 1154 int i; 1155 1156 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1157 kfree(i8042_ports[i].serio); 1158 i8042_ports[i].serio = NULL; 1159 } 1160 } 1161 1162 static void __init i8042_register_ports(void) 1163 { 1164 int i; 1165 1166 for (i = 0; i < I8042_NUM_PORTS; i++) { 1167 if (i8042_ports[i].serio) { 1168 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1169 i8042_ports[i].serio->name, 1170 (unsigned long) I8042_DATA_REG, 1171 (unsigned long) I8042_COMMAND_REG, 1172 i8042_ports[i].irq); 1173 serio_register_port(i8042_ports[i].serio); 1174 } 1175 } 1176 } 1177 1178 static void __devexit i8042_unregister_ports(void) 1179 { 1180 int i; 1181 1182 for (i = 0; i < I8042_NUM_PORTS; i++) { 1183 if (i8042_ports[i].serio) { 1184 serio_unregister_port(i8042_ports[i].serio); 1185 i8042_ports[i].serio = NULL; 1186 } 1187 } 1188 } 1189 1190 /* 1191 * Checks whether port belongs to i8042 controller. 1192 */ 1193 bool i8042_check_port_owner(const struct serio *port) 1194 { 1195 int i; 1196 1197 for (i = 0; i < I8042_NUM_PORTS; i++) 1198 if (i8042_ports[i].serio == port) 1199 return true; 1200 1201 return false; 1202 } 1203 EXPORT_SYMBOL(i8042_check_port_owner); 1204 1205 static void i8042_free_irqs(void) 1206 { 1207 if (i8042_aux_irq_registered) 1208 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1209 if (i8042_kbd_irq_registered) 1210 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1211 1212 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1213 } 1214 1215 static int __init i8042_setup_aux(void) 1216 { 1217 int (*aux_enable)(void); 1218 int error; 1219 int i; 1220 1221 if (i8042_check_aux()) 1222 return -ENODEV; 1223 1224 if (i8042_nomux || i8042_check_mux()) { 1225 error = i8042_create_aux_port(-1); 1226 if (error) 1227 goto err_free_ports; 1228 aux_enable = i8042_enable_aux_port; 1229 } else { 1230 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1231 error = i8042_create_aux_port(i); 1232 if (error) 1233 goto err_free_ports; 1234 } 1235 aux_enable = i8042_enable_mux_ports; 1236 } 1237 1238 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1239 "i8042", i8042_platform_device); 1240 if (error) 1241 goto err_free_ports; 1242 1243 if (aux_enable()) 1244 goto err_free_irq; 1245 1246 i8042_aux_irq_registered = true; 1247 return 0; 1248 1249 err_free_irq: 1250 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1251 err_free_ports: 1252 i8042_free_aux_ports(); 1253 return error; 1254 } 1255 1256 static int __init i8042_setup_kbd(void) 1257 { 1258 int error; 1259 1260 error = i8042_create_kbd_port(); 1261 if (error) 1262 return error; 1263 1264 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1265 "i8042", i8042_platform_device); 1266 if (error) 1267 goto err_free_port; 1268 1269 error = i8042_enable_kbd_port(); 1270 if (error) 1271 goto err_free_irq; 1272 1273 i8042_kbd_irq_registered = true; 1274 return 0; 1275 1276 err_free_irq: 1277 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1278 err_free_port: 1279 i8042_free_kbd_port(); 1280 return error; 1281 } 1282 1283 static int __init i8042_probe(struct platform_device *dev) 1284 { 1285 int error; 1286 1287 error = i8042_controller_selftest(); 1288 if (error) 1289 return error; 1290 1291 error = i8042_controller_init(); 1292 if (error) 1293 return error; 1294 1295 #ifdef CONFIG_X86 1296 if (i8042_dritek) 1297 i8042_dritek_enable(); 1298 #endif 1299 1300 if (!i8042_noaux) { 1301 error = i8042_setup_aux(); 1302 if (error && error != -ENODEV && error != -EBUSY) 1303 goto out_fail; 1304 } 1305 1306 if (!i8042_nokbd) { 1307 error = i8042_setup_kbd(); 1308 if (error) 1309 goto out_fail; 1310 } 1311 /* 1312 * Ok, everything is ready, let's register all serio ports 1313 */ 1314 i8042_register_ports(); 1315 1316 return 0; 1317 1318 out_fail: 1319 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1320 i8042_free_irqs(); 1321 i8042_controller_reset(); 1322 1323 return error; 1324 } 1325 1326 static int __devexit i8042_remove(struct platform_device *dev) 1327 { 1328 i8042_unregister_ports(); 1329 i8042_free_irqs(); 1330 i8042_controller_reset(); 1331 1332 return 0; 1333 } 1334 1335 static struct platform_driver i8042_driver = { 1336 .driver = { 1337 .name = "i8042", 1338 .owner = THIS_MODULE, 1339 #ifdef CONFIG_PM 1340 .pm = &i8042_pm_ops, 1341 #endif 1342 }, 1343 .remove = __devexit_p(i8042_remove), 1344 .shutdown = i8042_shutdown, 1345 }; 1346 1347 static int __init i8042_init(void) 1348 { 1349 int err; 1350 1351 dbg_init(); 1352 1353 err = i8042_platform_init(); 1354 if (err) 1355 return err; 1356 1357 err = i8042_controller_check(); 1358 if (err) 1359 goto err_platform_exit; 1360 1361 i8042_platform_device = platform_device_alloc("i8042", -1); 1362 if (!i8042_platform_device) { 1363 err = -ENOMEM; 1364 goto err_platform_exit; 1365 } 1366 1367 err = platform_device_add(i8042_platform_device); 1368 if (err) 1369 goto err_free_device; 1370 1371 err = platform_driver_probe(&i8042_driver, i8042_probe); 1372 if (err) 1373 goto err_del_device; 1374 1375 panic_blink = i8042_panic_blink; 1376 1377 return 0; 1378 1379 err_del_device: 1380 platform_device_del(i8042_platform_device); 1381 err_free_device: 1382 platform_device_put(i8042_platform_device); 1383 err_platform_exit: 1384 i8042_platform_exit(); 1385 1386 return err; 1387 } 1388 1389 static void __exit i8042_exit(void) 1390 { 1391 platform_driver_unregister(&i8042_driver); 1392 platform_device_unregister(i8042_platform_device); 1393 i8042_platform_exit(); 1394 1395 panic_blink = NULL; 1396 } 1397 1398 module_init(i8042_init); 1399 module_exit(i8042_exit); 1400