1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i8042 keyboard and mouse controller driver for Linux 4 * 5 * Copyright (c) 1999-2004 Vojtech Pavlik 6 */ 7 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/types.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/init.h> 17 #include <linux/serio.h> 18 #include <linux/err.h> 19 #include <linux/rcupdate.h> 20 #include <linux/platform_device.h> 21 #include <linux/i8042.h> 22 #include <linux/slab.h> 23 #include <linux/suspend.h> 24 #include <linux/property.h> 25 26 #include <asm/io.h> 27 28 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 29 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 30 MODULE_LICENSE("GPL"); 31 32 static bool i8042_nokbd; 33 module_param_named(nokbd, i8042_nokbd, bool, 0); 34 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 35 36 static bool i8042_noaux; 37 module_param_named(noaux, i8042_noaux, bool, 0); 38 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 39 40 static bool i8042_nomux; 41 module_param_named(nomux, i8042_nomux, bool, 0); 42 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 43 44 static bool i8042_unlock; 45 module_param_named(unlock, i8042_unlock, bool, 0); 46 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 47 48 enum i8042_controller_reset_mode { 49 I8042_RESET_NEVER, 50 I8042_RESET_ALWAYS, 51 I8042_RESET_ON_S2RAM, 52 #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM 53 }; 54 static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT; 55 static int i8042_set_reset(const char *val, const struct kernel_param *kp) 56 { 57 enum i8042_controller_reset_mode *arg = kp->arg; 58 int error; 59 bool reset; 60 61 if (val) { 62 error = kstrtobool(val, &reset); 63 if (error) 64 return error; 65 } else { 66 reset = true; 67 } 68 69 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER; 70 return 0; 71 } 72 73 static const struct kernel_param_ops param_ops_reset_param = { 74 .flags = KERNEL_PARAM_OPS_FL_NOARG, 75 .set = i8042_set_reset, 76 }; 77 #define param_check_reset_param(name, p) \ 78 __param_check(name, p, enum i8042_controller_reset_mode) 79 module_param_named(reset, i8042_reset, reset_param, 0); 80 MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both"); 81 82 static bool i8042_direct; 83 module_param_named(direct, i8042_direct, bool, 0); 84 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 85 86 static bool i8042_dumbkbd; 87 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 88 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 89 90 static bool i8042_noloop; 91 module_param_named(noloop, i8042_noloop, bool, 0); 92 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 93 94 static bool i8042_notimeout; 95 module_param_named(notimeout, i8042_notimeout, bool, 0); 96 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 97 98 static bool i8042_kbdreset; 99 module_param_named(kbdreset, i8042_kbdreset, bool, 0); 100 MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); 101 102 #ifdef CONFIG_X86 103 static bool i8042_dritek; 104 module_param_named(dritek, i8042_dritek, bool, 0); 105 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 106 #endif 107 108 #ifdef CONFIG_PNP 109 static bool i8042_nopnp; 110 module_param_named(nopnp, i8042_nopnp, bool, 0); 111 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 112 #endif 113 114 #define DEBUG 115 #ifdef DEBUG 116 static bool i8042_debug; 117 module_param_named(debug, i8042_debug, bool, 0600); 118 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 119 120 static bool i8042_unmask_kbd_data; 121 module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); 122 MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); 123 #endif 124 125 static bool i8042_bypass_aux_irq_test; 126 static char i8042_kbd_firmware_id[128]; 127 static char i8042_aux_firmware_id[128]; 128 static struct fwnode_handle *i8042_kbd_fwnode; 129 130 #include "i8042.h" 131 132 /* 133 * i8042_lock protects serialization between i8042_command and 134 * the interrupt handler. 135 */ 136 static DEFINE_SPINLOCK(i8042_lock); 137 138 /* 139 * Writers to AUX and KBD ports as well as users issuing i8042_command 140 * directly should acquire i8042_mutex (by means of calling 141 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 142 * they do not disturb each other (unfortunately in many i8042 143 * implementations write to one of the ports will immediately abort 144 * command that is being processed by another port). 145 */ 146 static DEFINE_MUTEX(i8042_mutex); 147 148 struct i8042_port { 149 struct serio *serio; 150 int irq; 151 bool exists; 152 bool driver_bound; 153 signed char mux; 154 }; 155 156 #define I8042_KBD_PORT_NO 0 157 #define I8042_AUX_PORT_NO 1 158 #define I8042_MUX_PORT_NO 2 159 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 160 161 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 162 163 static unsigned char i8042_initial_ctr; 164 static unsigned char i8042_ctr; 165 static bool i8042_mux_present; 166 static bool i8042_kbd_irq_registered; 167 static bool i8042_aux_irq_registered; 168 static unsigned char i8042_suppress_kbd_ack; 169 static struct platform_device *i8042_platform_device; 170 static struct notifier_block i8042_kbd_bind_notifier_block; 171 172 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 173 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 174 struct serio *serio); 175 176 void i8042_lock_chip(void) 177 { 178 mutex_lock(&i8042_mutex); 179 } 180 EXPORT_SYMBOL(i8042_lock_chip); 181 182 void i8042_unlock_chip(void) 183 { 184 mutex_unlock(&i8042_mutex); 185 } 186 EXPORT_SYMBOL(i8042_unlock_chip); 187 188 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 189 struct serio *serio)) 190 { 191 unsigned long flags; 192 int ret = 0; 193 194 spin_lock_irqsave(&i8042_lock, flags); 195 196 if (i8042_platform_filter) { 197 ret = -EBUSY; 198 goto out; 199 } 200 201 i8042_platform_filter = filter; 202 203 out: 204 spin_unlock_irqrestore(&i8042_lock, flags); 205 return ret; 206 } 207 EXPORT_SYMBOL(i8042_install_filter); 208 209 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 210 struct serio *port)) 211 { 212 unsigned long flags; 213 int ret = 0; 214 215 spin_lock_irqsave(&i8042_lock, flags); 216 217 if (i8042_platform_filter != filter) { 218 ret = -EINVAL; 219 goto out; 220 } 221 222 i8042_platform_filter = NULL; 223 224 out: 225 spin_unlock_irqrestore(&i8042_lock, flags); 226 return ret; 227 } 228 EXPORT_SYMBOL(i8042_remove_filter); 229 230 /* 231 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 232 * be ready for reading values from it / writing values to it. 233 * Called always with i8042_lock held. 234 */ 235 236 static int i8042_wait_read(void) 237 { 238 int i = 0; 239 240 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 241 udelay(50); 242 i++; 243 } 244 return -(i == I8042_CTL_TIMEOUT); 245 } 246 247 static int i8042_wait_write(void) 248 { 249 int i = 0; 250 251 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 252 udelay(50); 253 i++; 254 } 255 return -(i == I8042_CTL_TIMEOUT); 256 } 257 258 /* 259 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 260 * of the i8042 down the toilet. 261 */ 262 263 static int i8042_flush(void) 264 { 265 unsigned long flags; 266 unsigned char data, str; 267 int count = 0; 268 int retval = 0; 269 270 spin_lock_irqsave(&i8042_lock, flags); 271 272 while ((str = i8042_read_status()) & I8042_STR_OBF) { 273 if (count++ < I8042_BUFFER_SIZE) { 274 udelay(50); 275 data = i8042_read_data(); 276 dbg("%02x <- i8042 (flush, %s)\n", 277 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 278 } else { 279 retval = -EIO; 280 break; 281 } 282 } 283 284 spin_unlock_irqrestore(&i8042_lock, flags); 285 286 return retval; 287 } 288 289 /* 290 * i8042_command() executes a command on the i8042. It also sends the input 291 * parameter(s) of the commands to it, and receives the output value(s). The 292 * parameters are to be stored in the param array, and the output is placed 293 * into the same array. The number of the parameters and output values is 294 * encoded in bits 8-11 of the command number. 295 */ 296 297 static int __i8042_command(unsigned char *param, int command) 298 { 299 int i, error; 300 301 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 302 return -1; 303 304 error = i8042_wait_write(); 305 if (error) 306 return error; 307 308 dbg("%02x -> i8042 (command)\n", command & 0xff); 309 i8042_write_command(command & 0xff); 310 311 for (i = 0; i < ((command >> 12) & 0xf); i++) { 312 error = i8042_wait_write(); 313 if (error) { 314 dbg(" -- i8042 (wait write timeout)\n"); 315 return error; 316 } 317 dbg("%02x -> i8042 (parameter)\n", param[i]); 318 i8042_write_data(param[i]); 319 } 320 321 for (i = 0; i < ((command >> 8) & 0xf); i++) { 322 error = i8042_wait_read(); 323 if (error) { 324 dbg(" -- i8042 (wait read timeout)\n"); 325 return error; 326 } 327 328 if (command == I8042_CMD_AUX_LOOP && 329 !(i8042_read_status() & I8042_STR_AUXDATA)) { 330 dbg(" -- i8042 (auxerr)\n"); 331 return -1; 332 } 333 334 param[i] = i8042_read_data(); 335 dbg("%02x <- i8042 (return)\n", param[i]); 336 } 337 338 return 0; 339 } 340 341 int i8042_command(unsigned char *param, int command) 342 { 343 unsigned long flags; 344 int retval; 345 346 spin_lock_irqsave(&i8042_lock, flags); 347 retval = __i8042_command(param, command); 348 spin_unlock_irqrestore(&i8042_lock, flags); 349 350 return retval; 351 } 352 EXPORT_SYMBOL(i8042_command); 353 354 /* 355 * i8042_kbd_write() sends a byte out through the keyboard interface. 356 */ 357 358 static int i8042_kbd_write(struct serio *port, unsigned char c) 359 { 360 unsigned long flags; 361 int retval = 0; 362 363 spin_lock_irqsave(&i8042_lock, flags); 364 365 if (!(retval = i8042_wait_write())) { 366 dbg("%02x -> i8042 (kbd-data)\n", c); 367 i8042_write_data(c); 368 } 369 370 spin_unlock_irqrestore(&i8042_lock, flags); 371 372 return retval; 373 } 374 375 /* 376 * i8042_aux_write() sends a byte out through the aux interface. 377 */ 378 379 static int i8042_aux_write(struct serio *serio, unsigned char c) 380 { 381 struct i8042_port *port = serio->port_data; 382 383 return i8042_command(&c, port->mux == -1 ? 384 I8042_CMD_AUX_SEND : 385 I8042_CMD_MUX_SEND + port->mux); 386 } 387 388 389 /* 390 * i8042_port_close attempts to clear AUX or KBD port state by disabling 391 * and then re-enabling it. 392 */ 393 394 static void i8042_port_close(struct serio *serio) 395 { 396 int irq_bit; 397 int disable_bit; 398 const char *port_name; 399 400 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 401 irq_bit = I8042_CTR_AUXINT; 402 disable_bit = I8042_CTR_AUXDIS; 403 port_name = "AUX"; 404 } else { 405 irq_bit = I8042_CTR_KBDINT; 406 disable_bit = I8042_CTR_KBDDIS; 407 port_name = "KBD"; 408 } 409 410 i8042_ctr &= ~irq_bit; 411 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 412 pr_warn("Can't write CTR while closing %s port\n", port_name); 413 414 udelay(50); 415 416 i8042_ctr &= ~disable_bit; 417 i8042_ctr |= irq_bit; 418 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 419 pr_err("Can't reactivate %s port\n", port_name); 420 421 /* 422 * See if there is any data appeared while we were messing with 423 * port state. 424 */ 425 i8042_interrupt(0, NULL); 426 } 427 428 /* 429 * i8042_start() is called by serio core when port is about to finish 430 * registering. It will mark port as existing so i8042_interrupt can 431 * start sending data through it. 432 */ 433 static int i8042_start(struct serio *serio) 434 { 435 struct i8042_port *port = serio->port_data; 436 437 device_set_wakeup_capable(&serio->dev, true); 438 439 /* 440 * On platforms using suspend-to-idle, allow the keyboard to 441 * wake up the system from sleep by enabling keyboard wakeups 442 * by default. This is consistent with keyboard wakeup 443 * behavior on many platforms using suspend-to-RAM (ACPI S3) 444 * by default. 445 */ 446 if (pm_suspend_default_s2idle() && 447 serio == i8042_ports[I8042_KBD_PORT_NO].serio) { 448 device_set_wakeup_enable(&serio->dev, true); 449 } 450 451 spin_lock_irq(&i8042_lock); 452 port->exists = true; 453 spin_unlock_irq(&i8042_lock); 454 455 return 0; 456 } 457 458 /* 459 * i8042_stop() marks serio port as non-existing so i8042_interrupt 460 * will not try to send data to the port that is about to go away. 461 * The function is called by serio core as part of unregister procedure. 462 */ 463 static void i8042_stop(struct serio *serio) 464 { 465 struct i8042_port *port = serio->port_data; 466 467 spin_lock_irq(&i8042_lock); 468 port->exists = false; 469 port->serio = NULL; 470 spin_unlock_irq(&i8042_lock); 471 472 /* 473 * We need to make sure that interrupt handler finishes using 474 * our serio port before we return from this function. 475 * We synchronize with both AUX and KBD IRQs because there is 476 * a (very unlikely) chance that AUX IRQ is raised for KBD port 477 * and vice versa. 478 */ 479 synchronize_irq(I8042_AUX_IRQ); 480 synchronize_irq(I8042_KBD_IRQ); 481 } 482 483 /* 484 * i8042_filter() filters out unwanted bytes from the input data stream. 485 * It is called from i8042_interrupt and thus is running with interrupts 486 * off and i8042_lock held. 487 */ 488 static bool i8042_filter(unsigned char data, unsigned char str, 489 struct serio *serio) 490 { 491 if (unlikely(i8042_suppress_kbd_ack)) { 492 if ((~str & I8042_STR_AUXDATA) && 493 (data == 0xfa || data == 0xfe)) { 494 i8042_suppress_kbd_ack--; 495 dbg("Extra keyboard ACK - filtered out\n"); 496 return true; 497 } 498 } 499 500 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 501 dbg("Filtered out by platform filter\n"); 502 return true; 503 } 504 505 return false; 506 } 507 508 /* 509 * i8042_interrupt() is the most important function in this driver - 510 * it handles the interrupts from the i8042, and sends incoming bytes 511 * to the upper layers. 512 */ 513 514 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 515 { 516 struct i8042_port *port; 517 struct serio *serio; 518 unsigned long flags; 519 unsigned char str, data; 520 unsigned int dfl; 521 unsigned int port_no; 522 bool filtered; 523 int ret = 1; 524 525 spin_lock_irqsave(&i8042_lock, flags); 526 527 str = i8042_read_status(); 528 if (unlikely(~str & I8042_STR_OBF)) { 529 spin_unlock_irqrestore(&i8042_lock, flags); 530 if (irq) 531 dbg("Interrupt %d, without any data\n", irq); 532 ret = 0; 533 goto out; 534 } 535 536 data = i8042_read_data(); 537 538 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 539 static unsigned long last_transmit; 540 static unsigned char last_str; 541 542 dfl = 0; 543 if (str & I8042_STR_MUXERR) { 544 dbg("MUX error, status is %02x, data is %02x\n", 545 str, data); 546 /* 547 * When MUXERR condition is signalled the data register can only contain 548 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 549 * it is not always the case. Some KBCs also report 0xfc when there is 550 * nothing connected to the port while others sometimes get confused which 551 * port the data came from and signal error leaving the data intact. They 552 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 553 * to legacy mode yet, when we see one we'll add proper handling). 554 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 555 * rest assume that the data came from the same serio last byte 556 * was transmitted (if transmission happened not too long ago). 557 */ 558 559 switch (data) { 560 default: 561 if (time_before(jiffies, last_transmit + HZ/10)) { 562 str = last_str; 563 break; 564 } 565 fallthrough; /* report timeout */ 566 case 0xfc: 567 case 0xfd: 568 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 569 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 570 } 571 } 572 573 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 574 last_str = str; 575 last_transmit = jiffies; 576 } else { 577 578 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 579 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); 580 581 port_no = (str & I8042_STR_AUXDATA) ? 582 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 583 } 584 585 port = &i8042_ports[port_no]; 586 serio = port->exists ? port->serio : NULL; 587 588 filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n", 589 port_no, irq, 590 dfl & SERIO_PARITY ? ", bad parity" : "", 591 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 592 593 filtered = i8042_filter(data, str, serio); 594 595 spin_unlock_irqrestore(&i8042_lock, flags); 596 597 if (likely(serio && !filtered)) 598 serio_interrupt(serio, data, dfl); 599 600 out: 601 return IRQ_RETVAL(ret); 602 } 603 604 /* 605 * i8042_enable_kbd_port enables keyboard port on chip 606 */ 607 608 static int i8042_enable_kbd_port(void) 609 { 610 i8042_ctr &= ~I8042_CTR_KBDDIS; 611 i8042_ctr |= I8042_CTR_KBDINT; 612 613 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 614 i8042_ctr &= ~I8042_CTR_KBDINT; 615 i8042_ctr |= I8042_CTR_KBDDIS; 616 pr_err("Failed to enable KBD port\n"); 617 return -EIO; 618 } 619 620 return 0; 621 } 622 623 /* 624 * i8042_enable_aux_port enables AUX (mouse) port on chip 625 */ 626 627 static int i8042_enable_aux_port(void) 628 { 629 i8042_ctr &= ~I8042_CTR_AUXDIS; 630 i8042_ctr |= I8042_CTR_AUXINT; 631 632 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 633 i8042_ctr &= ~I8042_CTR_AUXINT; 634 i8042_ctr |= I8042_CTR_AUXDIS; 635 pr_err("Failed to enable AUX port\n"); 636 return -EIO; 637 } 638 639 return 0; 640 } 641 642 /* 643 * i8042_enable_mux_ports enables 4 individual AUX ports after 644 * the controller has been switched into Multiplexed mode 645 */ 646 647 static int i8042_enable_mux_ports(void) 648 { 649 unsigned char param; 650 int i; 651 652 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 653 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 654 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 655 } 656 657 return i8042_enable_aux_port(); 658 } 659 660 /* 661 * i8042_set_mux_mode checks whether the controller has an 662 * active multiplexor and puts the chip into Multiplexed (true) 663 * or Legacy (false) mode. 664 */ 665 666 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 667 { 668 669 unsigned char param, val; 670 /* 671 * Get rid of bytes in the queue. 672 */ 673 674 i8042_flush(); 675 676 /* 677 * Internal loopback test - send three bytes, they should come back from the 678 * mouse interface, the last should be version. 679 */ 680 681 param = val = 0xf0; 682 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 683 return -1; 684 param = val = multiplex ? 0x56 : 0xf6; 685 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 686 return -1; 687 param = val = multiplex ? 0xa4 : 0xa5; 688 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 689 return -1; 690 691 /* 692 * Workaround for interference with USB Legacy emulation 693 * that causes a v10.12 MUX to be found. 694 */ 695 if (param == 0xac) 696 return -1; 697 698 if (mux_version) 699 *mux_version = param; 700 701 return 0; 702 } 703 704 /* 705 * i8042_check_mux() checks whether the controller supports the PS/2 Active 706 * Multiplexing specification by Synaptics, Phoenix, Insyde and 707 * LCS/Telegraphics. 708 */ 709 710 static int __init i8042_check_mux(void) 711 { 712 unsigned char mux_version; 713 714 if (i8042_set_mux_mode(true, &mux_version)) 715 return -1; 716 717 pr_info("Detected active multiplexing controller, rev %d.%d\n", 718 (mux_version >> 4) & 0xf, mux_version & 0xf); 719 720 /* 721 * Disable all muxed ports by disabling AUX. 722 */ 723 i8042_ctr |= I8042_CTR_AUXDIS; 724 i8042_ctr &= ~I8042_CTR_AUXINT; 725 726 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 727 pr_err("Failed to disable AUX port, can't use MUX\n"); 728 return -EIO; 729 } 730 731 i8042_mux_present = true; 732 733 return 0; 734 } 735 736 /* 737 * The following is used to test AUX IRQ delivery. 738 */ 739 static struct completion i8042_aux_irq_delivered __initdata; 740 static bool i8042_irq_being_tested __initdata; 741 742 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 743 { 744 unsigned long flags; 745 unsigned char str, data; 746 int ret = 0; 747 748 spin_lock_irqsave(&i8042_lock, flags); 749 str = i8042_read_status(); 750 if (str & I8042_STR_OBF) { 751 data = i8042_read_data(); 752 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 753 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 754 if (i8042_irq_being_tested && 755 data == 0xa5 && (str & I8042_STR_AUXDATA)) 756 complete(&i8042_aux_irq_delivered); 757 ret = 1; 758 } 759 spin_unlock_irqrestore(&i8042_lock, flags); 760 761 return IRQ_RETVAL(ret); 762 } 763 764 /* 765 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 766 * verifies success by readinng CTR. Used when testing for presence of AUX 767 * port. 768 */ 769 static int __init i8042_toggle_aux(bool on) 770 { 771 unsigned char param; 772 int i; 773 774 if (i8042_command(¶m, 775 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 776 return -1; 777 778 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 779 for (i = 0; i < 100; i++) { 780 udelay(50); 781 782 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 783 return -1; 784 785 if (!(param & I8042_CTR_AUXDIS) == on) 786 return 0; 787 } 788 789 return -1; 790 } 791 792 /* 793 * i8042_check_aux() applies as much paranoia as it can at detecting 794 * the presence of an AUX interface. 795 */ 796 797 static int __init i8042_check_aux(void) 798 { 799 int retval = -1; 800 bool irq_registered = false; 801 bool aux_loop_broken = false; 802 unsigned long flags; 803 unsigned char param; 804 805 /* 806 * Get rid of bytes in the queue. 807 */ 808 809 i8042_flush(); 810 811 /* 812 * Internal loopback test - filters out AT-type i8042's. Unfortunately 813 * SiS screwed up and their 5597 doesn't support the LOOP command even 814 * though it has an AUX port. 815 */ 816 817 param = 0x5a; 818 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 819 if (retval || param != 0x5a) { 820 821 /* 822 * External connection test - filters out AT-soldered PS/2 i8042's 823 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 824 * 0xfa - no error on some notebooks which ignore the spec 825 * Because it's common for chipsets to return error on perfectly functioning 826 * AUX ports, we test for this only when the LOOP command failed. 827 */ 828 829 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 830 (param && param != 0xfa && param != 0xff)) 831 return -1; 832 833 /* 834 * If AUX_LOOP completed without error but returned unexpected data 835 * mark it as broken 836 */ 837 if (!retval) 838 aux_loop_broken = true; 839 } 840 841 /* 842 * Bit assignment test - filters out PS/2 i8042's in AT mode 843 */ 844 845 if (i8042_toggle_aux(false)) { 846 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 847 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 848 } 849 850 if (i8042_toggle_aux(true)) 851 return -1; 852 853 /* 854 * Reset keyboard (needed on some laptops to successfully detect 855 * touchpad, e.g., some Gigabyte laptop models with Elantech 856 * touchpads). 857 */ 858 if (i8042_kbdreset) { 859 pr_warn("Attempting to reset device connected to KBD port\n"); 860 i8042_kbd_write(NULL, (unsigned char) 0xff); 861 } 862 863 /* 864 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 865 * used it for a PCI card or somethig else. 866 */ 867 868 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 869 /* 870 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 871 * is working and hope we are right. 872 */ 873 retval = 0; 874 goto out; 875 } 876 877 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 878 "i8042", i8042_platform_device)) 879 goto out; 880 881 irq_registered = true; 882 883 if (i8042_enable_aux_port()) 884 goto out; 885 886 spin_lock_irqsave(&i8042_lock, flags); 887 888 init_completion(&i8042_aux_irq_delivered); 889 i8042_irq_being_tested = true; 890 891 param = 0xa5; 892 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 893 894 spin_unlock_irqrestore(&i8042_lock, flags); 895 896 if (retval) 897 goto out; 898 899 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 900 msecs_to_jiffies(250)) == 0) { 901 /* 902 * AUX IRQ was never delivered so we need to flush the controller to 903 * get rid of the byte we put there; otherwise keyboard may not work. 904 */ 905 dbg(" -- i8042 (aux irq test timeout)\n"); 906 i8042_flush(); 907 retval = -1; 908 } 909 910 out: 911 912 /* 913 * Disable the interface. 914 */ 915 916 i8042_ctr |= I8042_CTR_AUXDIS; 917 i8042_ctr &= ~I8042_CTR_AUXINT; 918 919 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 920 retval = -1; 921 922 if (irq_registered) 923 free_irq(I8042_AUX_IRQ, i8042_platform_device); 924 925 return retval; 926 } 927 928 static int i8042_controller_check(void) 929 { 930 if (i8042_flush()) { 931 pr_info("No controller found\n"); 932 return -ENODEV; 933 } 934 935 return 0; 936 } 937 938 static int i8042_controller_selftest(void) 939 { 940 unsigned char param; 941 int i = 0; 942 943 /* 944 * We try this 5 times; on some really fragile systems this does not 945 * take the first time... 946 */ 947 do { 948 949 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 950 pr_err("i8042 controller selftest timeout\n"); 951 return -ENODEV; 952 } 953 954 if (param == I8042_RET_CTL_TEST) 955 return 0; 956 957 dbg("i8042 controller selftest: %#x != %#x\n", 958 param, I8042_RET_CTL_TEST); 959 msleep(50); 960 } while (i++ < 5); 961 962 #ifdef CONFIG_X86 963 /* 964 * On x86, we don't fail entire i8042 initialization if controller 965 * reset fails in hopes that keyboard port will still be functional 966 * and user will still get a working keyboard. This is especially 967 * important on netbooks. On other arches we trust hardware more. 968 */ 969 pr_info("giving up on controller selftest, continuing anyway...\n"); 970 return 0; 971 #else 972 pr_err("i8042 controller selftest failed\n"); 973 return -EIO; 974 #endif 975 } 976 977 /* 978 * i8042_controller init initializes the i8042 controller, and, 979 * most importantly, sets it into non-xlated mode if that's 980 * desired. 981 */ 982 983 static int i8042_controller_init(void) 984 { 985 unsigned long flags; 986 int n = 0; 987 unsigned char ctr[2]; 988 989 /* 990 * Save the CTR for restore on unload / reboot. 991 */ 992 993 do { 994 if (n >= 10) { 995 pr_err("Unable to get stable CTR read\n"); 996 return -EIO; 997 } 998 999 if (n != 0) 1000 udelay(50); 1001 1002 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 1003 pr_err("Can't read CTR while initializing i8042\n"); 1004 return -EIO; 1005 } 1006 1007 } while (n < 2 || ctr[0] != ctr[1]); 1008 1009 i8042_initial_ctr = i8042_ctr = ctr[0]; 1010 1011 /* 1012 * Disable the keyboard interface and interrupt. 1013 */ 1014 1015 i8042_ctr |= I8042_CTR_KBDDIS; 1016 i8042_ctr &= ~I8042_CTR_KBDINT; 1017 1018 /* 1019 * Handle keylock. 1020 */ 1021 1022 spin_lock_irqsave(&i8042_lock, flags); 1023 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 1024 if (i8042_unlock) 1025 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 1026 else 1027 pr_warn("Warning: Keylock active\n"); 1028 } 1029 spin_unlock_irqrestore(&i8042_lock, flags); 1030 1031 /* 1032 * If the chip is configured into nontranslated mode by the BIOS, don't 1033 * bother enabling translating and be happy. 1034 */ 1035 1036 if (~i8042_ctr & I8042_CTR_XLATE) 1037 i8042_direct = true; 1038 1039 /* 1040 * Set nontranslated mode for the kbd interface if requested by an option. 1041 * After this the kbd interface becomes a simple serial in/out, like the aux 1042 * interface is. We don't do this by default, since it can confuse notebook 1043 * BIOSes. 1044 */ 1045 1046 if (i8042_direct) 1047 i8042_ctr &= ~I8042_CTR_XLATE; 1048 1049 /* 1050 * Write CTR back. 1051 */ 1052 1053 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1054 pr_err("Can't write CTR while initializing i8042\n"); 1055 return -EIO; 1056 } 1057 1058 /* 1059 * Flush whatever accumulated while we were disabling keyboard port. 1060 */ 1061 1062 i8042_flush(); 1063 1064 return 0; 1065 } 1066 1067 1068 /* 1069 * Reset the controller and reset CRT to the original value set by BIOS. 1070 */ 1071 1072 static void i8042_controller_reset(bool s2r_wants_reset) 1073 { 1074 i8042_flush(); 1075 1076 /* 1077 * Disable both KBD and AUX interfaces so they don't get in the way 1078 */ 1079 1080 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1081 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1082 1083 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1084 pr_warn("Can't write CTR while resetting\n"); 1085 1086 /* 1087 * Disable MUX mode if present. 1088 */ 1089 1090 if (i8042_mux_present) 1091 i8042_set_mux_mode(false, NULL); 1092 1093 /* 1094 * Reset the controller if requested. 1095 */ 1096 1097 if (i8042_reset == I8042_RESET_ALWAYS || 1098 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1099 i8042_controller_selftest(); 1100 } 1101 1102 /* 1103 * Restore the original control register setting. 1104 */ 1105 1106 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1107 pr_warn("Can't restore CTR\n"); 1108 } 1109 1110 1111 /* 1112 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1113 * when kernel panics. Flashing LEDs is useful for users running X who may 1114 * not see the console and will help distinguishing panics from "real" 1115 * lockups. 1116 * 1117 * Note that DELAY has a limit of 10ms so we will not get stuck here 1118 * waiting for KBC to free up even if KBD interrupt is off 1119 */ 1120 1121 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1122 1123 static long i8042_panic_blink(int state) 1124 { 1125 long delay = 0; 1126 char led; 1127 1128 led = (state) ? 0x01 | 0x04 : 0; 1129 while (i8042_read_status() & I8042_STR_IBF) 1130 DELAY; 1131 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1132 i8042_suppress_kbd_ack = 2; 1133 i8042_write_data(0xed); /* set leds */ 1134 DELAY; 1135 while (i8042_read_status() & I8042_STR_IBF) 1136 DELAY; 1137 DELAY; 1138 dbg("%02x -> i8042 (panic blink)\n", led); 1139 i8042_write_data(led); 1140 DELAY; 1141 return delay; 1142 } 1143 1144 #undef DELAY 1145 1146 #ifdef CONFIG_X86 1147 static void i8042_dritek_enable(void) 1148 { 1149 unsigned char param = 0x90; 1150 int error; 1151 1152 error = i8042_command(¶m, 0x1059); 1153 if (error) 1154 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1155 } 1156 #endif 1157 1158 #ifdef CONFIG_PM 1159 1160 /* 1161 * Here we try to reset everything back to a state we had 1162 * before suspending. 1163 */ 1164 1165 static int i8042_controller_resume(bool s2r_wants_reset) 1166 { 1167 int error; 1168 1169 error = i8042_controller_check(); 1170 if (error) 1171 return error; 1172 1173 if (i8042_reset == I8042_RESET_ALWAYS || 1174 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1175 error = i8042_controller_selftest(); 1176 if (error) 1177 return error; 1178 } 1179 1180 /* 1181 * Restore original CTR value and disable all ports 1182 */ 1183 1184 i8042_ctr = i8042_initial_ctr; 1185 if (i8042_direct) 1186 i8042_ctr &= ~I8042_CTR_XLATE; 1187 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1188 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1189 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1190 pr_warn("Can't write CTR to resume, retrying...\n"); 1191 msleep(50); 1192 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1193 pr_err("CTR write retry failed\n"); 1194 return -EIO; 1195 } 1196 } 1197 1198 1199 #ifdef CONFIG_X86 1200 if (i8042_dritek) 1201 i8042_dritek_enable(); 1202 #endif 1203 1204 if (i8042_mux_present) { 1205 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1206 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1207 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1208 i8042_enable_aux_port(); 1209 1210 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1211 i8042_enable_kbd_port(); 1212 1213 i8042_interrupt(0, NULL); 1214 1215 return 0; 1216 } 1217 1218 /* 1219 * Here we try to restore the original BIOS settings to avoid 1220 * upsetting it. 1221 */ 1222 1223 static int i8042_pm_suspend(struct device *dev) 1224 { 1225 int i; 1226 1227 if (pm_suspend_via_firmware()) 1228 i8042_controller_reset(true); 1229 1230 /* Set up serio interrupts for system wakeup. */ 1231 for (i = 0; i < I8042_NUM_PORTS; i++) { 1232 struct serio *serio = i8042_ports[i].serio; 1233 1234 if (serio && device_may_wakeup(&serio->dev)) 1235 enable_irq_wake(i8042_ports[i].irq); 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int i8042_pm_resume_noirq(struct device *dev) 1242 { 1243 if (!pm_resume_via_firmware()) 1244 i8042_interrupt(0, NULL); 1245 1246 return 0; 1247 } 1248 1249 static int i8042_pm_resume(struct device *dev) 1250 { 1251 bool want_reset; 1252 int i; 1253 1254 for (i = 0; i < I8042_NUM_PORTS; i++) { 1255 struct serio *serio = i8042_ports[i].serio; 1256 1257 if (serio && device_may_wakeup(&serio->dev)) 1258 disable_irq_wake(i8042_ports[i].irq); 1259 } 1260 1261 /* 1262 * If platform firmware was not going to be involved in suspend, we did 1263 * not restore the controller state to whatever it had been at boot 1264 * time, so we do not need to do anything. 1265 */ 1266 if (!pm_suspend_via_firmware()) 1267 return 0; 1268 1269 /* 1270 * We only need to reset the controller if we are resuming after handing 1271 * off control to the platform firmware, otherwise we can simply restore 1272 * the mode. 1273 */ 1274 want_reset = pm_resume_via_firmware(); 1275 1276 return i8042_controller_resume(want_reset); 1277 } 1278 1279 static int i8042_pm_thaw(struct device *dev) 1280 { 1281 i8042_interrupt(0, NULL); 1282 1283 return 0; 1284 } 1285 1286 static int i8042_pm_reset(struct device *dev) 1287 { 1288 i8042_controller_reset(false); 1289 1290 return 0; 1291 } 1292 1293 static int i8042_pm_restore(struct device *dev) 1294 { 1295 return i8042_controller_resume(false); 1296 } 1297 1298 static const struct dev_pm_ops i8042_pm_ops = { 1299 .suspend = i8042_pm_suspend, 1300 .resume_noirq = i8042_pm_resume_noirq, 1301 .resume = i8042_pm_resume, 1302 .thaw = i8042_pm_thaw, 1303 .poweroff = i8042_pm_reset, 1304 .restore = i8042_pm_restore, 1305 }; 1306 1307 #endif /* CONFIG_PM */ 1308 1309 /* 1310 * We need to reset the 8042 back to original mode on system shutdown, 1311 * because otherwise BIOSes will be confused. 1312 */ 1313 1314 static void i8042_shutdown(struct platform_device *dev) 1315 { 1316 i8042_controller_reset(false); 1317 } 1318 1319 static int __init i8042_create_kbd_port(void) 1320 { 1321 struct serio *serio; 1322 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1323 1324 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1325 if (!serio) 1326 return -ENOMEM; 1327 1328 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1329 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1330 serio->start = i8042_start; 1331 serio->stop = i8042_stop; 1332 serio->close = i8042_port_close; 1333 serio->ps2_cmd_mutex = &i8042_mutex; 1334 serio->port_data = port; 1335 serio->dev.parent = &i8042_platform_device->dev; 1336 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1337 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1338 strlcpy(serio->firmware_id, i8042_kbd_firmware_id, 1339 sizeof(serio->firmware_id)); 1340 set_primary_fwnode(&serio->dev, i8042_kbd_fwnode); 1341 1342 port->serio = serio; 1343 port->irq = I8042_KBD_IRQ; 1344 1345 return 0; 1346 } 1347 1348 static int __init i8042_create_aux_port(int idx) 1349 { 1350 struct serio *serio; 1351 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1352 struct i8042_port *port = &i8042_ports[port_no]; 1353 1354 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1355 if (!serio) 1356 return -ENOMEM; 1357 1358 serio->id.type = SERIO_8042; 1359 serio->write = i8042_aux_write; 1360 serio->start = i8042_start; 1361 serio->stop = i8042_stop; 1362 serio->ps2_cmd_mutex = &i8042_mutex; 1363 serio->port_data = port; 1364 serio->dev.parent = &i8042_platform_device->dev; 1365 if (idx < 0) { 1366 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1367 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1368 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1369 sizeof(serio->firmware_id)); 1370 serio->close = i8042_port_close; 1371 } else { 1372 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1373 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1374 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1375 sizeof(serio->firmware_id)); 1376 } 1377 1378 port->serio = serio; 1379 port->mux = idx; 1380 port->irq = I8042_AUX_IRQ; 1381 1382 return 0; 1383 } 1384 1385 static void __init i8042_free_kbd_port(void) 1386 { 1387 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1388 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1389 } 1390 1391 static void __init i8042_free_aux_ports(void) 1392 { 1393 int i; 1394 1395 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1396 kfree(i8042_ports[i].serio); 1397 i8042_ports[i].serio = NULL; 1398 } 1399 } 1400 1401 static void __init i8042_register_ports(void) 1402 { 1403 int i; 1404 1405 for (i = 0; i < I8042_NUM_PORTS; i++) { 1406 struct serio *serio = i8042_ports[i].serio; 1407 1408 if (!serio) 1409 continue; 1410 1411 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1412 serio->name, 1413 (unsigned long) I8042_DATA_REG, 1414 (unsigned long) I8042_COMMAND_REG, 1415 i8042_ports[i].irq); 1416 serio_register_port(serio); 1417 } 1418 } 1419 1420 static void i8042_unregister_ports(void) 1421 { 1422 int i; 1423 1424 for (i = 0; i < I8042_NUM_PORTS; i++) { 1425 if (i8042_ports[i].serio) { 1426 serio_unregister_port(i8042_ports[i].serio); 1427 i8042_ports[i].serio = NULL; 1428 } 1429 } 1430 } 1431 1432 static void i8042_free_irqs(void) 1433 { 1434 if (i8042_aux_irq_registered) 1435 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1436 if (i8042_kbd_irq_registered) 1437 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1438 1439 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1440 } 1441 1442 static int __init i8042_setup_aux(void) 1443 { 1444 int (*aux_enable)(void); 1445 int error; 1446 int i; 1447 1448 if (i8042_check_aux()) 1449 return -ENODEV; 1450 1451 if (i8042_nomux || i8042_check_mux()) { 1452 error = i8042_create_aux_port(-1); 1453 if (error) 1454 goto err_free_ports; 1455 aux_enable = i8042_enable_aux_port; 1456 } else { 1457 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1458 error = i8042_create_aux_port(i); 1459 if (error) 1460 goto err_free_ports; 1461 } 1462 aux_enable = i8042_enable_mux_ports; 1463 } 1464 1465 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1466 "i8042", i8042_platform_device); 1467 if (error) 1468 goto err_free_ports; 1469 1470 if (aux_enable()) 1471 goto err_free_irq; 1472 1473 i8042_aux_irq_registered = true; 1474 return 0; 1475 1476 err_free_irq: 1477 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1478 err_free_ports: 1479 i8042_free_aux_ports(); 1480 return error; 1481 } 1482 1483 static int __init i8042_setup_kbd(void) 1484 { 1485 int error; 1486 1487 error = i8042_create_kbd_port(); 1488 if (error) 1489 return error; 1490 1491 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1492 "i8042", i8042_platform_device); 1493 if (error) 1494 goto err_free_port; 1495 1496 error = i8042_enable_kbd_port(); 1497 if (error) 1498 goto err_free_irq; 1499 1500 i8042_kbd_irq_registered = true; 1501 return 0; 1502 1503 err_free_irq: 1504 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1505 err_free_port: 1506 i8042_free_kbd_port(); 1507 return error; 1508 } 1509 1510 static int i8042_kbd_bind_notifier(struct notifier_block *nb, 1511 unsigned long action, void *data) 1512 { 1513 struct device *dev = data; 1514 struct serio *serio = to_serio_port(dev); 1515 struct i8042_port *port = serio->port_data; 1516 1517 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) 1518 return 0; 1519 1520 switch (action) { 1521 case BUS_NOTIFY_BOUND_DRIVER: 1522 port->driver_bound = true; 1523 break; 1524 1525 case BUS_NOTIFY_UNBIND_DRIVER: 1526 port->driver_bound = false; 1527 break; 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int __init i8042_probe(struct platform_device *dev) 1534 { 1535 int error; 1536 1537 i8042_platform_device = dev; 1538 1539 if (i8042_reset == I8042_RESET_ALWAYS) { 1540 error = i8042_controller_selftest(); 1541 if (error) 1542 return error; 1543 } 1544 1545 error = i8042_controller_init(); 1546 if (error) 1547 return error; 1548 1549 #ifdef CONFIG_X86 1550 if (i8042_dritek) 1551 i8042_dritek_enable(); 1552 #endif 1553 1554 if (!i8042_noaux) { 1555 error = i8042_setup_aux(); 1556 if (error && error != -ENODEV && error != -EBUSY) 1557 goto out_fail; 1558 } 1559 1560 if (!i8042_nokbd) { 1561 error = i8042_setup_kbd(); 1562 if (error) 1563 goto out_fail; 1564 } 1565 /* 1566 * Ok, everything is ready, let's register all serio ports 1567 */ 1568 i8042_register_ports(); 1569 1570 return 0; 1571 1572 out_fail: 1573 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1574 i8042_free_irqs(); 1575 i8042_controller_reset(false); 1576 i8042_platform_device = NULL; 1577 1578 return error; 1579 } 1580 1581 static int i8042_remove(struct platform_device *dev) 1582 { 1583 i8042_unregister_ports(); 1584 i8042_free_irqs(); 1585 i8042_controller_reset(false); 1586 i8042_platform_device = NULL; 1587 1588 return 0; 1589 } 1590 1591 static struct platform_driver i8042_driver = { 1592 .driver = { 1593 .name = "i8042", 1594 #ifdef CONFIG_PM 1595 .pm = &i8042_pm_ops, 1596 #endif 1597 }, 1598 .remove = i8042_remove, 1599 .shutdown = i8042_shutdown, 1600 }; 1601 1602 static struct notifier_block i8042_kbd_bind_notifier_block = { 1603 .notifier_call = i8042_kbd_bind_notifier, 1604 }; 1605 1606 static int __init i8042_init(void) 1607 { 1608 struct platform_device *pdev; 1609 int err; 1610 1611 dbg_init(); 1612 1613 err = i8042_platform_init(); 1614 if (err) 1615 return err; 1616 1617 err = i8042_controller_check(); 1618 if (err) 1619 goto err_platform_exit; 1620 1621 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1622 if (IS_ERR(pdev)) { 1623 err = PTR_ERR(pdev); 1624 goto err_platform_exit; 1625 } 1626 1627 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1628 panic_blink = i8042_panic_blink; 1629 1630 return 0; 1631 1632 err_platform_exit: 1633 i8042_platform_exit(); 1634 return err; 1635 } 1636 1637 static void __exit i8042_exit(void) 1638 { 1639 platform_device_unregister(i8042_platform_device); 1640 platform_driver_unregister(&i8042_driver); 1641 i8042_platform_exit(); 1642 1643 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1644 panic_blink = NULL; 1645 } 1646 1647 module_init(i8042_init); 1648 module_exit(i8042_exit); 1649