1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/types.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/init.h> 21 #include <linux/serio.h> 22 #include <linux/err.h> 23 #include <linux/rcupdate.h> 24 #include <linux/platform_device.h> 25 #include <linux/i8042.h> 26 #include <linux/slab.h> 27 #include <linux/suspend.h> 28 29 #include <asm/io.h> 30 31 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 32 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 33 MODULE_LICENSE("GPL"); 34 35 static bool i8042_nokbd; 36 module_param_named(nokbd, i8042_nokbd, bool, 0); 37 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 38 39 static bool i8042_noaux; 40 module_param_named(noaux, i8042_noaux, bool, 0); 41 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 42 43 static bool i8042_nomux; 44 module_param_named(nomux, i8042_nomux, bool, 0); 45 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 46 47 static bool i8042_unlock; 48 module_param_named(unlock, i8042_unlock, bool, 0); 49 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 50 51 enum i8042_controller_reset_mode { 52 I8042_RESET_NEVER, 53 I8042_RESET_ALWAYS, 54 I8042_RESET_ON_S2RAM, 55 #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM 56 }; 57 static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT; 58 static int i8042_set_reset(const char *val, const struct kernel_param *kp) 59 { 60 enum i8042_controller_reset_mode *arg = kp->arg; 61 int error; 62 bool reset; 63 64 if (val) { 65 error = kstrtobool(val, &reset); 66 if (error) 67 return error; 68 } else { 69 reset = true; 70 } 71 72 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER; 73 return 0; 74 } 75 76 static const struct kernel_param_ops param_ops_reset_param = { 77 .flags = KERNEL_PARAM_OPS_FL_NOARG, 78 .set = i8042_set_reset, 79 }; 80 #define param_check_reset_param(name, p) \ 81 __param_check(name, p, enum i8042_controller_reset_mode) 82 module_param_named(reset, i8042_reset, reset_param, 0); 83 MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both"); 84 85 static bool i8042_direct; 86 module_param_named(direct, i8042_direct, bool, 0); 87 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 88 89 static bool i8042_dumbkbd; 90 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 91 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 92 93 static bool i8042_noloop; 94 module_param_named(noloop, i8042_noloop, bool, 0); 95 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 96 97 static bool i8042_notimeout; 98 module_param_named(notimeout, i8042_notimeout, bool, 0); 99 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 100 101 static bool i8042_kbdreset; 102 module_param_named(kbdreset, i8042_kbdreset, bool, 0); 103 MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); 104 105 #ifdef CONFIG_X86 106 static bool i8042_dritek; 107 module_param_named(dritek, i8042_dritek, bool, 0); 108 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 109 #endif 110 111 #ifdef CONFIG_PNP 112 static bool i8042_nopnp; 113 module_param_named(nopnp, i8042_nopnp, bool, 0); 114 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 115 #endif 116 117 #define DEBUG 118 #ifdef DEBUG 119 static bool i8042_debug; 120 module_param_named(debug, i8042_debug, bool, 0600); 121 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 122 123 static bool i8042_unmask_kbd_data; 124 module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); 125 MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); 126 #endif 127 128 static bool i8042_bypass_aux_irq_test; 129 static char i8042_kbd_firmware_id[128]; 130 static char i8042_aux_firmware_id[128]; 131 132 #include "i8042.h" 133 134 /* 135 * i8042_lock protects serialization between i8042_command and 136 * the interrupt handler. 137 */ 138 static DEFINE_SPINLOCK(i8042_lock); 139 140 /* 141 * Writers to AUX and KBD ports as well as users issuing i8042_command 142 * directly should acquire i8042_mutex (by means of calling 143 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 144 * they do not disturb each other (unfortunately in many i8042 145 * implementations write to one of the ports will immediately abort 146 * command that is being processed by another port). 147 */ 148 static DEFINE_MUTEX(i8042_mutex); 149 150 struct i8042_port { 151 struct serio *serio; 152 int irq; 153 bool exists; 154 bool driver_bound; 155 signed char mux; 156 }; 157 158 #define I8042_KBD_PORT_NO 0 159 #define I8042_AUX_PORT_NO 1 160 #define I8042_MUX_PORT_NO 2 161 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 162 163 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 164 165 static unsigned char i8042_initial_ctr; 166 static unsigned char i8042_ctr; 167 static bool i8042_mux_present; 168 static bool i8042_kbd_irq_registered; 169 static bool i8042_aux_irq_registered; 170 static unsigned char i8042_suppress_kbd_ack; 171 static struct platform_device *i8042_platform_device; 172 static struct notifier_block i8042_kbd_bind_notifier_block; 173 174 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 175 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 176 struct serio *serio); 177 178 void i8042_lock_chip(void) 179 { 180 mutex_lock(&i8042_mutex); 181 } 182 EXPORT_SYMBOL(i8042_lock_chip); 183 184 void i8042_unlock_chip(void) 185 { 186 mutex_unlock(&i8042_mutex); 187 } 188 EXPORT_SYMBOL(i8042_unlock_chip); 189 190 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 191 struct serio *serio)) 192 { 193 unsigned long flags; 194 int ret = 0; 195 196 spin_lock_irqsave(&i8042_lock, flags); 197 198 if (i8042_platform_filter) { 199 ret = -EBUSY; 200 goto out; 201 } 202 203 i8042_platform_filter = filter; 204 205 out: 206 spin_unlock_irqrestore(&i8042_lock, flags); 207 return ret; 208 } 209 EXPORT_SYMBOL(i8042_install_filter); 210 211 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 212 struct serio *port)) 213 { 214 unsigned long flags; 215 int ret = 0; 216 217 spin_lock_irqsave(&i8042_lock, flags); 218 219 if (i8042_platform_filter != filter) { 220 ret = -EINVAL; 221 goto out; 222 } 223 224 i8042_platform_filter = NULL; 225 226 out: 227 spin_unlock_irqrestore(&i8042_lock, flags); 228 return ret; 229 } 230 EXPORT_SYMBOL(i8042_remove_filter); 231 232 /* 233 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 234 * be ready for reading values from it / writing values to it. 235 * Called always with i8042_lock held. 236 */ 237 238 static int i8042_wait_read(void) 239 { 240 int i = 0; 241 242 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 243 udelay(50); 244 i++; 245 } 246 return -(i == I8042_CTL_TIMEOUT); 247 } 248 249 static int i8042_wait_write(void) 250 { 251 int i = 0; 252 253 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 254 udelay(50); 255 i++; 256 } 257 return -(i == I8042_CTL_TIMEOUT); 258 } 259 260 /* 261 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 262 * of the i8042 down the toilet. 263 */ 264 265 static int i8042_flush(void) 266 { 267 unsigned long flags; 268 unsigned char data, str; 269 int count = 0; 270 int retval = 0; 271 272 spin_lock_irqsave(&i8042_lock, flags); 273 274 while ((str = i8042_read_status()) & I8042_STR_OBF) { 275 if (count++ < I8042_BUFFER_SIZE) { 276 udelay(50); 277 data = i8042_read_data(); 278 dbg("%02x <- i8042 (flush, %s)\n", 279 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 280 } else { 281 retval = -EIO; 282 break; 283 } 284 } 285 286 spin_unlock_irqrestore(&i8042_lock, flags); 287 288 return retval; 289 } 290 291 /* 292 * i8042_command() executes a command on the i8042. It also sends the input 293 * parameter(s) of the commands to it, and receives the output value(s). The 294 * parameters are to be stored in the param array, and the output is placed 295 * into the same array. The number of the parameters and output values is 296 * encoded in bits 8-11 of the command number. 297 */ 298 299 static int __i8042_command(unsigned char *param, int command) 300 { 301 int i, error; 302 303 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 304 return -1; 305 306 error = i8042_wait_write(); 307 if (error) 308 return error; 309 310 dbg("%02x -> i8042 (command)\n", command & 0xff); 311 i8042_write_command(command & 0xff); 312 313 for (i = 0; i < ((command >> 12) & 0xf); i++) { 314 error = i8042_wait_write(); 315 if (error) { 316 dbg(" -- i8042 (wait write timeout)\n"); 317 return error; 318 } 319 dbg("%02x -> i8042 (parameter)\n", param[i]); 320 i8042_write_data(param[i]); 321 } 322 323 for (i = 0; i < ((command >> 8) & 0xf); i++) { 324 error = i8042_wait_read(); 325 if (error) { 326 dbg(" -- i8042 (wait read timeout)\n"); 327 return error; 328 } 329 330 if (command == I8042_CMD_AUX_LOOP && 331 !(i8042_read_status() & I8042_STR_AUXDATA)) { 332 dbg(" -- i8042 (auxerr)\n"); 333 return -1; 334 } 335 336 param[i] = i8042_read_data(); 337 dbg("%02x <- i8042 (return)\n", param[i]); 338 } 339 340 return 0; 341 } 342 343 int i8042_command(unsigned char *param, int command) 344 { 345 unsigned long flags; 346 int retval; 347 348 spin_lock_irqsave(&i8042_lock, flags); 349 retval = __i8042_command(param, command); 350 spin_unlock_irqrestore(&i8042_lock, flags); 351 352 return retval; 353 } 354 EXPORT_SYMBOL(i8042_command); 355 356 /* 357 * i8042_kbd_write() sends a byte out through the keyboard interface. 358 */ 359 360 static int i8042_kbd_write(struct serio *port, unsigned char c) 361 { 362 unsigned long flags; 363 int retval = 0; 364 365 spin_lock_irqsave(&i8042_lock, flags); 366 367 if (!(retval = i8042_wait_write())) { 368 dbg("%02x -> i8042 (kbd-data)\n", c); 369 i8042_write_data(c); 370 } 371 372 spin_unlock_irqrestore(&i8042_lock, flags); 373 374 return retval; 375 } 376 377 /* 378 * i8042_aux_write() sends a byte out through the aux interface. 379 */ 380 381 static int i8042_aux_write(struct serio *serio, unsigned char c) 382 { 383 struct i8042_port *port = serio->port_data; 384 385 return i8042_command(&c, port->mux == -1 ? 386 I8042_CMD_AUX_SEND : 387 I8042_CMD_MUX_SEND + port->mux); 388 } 389 390 391 /* 392 * i8042_port_close attempts to clear AUX or KBD port state by disabling 393 * and then re-enabling it. 394 */ 395 396 static void i8042_port_close(struct serio *serio) 397 { 398 int irq_bit; 399 int disable_bit; 400 const char *port_name; 401 402 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 403 irq_bit = I8042_CTR_AUXINT; 404 disable_bit = I8042_CTR_AUXDIS; 405 port_name = "AUX"; 406 } else { 407 irq_bit = I8042_CTR_KBDINT; 408 disable_bit = I8042_CTR_KBDDIS; 409 port_name = "KBD"; 410 } 411 412 i8042_ctr &= ~irq_bit; 413 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 414 pr_warn("Can't write CTR while closing %s port\n", port_name); 415 416 udelay(50); 417 418 i8042_ctr &= ~disable_bit; 419 i8042_ctr |= irq_bit; 420 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 421 pr_err("Can't reactivate %s port\n", port_name); 422 423 /* 424 * See if there is any data appeared while we were messing with 425 * port state. 426 */ 427 i8042_interrupt(0, NULL); 428 } 429 430 /* 431 * i8042_start() is called by serio core when port is about to finish 432 * registering. It will mark port as existing so i8042_interrupt can 433 * start sending data through it. 434 */ 435 static int i8042_start(struct serio *serio) 436 { 437 struct i8042_port *port = serio->port_data; 438 439 spin_lock_irq(&i8042_lock); 440 port->exists = true; 441 spin_unlock_irq(&i8042_lock); 442 443 return 0; 444 } 445 446 /* 447 * i8042_stop() marks serio port as non-existing so i8042_interrupt 448 * will not try to send data to the port that is about to go away. 449 * The function is called by serio core as part of unregister procedure. 450 */ 451 static void i8042_stop(struct serio *serio) 452 { 453 struct i8042_port *port = serio->port_data; 454 455 spin_lock_irq(&i8042_lock); 456 port->exists = false; 457 port->serio = NULL; 458 spin_unlock_irq(&i8042_lock); 459 460 /* 461 * We need to make sure that interrupt handler finishes using 462 * our serio port before we return from this function. 463 * We synchronize with both AUX and KBD IRQs because there is 464 * a (very unlikely) chance that AUX IRQ is raised for KBD port 465 * and vice versa. 466 */ 467 synchronize_irq(I8042_AUX_IRQ); 468 synchronize_irq(I8042_KBD_IRQ); 469 } 470 471 /* 472 * i8042_filter() filters out unwanted bytes from the input data stream. 473 * It is called from i8042_interrupt and thus is running with interrupts 474 * off and i8042_lock held. 475 */ 476 static bool i8042_filter(unsigned char data, unsigned char str, 477 struct serio *serio) 478 { 479 if (unlikely(i8042_suppress_kbd_ack)) { 480 if ((~str & I8042_STR_AUXDATA) && 481 (data == 0xfa || data == 0xfe)) { 482 i8042_suppress_kbd_ack--; 483 dbg("Extra keyboard ACK - filtered out\n"); 484 return true; 485 } 486 } 487 488 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 489 dbg("Filtered out by platform filter\n"); 490 return true; 491 } 492 493 return false; 494 } 495 496 /* 497 * i8042_interrupt() is the most important function in this driver - 498 * it handles the interrupts from the i8042, and sends incoming bytes 499 * to the upper layers. 500 */ 501 502 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 503 { 504 struct i8042_port *port; 505 struct serio *serio; 506 unsigned long flags; 507 unsigned char str, data; 508 unsigned int dfl; 509 unsigned int port_no; 510 bool filtered; 511 int ret = 1; 512 513 spin_lock_irqsave(&i8042_lock, flags); 514 515 str = i8042_read_status(); 516 if (unlikely(~str & I8042_STR_OBF)) { 517 spin_unlock_irqrestore(&i8042_lock, flags); 518 if (irq) 519 dbg("Interrupt %d, without any data\n", irq); 520 ret = 0; 521 goto out; 522 } 523 524 data = i8042_read_data(); 525 526 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 527 static unsigned long last_transmit; 528 static unsigned char last_str; 529 530 dfl = 0; 531 if (str & I8042_STR_MUXERR) { 532 dbg("MUX error, status is %02x, data is %02x\n", 533 str, data); 534 /* 535 * When MUXERR condition is signalled the data register can only contain 536 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 537 * it is not always the case. Some KBCs also report 0xfc when there is 538 * nothing connected to the port while others sometimes get confused which 539 * port the data came from and signal error leaving the data intact. They 540 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 541 * to legacy mode yet, when we see one we'll add proper handling). 542 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 543 * rest assume that the data came from the same serio last byte 544 * was transmitted (if transmission happened not too long ago). 545 */ 546 547 switch (data) { 548 default: 549 if (time_before(jiffies, last_transmit + HZ/10)) { 550 str = last_str; 551 break; 552 } 553 /* fall through - report timeout */ 554 case 0xfc: 555 case 0xfd: 556 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 557 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 558 } 559 } 560 561 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 562 last_str = str; 563 last_transmit = jiffies; 564 } else { 565 566 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 567 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); 568 569 port_no = (str & I8042_STR_AUXDATA) ? 570 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 571 } 572 573 port = &i8042_ports[port_no]; 574 serio = port->exists ? port->serio : NULL; 575 576 if (irq && serio) 577 pm_wakeup_event(&serio->dev, 0); 578 579 filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n", 580 port_no, irq, 581 dfl & SERIO_PARITY ? ", bad parity" : "", 582 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 583 584 filtered = i8042_filter(data, str, serio); 585 586 spin_unlock_irqrestore(&i8042_lock, flags); 587 588 if (likely(serio && !filtered)) 589 serio_interrupt(serio, data, dfl); 590 591 out: 592 return IRQ_RETVAL(ret); 593 } 594 595 /* 596 * i8042_enable_kbd_port enables keyboard port on chip 597 */ 598 599 static int i8042_enable_kbd_port(void) 600 { 601 i8042_ctr &= ~I8042_CTR_KBDDIS; 602 i8042_ctr |= I8042_CTR_KBDINT; 603 604 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 605 i8042_ctr &= ~I8042_CTR_KBDINT; 606 i8042_ctr |= I8042_CTR_KBDDIS; 607 pr_err("Failed to enable KBD port\n"); 608 return -EIO; 609 } 610 611 return 0; 612 } 613 614 /* 615 * i8042_enable_aux_port enables AUX (mouse) port on chip 616 */ 617 618 static int i8042_enable_aux_port(void) 619 { 620 i8042_ctr &= ~I8042_CTR_AUXDIS; 621 i8042_ctr |= I8042_CTR_AUXINT; 622 623 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 624 i8042_ctr &= ~I8042_CTR_AUXINT; 625 i8042_ctr |= I8042_CTR_AUXDIS; 626 pr_err("Failed to enable AUX port\n"); 627 return -EIO; 628 } 629 630 return 0; 631 } 632 633 /* 634 * i8042_enable_mux_ports enables 4 individual AUX ports after 635 * the controller has been switched into Multiplexed mode 636 */ 637 638 static int i8042_enable_mux_ports(void) 639 { 640 unsigned char param; 641 int i; 642 643 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 644 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 645 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 646 } 647 648 return i8042_enable_aux_port(); 649 } 650 651 /* 652 * i8042_set_mux_mode checks whether the controller has an 653 * active multiplexor and puts the chip into Multiplexed (true) 654 * or Legacy (false) mode. 655 */ 656 657 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 658 { 659 660 unsigned char param, val; 661 /* 662 * Get rid of bytes in the queue. 663 */ 664 665 i8042_flush(); 666 667 /* 668 * Internal loopback test - send three bytes, they should come back from the 669 * mouse interface, the last should be version. 670 */ 671 672 param = val = 0xf0; 673 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 674 return -1; 675 param = val = multiplex ? 0x56 : 0xf6; 676 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 677 return -1; 678 param = val = multiplex ? 0xa4 : 0xa5; 679 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 680 return -1; 681 682 /* 683 * Workaround for interference with USB Legacy emulation 684 * that causes a v10.12 MUX to be found. 685 */ 686 if (param == 0xac) 687 return -1; 688 689 if (mux_version) 690 *mux_version = param; 691 692 return 0; 693 } 694 695 /* 696 * i8042_check_mux() checks whether the controller supports the PS/2 Active 697 * Multiplexing specification by Synaptics, Phoenix, Insyde and 698 * LCS/Telegraphics. 699 */ 700 701 static int __init i8042_check_mux(void) 702 { 703 unsigned char mux_version; 704 705 if (i8042_set_mux_mode(true, &mux_version)) 706 return -1; 707 708 pr_info("Detected active multiplexing controller, rev %d.%d\n", 709 (mux_version >> 4) & 0xf, mux_version & 0xf); 710 711 /* 712 * Disable all muxed ports by disabling AUX. 713 */ 714 i8042_ctr |= I8042_CTR_AUXDIS; 715 i8042_ctr &= ~I8042_CTR_AUXINT; 716 717 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 718 pr_err("Failed to disable AUX port, can't use MUX\n"); 719 return -EIO; 720 } 721 722 i8042_mux_present = true; 723 724 return 0; 725 } 726 727 /* 728 * The following is used to test AUX IRQ delivery. 729 */ 730 static struct completion i8042_aux_irq_delivered __initdata; 731 static bool i8042_irq_being_tested __initdata; 732 733 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 734 { 735 unsigned long flags; 736 unsigned char str, data; 737 int ret = 0; 738 739 spin_lock_irqsave(&i8042_lock, flags); 740 str = i8042_read_status(); 741 if (str & I8042_STR_OBF) { 742 data = i8042_read_data(); 743 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 744 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 745 if (i8042_irq_being_tested && 746 data == 0xa5 && (str & I8042_STR_AUXDATA)) 747 complete(&i8042_aux_irq_delivered); 748 ret = 1; 749 } 750 spin_unlock_irqrestore(&i8042_lock, flags); 751 752 return IRQ_RETVAL(ret); 753 } 754 755 /* 756 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 757 * verifies success by readinng CTR. Used when testing for presence of AUX 758 * port. 759 */ 760 static int __init i8042_toggle_aux(bool on) 761 { 762 unsigned char param; 763 int i; 764 765 if (i8042_command(¶m, 766 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 767 return -1; 768 769 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 770 for (i = 0; i < 100; i++) { 771 udelay(50); 772 773 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 774 return -1; 775 776 if (!(param & I8042_CTR_AUXDIS) == on) 777 return 0; 778 } 779 780 return -1; 781 } 782 783 /* 784 * i8042_check_aux() applies as much paranoia as it can at detecting 785 * the presence of an AUX interface. 786 */ 787 788 static int __init i8042_check_aux(void) 789 { 790 int retval = -1; 791 bool irq_registered = false; 792 bool aux_loop_broken = false; 793 unsigned long flags; 794 unsigned char param; 795 796 /* 797 * Get rid of bytes in the queue. 798 */ 799 800 i8042_flush(); 801 802 /* 803 * Internal loopback test - filters out AT-type i8042's. Unfortunately 804 * SiS screwed up and their 5597 doesn't support the LOOP command even 805 * though it has an AUX port. 806 */ 807 808 param = 0x5a; 809 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 810 if (retval || param != 0x5a) { 811 812 /* 813 * External connection test - filters out AT-soldered PS/2 i8042's 814 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 815 * 0xfa - no error on some notebooks which ignore the spec 816 * Because it's common for chipsets to return error on perfectly functioning 817 * AUX ports, we test for this only when the LOOP command failed. 818 */ 819 820 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 821 (param && param != 0xfa && param != 0xff)) 822 return -1; 823 824 /* 825 * If AUX_LOOP completed without error but returned unexpected data 826 * mark it as broken 827 */ 828 if (!retval) 829 aux_loop_broken = true; 830 } 831 832 /* 833 * Bit assignment test - filters out PS/2 i8042's in AT mode 834 */ 835 836 if (i8042_toggle_aux(false)) { 837 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 838 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 839 } 840 841 if (i8042_toggle_aux(true)) 842 return -1; 843 844 /* 845 * Reset keyboard (needed on some laptops to successfully detect 846 * touchpad, e.g., some Gigabyte laptop models with Elantech 847 * touchpads). 848 */ 849 if (i8042_kbdreset) { 850 pr_warn("Attempting to reset device connected to KBD port\n"); 851 i8042_kbd_write(NULL, (unsigned char) 0xff); 852 } 853 854 /* 855 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 856 * used it for a PCI card or somethig else. 857 */ 858 859 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 860 /* 861 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 862 * is working and hope we are right. 863 */ 864 retval = 0; 865 goto out; 866 } 867 868 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 869 "i8042", i8042_platform_device)) 870 goto out; 871 872 irq_registered = true; 873 874 if (i8042_enable_aux_port()) 875 goto out; 876 877 spin_lock_irqsave(&i8042_lock, flags); 878 879 init_completion(&i8042_aux_irq_delivered); 880 i8042_irq_being_tested = true; 881 882 param = 0xa5; 883 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 884 885 spin_unlock_irqrestore(&i8042_lock, flags); 886 887 if (retval) 888 goto out; 889 890 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 891 msecs_to_jiffies(250)) == 0) { 892 /* 893 * AUX IRQ was never delivered so we need to flush the controller to 894 * get rid of the byte we put there; otherwise keyboard may not work. 895 */ 896 dbg(" -- i8042 (aux irq test timeout)\n"); 897 i8042_flush(); 898 retval = -1; 899 } 900 901 out: 902 903 /* 904 * Disable the interface. 905 */ 906 907 i8042_ctr |= I8042_CTR_AUXDIS; 908 i8042_ctr &= ~I8042_CTR_AUXINT; 909 910 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 911 retval = -1; 912 913 if (irq_registered) 914 free_irq(I8042_AUX_IRQ, i8042_platform_device); 915 916 return retval; 917 } 918 919 static int i8042_controller_check(void) 920 { 921 if (i8042_flush()) { 922 pr_info("No controller found\n"); 923 return -ENODEV; 924 } 925 926 return 0; 927 } 928 929 static int i8042_controller_selftest(void) 930 { 931 unsigned char param; 932 int i = 0; 933 934 /* 935 * We try this 5 times; on some really fragile systems this does not 936 * take the first time... 937 */ 938 do { 939 940 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 941 pr_err("i8042 controller selftest timeout\n"); 942 return -ENODEV; 943 } 944 945 if (param == I8042_RET_CTL_TEST) 946 return 0; 947 948 dbg("i8042 controller selftest: %#x != %#x\n", 949 param, I8042_RET_CTL_TEST); 950 msleep(50); 951 } while (i++ < 5); 952 953 #ifdef CONFIG_X86 954 /* 955 * On x86, we don't fail entire i8042 initialization if controller 956 * reset fails in hopes that keyboard port will still be functional 957 * and user will still get a working keyboard. This is especially 958 * important on netbooks. On other arches we trust hardware more. 959 */ 960 pr_info("giving up on controller selftest, continuing anyway...\n"); 961 return 0; 962 #else 963 pr_err("i8042 controller selftest failed\n"); 964 return -EIO; 965 #endif 966 } 967 968 /* 969 * i8042_controller init initializes the i8042 controller, and, 970 * most importantly, sets it into non-xlated mode if that's 971 * desired. 972 */ 973 974 static int i8042_controller_init(void) 975 { 976 unsigned long flags; 977 int n = 0; 978 unsigned char ctr[2]; 979 980 /* 981 * Save the CTR for restore on unload / reboot. 982 */ 983 984 do { 985 if (n >= 10) { 986 pr_err("Unable to get stable CTR read\n"); 987 return -EIO; 988 } 989 990 if (n != 0) 991 udelay(50); 992 993 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 994 pr_err("Can't read CTR while initializing i8042\n"); 995 return -EIO; 996 } 997 998 } while (n < 2 || ctr[0] != ctr[1]); 999 1000 i8042_initial_ctr = i8042_ctr = ctr[0]; 1001 1002 /* 1003 * Disable the keyboard interface and interrupt. 1004 */ 1005 1006 i8042_ctr |= I8042_CTR_KBDDIS; 1007 i8042_ctr &= ~I8042_CTR_KBDINT; 1008 1009 /* 1010 * Handle keylock. 1011 */ 1012 1013 spin_lock_irqsave(&i8042_lock, flags); 1014 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 1015 if (i8042_unlock) 1016 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 1017 else 1018 pr_warn("Warning: Keylock active\n"); 1019 } 1020 spin_unlock_irqrestore(&i8042_lock, flags); 1021 1022 /* 1023 * If the chip is configured into nontranslated mode by the BIOS, don't 1024 * bother enabling translating and be happy. 1025 */ 1026 1027 if (~i8042_ctr & I8042_CTR_XLATE) 1028 i8042_direct = true; 1029 1030 /* 1031 * Set nontranslated mode for the kbd interface if requested by an option. 1032 * After this the kbd interface becomes a simple serial in/out, like the aux 1033 * interface is. We don't do this by default, since it can confuse notebook 1034 * BIOSes. 1035 */ 1036 1037 if (i8042_direct) 1038 i8042_ctr &= ~I8042_CTR_XLATE; 1039 1040 /* 1041 * Write CTR back. 1042 */ 1043 1044 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1045 pr_err("Can't write CTR while initializing i8042\n"); 1046 return -EIO; 1047 } 1048 1049 /* 1050 * Flush whatever accumulated while we were disabling keyboard port. 1051 */ 1052 1053 i8042_flush(); 1054 1055 return 0; 1056 } 1057 1058 1059 /* 1060 * Reset the controller and reset CRT to the original value set by BIOS. 1061 */ 1062 1063 static void i8042_controller_reset(bool s2r_wants_reset) 1064 { 1065 i8042_flush(); 1066 1067 /* 1068 * Disable both KBD and AUX interfaces so they don't get in the way 1069 */ 1070 1071 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1072 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1073 1074 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1075 pr_warn("Can't write CTR while resetting\n"); 1076 1077 /* 1078 * Disable MUX mode if present. 1079 */ 1080 1081 if (i8042_mux_present) 1082 i8042_set_mux_mode(false, NULL); 1083 1084 /* 1085 * Reset the controller if requested. 1086 */ 1087 1088 if (i8042_reset == I8042_RESET_ALWAYS || 1089 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1090 i8042_controller_selftest(); 1091 } 1092 1093 /* 1094 * Restore the original control register setting. 1095 */ 1096 1097 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1098 pr_warn("Can't restore CTR\n"); 1099 } 1100 1101 1102 /* 1103 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1104 * when kernel panics. Flashing LEDs is useful for users running X who may 1105 * not see the console and will help distinguishing panics from "real" 1106 * lockups. 1107 * 1108 * Note that DELAY has a limit of 10ms so we will not get stuck here 1109 * waiting for KBC to free up even if KBD interrupt is off 1110 */ 1111 1112 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1113 1114 static long i8042_panic_blink(int state) 1115 { 1116 long delay = 0; 1117 char led; 1118 1119 led = (state) ? 0x01 | 0x04 : 0; 1120 while (i8042_read_status() & I8042_STR_IBF) 1121 DELAY; 1122 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1123 i8042_suppress_kbd_ack = 2; 1124 i8042_write_data(0xed); /* set leds */ 1125 DELAY; 1126 while (i8042_read_status() & I8042_STR_IBF) 1127 DELAY; 1128 DELAY; 1129 dbg("%02x -> i8042 (panic blink)\n", led); 1130 i8042_write_data(led); 1131 DELAY; 1132 return delay; 1133 } 1134 1135 #undef DELAY 1136 1137 #ifdef CONFIG_X86 1138 static void i8042_dritek_enable(void) 1139 { 1140 unsigned char param = 0x90; 1141 int error; 1142 1143 error = i8042_command(¶m, 0x1059); 1144 if (error) 1145 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1146 } 1147 #endif 1148 1149 #ifdef CONFIG_PM 1150 1151 /* 1152 * Here we try to reset everything back to a state we had 1153 * before suspending. 1154 */ 1155 1156 static int i8042_controller_resume(bool s2r_wants_reset) 1157 { 1158 int error; 1159 1160 error = i8042_controller_check(); 1161 if (error) 1162 return error; 1163 1164 if (i8042_reset == I8042_RESET_ALWAYS || 1165 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1166 error = i8042_controller_selftest(); 1167 if (error) 1168 return error; 1169 } 1170 1171 /* 1172 * Restore original CTR value and disable all ports 1173 */ 1174 1175 i8042_ctr = i8042_initial_ctr; 1176 if (i8042_direct) 1177 i8042_ctr &= ~I8042_CTR_XLATE; 1178 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1179 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1180 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1181 pr_warn("Can't write CTR to resume, retrying...\n"); 1182 msleep(50); 1183 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1184 pr_err("CTR write retry failed\n"); 1185 return -EIO; 1186 } 1187 } 1188 1189 1190 #ifdef CONFIG_X86 1191 if (i8042_dritek) 1192 i8042_dritek_enable(); 1193 #endif 1194 1195 if (i8042_mux_present) { 1196 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1197 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1198 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1199 i8042_enable_aux_port(); 1200 1201 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1202 i8042_enable_kbd_port(); 1203 1204 i8042_interrupt(0, NULL); 1205 1206 return 0; 1207 } 1208 1209 /* 1210 * Here we try to restore the original BIOS settings to avoid 1211 * upsetting it. 1212 */ 1213 1214 static int i8042_pm_suspend(struct device *dev) 1215 { 1216 int i; 1217 1218 if (pm_suspend_via_firmware()) 1219 i8042_controller_reset(true); 1220 1221 /* Set up serio interrupts for system wakeup. */ 1222 for (i = 0; i < I8042_NUM_PORTS; i++) { 1223 struct serio *serio = i8042_ports[i].serio; 1224 1225 if (serio && device_may_wakeup(&serio->dev)) 1226 enable_irq_wake(i8042_ports[i].irq); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int i8042_pm_resume_noirq(struct device *dev) 1233 { 1234 if (!pm_resume_via_firmware()) 1235 i8042_interrupt(0, NULL); 1236 1237 return 0; 1238 } 1239 1240 static int i8042_pm_resume(struct device *dev) 1241 { 1242 bool want_reset; 1243 int i; 1244 1245 for (i = 0; i < I8042_NUM_PORTS; i++) { 1246 struct serio *serio = i8042_ports[i].serio; 1247 1248 if (serio && device_may_wakeup(&serio->dev)) 1249 disable_irq_wake(i8042_ports[i].irq); 1250 } 1251 1252 /* 1253 * If platform firmware was not going to be involved in suspend, we did 1254 * not restore the controller state to whatever it had been at boot 1255 * time, so we do not need to do anything. 1256 */ 1257 if (!pm_suspend_via_firmware()) 1258 return 0; 1259 1260 /* 1261 * We only need to reset the controller if we are resuming after handing 1262 * off control to the platform firmware, otherwise we can simply restore 1263 * the mode. 1264 */ 1265 want_reset = pm_resume_via_firmware(); 1266 1267 return i8042_controller_resume(want_reset); 1268 } 1269 1270 static int i8042_pm_thaw(struct device *dev) 1271 { 1272 i8042_interrupt(0, NULL); 1273 1274 return 0; 1275 } 1276 1277 static int i8042_pm_reset(struct device *dev) 1278 { 1279 i8042_controller_reset(false); 1280 1281 return 0; 1282 } 1283 1284 static int i8042_pm_restore(struct device *dev) 1285 { 1286 return i8042_controller_resume(false); 1287 } 1288 1289 static const struct dev_pm_ops i8042_pm_ops = { 1290 .suspend = i8042_pm_suspend, 1291 .resume_noirq = i8042_pm_resume_noirq, 1292 .resume = i8042_pm_resume, 1293 .thaw = i8042_pm_thaw, 1294 .poweroff = i8042_pm_reset, 1295 .restore = i8042_pm_restore, 1296 }; 1297 1298 #endif /* CONFIG_PM */ 1299 1300 /* 1301 * We need to reset the 8042 back to original mode on system shutdown, 1302 * because otherwise BIOSes will be confused. 1303 */ 1304 1305 static void i8042_shutdown(struct platform_device *dev) 1306 { 1307 i8042_controller_reset(false); 1308 } 1309 1310 static int __init i8042_create_kbd_port(void) 1311 { 1312 struct serio *serio; 1313 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1314 1315 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1316 if (!serio) 1317 return -ENOMEM; 1318 1319 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1320 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1321 serio->start = i8042_start; 1322 serio->stop = i8042_stop; 1323 serio->close = i8042_port_close; 1324 serio->ps2_cmd_mutex = &i8042_mutex; 1325 serio->port_data = port; 1326 serio->dev.parent = &i8042_platform_device->dev; 1327 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1328 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1329 strlcpy(serio->firmware_id, i8042_kbd_firmware_id, 1330 sizeof(serio->firmware_id)); 1331 1332 port->serio = serio; 1333 port->irq = I8042_KBD_IRQ; 1334 1335 return 0; 1336 } 1337 1338 static int __init i8042_create_aux_port(int idx) 1339 { 1340 struct serio *serio; 1341 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1342 struct i8042_port *port = &i8042_ports[port_no]; 1343 1344 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1345 if (!serio) 1346 return -ENOMEM; 1347 1348 serio->id.type = SERIO_8042; 1349 serio->write = i8042_aux_write; 1350 serio->start = i8042_start; 1351 serio->stop = i8042_stop; 1352 serio->ps2_cmd_mutex = &i8042_mutex; 1353 serio->port_data = port; 1354 serio->dev.parent = &i8042_platform_device->dev; 1355 if (idx < 0) { 1356 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1357 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1358 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1359 sizeof(serio->firmware_id)); 1360 serio->close = i8042_port_close; 1361 } else { 1362 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1363 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1364 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1365 sizeof(serio->firmware_id)); 1366 } 1367 1368 port->serio = serio; 1369 port->mux = idx; 1370 port->irq = I8042_AUX_IRQ; 1371 1372 return 0; 1373 } 1374 1375 static void __init i8042_free_kbd_port(void) 1376 { 1377 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1378 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1379 } 1380 1381 static void __init i8042_free_aux_ports(void) 1382 { 1383 int i; 1384 1385 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1386 kfree(i8042_ports[i].serio); 1387 i8042_ports[i].serio = NULL; 1388 } 1389 } 1390 1391 static void __init i8042_register_ports(void) 1392 { 1393 int i; 1394 1395 for (i = 0; i < I8042_NUM_PORTS; i++) { 1396 struct serio *serio = i8042_ports[i].serio; 1397 1398 if (!serio) 1399 continue; 1400 1401 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1402 serio->name, 1403 (unsigned long) I8042_DATA_REG, 1404 (unsigned long) I8042_COMMAND_REG, 1405 i8042_ports[i].irq); 1406 serio_register_port(serio); 1407 device_set_wakeup_capable(&serio->dev, true); 1408 1409 /* 1410 * On platforms using suspend-to-idle, allow the keyboard to 1411 * wake up the system from sleep by enabling keyboard wakeups 1412 * by default. This is consistent with keyboard wakeup 1413 * behavior on many platforms using suspend-to-RAM (ACPI S3) 1414 * by default. 1415 */ 1416 if (pm_suspend_via_s2idle() && i == I8042_KBD_PORT_NO) 1417 device_set_wakeup_enable(&serio->dev, true); 1418 } 1419 } 1420 1421 static void i8042_unregister_ports(void) 1422 { 1423 int i; 1424 1425 for (i = 0; i < I8042_NUM_PORTS; i++) { 1426 if (i8042_ports[i].serio) { 1427 serio_unregister_port(i8042_ports[i].serio); 1428 i8042_ports[i].serio = NULL; 1429 } 1430 } 1431 } 1432 1433 static void i8042_free_irqs(void) 1434 { 1435 if (i8042_aux_irq_registered) 1436 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1437 if (i8042_kbd_irq_registered) 1438 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1439 1440 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1441 } 1442 1443 static int __init i8042_setup_aux(void) 1444 { 1445 int (*aux_enable)(void); 1446 int error; 1447 int i; 1448 1449 if (i8042_check_aux()) 1450 return -ENODEV; 1451 1452 if (i8042_nomux || i8042_check_mux()) { 1453 error = i8042_create_aux_port(-1); 1454 if (error) 1455 goto err_free_ports; 1456 aux_enable = i8042_enable_aux_port; 1457 } else { 1458 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1459 error = i8042_create_aux_port(i); 1460 if (error) 1461 goto err_free_ports; 1462 } 1463 aux_enable = i8042_enable_mux_ports; 1464 } 1465 1466 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1467 "i8042", i8042_platform_device); 1468 if (error) 1469 goto err_free_ports; 1470 1471 if (aux_enable()) 1472 goto err_free_irq; 1473 1474 i8042_aux_irq_registered = true; 1475 return 0; 1476 1477 err_free_irq: 1478 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1479 err_free_ports: 1480 i8042_free_aux_ports(); 1481 return error; 1482 } 1483 1484 static int __init i8042_setup_kbd(void) 1485 { 1486 int error; 1487 1488 error = i8042_create_kbd_port(); 1489 if (error) 1490 return error; 1491 1492 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1493 "i8042", i8042_platform_device); 1494 if (error) 1495 goto err_free_port; 1496 1497 error = i8042_enable_kbd_port(); 1498 if (error) 1499 goto err_free_irq; 1500 1501 i8042_kbd_irq_registered = true; 1502 return 0; 1503 1504 err_free_irq: 1505 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1506 err_free_port: 1507 i8042_free_kbd_port(); 1508 return error; 1509 } 1510 1511 static int i8042_kbd_bind_notifier(struct notifier_block *nb, 1512 unsigned long action, void *data) 1513 { 1514 struct device *dev = data; 1515 struct serio *serio = to_serio_port(dev); 1516 struct i8042_port *port = serio->port_data; 1517 1518 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) 1519 return 0; 1520 1521 switch (action) { 1522 case BUS_NOTIFY_BOUND_DRIVER: 1523 port->driver_bound = true; 1524 break; 1525 1526 case BUS_NOTIFY_UNBIND_DRIVER: 1527 port->driver_bound = false; 1528 break; 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int __init i8042_probe(struct platform_device *dev) 1535 { 1536 int error; 1537 1538 i8042_platform_device = dev; 1539 1540 if (i8042_reset == I8042_RESET_ALWAYS) { 1541 error = i8042_controller_selftest(); 1542 if (error) 1543 return error; 1544 } 1545 1546 error = i8042_controller_init(); 1547 if (error) 1548 return error; 1549 1550 #ifdef CONFIG_X86 1551 if (i8042_dritek) 1552 i8042_dritek_enable(); 1553 #endif 1554 1555 if (!i8042_noaux) { 1556 error = i8042_setup_aux(); 1557 if (error && error != -ENODEV && error != -EBUSY) 1558 goto out_fail; 1559 } 1560 1561 if (!i8042_nokbd) { 1562 error = i8042_setup_kbd(); 1563 if (error) 1564 goto out_fail; 1565 } 1566 /* 1567 * Ok, everything is ready, let's register all serio ports 1568 */ 1569 i8042_register_ports(); 1570 1571 return 0; 1572 1573 out_fail: 1574 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1575 i8042_free_irqs(); 1576 i8042_controller_reset(false); 1577 i8042_platform_device = NULL; 1578 1579 return error; 1580 } 1581 1582 static int i8042_remove(struct platform_device *dev) 1583 { 1584 i8042_unregister_ports(); 1585 i8042_free_irqs(); 1586 i8042_controller_reset(false); 1587 i8042_platform_device = NULL; 1588 1589 return 0; 1590 } 1591 1592 static struct platform_driver i8042_driver = { 1593 .driver = { 1594 .name = "i8042", 1595 #ifdef CONFIG_PM 1596 .pm = &i8042_pm_ops, 1597 #endif 1598 }, 1599 .remove = i8042_remove, 1600 .shutdown = i8042_shutdown, 1601 }; 1602 1603 static struct notifier_block i8042_kbd_bind_notifier_block = { 1604 .notifier_call = i8042_kbd_bind_notifier, 1605 }; 1606 1607 static int __init i8042_init(void) 1608 { 1609 struct platform_device *pdev; 1610 int err; 1611 1612 dbg_init(); 1613 1614 err = i8042_platform_init(); 1615 if (err) 1616 return err; 1617 1618 err = i8042_controller_check(); 1619 if (err) 1620 goto err_platform_exit; 1621 1622 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1623 if (IS_ERR(pdev)) { 1624 err = PTR_ERR(pdev); 1625 goto err_platform_exit; 1626 } 1627 1628 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1629 panic_blink = i8042_panic_blink; 1630 1631 return 0; 1632 1633 err_platform_exit: 1634 i8042_platform_exit(); 1635 return err; 1636 } 1637 1638 static void __exit i8042_exit(void) 1639 { 1640 platform_device_unregister(i8042_platform_device); 1641 platform_driver_unregister(&i8042_driver); 1642 i8042_platform_exit(); 1643 1644 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1645 panic_blink = NULL; 1646 } 1647 1648 module_init(i8042_init); 1649 module_exit(i8042_exit); 1650