1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/init.h> 19 #include <linux/serio.h> 20 #include <linux/err.h> 21 #include <linux/rcupdate.h> 22 #include <linux/platform_device.h> 23 #include <linux/i8042.h> 24 #include <linux/slab.h> 25 26 #include <asm/io.h> 27 28 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 29 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 30 MODULE_LICENSE("GPL"); 31 32 static bool i8042_nokbd; 33 module_param_named(nokbd, i8042_nokbd, bool, 0); 34 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 35 36 static bool i8042_noaux; 37 module_param_named(noaux, i8042_noaux, bool, 0); 38 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 39 40 static bool i8042_nomux; 41 module_param_named(nomux, i8042_nomux, bool, 0); 42 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 43 44 static bool i8042_unlock; 45 module_param_named(unlock, i8042_unlock, bool, 0); 46 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 47 48 static bool i8042_reset; 49 module_param_named(reset, i8042_reset, bool, 0); 50 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 51 52 static bool i8042_direct; 53 module_param_named(direct, i8042_direct, bool, 0); 54 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 55 56 static bool i8042_dumbkbd; 57 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 58 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 59 60 static bool i8042_noloop; 61 module_param_named(noloop, i8042_noloop, bool, 0); 62 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 63 64 #ifdef CONFIG_X86 65 static bool i8042_dritek; 66 module_param_named(dritek, i8042_dritek, bool, 0); 67 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 68 #endif 69 70 #ifdef CONFIG_PNP 71 static bool i8042_nopnp; 72 module_param_named(nopnp, i8042_nopnp, bool, 0); 73 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 74 #endif 75 76 #define DEBUG 77 #ifdef DEBUG 78 static bool i8042_debug; 79 module_param_named(debug, i8042_debug, bool, 0600); 80 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 81 #endif 82 83 static bool i8042_bypass_aux_irq_test; 84 85 #include "i8042.h" 86 87 /* 88 * i8042_lock protects serialization between i8042_command and 89 * the interrupt handler. 90 */ 91 static DEFINE_SPINLOCK(i8042_lock); 92 93 /* 94 * Writers to AUX and KBD ports as well as users issuing i8042_command 95 * directly should acquire i8042_mutex (by means of calling 96 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 97 * they do not disturb each other (unfortunately in many i8042 98 * implementations write to one of the ports will immediately abort 99 * command that is being processed by another port). 100 */ 101 static DEFINE_MUTEX(i8042_mutex); 102 103 struct i8042_port { 104 struct serio *serio; 105 int irq; 106 bool exists; 107 signed char mux; 108 }; 109 110 #define I8042_KBD_PORT_NO 0 111 #define I8042_AUX_PORT_NO 1 112 #define I8042_MUX_PORT_NO 2 113 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 114 115 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 116 117 static unsigned char i8042_initial_ctr; 118 static unsigned char i8042_ctr; 119 static bool i8042_mux_present; 120 static bool i8042_kbd_irq_registered; 121 static bool i8042_aux_irq_registered; 122 static unsigned char i8042_suppress_kbd_ack; 123 static struct platform_device *i8042_platform_device; 124 125 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 126 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 127 struct serio *serio); 128 129 void i8042_lock_chip(void) 130 { 131 mutex_lock(&i8042_mutex); 132 } 133 EXPORT_SYMBOL(i8042_lock_chip); 134 135 void i8042_unlock_chip(void) 136 { 137 mutex_unlock(&i8042_mutex); 138 } 139 EXPORT_SYMBOL(i8042_unlock_chip); 140 141 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 142 struct serio *serio)) 143 { 144 unsigned long flags; 145 int ret = 0; 146 147 spin_lock_irqsave(&i8042_lock, flags); 148 149 if (i8042_platform_filter) { 150 ret = -EBUSY; 151 goto out; 152 } 153 154 i8042_platform_filter = filter; 155 156 out: 157 spin_unlock_irqrestore(&i8042_lock, flags); 158 return ret; 159 } 160 EXPORT_SYMBOL(i8042_install_filter); 161 162 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 163 struct serio *port)) 164 { 165 unsigned long flags; 166 int ret = 0; 167 168 spin_lock_irqsave(&i8042_lock, flags); 169 170 if (i8042_platform_filter != filter) { 171 ret = -EINVAL; 172 goto out; 173 } 174 175 i8042_platform_filter = NULL; 176 177 out: 178 spin_unlock_irqrestore(&i8042_lock, flags); 179 return ret; 180 } 181 EXPORT_SYMBOL(i8042_remove_filter); 182 183 /* 184 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 185 * be ready for reading values from it / writing values to it. 186 * Called always with i8042_lock held. 187 */ 188 189 static int i8042_wait_read(void) 190 { 191 int i = 0; 192 193 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 194 udelay(50); 195 i++; 196 } 197 return -(i == I8042_CTL_TIMEOUT); 198 } 199 200 static int i8042_wait_write(void) 201 { 202 int i = 0; 203 204 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 205 udelay(50); 206 i++; 207 } 208 return -(i == I8042_CTL_TIMEOUT); 209 } 210 211 /* 212 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 213 * of the i8042 down the toilet. 214 */ 215 216 static int i8042_flush(void) 217 { 218 unsigned long flags; 219 unsigned char data, str; 220 int i = 0; 221 222 spin_lock_irqsave(&i8042_lock, flags); 223 224 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 225 udelay(50); 226 data = i8042_read_data(); 227 i++; 228 dbg("%02x <- i8042 (flush, %s)", data, 229 str & I8042_STR_AUXDATA ? "aux" : "kbd"); 230 } 231 232 spin_unlock_irqrestore(&i8042_lock, flags); 233 234 return i; 235 } 236 237 /* 238 * i8042_command() executes a command on the i8042. It also sends the input 239 * parameter(s) of the commands to it, and receives the output value(s). The 240 * parameters are to be stored in the param array, and the output is placed 241 * into the same array. The number of the parameters and output values is 242 * encoded in bits 8-11 of the command number. 243 */ 244 245 static int __i8042_command(unsigned char *param, int command) 246 { 247 int i, error; 248 249 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 250 return -1; 251 252 error = i8042_wait_write(); 253 if (error) 254 return error; 255 256 dbg("%02x -> i8042 (command)", command & 0xff); 257 i8042_write_command(command & 0xff); 258 259 for (i = 0; i < ((command >> 12) & 0xf); i++) { 260 error = i8042_wait_write(); 261 if (error) 262 return error; 263 dbg("%02x -> i8042 (parameter)", param[i]); 264 i8042_write_data(param[i]); 265 } 266 267 for (i = 0; i < ((command >> 8) & 0xf); i++) { 268 error = i8042_wait_read(); 269 if (error) { 270 dbg(" -- i8042 (timeout)"); 271 return error; 272 } 273 274 if (command == I8042_CMD_AUX_LOOP && 275 !(i8042_read_status() & I8042_STR_AUXDATA)) { 276 dbg(" -- i8042 (auxerr)"); 277 return -1; 278 } 279 280 param[i] = i8042_read_data(); 281 dbg("%02x <- i8042 (return)", param[i]); 282 } 283 284 return 0; 285 } 286 287 int i8042_command(unsigned char *param, int command) 288 { 289 unsigned long flags; 290 int retval; 291 292 spin_lock_irqsave(&i8042_lock, flags); 293 retval = __i8042_command(param, command); 294 spin_unlock_irqrestore(&i8042_lock, flags); 295 296 return retval; 297 } 298 EXPORT_SYMBOL(i8042_command); 299 300 /* 301 * i8042_kbd_write() sends a byte out through the keyboard interface. 302 */ 303 304 static int i8042_kbd_write(struct serio *port, unsigned char c) 305 { 306 unsigned long flags; 307 int retval = 0; 308 309 spin_lock_irqsave(&i8042_lock, flags); 310 311 if (!(retval = i8042_wait_write())) { 312 dbg("%02x -> i8042 (kbd-data)", c); 313 i8042_write_data(c); 314 } 315 316 spin_unlock_irqrestore(&i8042_lock, flags); 317 318 return retval; 319 } 320 321 /* 322 * i8042_aux_write() sends a byte out through the aux interface. 323 */ 324 325 static int i8042_aux_write(struct serio *serio, unsigned char c) 326 { 327 struct i8042_port *port = serio->port_data; 328 329 return i8042_command(&c, port->mux == -1 ? 330 I8042_CMD_AUX_SEND : 331 I8042_CMD_MUX_SEND + port->mux); 332 } 333 334 335 /* 336 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 337 * and then re-enabling it. 338 */ 339 340 static void i8042_port_close(struct serio *serio) 341 { 342 int irq_bit; 343 int disable_bit; 344 const char *port_name; 345 346 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 347 irq_bit = I8042_CTR_AUXINT; 348 disable_bit = I8042_CTR_AUXDIS; 349 port_name = "AUX"; 350 } else { 351 irq_bit = I8042_CTR_KBDINT; 352 disable_bit = I8042_CTR_KBDDIS; 353 port_name = "KBD"; 354 } 355 356 i8042_ctr &= ~irq_bit; 357 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 358 printk(KERN_WARNING 359 "i8042.c: Can't write CTR while closing %s port.\n", 360 port_name); 361 362 udelay(50); 363 364 i8042_ctr &= ~disable_bit; 365 i8042_ctr |= irq_bit; 366 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 367 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", 368 port_name); 369 370 /* 371 * See if there is any data appeared while we were messing with 372 * port state. 373 */ 374 i8042_interrupt(0, NULL); 375 } 376 377 /* 378 * i8042_start() is called by serio core when port is about to finish 379 * registering. It will mark port as existing so i8042_interrupt can 380 * start sending data through it. 381 */ 382 static int i8042_start(struct serio *serio) 383 { 384 struct i8042_port *port = serio->port_data; 385 386 port->exists = true; 387 mb(); 388 return 0; 389 } 390 391 /* 392 * i8042_stop() marks serio port as non-existing so i8042_interrupt 393 * will not try to send data to the port that is about to go away. 394 * The function is called by serio core as part of unregister procedure. 395 */ 396 static void i8042_stop(struct serio *serio) 397 { 398 struct i8042_port *port = serio->port_data; 399 400 port->exists = false; 401 402 /* 403 * We synchronize with both AUX and KBD IRQs because there is 404 * a (very unlikely) chance that AUX IRQ is raised for KBD port 405 * and vice versa. 406 */ 407 synchronize_irq(I8042_AUX_IRQ); 408 synchronize_irq(I8042_KBD_IRQ); 409 port->serio = NULL; 410 } 411 412 /* 413 * i8042_filter() filters out unwanted bytes from the input data stream. 414 * It is called from i8042_interrupt and thus is running with interrupts 415 * off and i8042_lock held. 416 */ 417 static bool i8042_filter(unsigned char data, unsigned char str, 418 struct serio *serio) 419 { 420 if (unlikely(i8042_suppress_kbd_ack)) { 421 if ((~str & I8042_STR_AUXDATA) && 422 (data == 0xfa || data == 0xfe)) { 423 i8042_suppress_kbd_ack--; 424 dbg("Extra keyboard ACK - filtered out\n"); 425 return true; 426 } 427 } 428 429 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 430 dbg("Filtered out by platform filter\n"); 431 return true; 432 } 433 434 return false; 435 } 436 437 /* 438 * i8042_interrupt() is the most important function in this driver - 439 * it handles the interrupts from the i8042, and sends incoming bytes 440 * to the upper layers. 441 */ 442 443 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 444 { 445 struct i8042_port *port; 446 struct serio *serio; 447 unsigned long flags; 448 unsigned char str, data; 449 unsigned int dfl; 450 unsigned int port_no; 451 bool filtered; 452 int ret = 1; 453 454 spin_lock_irqsave(&i8042_lock, flags); 455 456 str = i8042_read_status(); 457 if (unlikely(~str & I8042_STR_OBF)) { 458 spin_unlock_irqrestore(&i8042_lock, flags); 459 if (irq) dbg("Interrupt %d, without any data", irq); 460 ret = 0; 461 goto out; 462 } 463 464 data = i8042_read_data(); 465 466 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 467 static unsigned long last_transmit; 468 static unsigned char last_str; 469 470 dfl = 0; 471 if (str & I8042_STR_MUXERR) { 472 dbg("MUX error, status is %02x, data is %02x", str, data); 473 /* 474 * When MUXERR condition is signalled the data register can only contain 475 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 476 * it is not always the case. Some KBCs also report 0xfc when there is 477 * nothing connected to the port while others sometimes get confused which 478 * port the data came from and signal error leaving the data intact. They 479 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 480 * to legacy mode yet, when we see one we'll add proper handling). 481 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 482 * rest assume that the data came from the same serio last byte 483 * was transmitted (if transmission happened not too long ago). 484 */ 485 486 switch (data) { 487 default: 488 if (time_before(jiffies, last_transmit + HZ/10)) { 489 str = last_str; 490 break; 491 } 492 /* fall through - report timeout */ 493 case 0xfc: 494 case 0xfd: 495 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 496 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 497 } 498 } 499 500 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 501 last_str = str; 502 last_transmit = jiffies; 503 } else { 504 505 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 506 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); 507 508 port_no = (str & I8042_STR_AUXDATA) ? 509 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 510 } 511 512 port = &i8042_ports[port_no]; 513 serio = port->exists ? port->serio : NULL; 514 515 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", 516 data, port_no, irq, 517 dfl & SERIO_PARITY ? ", bad parity" : "", 518 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 519 520 filtered = i8042_filter(data, str, serio); 521 522 spin_unlock_irqrestore(&i8042_lock, flags); 523 524 if (likely(port->exists && !filtered)) 525 serio_interrupt(serio, data, dfl); 526 527 out: 528 return IRQ_RETVAL(ret); 529 } 530 531 /* 532 * i8042_enable_kbd_port enables keyboard port on chip 533 */ 534 535 static int i8042_enable_kbd_port(void) 536 { 537 i8042_ctr &= ~I8042_CTR_KBDDIS; 538 i8042_ctr |= I8042_CTR_KBDINT; 539 540 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 541 i8042_ctr &= ~I8042_CTR_KBDINT; 542 i8042_ctr |= I8042_CTR_KBDDIS; 543 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); 544 return -EIO; 545 } 546 547 return 0; 548 } 549 550 /* 551 * i8042_enable_aux_port enables AUX (mouse) port on chip 552 */ 553 554 static int i8042_enable_aux_port(void) 555 { 556 i8042_ctr &= ~I8042_CTR_AUXDIS; 557 i8042_ctr |= I8042_CTR_AUXINT; 558 559 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 560 i8042_ctr &= ~I8042_CTR_AUXINT; 561 i8042_ctr |= I8042_CTR_AUXDIS; 562 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); 563 return -EIO; 564 } 565 566 return 0; 567 } 568 569 /* 570 * i8042_enable_mux_ports enables 4 individual AUX ports after 571 * the controller has been switched into Multiplexed mode 572 */ 573 574 static int i8042_enable_mux_ports(void) 575 { 576 unsigned char param; 577 int i; 578 579 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 580 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 581 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 582 } 583 584 return i8042_enable_aux_port(); 585 } 586 587 /* 588 * i8042_set_mux_mode checks whether the controller has an 589 * active multiplexor and puts the chip into Multiplexed (true) 590 * or Legacy (false) mode. 591 */ 592 593 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 594 { 595 596 unsigned char param, val; 597 /* 598 * Get rid of bytes in the queue. 599 */ 600 601 i8042_flush(); 602 603 /* 604 * Internal loopback test - send three bytes, they should come back from the 605 * mouse interface, the last should be version. 606 */ 607 608 param = val = 0xf0; 609 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 610 return -1; 611 param = val = multiplex ? 0x56 : 0xf6; 612 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 613 return -1; 614 param = val = multiplex ? 0xa4 : 0xa5; 615 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 616 return -1; 617 618 /* 619 * Workaround for interference with USB Legacy emulation 620 * that causes a v10.12 MUX to be found. 621 */ 622 if (param == 0xac) 623 return -1; 624 625 if (mux_version) 626 *mux_version = param; 627 628 return 0; 629 } 630 631 /* 632 * i8042_check_mux() checks whether the controller supports the PS/2 Active 633 * Multiplexing specification by Synaptics, Phoenix, Insyde and 634 * LCS/Telegraphics. 635 */ 636 637 static int __init i8042_check_mux(void) 638 { 639 unsigned char mux_version; 640 641 if (i8042_set_mux_mode(true, &mux_version)) 642 return -1; 643 644 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", 645 (mux_version >> 4) & 0xf, mux_version & 0xf); 646 647 /* 648 * Disable all muxed ports by disabling AUX. 649 */ 650 i8042_ctr |= I8042_CTR_AUXDIS; 651 i8042_ctr &= ~I8042_CTR_AUXINT; 652 653 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 654 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); 655 return -EIO; 656 } 657 658 i8042_mux_present = true; 659 660 return 0; 661 } 662 663 /* 664 * The following is used to test AUX IRQ delivery. 665 */ 666 static struct completion i8042_aux_irq_delivered __initdata; 667 static bool i8042_irq_being_tested __initdata; 668 669 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 670 { 671 unsigned long flags; 672 unsigned char str, data; 673 int ret = 0; 674 675 spin_lock_irqsave(&i8042_lock, flags); 676 str = i8042_read_status(); 677 if (str & I8042_STR_OBF) { 678 data = i8042_read_data(); 679 dbg("%02x <- i8042 (aux_test_irq, %s)", 680 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 681 if (i8042_irq_being_tested && 682 data == 0xa5 && (str & I8042_STR_AUXDATA)) 683 complete(&i8042_aux_irq_delivered); 684 ret = 1; 685 } 686 spin_unlock_irqrestore(&i8042_lock, flags); 687 688 return IRQ_RETVAL(ret); 689 } 690 691 /* 692 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 693 * verifies success by readinng CTR. Used when testing for presence of AUX 694 * port. 695 */ 696 static int __init i8042_toggle_aux(bool on) 697 { 698 unsigned char param; 699 int i; 700 701 if (i8042_command(¶m, 702 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 703 return -1; 704 705 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 706 for (i = 0; i < 100; i++) { 707 udelay(50); 708 709 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 710 return -1; 711 712 if (!(param & I8042_CTR_AUXDIS) == on) 713 return 0; 714 } 715 716 return -1; 717 } 718 719 /* 720 * i8042_check_aux() applies as much paranoia as it can at detecting 721 * the presence of an AUX interface. 722 */ 723 724 static int __init i8042_check_aux(void) 725 { 726 int retval = -1; 727 bool irq_registered = false; 728 bool aux_loop_broken = false; 729 unsigned long flags; 730 unsigned char param; 731 732 /* 733 * Get rid of bytes in the queue. 734 */ 735 736 i8042_flush(); 737 738 /* 739 * Internal loopback test - filters out AT-type i8042's. Unfortunately 740 * SiS screwed up and their 5597 doesn't support the LOOP command even 741 * though it has an AUX port. 742 */ 743 744 param = 0x5a; 745 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 746 if (retval || param != 0x5a) { 747 748 /* 749 * External connection test - filters out AT-soldered PS/2 i8042's 750 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 751 * 0xfa - no error on some notebooks which ignore the spec 752 * Because it's common for chipsets to return error on perfectly functioning 753 * AUX ports, we test for this only when the LOOP command failed. 754 */ 755 756 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 757 (param && param != 0xfa && param != 0xff)) 758 return -1; 759 760 /* 761 * If AUX_LOOP completed without error but returned unexpected data 762 * mark it as broken 763 */ 764 if (!retval) 765 aux_loop_broken = true; 766 } 767 768 /* 769 * Bit assignment test - filters out PS/2 i8042's in AT mode 770 */ 771 772 if (i8042_toggle_aux(false)) { 773 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 774 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); 775 } 776 777 if (i8042_toggle_aux(true)) 778 return -1; 779 780 /* 781 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 782 * used it for a PCI card or somethig else. 783 */ 784 785 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 786 /* 787 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 788 * is working and hope we are right. 789 */ 790 retval = 0; 791 goto out; 792 } 793 794 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 795 "i8042", i8042_platform_device)) 796 goto out; 797 798 irq_registered = true; 799 800 if (i8042_enable_aux_port()) 801 goto out; 802 803 spin_lock_irqsave(&i8042_lock, flags); 804 805 init_completion(&i8042_aux_irq_delivered); 806 i8042_irq_being_tested = true; 807 808 param = 0xa5; 809 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 810 811 spin_unlock_irqrestore(&i8042_lock, flags); 812 813 if (retval) 814 goto out; 815 816 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 817 msecs_to_jiffies(250)) == 0) { 818 /* 819 * AUX IRQ was never delivered so we need to flush the controller to 820 * get rid of the byte we put there; otherwise keyboard may not work. 821 */ 822 dbg(" -- i8042 (aux irq test timeout)"); 823 i8042_flush(); 824 retval = -1; 825 } 826 827 out: 828 829 /* 830 * Disable the interface. 831 */ 832 833 i8042_ctr |= I8042_CTR_AUXDIS; 834 i8042_ctr &= ~I8042_CTR_AUXINT; 835 836 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 837 retval = -1; 838 839 if (irq_registered) 840 free_irq(I8042_AUX_IRQ, i8042_platform_device); 841 842 return retval; 843 } 844 845 static int i8042_controller_check(void) 846 { 847 if (i8042_flush() == I8042_BUFFER_SIZE) { 848 printk(KERN_ERR "i8042.c: No controller found.\n"); 849 return -ENODEV; 850 } 851 852 return 0; 853 } 854 855 static int i8042_controller_selftest(void) 856 { 857 unsigned char param; 858 int i = 0; 859 860 /* 861 * We try this 5 times; on some really fragile systems this does not 862 * take the first time... 863 */ 864 do { 865 866 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 867 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); 868 return -ENODEV; 869 } 870 871 if (param == I8042_RET_CTL_TEST) 872 return 0; 873 874 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", 875 param, I8042_RET_CTL_TEST); 876 msleep(50); 877 } while (i++ < 5); 878 879 #ifdef CONFIG_X86 880 /* 881 * On x86, we don't fail entire i8042 initialization if controller 882 * reset fails in hopes that keyboard port will still be functional 883 * and user will still get a working keyboard. This is especially 884 * important on netbooks. On other arches we trust hardware more. 885 */ 886 printk(KERN_INFO 887 "i8042: giving up on controller selftest, continuing anyway...\n"); 888 return 0; 889 #else 890 return -EIO; 891 #endif 892 } 893 894 /* 895 * i8042_controller init initializes the i8042 controller, and, 896 * most importantly, sets it into non-xlated mode if that's 897 * desired. 898 */ 899 900 static int i8042_controller_init(void) 901 { 902 unsigned long flags; 903 int n = 0; 904 unsigned char ctr[2]; 905 906 /* 907 * Save the CTR for restore on unload / reboot. 908 */ 909 910 do { 911 if (n >= 10) { 912 printk(KERN_ERR 913 "i8042.c: Unable to get stable CTR read.\n"); 914 return -EIO; 915 } 916 917 if (n != 0) 918 udelay(50); 919 920 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 921 printk(KERN_ERR 922 "i8042.c: Can't read CTR while initializing i8042.\n"); 923 return -EIO; 924 } 925 926 } while (n < 2 || ctr[0] != ctr[1]); 927 928 i8042_initial_ctr = i8042_ctr = ctr[0]; 929 930 /* 931 * Disable the keyboard interface and interrupt. 932 */ 933 934 i8042_ctr |= I8042_CTR_KBDDIS; 935 i8042_ctr &= ~I8042_CTR_KBDINT; 936 937 /* 938 * Handle keylock. 939 */ 940 941 spin_lock_irqsave(&i8042_lock, flags); 942 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 943 if (i8042_unlock) 944 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 945 else 946 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); 947 } 948 spin_unlock_irqrestore(&i8042_lock, flags); 949 950 /* 951 * If the chip is configured into nontranslated mode by the BIOS, don't 952 * bother enabling translating and be happy. 953 */ 954 955 if (~i8042_ctr & I8042_CTR_XLATE) 956 i8042_direct = true; 957 958 /* 959 * Set nontranslated mode for the kbd interface if requested by an option. 960 * After this the kbd interface becomes a simple serial in/out, like the aux 961 * interface is. We don't do this by default, since it can confuse notebook 962 * BIOSes. 963 */ 964 965 if (i8042_direct) 966 i8042_ctr &= ~I8042_CTR_XLATE; 967 968 /* 969 * Write CTR back. 970 */ 971 972 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 973 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); 974 return -EIO; 975 } 976 977 /* 978 * Flush whatever accumulated while we were disabling keyboard port. 979 */ 980 981 i8042_flush(); 982 983 return 0; 984 } 985 986 987 /* 988 * Reset the controller and reset CRT to the original value set by BIOS. 989 */ 990 991 static void i8042_controller_reset(void) 992 { 993 i8042_flush(); 994 995 /* 996 * Disable both KBD and AUX interfaces so they don't get in the way 997 */ 998 999 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1000 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1001 1002 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1003 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); 1004 1005 /* 1006 * Disable MUX mode if present. 1007 */ 1008 1009 if (i8042_mux_present) 1010 i8042_set_mux_mode(false, NULL); 1011 1012 /* 1013 * Reset the controller if requested. 1014 */ 1015 1016 if (i8042_reset) 1017 i8042_controller_selftest(); 1018 1019 /* 1020 * Restore the original control register setting. 1021 */ 1022 1023 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1024 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); 1025 } 1026 1027 1028 /* 1029 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1030 * when kernel panics. Flashing LEDs is useful for users running X who may 1031 * not see the console and will help distingushing panics from "real" 1032 * lockups. 1033 * 1034 * Note that DELAY has a limit of 10ms so we will not get stuck here 1035 * waiting for KBC to free up even if KBD interrupt is off 1036 */ 1037 1038 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1039 1040 static long i8042_panic_blink(int state) 1041 { 1042 long delay = 0; 1043 char led; 1044 1045 led = (state) ? 0x01 | 0x04 : 0; 1046 while (i8042_read_status() & I8042_STR_IBF) 1047 DELAY; 1048 dbg("%02x -> i8042 (panic blink)", 0xed); 1049 i8042_suppress_kbd_ack = 2; 1050 i8042_write_data(0xed); /* set leds */ 1051 DELAY; 1052 while (i8042_read_status() & I8042_STR_IBF) 1053 DELAY; 1054 DELAY; 1055 dbg("%02x -> i8042 (panic blink)", led); 1056 i8042_write_data(led); 1057 DELAY; 1058 return delay; 1059 } 1060 1061 #undef DELAY 1062 1063 #ifdef CONFIG_X86 1064 static void i8042_dritek_enable(void) 1065 { 1066 unsigned char param = 0x90; 1067 int error; 1068 1069 error = i8042_command(¶m, 0x1059); 1070 if (error) 1071 printk(KERN_WARNING 1072 "Failed to enable DRITEK extension: %d\n", 1073 error); 1074 } 1075 #endif 1076 1077 #ifdef CONFIG_PM 1078 1079 /* 1080 * Here we try to reset everything back to a state we had 1081 * before suspending. 1082 */ 1083 1084 static int i8042_controller_resume(bool force_reset) 1085 { 1086 int error; 1087 1088 error = i8042_controller_check(); 1089 if (error) 1090 return error; 1091 1092 if (i8042_reset || force_reset) { 1093 error = i8042_controller_selftest(); 1094 if (error) 1095 return error; 1096 } 1097 1098 /* 1099 * Restore original CTR value and disable all ports 1100 */ 1101 1102 i8042_ctr = i8042_initial_ctr; 1103 if (i8042_direct) 1104 i8042_ctr &= ~I8042_CTR_XLATE; 1105 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1106 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1107 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1108 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); 1109 msleep(50); 1110 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1111 printk(KERN_ERR "i8042: CTR write retry failed\n"); 1112 return -EIO; 1113 } 1114 } 1115 1116 1117 #ifdef CONFIG_X86 1118 if (i8042_dritek) 1119 i8042_dritek_enable(); 1120 #endif 1121 1122 if (i8042_mux_present) { 1123 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1124 printk(KERN_WARNING 1125 "i8042: failed to resume active multiplexor, " 1126 "mouse won't work.\n"); 1127 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1128 i8042_enable_aux_port(); 1129 1130 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1131 i8042_enable_kbd_port(); 1132 1133 i8042_interrupt(0, NULL); 1134 1135 return 0; 1136 } 1137 1138 /* 1139 * Here we try to restore the original BIOS settings to avoid 1140 * upsetting it. 1141 */ 1142 1143 static int i8042_pm_reset(struct device *dev) 1144 { 1145 i8042_controller_reset(); 1146 1147 return 0; 1148 } 1149 1150 static int i8042_pm_resume(struct device *dev) 1151 { 1152 /* 1153 * On resume from S2R we always try to reset the controller 1154 * to bring it in a sane state. (In case of S2D we expect 1155 * BIOS to reset the controller for us.) 1156 */ 1157 return i8042_controller_resume(true); 1158 } 1159 1160 static int i8042_pm_thaw(struct device *dev) 1161 { 1162 i8042_interrupt(0, NULL); 1163 1164 return 0; 1165 } 1166 1167 static int i8042_pm_restore(struct device *dev) 1168 { 1169 return i8042_controller_resume(false); 1170 } 1171 1172 static const struct dev_pm_ops i8042_pm_ops = { 1173 .suspend = i8042_pm_reset, 1174 .resume = i8042_pm_resume, 1175 .thaw = i8042_pm_thaw, 1176 .poweroff = i8042_pm_reset, 1177 .restore = i8042_pm_restore, 1178 }; 1179 1180 #endif /* CONFIG_PM */ 1181 1182 /* 1183 * We need to reset the 8042 back to original mode on system shutdown, 1184 * because otherwise BIOSes will be confused. 1185 */ 1186 1187 static void i8042_shutdown(struct platform_device *dev) 1188 { 1189 i8042_controller_reset(); 1190 } 1191 1192 static int __init i8042_create_kbd_port(void) 1193 { 1194 struct serio *serio; 1195 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1196 1197 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1198 if (!serio) 1199 return -ENOMEM; 1200 1201 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1202 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1203 serio->start = i8042_start; 1204 serio->stop = i8042_stop; 1205 serio->close = i8042_port_close; 1206 serio->port_data = port; 1207 serio->dev.parent = &i8042_platform_device->dev; 1208 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1209 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1210 1211 port->serio = serio; 1212 port->irq = I8042_KBD_IRQ; 1213 1214 return 0; 1215 } 1216 1217 static int __init i8042_create_aux_port(int idx) 1218 { 1219 struct serio *serio; 1220 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1221 struct i8042_port *port = &i8042_ports[port_no]; 1222 1223 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1224 if (!serio) 1225 return -ENOMEM; 1226 1227 serio->id.type = SERIO_8042; 1228 serio->write = i8042_aux_write; 1229 serio->start = i8042_start; 1230 serio->stop = i8042_stop; 1231 serio->port_data = port; 1232 serio->dev.parent = &i8042_platform_device->dev; 1233 if (idx < 0) { 1234 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1235 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1236 serio->close = i8042_port_close; 1237 } else { 1238 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1239 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1240 } 1241 1242 port->serio = serio; 1243 port->mux = idx; 1244 port->irq = I8042_AUX_IRQ; 1245 1246 return 0; 1247 } 1248 1249 static void __init i8042_free_kbd_port(void) 1250 { 1251 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1252 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1253 } 1254 1255 static void __init i8042_free_aux_ports(void) 1256 { 1257 int i; 1258 1259 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1260 kfree(i8042_ports[i].serio); 1261 i8042_ports[i].serio = NULL; 1262 } 1263 } 1264 1265 static void __init i8042_register_ports(void) 1266 { 1267 int i; 1268 1269 for (i = 0; i < I8042_NUM_PORTS; i++) { 1270 if (i8042_ports[i].serio) { 1271 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1272 i8042_ports[i].serio->name, 1273 (unsigned long) I8042_DATA_REG, 1274 (unsigned long) I8042_COMMAND_REG, 1275 i8042_ports[i].irq); 1276 serio_register_port(i8042_ports[i].serio); 1277 } 1278 } 1279 } 1280 1281 static void __devexit i8042_unregister_ports(void) 1282 { 1283 int i; 1284 1285 for (i = 0; i < I8042_NUM_PORTS; i++) { 1286 if (i8042_ports[i].serio) { 1287 serio_unregister_port(i8042_ports[i].serio); 1288 i8042_ports[i].serio = NULL; 1289 } 1290 } 1291 } 1292 1293 /* 1294 * Checks whether port belongs to i8042 controller. 1295 */ 1296 bool i8042_check_port_owner(const struct serio *port) 1297 { 1298 int i; 1299 1300 for (i = 0; i < I8042_NUM_PORTS; i++) 1301 if (i8042_ports[i].serio == port) 1302 return true; 1303 1304 return false; 1305 } 1306 EXPORT_SYMBOL(i8042_check_port_owner); 1307 1308 static void i8042_free_irqs(void) 1309 { 1310 if (i8042_aux_irq_registered) 1311 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1312 if (i8042_kbd_irq_registered) 1313 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1314 1315 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1316 } 1317 1318 static int __init i8042_setup_aux(void) 1319 { 1320 int (*aux_enable)(void); 1321 int error; 1322 int i; 1323 1324 if (i8042_check_aux()) 1325 return -ENODEV; 1326 1327 if (i8042_nomux || i8042_check_mux()) { 1328 error = i8042_create_aux_port(-1); 1329 if (error) 1330 goto err_free_ports; 1331 aux_enable = i8042_enable_aux_port; 1332 } else { 1333 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1334 error = i8042_create_aux_port(i); 1335 if (error) 1336 goto err_free_ports; 1337 } 1338 aux_enable = i8042_enable_mux_ports; 1339 } 1340 1341 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1342 "i8042", i8042_platform_device); 1343 if (error) 1344 goto err_free_ports; 1345 1346 if (aux_enable()) 1347 goto err_free_irq; 1348 1349 i8042_aux_irq_registered = true; 1350 return 0; 1351 1352 err_free_irq: 1353 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1354 err_free_ports: 1355 i8042_free_aux_ports(); 1356 return error; 1357 } 1358 1359 static int __init i8042_setup_kbd(void) 1360 { 1361 int error; 1362 1363 error = i8042_create_kbd_port(); 1364 if (error) 1365 return error; 1366 1367 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1368 "i8042", i8042_platform_device); 1369 if (error) 1370 goto err_free_port; 1371 1372 error = i8042_enable_kbd_port(); 1373 if (error) 1374 goto err_free_irq; 1375 1376 i8042_kbd_irq_registered = true; 1377 return 0; 1378 1379 err_free_irq: 1380 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1381 err_free_port: 1382 i8042_free_kbd_port(); 1383 return error; 1384 } 1385 1386 static int __init i8042_probe(struct platform_device *dev) 1387 { 1388 int error; 1389 1390 i8042_platform_device = dev; 1391 1392 if (i8042_reset) { 1393 error = i8042_controller_selftest(); 1394 if (error) 1395 return error; 1396 } 1397 1398 error = i8042_controller_init(); 1399 if (error) 1400 return error; 1401 1402 #ifdef CONFIG_X86 1403 if (i8042_dritek) 1404 i8042_dritek_enable(); 1405 #endif 1406 1407 if (!i8042_noaux) { 1408 error = i8042_setup_aux(); 1409 if (error && error != -ENODEV && error != -EBUSY) 1410 goto out_fail; 1411 } 1412 1413 if (!i8042_nokbd) { 1414 error = i8042_setup_kbd(); 1415 if (error) 1416 goto out_fail; 1417 } 1418 /* 1419 * Ok, everything is ready, let's register all serio ports 1420 */ 1421 i8042_register_ports(); 1422 1423 return 0; 1424 1425 out_fail: 1426 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1427 i8042_free_irqs(); 1428 i8042_controller_reset(); 1429 i8042_platform_device = NULL; 1430 1431 return error; 1432 } 1433 1434 static int __devexit i8042_remove(struct platform_device *dev) 1435 { 1436 i8042_unregister_ports(); 1437 i8042_free_irqs(); 1438 i8042_controller_reset(); 1439 i8042_platform_device = NULL; 1440 1441 return 0; 1442 } 1443 1444 static struct platform_driver i8042_driver = { 1445 .driver = { 1446 .name = "i8042", 1447 .owner = THIS_MODULE, 1448 #ifdef CONFIG_PM 1449 .pm = &i8042_pm_ops, 1450 #endif 1451 }, 1452 .remove = __devexit_p(i8042_remove), 1453 .shutdown = i8042_shutdown, 1454 }; 1455 1456 static int __init i8042_init(void) 1457 { 1458 struct platform_device *pdev; 1459 int err; 1460 1461 dbg_init(); 1462 1463 err = i8042_platform_init(); 1464 if (err) 1465 return err; 1466 1467 err = i8042_controller_check(); 1468 if (err) 1469 goto err_platform_exit; 1470 1471 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1472 if (IS_ERR(pdev)) { 1473 err = PTR_ERR(pdev); 1474 goto err_platform_exit; 1475 } 1476 1477 panic_blink = i8042_panic_blink; 1478 1479 return 0; 1480 1481 err_platform_exit: 1482 i8042_platform_exit(); 1483 return err; 1484 } 1485 1486 static void __exit i8042_exit(void) 1487 { 1488 platform_device_unregister(i8042_platform_device); 1489 platform_driver_unregister(&i8042_driver); 1490 i8042_platform_exit(); 1491 1492 panic_blink = NULL; 1493 } 1494 1495 module_init(i8042_init); 1496 module_exit(i8042_exit); 1497