1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/init.h> 19 #include <linux/serio.h> 20 #include <linux/err.h> 21 #include <linux/rcupdate.h> 22 #include <linux/platform_device.h> 23 #include <linux/i8042.h> 24 25 #include <asm/io.h> 26 27 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 28 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 29 MODULE_LICENSE("GPL"); 30 31 static bool i8042_nokbd; 32 module_param_named(nokbd, i8042_nokbd, bool, 0); 33 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 34 35 static bool i8042_noaux; 36 module_param_named(noaux, i8042_noaux, bool, 0); 37 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 38 39 static bool i8042_nomux; 40 module_param_named(nomux, i8042_nomux, bool, 0); 41 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); 42 43 static bool i8042_unlock; 44 module_param_named(unlock, i8042_unlock, bool, 0); 45 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 46 47 static bool i8042_reset; 48 module_param_named(reset, i8042_reset, bool, 0); 49 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 50 51 static bool i8042_direct; 52 module_param_named(direct, i8042_direct, bool, 0); 53 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 54 55 static bool i8042_dumbkbd; 56 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 57 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 58 59 static bool i8042_noloop; 60 module_param_named(noloop, i8042_noloop, bool, 0); 61 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 62 63 static unsigned int i8042_blink_frequency = 500; 64 module_param_named(panicblink, i8042_blink_frequency, uint, 0600); 65 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); 66 67 #ifdef CONFIG_X86 68 static bool i8042_dritek; 69 module_param_named(dritek, i8042_dritek, bool, 0); 70 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 71 #endif 72 73 #ifdef CONFIG_PNP 74 static bool i8042_nopnp; 75 module_param_named(nopnp, i8042_nopnp, bool, 0); 76 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 77 #endif 78 79 #define DEBUG 80 #ifdef DEBUG 81 static bool i8042_debug; 82 module_param_named(debug, i8042_debug, bool, 0600); 83 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 84 #endif 85 86 static bool i8042_bypass_aux_irq_test; 87 88 #include "i8042.h" 89 90 /* 91 * i8042_lock protects serialization between i8042_command and 92 * the interrupt handler. 93 */ 94 static DEFINE_SPINLOCK(i8042_lock); 95 96 /* 97 * Writers to AUX and KBD ports as well as users issuing i8042_command 98 * directly should acquire i8042_mutex (by means of calling 99 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 100 * they do not disturb each other (unfortunately in many i8042 101 * implementations write to one of the ports will immediately abort 102 * command that is being processed by another port). 103 */ 104 static DEFINE_MUTEX(i8042_mutex); 105 106 struct i8042_port { 107 struct serio *serio; 108 int irq; 109 bool exists; 110 signed char mux; 111 }; 112 113 #define I8042_KBD_PORT_NO 0 114 #define I8042_AUX_PORT_NO 1 115 #define I8042_MUX_PORT_NO 2 116 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 117 118 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 119 120 static unsigned char i8042_initial_ctr; 121 static unsigned char i8042_ctr; 122 static bool i8042_mux_present; 123 static bool i8042_kbd_irq_registered; 124 static bool i8042_aux_irq_registered; 125 static unsigned char i8042_suppress_kbd_ack; 126 static struct platform_device *i8042_platform_device; 127 128 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 129 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 130 struct serio *serio); 131 132 void i8042_lock_chip(void) 133 { 134 mutex_lock(&i8042_mutex); 135 } 136 EXPORT_SYMBOL(i8042_lock_chip); 137 138 void i8042_unlock_chip(void) 139 { 140 mutex_unlock(&i8042_mutex); 141 } 142 EXPORT_SYMBOL(i8042_unlock_chip); 143 144 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 145 struct serio *serio)) 146 { 147 unsigned long flags; 148 int ret = 0; 149 150 spin_lock_irqsave(&i8042_lock, flags); 151 152 if (i8042_platform_filter) { 153 ret = -EBUSY; 154 goto out; 155 } 156 157 i8042_platform_filter = filter; 158 159 out: 160 spin_unlock_irqrestore(&i8042_lock, flags); 161 return ret; 162 } 163 EXPORT_SYMBOL(i8042_install_filter); 164 165 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 166 struct serio *port)) 167 { 168 unsigned long flags; 169 int ret = 0; 170 171 spin_lock_irqsave(&i8042_lock, flags); 172 173 if (i8042_platform_filter != filter) { 174 ret = -EINVAL; 175 goto out; 176 } 177 178 i8042_platform_filter = NULL; 179 180 out: 181 spin_unlock_irqrestore(&i8042_lock, flags); 182 return ret; 183 } 184 EXPORT_SYMBOL(i8042_remove_filter); 185 186 /* 187 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 188 * be ready for reading values from it / writing values to it. 189 * Called always with i8042_lock held. 190 */ 191 192 static int i8042_wait_read(void) 193 { 194 int i = 0; 195 196 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 197 udelay(50); 198 i++; 199 } 200 return -(i == I8042_CTL_TIMEOUT); 201 } 202 203 static int i8042_wait_write(void) 204 { 205 int i = 0; 206 207 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 208 udelay(50); 209 i++; 210 } 211 return -(i == I8042_CTL_TIMEOUT); 212 } 213 214 /* 215 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 216 * of the i8042 down the toilet. 217 */ 218 219 static int i8042_flush(void) 220 { 221 unsigned long flags; 222 unsigned char data, str; 223 int i = 0; 224 225 spin_lock_irqsave(&i8042_lock, flags); 226 227 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 228 udelay(50); 229 data = i8042_read_data(); 230 i++; 231 dbg("%02x <- i8042 (flush, %s)", data, 232 str & I8042_STR_AUXDATA ? "aux" : "kbd"); 233 } 234 235 spin_unlock_irqrestore(&i8042_lock, flags); 236 237 return i; 238 } 239 240 /* 241 * i8042_command() executes a command on the i8042. It also sends the input 242 * parameter(s) of the commands to it, and receives the output value(s). The 243 * parameters are to be stored in the param array, and the output is placed 244 * into the same array. The number of the parameters and output values is 245 * encoded in bits 8-11 of the command number. 246 */ 247 248 static int __i8042_command(unsigned char *param, int command) 249 { 250 int i, error; 251 252 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 253 return -1; 254 255 error = i8042_wait_write(); 256 if (error) 257 return error; 258 259 dbg("%02x -> i8042 (command)", command & 0xff); 260 i8042_write_command(command & 0xff); 261 262 for (i = 0; i < ((command >> 12) & 0xf); i++) { 263 error = i8042_wait_write(); 264 if (error) 265 return error; 266 dbg("%02x -> i8042 (parameter)", param[i]); 267 i8042_write_data(param[i]); 268 } 269 270 for (i = 0; i < ((command >> 8) & 0xf); i++) { 271 error = i8042_wait_read(); 272 if (error) { 273 dbg(" -- i8042 (timeout)"); 274 return error; 275 } 276 277 if (command == I8042_CMD_AUX_LOOP && 278 !(i8042_read_status() & I8042_STR_AUXDATA)) { 279 dbg(" -- i8042 (auxerr)"); 280 return -1; 281 } 282 283 param[i] = i8042_read_data(); 284 dbg("%02x <- i8042 (return)", param[i]); 285 } 286 287 return 0; 288 } 289 290 int i8042_command(unsigned char *param, int command) 291 { 292 unsigned long flags; 293 int retval; 294 295 spin_lock_irqsave(&i8042_lock, flags); 296 retval = __i8042_command(param, command); 297 spin_unlock_irqrestore(&i8042_lock, flags); 298 299 return retval; 300 } 301 EXPORT_SYMBOL(i8042_command); 302 303 /* 304 * i8042_kbd_write() sends a byte out through the keyboard interface. 305 */ 306 307 static int i8042_kbd_write(struct serio *port, unsigned char c) 308 { 309 unsigned long flags; 310 int retval = 0; 311 312 spin_lock_irqsave(&i8042_lock, flags); 313 314 if (!(retval = i8042_wait_write())) { 315 dbg("%02x -> i8042 (kbd-data)", c); 316 i8042_write_data(c); 317 } 318 319 spin_unlock_irqrestore(&i8042_lock, flags); 320 321 return retval; 322 } 323 324 /* 325 * i8042_aux_write() sends a byte out through the aux interface. 326 */ 327 328 static int i8042_aux_write(struct serio *serio, unsigned char c) 329 { 330 struct i8042_port *port = serio->port_data; 331 332 return i8042_command(&c, port->mux == -1 ? 333 I8042_CMD_AUX_SEND : 334 I8042_CMD_MUX_SEND + port->mux); 335 } 336 337 338 /* 339 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 340 * and then re-enabling it. 341 */ 342 343 static void i8042_port_close(struct serio *serio) 344 { 345 int irq_bit; 346 int disable_bit; 347 const char *port_name; 348 349 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 350 irq_bit = I8042_CTR_AUXINT; 351 disable_bit = I8042_CTR_AUXDIS; 352 port_name = "AUX"; 353 } else { 354 irq_bit = I8042_CTR_KBDINT; 355 disable_bit = I8042_CTR_KBDDIS; 356 port_name = "KBD"; 357 } 358 359 i8042_ctr &= ~irq_bit; 360 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 361 printk(KERN_WARNING 362 "i8042.c: Can't write CTR while closing %s port.\n", 363 port_name); 364 365 udelay(50); 366 367 i8042_ctr &= ~disable_bit; 368 i8042_ctr |= irq_bit; 369 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 370 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", 371 port_name); 372 373 /* 374 * See if there is any data appeared while we were messing with 375 * port state. 376 */ 377 i8042_interrupt(0, NULL); 378 } 379 380 /* 381 * i8042_start() is called by serio core when port is about to finish 382 * registering. It will mark port as existing so i8042_interrupt can 383 * start sending data through it. 384 */ 385 static int i8042_start(struct serio *serio) 386 { 387 struct i8042_port *port = serio->port_data; 388 389 port->exists = true; 390 mb(); 391 return 0; 392 } 393 394 /* 395 * i8042_stop() marks serio port as non-existing so i8042_interrupt 396 * will not try to send data to the port that is about to go away. 397 * The function is called by serio core as part of unregister procedure. 398 */ 399 static void i8042_stop(struct serio *serio) 400 { 401 struct i8042_port *port = serio->port_data; 402 403 port->exists = false; 404 405 /* 406 * We synchronize with both AUX and KBD IRQs because there is 407 * a (very unlikely) chance that AUX IRQ is raised for KBD port 408 * and vice versa. 409 */ 410 synchronize_irq(I8042_AUX_IRQ); 411 synchronize_irq(I8042_KBD_IRQ); 412 port->serio = NULL; 413 } 414 415 /* 416 * i8042_filter() filters out unwanted bytes from the input data stream. 417 * It is called from i8042_interrupt and thus is running with interrupts 418 * off and i8042_lock held. 419 */ 420 static bool i8042_filter(unsigned char data, unsigned char str, 421 struct serio *serio) 422 { 423 if (unlikely(i8042_suppress_kbd_ack)) { 424 if ((~str & I8042_STR_AUXDATA) && 425 (data == 0xfa || data == 0xfe)) { 426 i8042_suppress_kbd_ack--; 427 dbg("Extra keyboard ACK - filtered out\n"); 428 return true; 429 } 430 } 431 432 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 433 dbg("Filtered out by platfrom filter\n"); 434 return true; 435 } 436 437 return false; 438 } 439 440 /* 441 * i8042_interrupt() is the most important function in this driver - 442 * it handles the interrupts from the i8042, and sends incoming bytes 443 * to the upper layers. 444 */ 445 446 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 447 { 448 struct i8042_port *port; 449 struct serio *serio; 450 unsigned long flags; 451 unsigned char str, data; 452 unsigned int dfl; 453 unsigned int port_no; 454 bool filtered; 455 int ret = 1; 456 457 spin_lock_irqsave(&i8042_lock, flags); 458 459 str = i8042_read_status(); 460 if (unlikely(~str & I8042_STR_OBF)) { 461 spin_unlock_irqrestore(&i8042_lock, flags); 462 if (irq) dbg("Interrupt %d, without any data", irq); 463 ret = 0; 464 goto out; 465 } 466 467 data = i8042_read_data(); 468 469 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 470 static unsigned long last_transmit; 471 static unsigned char last_str; 472 473 dfl = 0; 474 if (str & I8042_STR_MUXERR) { 475 dbg("MUX error, status is %02x, data is %02x", str, data); 476 /* 477 * When MUXERR condition is signalled the data register can only contain 478 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 479 * it is not always the case. Some KBCs also report 0xfc when there is 480 * nothing connected to the port while others sometimes get confused which 481 * port the data came from and signal error leaving the data intact. They 482 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 483 * to legacy mode yet, when we see one we'll add proper handling). 484 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 485 * rest assume that the data came from the same serio last byte 486 * was transmitted (if transmission happened not too long ago). 487 */ 488 489 switch (data) { 490 default: 491 if (time_before(jiffies, last_transmit + HZ/10)) { 492 str = last_str; 493 break; 494 } 495 /* fall through - report timeout */ 496 case 0xfc: 497 case 0xfd: 498 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 499 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 500 } 501 } 502 503 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 504 last_str = str; 505 last_transmit = jiffies; 506 } else { 507 508 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 509 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); 510 511 port_no = (str & I8042_STR_AUXDATA) ? 512 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 513 } 514 515 port = &i8042_ports[port_no]; 516 serio = port->exists ? port->serio : NULL; 517 518 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", 519 data, port_no, irq, 520 dfl & SERIO_PARITY ? ", bad parity" : "", 521 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 522 523 filtered = i8042_filter(data, str, serio); 524 525 spin_unlock_irqrestore(&i8042_lock, flags); 526 527 if (likely(port->exists && !filtered)) 528 serio_interrupt(serio, data, dfl); 529 530 out: 531 return IRQ_RETVAL(ret); 532 } 533 534 /* 535 * i8042_enable_kbd_port enables keyboard port on chip 536 */ 537 538 static int i8042_enable_kbd_port(void) 539 { 540 i8042_ctr &= ~I8042_CTR_KBDDIS; 541 i8042_ctr |= I8042_CTR_KBDINT; 542 543 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 544 i8042_ctr &= ~I8042_CTR_KBDINT; 545 i8042_ctr |= I8042_CTR_KBDDIS; 546 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); 547 return -EIO; 548 } 549 550 return 0; 551 } 552 553 /* 554 * i8042_enable_aux_port enables AUX (mouse) port on chip 555 */ 556 557 static int i8042_enable_aux_port(void) 558 { 559 i8042_ctr &= ~I8042_CTR_AUXDIS; 560 i8042_ctr |= I8042_CTR_AUXINT; 561 562 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 563 i8042_ctr &= ~I8042_CTR_AUXINT; 564 i8042_ctr |= I8042_CTR_AUXDIS; 565 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); 566 return -EIO; 567 } 568 569 return 0; 570 } 571 572 /* 573 * i8042_enable_mux_ports enables 4 individual AUX ports after 574 * the controller has been switched into Multiplexed mode 575 */ 576 577 static int i8042_enable_mux_ports(void) 578 { 579 unsigned char param; 580 int i; 581 582 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 583 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 584 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 585 } 586 587 return i8042_enable_aux_port(); 588 } 589 590 /* 591 * i8042_set_mux_mode checks whether the controller has an 592 * active multiplexor and puts the chip into Multiplexed (true) 593 * or Legacy (false) mode. 594 */ 595 596 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 597 { 598 599 unsigned char param, val; 600 /* 601 * Get rid of bytes in the queue. 602 */ 603 604 i8042_flush(); 605 606 /* 607 * Internal loopback test - send three bytes, they should come back from the 608 * mouse interface, the last should be version. 609 */ 610 611 param = val = 0xf0; 612 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 613 return -1; 614 param = val = multiplex ? 0x56 : 0xf6; 615 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 616 return -1; 617 param = val = multiplex ? 0xa4 : 0xa5; 618 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 619 return -1; 620 621 /* 622 * Workaround for interference with USB Legacy emulation 623 * that causes a v10.12 MUX to be found. 624 */ 625 if (param == 0xac) 626 return -1; 627 628 if (mux_version) 629 *mux_version = param; 630 631 return 0; 632 } 633 634 /* 635 * i8042_check_mux() checks whether the controller supports the PS/2 Active 636 * Multiplexing specification by Synaptics, Phoenix, Insyde and 637 * LCS/Telegraphics. 638 */ 639 640 static int __init i8042_check_mux(void) 641 { 642 unsigned char mux_version; 643 644 if (i8042_set_mux_mode(true, &mux_version)) 645 return -1; 646 647 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", 648 (mux_version >> 4) & 0xf, mux_version & 0xf); 649 650 /* 651 * Disable all muxed ports by disabling AUX. 652 */ 653 i8042_ctr |= I8042_CTR_AUXDIS; 654 i8042_ctr &= ~I8042_CTR_AUXINT; 655 656 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 657 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); 658 return -EIO; 659 } 660 661 i8042_mux_present = true; 662 663 return 0; 664 } 665 666 /* 667 * The following is used to test AUX IRQ delivery. 668 */ 669 static struct completion i8042_aux_irq_delivered __initdata; 670 static bool i8042_irq_being_tested __initdata; 671 672 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 673 { 674 unsigned long flags; 675 unsigned char str, data; 676 int ret = 0; 677 678 spin_lock_irqsave(&i8042_lock, flags); 679 str = i8042_read_status(); 680 if (str & I8042_STR_OBF) { 681 data = i8042_read_data(); 682 dbg("%02x <- i8042 (aux_test_irq, %s)", 683 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 684 if (i8042_irq_being_tested && 685 data == 0xa5 && (str & I8042_STR_AUXDATA)) 686 complete(&i8042_aux_irq_delivered); 687 ret = 1; 688 } 689 spin_unlock_irqrestore(&i8042_lock, flags); 690 691 return IRQ_RETVAL(ret); 692 } 693 694 /* 695 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 696 * verifies success by readinng CTR. Used when testing for presence of AUX 697 * port. 698 */ 699 static int __init i8042_toggle_aux(bool on) 700 { 701 unsigned char param; 702 int i; 703 704 if (i8042_command(¶m, 705 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 706 return -1; 707 708 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 709 for (i = 0; i < 100; i++) { 710 udelay(50); 711 712 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 713 return -1; 714 715 if (!(param & I8042_CTR_AUXDIS) == on) 716 return 0; 717 } 718 719 return -1; 720 } 721 722 /* 723 * i8042_check_aux() applies as much paranoia as it can at detecting 724 * the presence of an AUX interface. 725 */ 726 727 static int __init i8042_check_aux(void) 728 { 729 int retval = -1; 730 bool irq_registered = false; 731 bool aux_loop_broken = false; 732 unsigned long flags; 733 unsigned char param; 734 735 /* 736 * Get rid of bytes in the queue. 737 */ 738 739 i8042_flush(); 740 741 /* 742 * Internal loopback test - filters out AT-type i8042's. Unfortunately 743 * SiS screwed up and their 5597 doesn't support the LOOP command even 744 * though it has an AUX port. 745 */ 746 747 param = 0x5a; 748 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 749 if (retval || param != 0x5a) { 750 751 /* 752 * External connection test - filters out AT-soldered PS/2 i8042's 753 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 754 * 0xfa - no error on some notebooks which ignore the spec 755 * Because it's common for chipsets to return error on perfectly functioning 756 * AUX ports, we test for this only when the LOOP command failed. 757 */ 758 759 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 760 (param && param != 0xfa && param != 0xff)) 761 return -1; 762 763 /* 764 * If AUX_LOOP completed without error but returned unexpected data 765 * mark it as broken 766 */ 767 if (!retval) 768 aux_loop_broken = true; 769 } 770 771 /* 772 * Bit assignment test - filters out PS/2 i8042's in AT mode 773 */ 774 775 if (i8042_toggle_aux(false)) { 776 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 777 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); 778 } 779 780 if (i8042_toggle_aux(true)) 781 return -1; 782 783 /* 784 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 785 * used it for a PCI card or somethig else. 786 */ 787 788 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 789 /* 790 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 791 * is working and hope we are right. 792 */ 793 retval = 0; 794 goto out; 795 } 796 797 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 798 "i8042", i8042_platform_device)) 799 goto out; 800 801 irq_registered = true; 802 803 if (i8042_enable_aux_port()) 804 goto out; 805 806 spin_lock_irqsave(&i8042_lock, flags); 807 808 init_completion(&i8042_aux_irq_delivered); 809 i8042_irq_being_tested = true; 810 811 param = 0xa5; 812 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 813 814 spin_unlock_irqrestore(&i8042_lock, flags); 815 816 if (retval) 817 goto out; 818 819 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 820 msecs_to_jiffies(250)) == 0) { 821 /* 822 * AUX IRQ was never delivered so we need to flush the controller to 823 * get rid of the byte we put there; otherwise keyboard may not work. 824 */ 825 dbg(" -- i8042 (aux irq test timeout)"); 826 i8042_flush(); 827 retval = -1; 828 } 829 830 out: 831 832 /* 833 * Disable the interface. 834 */ 835 836 i8042_ctr |= I8042_CTR_AUXDIS; 837 i8042_ctr &= ~I8042_CTR_AUXINT; 838 839 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 840 retval = -1; 841 842 if (irq_registered) 843 free_irq(I8042_AUX_IRQ, i8042_platform_device); 844 845 return retval; 846 } 847 848 static int i8042_controller_check(void) 849 { 850 if (i8042_flush() == I8042_BUFFER_SIZE) { 851 printk(KERN_ERR "i8042.c: No controller found.\n"); 852 return -ENODEV; 853 } 854 855 return 0; 856 } 857 858 static int i8042_controller_selftest(void) 859 { 860 unsigned char param; 861 int i = 0; 862 863 if (!i8042_reset) 864 return 0; 865 866 /* 867 * We try this 5 times; on some really fragile systems this does not 868 * take the first time... 869 */ 870 do { 871 872 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 873 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); 874 return -ENODEV; 875 } 876 877 if (param == I8042_RET_CTL_TEST) 878 return 0; 879 880 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", 881 param, I8042_RET_CTL_TEST); 882 msleep(50); 883 } while (i++ < 5); 884 885 #ifdef CONFIG_X86 886 /* 887 * On x86, we don't fail entire i8042 initialization if controller 888 * reset fails in hopes that keyboard port will still be functional 889 * and user will still get a working keyboard. This is especially 890 * important on netbooks. On other arches we trust hardware more. 891 */ 892 printk(KERN_INFO 893 "i8042: giving up on controller selftest, continuing anyway...\n"); 894 return 0; 895 #else 896 return -EIO; 897 #endif 898 } 899 900 /* 901 * i8042_controller init initializes the i8042 controller, and, 902 * most importantly, sets it into non-xlated mode if that's 903 * desired. 904 */ 905 906 static int i8042_controller_init(void) 907 { 908 unsigned long flags; 909 int n = 0; 910 unsigned char ctr[2]; 911 912 /* 913 * Save the CTR for restore on unload / reboot. 914 */ 915 916 do { 917 if (n >= 10) { 918 printk(KERN_ERR 919 "i8042.c: Unable to get stable CTR read.\n"); 920 return -EIO; 921 } 922 923 if (n != 0) 924 udelay(50); 925 926 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 927 printk(KERN_ERR 928 "i8042.c: Can't read CTR while initializing i8042.\n"); 929 return -EIO; 930 } 931 932 } while (n < 2 || ctr[0] != ctr[1]); 933 934 i8042_initial_ctr = i8042_ctr = ctr[0]; 935 936 /* 937 * Disable the keyboard interface and interrupt. 938 */ 939 940 i8042_ctr |= I8042_CTR_KBDDIS; 941 i8042_ctr &= ~I8042_CTR_KBDINT; 942 943 /* 944 * Handle keylock. 945 */ 946 947 spin_lock_irqsave(&i8042_lock, flags); 948 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 949 if (i8042_unlock) 950 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 951 else 952 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); 953 } 954 spin_unlock_irqrestore(&i8042_lock, flags); 955 956 /* 957 * If the chip is configured into nontranslated mode by the BIOS, don't 958 * bother enabling translating and be happy. 959 */ 960 961 if (~i8042_ctr & I8042_CTR_XLATE) 962 i8042_direct = true; 963 964 /* 965 * Set nontranslated mode for the kbd interface if requested by an option. 966 * After this the kbd interface becomes a simple serial in/out, like the aux 967 * interface is. We don't do this by default, since it can confuse notebook 968 * BIOSes. 969 */ 970 971 if (i8042_direct) 972 i8042_ctr &= ~I8042_CTR_XLATE; 973 974 /* 975 * Write CTR back. 976 */ 977 978 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 979 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); 980 return -EIO; 981 } 982 983 /* 984 * Flush whatever accumulated while we were disabling keyboard port. 985 */ 986 987 i8042_flush(); 988 989 return 0; 990 } 991 992 993 /* 994 * Reset the controller and reset CRT to the original value set by BIOS. 995 */ 996 997 static void i8042_controller_reset(void) 998 { 999 i8042_flush(); 1000 1001 /* 1002 * Disable both KBD and AUX interfaces so they don't get in the way 1003 */ 1004 1005 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1006 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1007 1008 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1009 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); 1010 1011 /* 1012 * Disable MUX mode if present. 1013 */ 1014 1015 if (i8042_mux_present) 1016 i8042_set_mux_mode(false, NULL); 1017 1018 /* 1019 * Reset the controller if requested. 1020 */ 1021 1022 i8042_controller_selftest(); 1023 1024 /* 1025 * Restore the original control register setting. 1026 */ 1027 1028 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1029 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); 1030 } 1031 1032 1033 /* 1034 * i8042_panic_blink() will flash the keyboard LEDs and is called when 1035 * kernel panics. Flashing LEDs is useful for users running X who may 1036 * not see the console and will help distingushing panics from "real" 1037 * lockups. 1038 * 1039 * Note that DELAY has a limit of 10ms so we will not get stuck here 1040 * waiting for KBC to free up even if KBD interrupt is off 1041 */ 1042 1043 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1044 1045 static long i8042_panic_blink(long count) 1046 { 1047 long delay = 0; 1048 static long last_blink; 1049 static char led; 1050 1051 /* 1052 * We expect frequency to be about 1/2s. KDB uses about 1s. 1053 * Make sure they are different. 1054 */ 1055 if (!i8042_blink_frequency) 1056 return 0; 1057 if (count - last_blink < i8042_blink_frequency) 1058 return 0; 1059 1060 led ^= 0x01 | 0x04; 1061 while (i8042_read_status() & I8042_STR_IBF) 1062 DELAY; 1063 dbg("%02x -> i8042 (panic blink)", 0xed); 1064 i8042_suppress_kbd_ack = 2; 1065 i8042_write_data(0xed); /* set leds */ 1066 DELAY; 1067 while (i8042_read_status() & I8042_STR_IBF) 1068 DELAY; 1069 DELAY; 1070 dbg("%02x -> i8042 (panic blink)", led); 1071 i8042_write_data(led); 1072 DELAY; 1073 last_blink = count; 1074 return delay; 1075 } 1076 1077 #undef DELAY 1078 1079 #ifdef CONFIG_X86 1080 static void i8042_dritek_enable(void) 1081 { 1082 char param = 0x90; 1083 int error; 1084 1085 error = i8042_command(¶m, 0x1059); 1086 if (error) 1087 printk(KERN_WARNING 1088 "Failed to enable DRITEK extension: %d\n", 1089 error); 1090 } 1091 #endif 1092 1093 #ifdef CONFIG_PM 1094 1095 /* 1096 * Here we try to restore the original BIOS settings to avoid 1097 * upsetting it. 1098 */ 1099 1100 static int i8042_pm_reset(struct device *dev) 1101 { 1102 i8042_controller_reset(); 1103 1104 return 0; 1105 } 1106 1107 /* 1108 * Here we try to reset everything back to a state we had 1109 * before suspending. 1110 */ 1111 1112 static int i8042_pm_restore(struct device *dev) 1113 { 1114 int error; 1115 1116 error = i8042_controller_check(); 1117 if (error) 1118 return error; 1119 1120 error = i8042_controller_selftest(); 1121 if (error) 1122 return error; 1123 1124 /* 1125 * Restore original CTR value and disable all ports 1126 */ 1127 1128 i8042_ctr = i8042_initial_ctr; 1129 if (i8042_direct) 1130 i8042_ctr &= ~I8042_CTR_XLATE; 1131 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1132 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1133 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1134 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); 1135 msleep(50); 1136 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1137 printk(KERN_ERR "i8042: CTR write retry failed\n"); 1138 return -EIO; 1139 } 1140 } 1141 1142 1143 #ifdef CONFIG_X86 1144 if (i8042_dritek) 1145 i8042_dritek_enable(); 1146 #endif 1147 1148 if (i8042_mux_present) { 1149 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1150 printk(KERN_WARNING 1151 "i8042: failed to resume active multiplexor, " 1152 "mouse won't work.\n"); 1153 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1154 i8042_enable_aux_port(); 1155 1156 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1157 i8042_enable_kbd_port(); 1158 1159 i8042_interrupt(0, NULL); 1160 1161 return 0; 1162 } 1163 1164 static const struct dev_pm_ops i8042_pm_ops = { 1165 .suspend = i8042_pm_reset, 1166 .resume = i8042_pm_restore, 1167 .poweroff = i8042_pm_reset, 1168 .restore = i8042_pm_restore, 1169 }; 1170 1171 #endif /* CONFIG_PM */ 1172 1173 /* 1174 * We need to reset the 8042 back to original mode on system shutdown, 1175 * because otherwise BIOSes will be confused. 1176 */ 1177 1178 static void i8042_shutdown(struct platform_device *dev) 1179 { 1180 i8042_controller_reset(); 1181 } 1182 1183 static int __init i8042_create_kbd_port(void) 1184 { 1185 struct serio *serio; 1186 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1187 1188 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1189 if (!serio) 1190 return -ENOMEM; 1191 1192 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1193 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1194 serio->start = i8042_start; 1195 serio->stop = i8042_stop; 1196 serio->close = i8042_port_close; 1197 serio->port_data = port; 1198 serio->dev.parent = &i8042_platform_device->dev; 1199 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1200 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1201 1202 port->serio = serio; 1203 port->irq = I8042_KBD_IRQ; 1204 1205 return 0; 1206 } 1207 1208 static int __init i8042_create_aux_port(int idx) 1209 { 1210 struct serio *serio; 1211 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1212 struct i8042_port *port = &i8042_ports[port_no]; 1213 1214 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1215 if (!serio) 1216 return -ENOMEM; 1217 1218 serio->id.type = SERIO_8042; 1219 serio->write = i8042_aux_write; 1220 serio->start = i8042_start; 1221 serio->stop = i8042_stop; 1222 serio->port_data = port; 1223 serio->dev.parent = &i8042_platform_device->dev; 1224 if (idx < 0) { 1225 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1226 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1227 serio->close = i8042_port_close; 1228 } else { 1229 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1230 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1231 } 1232 1233 port->serio = serio; 1234 port->mux = idx; 1235 port->irq = I8042_AUX_IRQ; 1236 1237 return 0; 1238 } 1239 1240 static void __init i8042_free_kbd_port(void) 1241 { 1242 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1243 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1244 } 1245 1246 static void __init i8042_free_aux_ports(void) 1247 { 1248 int i; 1249 1250 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1251 kfree(i8042_ports[i].serio); 1252 i8042_ports[i].serio = NULL; 1253 } 1254 } 1255 1256 static void __init i8042_register_ports(void) 1257 { 1258 int i; 1259 1260 for (i = 0; i < I8042_NUM_PORTS; i++) { 1261 if (i8042_ports[i].serio) { 1262 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1263 i8042_ports[i].serio->name, 1264 (unsigned long) I8042_DATA_REG, 1265 (unsigned long) I8042_COMMAND_REG, 1266 i8042_ports[i].irq); 1267 serio_register_port(i8042_ports[i].serio); 1268 } 1269 } 1270 } 1271 1272 static void __devexit i8042_unregister_ports(void) 1273 { 1274 int i; 1275 1276 for (i = 0; i < I8042_NUM_PORTS; i++) { 1277 if (i8042_ports[i].serio) { 1278 serio_unregister_port(i8042_ports[i].serio); 1279 i8042_ports[i].serio = NULL; 1280 } 1281 } 1282 } 1283 1284 /* 1285 * Checks whether port belongs to i8042 controller. 1286 */ 1287 bool i8042_check_port_owner(const struct serio *port) 1288 { 1289 int i; 1290 1291 for (i = 0; i < I8042_NUM_PORTS; i++) 1292 if (i8042_ports[i].serio == port) 1293 return true; 1294 1295 return false; 1296 } 1297 EXPORT_SYMBOL(i8042_check_port_owner); 1298 1299 static void i8042_free_irqs(void) 1300 { 1301 if (i8042_aux_irq_registered) 1302 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1303 if (i8042_kbd_irq_registered) 1304 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1305 1306 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1307 } 1308 1309 static int __init i8042_setup_aux(void) 1310 { 1311 int (*aux_enable)(void); 1312 int error; 1313 int i; 1314 1315 if (i8042_check_aux()) 1316 return -ENODEV; 1317 1318 if (i8042_nomux || i8042_check_mux()) { 1319 error = i8042_create_aux_port(-1); 1320 if (error) 1321 goto err_free_ports; 1322 aux_enable = i8042_enable_aux_port; 1323 } else { 1324 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1325 error = i8042_create_aux_port(i); 1326 if (error) 1327 goto err_free_ports; 1328 } 1329 aux_enable = i8042_enable_mux_ports; 1330 } 1331 1332 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1333 "i8042", i8042_platform_device); 1334 if (error) 1335 goto err_free_ports; 1336 1337 if (aux_enable()) 1338 goto err_free_irq; 1339 1340 i8042_aux_irq_registered = true; 1341 return 0; 1342 1343 err_free_irq: 1344 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1345 err_free_ports: 1346 i8042_free_aux_ports(); 1347 return error; 1348 } 1349 1350 static int __init i8042_setup_kbd(void) 1351 { 1352 int error; 1353 1354 error = i8042_create_kbd_port(); 1355 if (error) 1356 return error; 1357 1358 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1359 "i8042", i8042_platform_device); 1360 if (error) 1361 goto err_free_port; 1362 1363 error = i8042_enable_kbd_port(); 1364 if (error) 1365 goto err_free_irq; 1366 1367 i8042_kbd_irq_registered = true; 1368 return 0; 1369 1370 err_free_irq: 1371 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1372 err_free_port: 1373 i8042_free_kbd_port(); 1374 return error; 1375 } 1376 1377 static int __init i8042_probe(struct platform_device *dev) 1378 { 1379 int error; 1380 1381 error = i8042_controller_selftest(); 1382 if (error) 1383 return error; 1384 1385 error = i8042_controller_init(); 1386 if (error) 1387 return error; 1388 1389 #ifdef CONFIG_X86 1390 if (i8042_dritek) 1391 i8042_dritek_enable(); 1392 #endif 1393 1394 if (!i8042_noaux) { 1395 error = i8042_setup_aux(); 1396 if (error && error != -ENODEV && error != -EBUSY) 1397 goto out_fail; 1398 } 1399 1400 if (!i8042_nokbd) { 1401 error = i8042_setup_kbd(); 1402 if (error) 1403 goto out_fail; 1404 } 1405 /* 1406 * Ok, everything is ready, let's register all serio ports 1407 */ 1408 i8042_register_ports(); 1409 1410 return 0; 1411 1412 out_fail: 1413 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1414 i8042_free_irqs(); 1415 i8042_controller_reset(); 1416 1417 return error; 1418 } 1419 1420 static int __devexit i8042_remove(struct platform_device *dev) 1421 { 1422 i8042_unregister_ports(); 1423 i8042_free_irqs(); 1424 i8042_controller_reset(); 1425 1426 return 0; 1427 } 1428 1429 static struct platform_driver i8042_driver = { 1430 .driver = { 1431 .name = "i8042", 1432 .owner = THIS_MODULE, 1433 #ifdef CONFIG_PM 1434 .pm = &i8042_pm_ops, 1435 #endif 1436 }, 1437 .remove = __devexit_p(i8042_remove), 1438 .shutdown = i8042_shutdown, 1439 }; 1440 1441 static int __init i8042_init(void) 1442 { 1443 int err; 1444 1445 dbg_init(); 1446 1447 err = i8042_platform_init(); 1448 if (err) 1449 return err; 1450 1451 err = i8042_controller_check(); 1452 if (err) 1453 goto err_platform_exit; 1454 1455 i8042_platform_device = platform_device_alloc("i8042", -1); 1456 if (!i8042_platform_device) { 1457 err = -ENOMEM; 1458 goto err_platform_exit; 1459 } 1460 1461 err = platform_device_add(i8042_platform_device); 1462 if (err) 1463 goto err_free_device; 1464 1465 err = platform_driver_probe(&i8042_driver, i8042_probe); 1466 if (err) 1467 goto err_del_device; 1468 1469 panic_blink = i8042_panic_blink; 1470 1471 return 0; 1472 1473 err_del_device: 1474 platform_device_del(i8042_platform_device); 1475 err_free_device: 1476 platform_device_put(i8042_platform_device); 1477 err_platform_exit: 1478 i8042_platform_exit(); 1479 1480 return err; 1481 } 1482 1483 static void __exit i8042_exit(void) 1484 { 1485 platform_driver_unregister(&i8042_driver); 1486 platform_device_unregister(i8042_platform_device); 1487 i8042_platform_exit(); 1488 1489 panic_blink = NULL; 1490 } 1491 1492 module_init(i8042_init); 1493 module_exit(i8042_exit); 1494