1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/init.h> 19 #include <linux/serio.h> 20 #include <linux/err.h> 21 #include <linux/rcupdate.h> 22 #include <linux/platform_device.h> 23 #include <linux/i8042.h> 24 #include <linux/slab.h> 25 26 #include <asm/io.h> 27 28 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 29 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 30 MODULE_LICENSE("GPL"); 31 32 static bool i8042_nokbd; 33 module_param_named(nokbd, i8042_nokbd, bool, 0); 34 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 35 36 static bool i8042_noaux; 37 module_param_named(noaux, i8042_noaux, bool, 0); 38 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 39 40 static bool i8042_nomux; 41 module_param_named(nomux, i8042_nomux, bool, 0); 42 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 43 44 static bool i8042_unlock; 45 module_param_named(unlock, i8042_unlock, bool, 0); 46 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 47 48 static bool i8042_reset; 49 module_param_named(reset, i8042_reset, bool, 0); 50 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 51 52 static bool i8042_direct; 53 module_param_named(direct, i8042_direct, bool, 0); 54 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 55 56 static bool i8042_dumbkbd; 57 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 58 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 59 60 static bool i8042_noloop; 61 module_param_named(noloop, i8042_noloop, bool, 0); 62 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 63 64 static unsigned int i8042_blink_frequency = 500; 65 module_param_named(panicblink, i8042_blink_frequency, uint, 0600); 66 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); 67 68 #ifdef CONFIG_X86 69 static bool i8042_dritek; 70 module_param_named(dritek, i8042_dritek, bool, 0); 71 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 72 #endif 73 74 #ifdef CONFIG_PNP 75 static bool i8042_nopnp; 76 module_param_named(nopnp, i8042_nopnp, bool, 0); 77 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 78 #endif 79 80 #define DEBUG 81 #ifdef DEBUG 82 static bool i8042_debug; 83 module_param_named(debug, i8042_debug, bool, 0600); 84 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 85 #endif 86 87 static bool i8042_bypass_aux_irq_test; 88 89 #include "i8042.h" 90 91 /* 92 * i8042_lock protects serialization between i8042_command and 93 * the interrupt handler. 94 */ 95 static DEFINE_SPINLOCK(i8042_lock); 96 97 /* 98 * Writers to AUX and KBD ports as well as users issuing i8042_command 99 * directly should acquire i8042_mutex (by means of calling 100 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 101 * they do not disturb each other (unfortunately in many i8042 102 * implementations write to one of the ports will immediately abort 103 * command that is being processed by another port). 104 */ 105 static DEFINE_MUTEX(i8042_mutex); 106 107 struct i8042_port { 108 struct serio *serio; 109 int irq; 110 bool exists; 111 signed char mux; 112 }; 113 114 #define I8042_KBD_PORT_NO 0 115 #define I8042_AUX_PORT_NO 1 116 #define I8042_MUX_PORT_NO 2 117 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 118 119 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 120 121 static unsigned char i8042_initial_ctr; 122 static unsigned char i8042_ctr; 123 static bool i8042_mux_present; 124 static bool i8042_kbd_irq_registered; 125 static bool i8042_aux_irq_registered; 126 static unsigned char i8042_suppress_kbd_ack; 127 static struct platform_device *i8042_platform_device; 128 129 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 130 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 131 struct serio *serio); 132 133 void i8042_lock_chip(void) 134 { 135 mutex_lock(&i8042_mutex); 136 } 137 EXPORT_SYMBOL(i8042_lock_chip); 138 139 void i8042_unlock_chip(void) 140 { 141 mutex_unlock(&i8042_mutex); 142 } 143 EXPORT_SYMBOL(i8042_unlock_chip); 144 145 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 146 struct serio *serio)) 147 { 148 unsigned long flags; 149 int ret = 0; 150 151 spin_lock_irqsave(&i8042_lock, flags); 152 153 if (i8042_platform_filter) { 154 ret = -EBUSY; 155 goto out; 156 } 157 158 i8042_platform_filter = filter; 159 160 out: 161 spin_unlock_irqrestore(&i8042_lock, flags); 162 return ret; 163 } 164 EXPORT_SYMBOL(i8042_install_filter); 165 166 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 167 struct serio *port)) 168 { 169 unsigned long flags; 170 int ret = 0; 171 172 spin_lock_irqsave(&i8042_lock, flags); 173 174 if (i8042_platform_filter != filter) { 175 ret = -EINVAL; 176 goto out; 177 } 178 179 i8042_platform_filter = NULL; 180 181 out: 182 spin_unlock_irqrestore(&i8042_lock, flags); 183 return ret; 184 } 185 EXPORT_SYMBOL(i8042_remove_filter); 186 187 /* 188 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 189 * be ready for reading values from it / writing values to it. 190 * Called always with i8042_lock held. 191 */ 192 193 static int i8042_wait_read(void) 194 { 195 int i = 0; 196 197 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 198 udelay(50); 199 i++; 200 } 201 return -(i == I8042_CTL_TIMEOUT); 202 } 203 204 static int i8042_wait_write(void) 205 { 206 int i = 0; 207 208 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 209 udelay(50); 210 i++; 211 } 212 return -(i == I8042_CTL_TIMEOUT); 213 } 214 215 /* 216 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 217 * of the i8042 down the toilet. 218 */ 219 220 static int i8042_flush(void) 221 { 222 unsigned long flags; 223 unsigned char data, str; 224 int i = 0; 225 226 spin_lock_irqsave(&i8042_lock, flags); 227 228 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 229 udelay(50); 230 data = i8042_read_data(); 231 i++; 232 dbg("%02x <- i8042 (flush, %s)", data, 233 str & I8042_STR_AUXDATA ? "aux" : "kbd"); 234 } 235 236 spin_unlock_irqrestore(&i8042_lock, flags); 237 238 return i; 239 } 240 241 /* 242 * i8042_command() executes a command on the i8042. It also sends the input 243 * parameter(s) of the commands to it, and receives the output value(s). The 244 * parameters are to be stored in the param array, and the output is placed 245 * into the same array. The number of the parameters and output values is 246 * encoded in bits 8-11 of the command number. 247 */ 248 249 static int __i8042_command(unsigned char *param, int command) 250 { 251 int i, error; 252 253 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 254 return -1; 255 256 error = i8042_wait_write(); 257 if (error) 258 return error; 259 260 dbg("%02x -> i8042 (command)", command & 0xff); 261 i8042_write_command(command & 0xff); 262 263 for (i = 0; i < ((command >> 12) & 0xf); i++) { 264 error = i8042_wait_write(); 265 if (error) 266 return error; 267 dbg("%02x -> i8042 (parameter)", param[i]); 268 i8042_write_data(param[i]); 269 } 270 271 for (i = 0; i < ((command >> 8) & 0xf); i++) { 272 error = i8042_wait_read(); 273 if (error) { 274 dbg(" -- i8042 (timeout)"); 275 return error; 276 } 277 278 if (command == I8042_CMD_AUX_LOOP && 279 !(i8042_read_status() & I8042_STR_AUXDATA)) { 280 dbg(" -- i8042 (auxerr)"); 281 return -1; 282 } 283 284 param[i] = i8042_read_data(); 285 dbg("%02x <- i8042 (return)", param[i]); 286 } 287 288 return 0; 289 } 290 291 int i8042_command(unsigned char *param, int command) 292 { 293 unsigned long flags; 294 int retval; 295 296 spin_lock_irqsave(&i8042_lock, flags); 297 retval = __i8042_command(param, command); 298 spin_unlock_irqrestore(&i8042_lock, flags); 299 300 return retval; 301 } 302 EXPORT_SYMBOL(i8042_command); 303 304 /* 305 * i8042_kbd_write() sends a byte out through the keyboard interface. 306 */ 307 308 static int i8042_kbd_write(struct serio *port, unsigned char c) 309 { 310 unsigned long flags; 311 int retval = 0; 312 313 spin_lock_irqsave(&i8042_lock, flags); 314 315 if (!(retval = i8042_wait_write())) { 316 dbg("%02x -> i8042 (kbd-data)", c); 317 i8042_write_data(c); 318 } 319 320 spin_unlock_irqrestore(&i8042_lock, flags); 321 322 return retval; 323 } 324 325 /* 326 * i8042_aux_write() sends a byte out through the aux interface. 327 */ 328 329 static int i8042_aux_write(struct serio *serio, unsigned char c) 330 { 331 struct i8042_port *port = serio->port_data; 332 333 return i8042_command(&c, port->mux == -1 ? 334 I8042_CMD_AUX_SEND : 335 I8042_CMD_MUX_SEND + port->mux); 336 } 337 338 339 /* 340 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 341 * and then re-enabling it. 342 */ 343 344 static void i8042_port_close(struct serio *serio) 345 { 346 int irq_bit; 347 int disable_bit; 348 const char *port_name; 349 350 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 351 irq_bit = I8042_CTR_AUXINT; 352 disable_bit = I8042_CTR_AUXDIS; 353 port_name = "AUX"; 354 } else { 355 irq_bit = I8042_CTR_KBDINT; 356 disable_bit = I8042_CTR_KBDDIS; 357 port_name = "KBD"; 358 } 359 360 i8042_ctr &= ~irq_bit; 361 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 362 printk(KERN_WARNING 363 "i8042.c: Can't write CTR while closing %s port.\n", 364 port_name); 365 366 udelay(50); 367 368 i8042_ctr &= ~disable_bit; 369 i8042_ctr |= irq_bit; 370 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 371 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", 372 port_name); 373 374 /* 375 * See if there is any data appeared while we were messing with 376 * port state. 377 */ 378 i8042_interrupt(0, NULL); 379 } 380 381 /* 382 * i8042_start() is called by serio core when port is about to finish 383 * registering. It will mark port as existing so i8042_interrupt can 384 * start sending data through it. 385 */ 386 static int i8042_start(struct serio *serio) 387 { 388 struct i8042_port *port = serio->port_data; 389 390 port->exists = true; 391 mb(); 392 return 0; 393 } 394 395 /* 396 * i8042_stop() marks serio port as non-existing so i8042_interrupt 397 * will not try to send data to the port that is about to go away. 398 * The function is called by serio core as part of unregister procedure. 399 */ 400 static void i8042_stop(struct serio *serio) 401 { 402 struct i8042_port *port = serio->port_data; 403 404 port->exists = false; 405 406 /* 407 * We synchronize with both AUX and KBD IRQs because there is 408 * a (very unlikely) chance that AUX IRQ is raised for KBD port 409 * and vice versa. 410 */ 411 synchronize_irq(I8042_AUX_IRQ); 412 synchronize_irq(I8042_KBD_IRQ); 413 port->serio = NULL; 414 } 415 416 /* 417 * i8042_filter() filters out unwanted bytes from the input data stream. 418 * It is called from i8042_interrupt and thus is running with interrupts 419 * off and i8042_lock held. 420 */ 421 static bool i8042_filter(unsigned char data, unsigned char str, 422 struct serio *serio) 423 { 424 if (unlikely(i8042_suppress_kbd_ack)) { 425 if ((~str & I8042_STR_AUXDATA) && 426 (data == 0xfa || data == 0xfe)) { 427 i8042_suppress_kbd_ack--; 428 dbg("Extra keyboard ACK - filtered out\n"); 429 return true; 430 } 431 } 432 433 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 434 dbg("Filtered out by platform filter\n"); 435 return true; 436 } 437 438 return false; 439 } 440 441 /* 442 * i8042_interrupt() is the most important function in this driver - 443 * it handles the interrupts from the i8042, and sends incoming bytes 444 * to the upper layers. 445 */ 446 447 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 448 { 449 struct i8042_port *port; 450 struct serio *serio; 451 unsigned long flags; 452 unsigned char str, data; 453 unsigned int dfl; 454 unsigned int port_no; 455 bool filtered; 456 int ret = 1; 457 458 spin_lock_irqsave(&i8042_lock, flags); 459 460 str = i8042_read_status(); 461 if (unlikely(~str & I8042_STR_OBF)) { 462 spin_unlock_irqrestore(&i8042_lock, flags); 463 if (irq) dbg("Interrupt %d, without any data", irq); 464 ret = 0; 465 goto out; 466 } 467 468 data = i8042_read_data(); 469 470 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 471 static unsigned long last_transmit; 472 static unsigned char last_str; 473 474 dfl = 0; 475 if (str & I8042_STR_MUXERR) { 476 dbg("MUX error, status is %02x, data is %02x", str, data); 477 /* 478 * When MUXERR condition is signalled the data register can only contain 479 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 480 * it is not always the case. Some KBCs also report 0xfc when there is 481 * nothing connected to the port while others sometimes get confused which 482 * port the data came from and signal error leaving the data intact. They 483 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 484 * to legacy mode yet, when we see one we'll add proper handling). 485 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 486 * rest assume that the data came from the same serio last byte 487 * was transmitted (if transmission happened not too long ago). 488 */ 489 490 switch (data) { 491 default: 492 if (time_before(jiffies, last_transmit + HZ/10)) { 493 str = last_str; 494 break; 495 } 496 /* fall through - report timeout */ 497 case 0xfc: 498 case 0xfd: 499 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 500 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 501 } 502 } 503 504 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 505 last_str = str; 506 last_transmit = jiffies; 507 } else { 508 509 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 510 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); 511 512 port_no = (str & I8042_STR_AUXDATA) ? 513 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 514 } 515 516 port = &i8042_ports[port_no]; 517 serio = port->exists ? port->serio : NULL; 518 519 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", 520 data, port_no, irq, 521 dfl & SERIO_PARITY ? ", bad parity" : "", 522 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 523 524 filtered = i8042_filter(data, str, serio); 525 526 spin_unlock_irqrestore(&i8042_lock, flags); 527 528 if (likely(port->exists && !filtered)) 529 serio_interrupt(serio, data, dfl); 530 531 out: 532 return IRQ_RETVAL(ret); 533 } 534 535 /* 536 * i8042_enable_kbd_port enables keyboard port on chip 537 */ 538 539 static int i8042_enable_kbd_port(void) 540 { 541 i8042_ctr &= ~I8042_CTR_KBDDIS; 542 i8042_ctr |= I8042_CTR_KBDINT; 543 544 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 545 i8042_ctr &= ~I8042_CTR_KBDINT; 546 i8042_ctr |= I8042_CTR_KBDDIS; 547 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); 548 return -EIO; 549 } 550 551 return 0; 552 } 553 554 /* 555 * i8042_enable_aux_port enables AUX (mouse) port on chip 556 */ 557 558 static int i8042_enable_aux_port(void) 559 { 560 i8042_ctr &= ~I8042_CTR_AUXDIS; 561 i8042_ctr |= I8042_CTR_AUXINT; 562 563 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 564 i8042_ctr &= ~I8042_CTR_AUXINT; 565 i8042_ctr |= I8042_CTR_AUXDIS; 566 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); 567 return -EIO; 568 } 569 570 return 0; 571 } 572 573 /* 574 * i8042_enable_mux_ports enables 4 individual AUX ports after 575 * the controller has been switched into Multiplexed mode 576 */ 577 578 static int i8042_enable_mux_ports(void) 579 { 580 unsigned char param; 581 int i; 582 583 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 584 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 585 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 586 } 587 588 return i8042_enable_aux_port(); 589 } 590 591 /* 592 * i8042_set_mux_mode checks whether the controller has an 593 * active multiplexor and puts the chip into Multiplexed (true) 594 * or Legacy (false) mode. 595 */ 596 597 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 598 { 599 600 unsigned char param, val; 601 /* 602 * Get rid of bytes in the queue. 603 */ 604 605 i8042_flush(); 606 607 /* 608 * Internal loopback test - send three bytes, they should come back from the 609 * mouse interface, the last should be version. 610 */ 611 612 param = val = 0xf0; 613 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 614 return -1; 615 param = val = multiplex ? 0x56 : 0xf6; 616 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 617 return -1; 618 param = val = multiplex ? 0xa4 : 0xa5; 619 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 620 return -1; 621 622 /* 623 * Workaround for interference with USB Legacy emulation 624 * that causes a v10.12 MUX to be found. 625 */ 626 if (param == 0xac) 627 return -1; 628 629 if (mux_version) 630 *mux_version = param; 631 632 return 0; 633 } 634 635 /* 636 * i8042_check_mux() checks whether the controller supports the PS/2 Active 637 * Multiplexing specification by Synaptics, Phoenix, Insyde and 638 * LCS/Telegraphics. 639 */ 640 641 static int __init i8042_check_mux(void) 642 { 643 unsigned char mux_version; 644 645 if (i8042_set_mux_mode(true, &mux_version)) 646 return -1; 647 648 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", 649 (mux_version >> 4) & 0xf, mux_version & 0xf); 650 651 /* 652 * Disable all muxed ports by disabling AUX. 653 */ 654 i8042_ctr |= I8042_CTR_AUXDIS; 655 i8042_ctr &= ~I8042_CTR_AUXINT; 656 657 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 658 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); 659 return -EIO; 660 } 661 662 i8042_mux_present = true; 663 664 return 0; 665 } 666 667 /* 668 * The following is used to test AUX IRQ delivery. 669 */ 670 static struct completion i8042_aux_irq_delivered __initdata; 671 static bool i8042_irq_being_tested __initdata; 672 673 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 674 { 675 unsigned long flags; 676 unsigned char str, data; 677 int ret = 0; 678 679 spin_lock_irqsave(&i8042_lock, flags); 680 str = i8042_read_status(); 681 if (str & I8042_STR_OBF) { 682 data = i8042_read_data(); 683 dbg("%02x <- i8042 (aux_test_irq, %s)", 684 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 685 if (i8042_irq_being_tested && 686 data == 0xa5 && (str & I8042_STR_AUXDATA)) 687 complete(&i8042_aux_irq_delivered); 688 ret = 1; 689 } 690 spin_unlock_irqrestore(&i8042_lock, flags); 691 692 return IRQ_RETVAL(ret); 693 } 694 695 /* 696 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 697 * verifies success by readinng CTR. Used when testing for presence of AUX 698 * port. 699 */ 700 static int __init i8042_toggle_aux(bool on) 701 { 702 unsigned char param; 703 int i; 704 705 if (i8042_command(¶m, 706 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 707 return -1; 708 709 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 710 for (i = 0; i < 100; i++) { 711 udelay(50); 712 713 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 714 return -1; 715 716 if (!(param & I8042_CTR_AUXDIS) == on) 717 return 0; 718 } 719 720 return -1; 721 } 722 723 /* 724 * i8042_check_aux() applies as much paranoia as it can at detecting 725 * the presence of an AUX interface. 726 */ 727 728 static int __init i8042_check_aux(void) 729 { 730 int retval = -1; 731 bool irq_registered = false; 732 bool aux_loop_broken = false; 733 unsigned long flags; 734 unsigned char param; 735 736 /* 737 * Get rid of bytes in the queue. 738 */ 739 740 i8042_flush(); 741 742 /* 743 * Internal loopback test - filters out AT-type i8042's. Unfortunately 744 * SiS screwed up and their 5597 doesn't support the LOOP command even 745 * though it has an AUX port. 746 */ 747 748 param = 0x5a; 749 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 750 if (retval || param != 0x5a) { 751 752 /* 753 * External connection test - filters out AT-soldered PS/2 i8042's 754 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 755 * 0xfa - no error on some notebooks which ignore the spec 756 * Because it's common for chipsets to return error on perfectly functioning 757 * AUX ports, we test for this only when the LOOP command failed. 758 */ 759 760 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 761 (param && param != 0xfa && param != 0xff)) 762 return -1; 763 764 /* 765 * If AUX_LOOP completed without error but returned unexpected data 766 * mark it as broken 767 */ 768 if (!retval) 769 aux_loop_broken = true; 770 } 771 772 /* 773 * Bit assignment test - filters out PS/2 i8042's in AT mode 774 */ 775 776 if (i8042_toggle_aux(false)) { 777 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 778 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); 779 } 780 781 if (i8042_toggle_aux(true)) 782 return -1; 783 784 /* 785 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 786 * used it for a PCI card or somethig else. 787 */ 788 789 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 790 /* 791 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 792 * is working and hope we are right. 793 */ 794 retval = 0; 795 goto out; 796 } 797 798 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 799 "i8042", i8042_platform_device)) 800 goto out; 801 802 irq_registered = true; 803 804 if (i8042_enable_aux_port()) 805 goto out; 806 807 spin_lock_irqsave(&i8042_lock, flags); 808 809 init_completion(&i8042_aux_irq_delivered); 810 i8042_irq_being_tested = true; 811 812 param = 0xa5; 813 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 814 815 spin_unlock_irqrestore(&i8042_lock, flags); 816 817 if (retval) 818 goto out; 819 820 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 821 msecs_to_jiffies(250)) == 0) { 822 /* 823 * AUX IRQ was never delivered so we need to flush the controller to 824 * get rid of the byte we put there; otherwise keyboard may not work. 825 */ 826 dbg(" -- i8042 (aux irq test timeout)"); 827 i8042_flush(); 828 retval = -1; 829 } 830 831 out: 832 833 /* 834 * Disable the interface. 835 */ 836 837 i8042_ctr |= I8042_CTR_AUXDIS; 838 i8042_ctr &= ~I8042_CTR_AUXINT; 839 840 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 841 retval = -1; 842 843 if (irq_registered) 844 free_irq(I8042_AUX_IRQ, i8042_platform_device); 845 846 return retval; 847 } 848 849 static int i8042_controller_check(void) 850 { 851 if (i8042_flush() == I8042_BUFFER_SIZE) { 852 printk(KERN_ERR "i8042.c: No controller found.\n"); 853 return -ENODEV; 854 } 855 856 return 0; 857 } 858 859 static int i8042_controller_selftest(void) 860 { 861 unsigned char param; 862 int i = 0; 863 864 if (!i8042_reset) 865 return 0; 866 867 /* 868 * We try this 5 times; on some really fragile systems this does not 869 * take the first time... 870 */ 871 do { 872 873 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 874 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); 875 return -ENODEV; 876 } 877 878 if (param == I8042_RET_CTL_TEST) 879 return 0; 880 881 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", 882 param, I8042_RET_CTL_TEST); 883 msleep(50); 884 } while (i++ < 5); 885 886 #ifdef CONFIG_X86 887 /* 888 * On x86, we don't fail entire i8042 initialization if controller 889 * reset fails in hopes that keyboard port will still be functional 890 * and user will still get a working keyboard. This is especially 891 * important on netbooks. On other arches we trust hardware more. 892 */ 893 printk(KERN_INFO 894 "i8042: giving up on controller selftest, continuing anyway...\n"); 895 return 0; 896 #else 897 return -EIO; 898 #endif 899 } 900 901 /* 902 * i8042_controller init initializes the i8042 controller, and, 903 * most importantly, sets it into non-xlated mode if that's 904 * desired. 905 */ 906 907 static int i8042_controller_init(void) 908 { 909 unsigned long flags; 910 int n = 0; 911 unsigned char ctr[2]; 912 913 /* 914 * Save the CTR for restore on unload / reboot. 915 */ 916 917 do { 918 if (n >= 10) { 919 printk(KERN_ERR 920 "i8042.c: Unable to get stable CTR read.\n"); 921 return -EIO; 922 } 923 924 if (n != 0) 925 udelay(50); 926 927 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 928 printk(KERN_ERR 929 "i8042.c: Can't read CTR while initializing i8042.\n"); 930 return -EIO; 931 } 932 933 } while (n < 2 || ctr[0] != ctr[1]); 934 935 i8042_initial_ctr = i8042_ctr = ctr[0]; 936 937 /* 938 * Disable the keyboard interface and interrupt. 939 */ 940 941 i8042_ctr |= I8042_CTR_KBDDIS; 942 i8042_ctr &= ~I8042_CTR_KBDINT; 943 944 /* 945 * Handle keylock. 946 */ 947 948 spin_lock_irqsave(&i8042_lock, flags); 949 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 950 if (i8042_unlock) 951 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 952 else 953 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); 954 } 955 spin_unlock_irqrestore(&i8042_lock, flags); 956 957 /* 958 * If the chip is configured into nontranslated mode by the BIOS, don't 959 * bother enabling translating and be happy. 960 */ 961 962 if (~i8042_ctr & I8042_CTR_XLATE) 963 i8042_direct = true; 964 965 /* 966 * Set nontranslated mode for the kbd interface if requested by an option. 967 * After this the kbd interface becomes a simple serial in/out, like the aux 968 * interface is. We don't do this by default, since it can confuse notebook 969 * BIOSes. 970 */ 971 972 if (i8042_direct) 973 i8042_ctr &= ~I8042_CTR_XLATE; 974 975 /* 976 * Write CTR back. 977 */ 978 979 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 980 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); 981 return -EIO; 982 } 983 984 /* 985 * Flush whatever accumulated while we were disabling keyboard port. 986 */ 987 988 i8042_flush(); 989 990 return 0; 991 } 992 993 994 /* 995 * Reset the controller and reset CRT to the original value set by BIOS. 996 */ 997 998 static void i8042_controller_reset(void) 999 { 1000 i8042_flush(); 1001 1002 /* 1003 * Disable both KBD and AUX interfaces so they don't get in the way 1004 */ 1005 1006 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1007 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1008 1009 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1010 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); 1011 1012 /* 1013 * Disable MUX mode if present. 1014 */ 1015 1016 if (i8042_mux_present) 1017 i8042_set_mux_mode(false, NULL); 1018 1019 /* 1020 * Reset the controller if requested. 1021 */ 1022 1023 i8042_controller_selftest(); 1024 1025 /* 1026 * Restore the original control register setting. 1027 */ 1028 1029 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1030 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); 1031 } 1032 1033 1034 /* 1035 * i8042_panic_blink() will flash the keyboard LEDs and is called when 1036 * kernel panics. Flashing LEDs is useful for users running X who may 1037 * not see the console and will help distingushing panics from "real" 1038 * lockups. 1039 * 1040 * Note that DELAY has a limit of 10ms so we will not get stuck here 1041 * waiting for KBC to free up even if KBD interrupt is off 1042 */ 1043 1044 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1045 1046 static long i8042_panic_blink(long count) 1047 { 1048 long delay = 0; 1049 static long last_blink; 1050 static char led; 1051 1052 /* 1053 * We expect frequency to be about 1/2s. KDB uses about 1s. 1054 * Make sure they are different. 1055 */ 1056 if (!i8042_blink_frequency) 1057 return 0; 1058 if (count - last_blink < i8042_blink_frequency) 1059 return 0; 1060 1061 led ^= 0x01 | 0x04; 1062 while (i8042_read_status() & I8042_STR_IBF) 1063 DELAY; 1064 dbg("%02x -> i8042 (panic blink)", 0xed); 1065 i8042_suppress_kbd_ack = 2; 1066 i8042_write_data(0xed); /* set leds */ 1067 DELAY; 1068 while (i8042_read_status() & I8042_STR_IBF) 1069 DELAY; 1070 DELAY; 1071 dbg("%02x -> i8042 (panic blink)", led); 1072 i8042_write_data(led); 1073 DELAY; 1074 last_blink = count; 1075 return delay; 1076 } 1077 1078 #undef DELAY 1079 1080 #ifdef CONFIG_X86 1081 static void i8042_dritek_enable(void) 1082 { 1083 char param = 0x90; 1084 int error; 1085 1086 error = i8042_command(¶m, 0x1059); 1087 if (error) 1088 printk(KERN_WARNING 1089 "Failed to enable DRITEK extension: %d\n", 1090 error); 1091 } 1092 #endif 1093 1094 #ifdef CONFIG_PM 1095 1096 /* 1097 * Here we try to restore the original BIOS settings to avoid 1098 * upsetting it. 1099 */ 1100 1101 static int i8042_pm_reset(struct device *dev) 1102 { 1103 i8042_controller_reset(); 1104 1105 return 0; 1106 } 1107 1108 /* 1109 * Here we try to reset everything back to a state we had 1110 * before suspending. 1111 */ 1112 1113 static int i8042_pm_restore(struct device *dev) 1114 { 1115 int error; 1116 1117 error = i8042_controller_check(); 1118 if (error) 1119 return error; 1120 1121 error = i8042_controller_selftest(); 1122 if (error) 1123 return error; 1124 1125 /* 1126 * Restore original CTR value and disable all ports 1127 */ 1128 1129 i8042_ctr = i8042_initial_ctr; 1130 if (i8042_direct) 1131 i8042_ctr &= ~I8042_CTR_XLATE; 1132 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1133 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1134 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1135 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); 1136 msleep(50); 1137 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1138 printk(KERN_ERR "i8042: CTR write retry failed\n"); 1139 return -EIO; 1140 } 1141 } 1142 1143 1144 #ifdef CONFIG_X86 1145 if (i8042_dritek) 1146 i8042_dritek_enable(); 1147 #endif 1148 1149 if (i8042_mux_present) { 1150 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1151 printk(KERN_WARNING 1152 "i8042: failed to resume active multiplexor, " 1153 "mouse won't work.\n"); 1154 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1155 i8042_enable_aux_port(); 1156 1157 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1158 i8042_enable_kbd_port(); 1159 1160 i8042_interrupt(0, NULL); 1161 1162 return 0; 1163 } 1164 1165 static int i8042_pm_thaw(struct device *dev) 1166 { 1167 i8042_interrupt(0, NULL); 1168 1169 return 0; 1170 } 1171 1172 static const struct dev_pm_ops i8042_pm_ops = { 1173 .suspend = i8042_pm_reset, 1174 .resume = i8042_pm_restore, 1175 .thaw = i8042_pm_thaw, 1176 .poweroff = i8042_pm_reset, 1177 .restore = i8042_pm_restore, 1178 }; 1179 1180 #endif /* CONFIG_PM */ 1181 1182 /* 1183 * We need to reset the 8042 back to original mode on system shutdown, 1184 * because otherwise BIOSes will be confused. 1185 */ 1186 1187 static void i8042_shutdown(struct platform_device *dev) 1188 { 1189 i8042_controller_reset(); 1190 } 1191 1192 static int __init i8042_create_kbd_port(void) 1193 { 1194 struct serio *serio; 1195 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1196 1197 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1198 if (!serio) 1199 return -ENOMEM; 1200 1201 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1202 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1203 serio->start = i8042_start; 1204 serio->stop = i8042_stop; 1205 serio->close = i8042_port_close; 1206 serio->port_data = port; 1207 serio->dev.parent = &i8042_platform_device->dev; 1208 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1209 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1210 1211 port->serio = serio; 1212 port->irq = I8042_KBD_IRQ; 1213 1214 return 0; 1215 } 1216 1217 static int __init i8042_create_aux_port(int idx) 1218 { 1219 struct serio *serio; 1220 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1221 struct i8042_port *port = &i8042_ports[port_no]; 1222 1223 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1224 if (!serio) 1225 return -ENOMEM; 1226 1227 serio->id.type = SERIO_8042; 1228 serio->write = i8042_aux_write; 1229 serio->start = i8042_start; 1230 serio->stop = i8042_stop; 1231 serio->port_data = port; 1232 serio->dev.parent = &i8042_platform_device->dev; 1233 if (idx < 0) { 1234 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1235 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1236 serio->close = i8042_port_close; 1237 } else { 1238 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1239 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1240 } 1241 1242 port->serio = serio; 1243 port->mux = idx; 1244 port->irq = I8042_AUX_IRQ; 1245 1246 return 0; 1247 } 1248 1249 static void __init i8042_free_kbd_port(void) 1250 { 1251 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1252 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1253 } 1254 1255 static void __init i8042_free_aux_ports(void) 1256 { 1257 int i; 1258 1259 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1260 kfree(i8042_ports[i].serio); 1261 i8042_ports[i].serio = NULL; 1262 } 1263 } 1264 1265 static void __init i8042_register_ports(void) 1266 { 1267 int i; 1268 1269 for (i = 0; i < I8042_NUM_PORTS; i++) { 1270 if (i8042_ports[i].serio) { 1271 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1272 i8042_ports[i].serio->name, 1273 (unsigned long) I8042_DATA_REG, 1274 (unsigned long) I8042_COMMAND_REG, 1275 i8042_ports[i].irq); 1276 serio_register_port(i8042_ports[i].serio); 1277 } 1278 } 1279 } 1280 1281 static void __devexit i8042_unregister_ports(void) 1282 { 1283 int i; 1284 1285 for (i = 0; i < I8042_NUM_PORTS; i++) { 1286 if (i8042_ports[i].serio) { 1287 serio_unregister_port(i8042_ports[i].serio); 1288 i8042_ports[i].serio = NULL; 1289 } 1290 } 1291 } 1292 1293 /* 1294 * Checks whether port belongs to i8042 controller. 1295 */ 1296 bool i8042_check_port_owner(const struct serio *port) 1297 { 1298 int i; 1299 1300 for (i = 0; i < I8042_NUM_PORTS; i++) 1301 if (i8042_ports[i].serio == port) 1302 return true; 1303 1304 return false; 1305 } 1306 EXPORT_SYMBOL(i8042_check_port_owner); 1307 1308 static void i8042_free_irqs(void) 1309 { 1310 if (i8042_aux_irq_registered) 1311 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1312 if (i8042_kbd_irq_registered) 1313 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1314 1315 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1316 } 1317 1318 static int __init i8042_setup_aux(void) 1319 { 1320 int (*aux_enable)(void); 1321 int error; 1322 int i; 1323 1324 if (i8042_check_aux()) 1325 return -ENODEV; 1326 1327 if (i8042_nomux || i8042_check_mux()) { 1328 error = i8042_create_aux_port(-1); 1329 if (error) 1330 goto err_free_ports; 1331 aux_enable = i8042_enable_aux_port; 1332 } else { 1333 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1334 error = i8042_create_aux_port(i); 1335 if (error) 1336 goto err_free_ports; 1337 } 1338 aux_enable = i8042_enable_mux_ports; 1339 } 1340 1341 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1342 "i8042", i8042_platform_device); 1343 if (error) 1344 goto err_free_ports; 1345 1346 if (aux_enable()) 1347 goto err_free_irq; 1348 1349 i8042_aux_irq_registered = true; 1350 return 0; 1351 1352 err_free_irq: 1353 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1354 err_free_ports: 1355 i8042_free_aux_ports(); 1356 return error; 1357 } 1358 1359 static int __init i8042_setup_kbd(void) 1360 { 1361 int error; 1362 1363 error = i8042_create_kbd_port(); 1364 if (error) 1365 return error; 1366 1367 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1368 "i8042", i8042_platform_device); 1369 if (error) 1370 goto err_free_port; 1371 1372 error = i8042_enable_kbd_port(); 1373 if (error) 1374 goto err_free_irq; 1375 1376 i8042_kbd_irq_registered = true; 1377 return 0; 1378 1379 err_free_irq: 1380 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1381 err_free_port: 1382 i8042_free_kbd_port(); 1383 return error; 1384 } 1385 1386 static int __init i8042_probe(struct platform_device *dev) 1387 { 1388 int error; 1389 1390 i8042_platform_device = dev; 1391 1392 error = i8042_controller_selftest(); 1393 if (error) 1394 return error; 1395 1396 error = i8042_controller_init(); 1397 if (error) 1398 return error; 1399 1400 #ifdef CONFIG_X86 1401 if (i8042_dritek) 1402 i8042_dritek_enable(); 1403 #endif 1404 1405 if (!i8042_noaux) { 1406 error = i8042_setup_aux(); 1407 if (error && error != -ENODEV && error != -EBUSY) 1408 goto out_fail; 1409 } 1410 1411 if (!i8042_nokbd) { 1412 error = i8042_setup_kbd(); 1413 if (error) 1414 goto out_fail; 1415 } 1416 /* 1417 * Ok, everything is ready, let's register all serio ports 1418 */ 1419 i8042_register_ports(); 1420 1421 return 0; 1422 1423 out_fail: 1424 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1425 i8042_free_irqs(); 1426 i8042_controller_reset(); 1427 i8042_platform_device = NULL; 1428 1429 return error; 1430 } 1431 1432 static int __devexit i8042_remove(struct platform_device *dev) 1433 { 1434 i8042_unregister_ports(); 1435 i8042_free_irqs(); 1436 i8042_controller_reset(); 1437 i8042_platform_device = NULL; 1438 1439 return 0; 1440 } 1441 1442 static struct platform_driver i8042_driver = { 1443 .driver = { 1444 .name = "i8042", 1445 .owner = THIS_MODULE, 1446 #ifdef CONFIG_PM 1447 .pm = &i8042_pm_ops, 1448 #endif 1449 }, 1450 .remove = __devexit_p(i8042_remove), 1451 .shutdown = i8042_shutdown, 1452 }; 1453 1454 static int __init i8042_init(void) 1455 { 1456 struct platform_device *pdev; 1457 int err; 1458 1459 dbg_init(); 1460 1461 err = i8042_platform_init(); 1462 if (err) 1463 return err; 1464 1465 err = i8042_controller_check(); 1466 if (err) 1467 goto err_platform_exit; 1468 1469 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1470 if (IS_ERR(pdev)) { 1471 err = PTR_ERR(pdev); 1472 goto err_platform_exit; 1473 } 1474 1475 panic_blink = i8042_panic_blink; 1476 1477 return 0; 1478 1479 err_platform_exit: 1480 i8042_platform_exit(); 1481 return err; 1482 } 1483 1484 static void __exit i8042_exit(void) 1485 { 1486 platform_driver_unregister(&i8042_driver); 1487 platform_device_unregister(i8042_platform_device); 1488 i8042_platform_exit(); 1489 1490 panic_blink = NULL; 1491 } 1492 1493 module_init(i8042_init); 1494 module_exit(i8042_exit); 1495