1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/types.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/init.h> 21 #include <linux/serio.h> 22 #include <linux/err.h> 23 #include <linux/rcupdate.h> 24 #include <linux/platform_device.h> 25 #include <linux/i8042.h> 26 #include <linux/slab.h> 27 28 #include <asm/io.h> 29 30 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 31 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 32 MODULE_LICENSE("GPL"); 33 34 static bool i8042_nokbd; 35 module_param_named(nokbd, i8042_nokbd, bool, 0); 36 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 37 38 static bool i8042_noaux; 39 module_param_named(noaux, i8042_noaux, bool, 0); 40 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 41 42 static bool i8042_nomux; 43 module_param_named(nomux, i8042_nomux, bool, 0); 44 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 45 46 static bool i8042_unlock; 47 module_param_named(unlock, i8042_unlock, bool, 0); 48 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 49 50 static bool i8042_reset; 51 module_param_named(reset, i8042_reset, bool, 0); 52 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 53 54 static bool i8042_direct; 55 module_param_named(direct, i8042_direct, bool, 0); 56 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 57 58 static bool i8042_dumbkbd; 59 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 60 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 61 62 static bool i8042_noloop; 63 module_param_named(noloop, i8042_noloop, bool, 0); 64 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 65 66 static bool i8042_notimeout; 67 module_param_named(notimeout, i8042_notimeout, bool, 0); 68 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 69 70 #ifdef CONFIG_X86 71 static bool i8042_dritek; 72 module_param_named(dritek, i8042_dritek, bool, 0); 73 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 74 #endif 75 76 #ifdef CONFIG_PNP 77 static bool i8042_nopnp; 78 module_param_named(nopnp, i8042_nopnp, bool, 0); 79 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 80 #endif 81 82 #define DEBUG 83 #ifdef DEBUG 84 static bool i8042_debug; 85 module_param_named(debug, i8042_debug, bool, 0600); 86 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 87 #endif 88 89 static bool i8042_bypass_aux_irq_test; 90 91 #include "i8042.h" 92 93 /* 94 * i8042_lock protects serialization between i8042_command and 95 * the interrupt handler. 96 */ 97 static DEFINE_SPINLOCK(i8042_lock); 98 99 /* 100 * Writers to AUX and KBD ports as well as users issuing i8042_command 101 * directly should acquire i8042_mutex (by means of calling 102 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 103 * they do not disturb each other (unfortunately in many i8042 104 * implementations write to one of the ports will immediately abort 105 * command that is being processed by another port). 106 */ 107 static DEFINE_MUTEX(i8042_mutex); 108 109 struct i8042_port { 110 struct serio *serio; 111 int irq; 112 bool exists; 113 signed char mux; 114 }; 115 116 #define I8042_KBD_PORT_NO 0 117 #define I8042_AUX_PORT_NO 1 118 #define I8042_MUX_PORT_NO 2 119 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 120 121 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 122 123 static unsigned char i8042_initial_ctr; 124 static unsigned char i8042_ctr; 125 static bool i8042_mux_present; 126 static bool i8042_kbd_irq_registered; 127 static bool i8042_aux_irq_registered; 128 static unsigned char i8042_suppress_kbd_ack; 129 static struct platform_device *i8042_platform_device; 130 131 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 132 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 133 struct serio *serio); 134 135 void i8042_lock_chip(void) 136 { 137 mutex_lock(&i8042_mutex); 138 } 139 EXPORT_SYMBOL(i8042_lock_chip); 140 141 void i8042_unlock_chip(void) 142 { 143 mutex_unlock(&i8042_mutex); 144 } 145 EXPORT_SYMBOL(i8042_unlock_chip); 146 147 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 148 struct serio *serio)) 149 { 150 unsigned long flags; 151 int ret = 0; 152 153 spin_lock_irqsave(&i8042_lock, flags); 154 155 if (i8042_platform_filter) { 156 ret = -EBUSY; 157 goto out; 158 } 159 160 i8042_platform_filter = filter; 161 162 out: 163 spin_unlock_irqrestore(&i8042_lock, flags); 164 return ret; 165 } 166 EXPORT_SYMBOL(i8042_install_filter); 167 168 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 169 struct serio *port)) 170 { 171 unsigned long flags; 172 int ret = 0; 173 174 spin_lock_irqsave(&i8042_lock, flags); 175 176 if (i8042_platform_filter != filter) { 177 ret = -EINVAL; 178 goto out; 179 } 180 181 i8042_platform_filter = NULL; 182 183 out: 184 spin_unlock_irqrestore(&i8042_lock, flags); 185 return ret; 186 } 187 EXPORT_SYMBOL(i8042_remove_filter); 188 189 /* 190 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 191 * be ready for reading values from it / writing values to it. 192 * Called always with i8042_lock held. 193 */ 194 195 static int i8042_wait_read(void) 196 { 197 int i = 0; 198 199 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 200 udelay(50); 201 i++; 202 } 203 return -(i == I8042_CTL_TIMEOUT); 204 } 205 206 static int i8042_wait_write(void) 207 { 208 int i = 0; 209 210 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 211 udelay(50); 212 i++; 213 } 214 return -(i == I8042_CTL_TIMEOUT); 215 } 216 217 /* 218 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 219 * of the i8042 down the toilet. 220 */ 221 222 static int i8042_flush(void) 223 { 224 unsigned long flags; 225 unsigned char data, str; 226 int i = 0; 227 228 spin_lock_irqsave(&i8042_lock, flags); 229 230 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 231 udelay(50); 232 data = i8042_read_data(); 233 i++; 234 dbg("%02x <- i8042 (flush, %s)\n", 235 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 236 } 237 238 spin_unlock_irqrestore(&i8042_lock, flags); 239 240 return i; 241 } 242 243 /* 244 * i8042_command() executes a command on the i8042. It also sends the input 245 * parameter(s) of the commands to it, and receives the output value(s). The 246 * parameters are to be stored in the param array, and the output is placed 247 * into the same array. The number of the parameters and output values is 248 * encoded in bits 8-11 of the command number. 249 */ 250 251 static int __i8042_command(unsigned char *param, int command) 252 { 253 int i, error; 254 255 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 256 return -1; 257 258 error = i8042_wait_write(); 259 if (error) 260 return error; 261 262 dbg("%02x -> i8042 (command)\n", command & 0xff); 263 i8042_write_command(command & 0xff); 264 265 for (i = 0; i < ((command >> 12) & 0xf); i++) { 266 error = i8042_wait_write(); 267 if (error) 268 return error; 269 dbg("%02x -> i8042 (parameter)\n", param[i]); 270 i8042_write_data(param[i]); 271 } 272 273 for (i = 0; i < ((command >> 8) & 0xf); i++) { 274 error = i8042_wait_read(); 275 if (error) { 276 dbg(" -- i8042 (timeout)\n"); 277 return error; 278 } 279 280 if (command == I8042_CMD_AUX_LOOP && 281 !(i8042_read_status() & I8042_STR_AUXDATA)) { 282 dbg(" -- i8042 (auxerr)\n"); 283 return -1; 284 } 285 286 param[i] = i8042_read_data(); 287 dbg("%02x <- i8042 (return)\n", param[i]); 288 } 289 290 return 0; 291 } 292 293 int i8042_command(unsigned char *param, int command) 294 { 295 unsigned long flags; 296 int retval; 297 298 spin_lock_irqsave(&i8042_lock, flags); 299 retval = __i8042_command(param, command); 300 spin_unlock_irqrestore(&i8042_lock, flags); 301 302 return retval; 303 } 304 EXPORT_SYMBOL(i8042_command); 305 306 /* 307 * i8042_kbd_write() sends a byte out through the keyboard interface. 308 */ 309 310 static int i8042_kbd_write(struct serio *port, unsigned char c) 311 { 312 unsigned long flags; 313 int retval = 0; 314 315 spin_lock_irqsave(&i8042_lock, flags); 316 317 if (!(retval = i8042_wait_write())) { 318 dbg("%02x -> i8042 (kbd-data)\n", c); 319 i8042_write_data(c); 320 } 321 322 spin_unlock_irqrestore(&i8042_lock, flags); 323 324 return retval; 325 } 326 327 /* 328 * i8042_aux_write() sends a byte out through the aux interface. 329 */ 330 331 static int i8042_aux_write(struct serio *serio, unsigned char c) 332 { 333 struct i8042_port *port = serio->port_data; 334 335 return i8042_command(&c, port->mux == -1 ? 336 I8042_CMD_AUX_SEND : 337 I8042_CMD_MUX_SEND + port->mux); 338 } 339 340 341 /* 342 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 343 * and then re-enabling it. 344 */ 345 346 static void i8042_port_close(struct serio *serio) 347 { 348 int irq_bit; 349 int disable_bit; 350 const char *port_name; 351 352 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 353 irq_bit = I8042_CTR_AUXINT; 354 disable_bit = I8042_CTR_AUXDIS; 355 port_name = "AUX"; 356 } else { 357 irq_bit = I8042_CTR_KBDINT; 358 disable_bit = I8042_CTR_KBDDIS; 359 port_name = "KBD"; 360 } 361 362 i8042_ctr &= ~irq_bit; 363 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 364 pr_warn("Can't write CTR while closing %s port\n", port_name); 365 366 udelay(50); 367 368 i8042_ctr &= ~disable_bit; 369 i8042_ctr |= irq_bit; 370 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 371 pr_err("Can't reactivate %s port\n", port_name); 372 373 /* 374 * See if there is any data appeared while we were messing with 375 * port state. 376 */ 377 i8042_interrupt(0, NULL); 378 } 379 380 /* 381 * i8042_start() is called by serio core when port is about to finish 382 * registering. It will mark port as existing so i8042_interrupt can 383 * start sending data through it. 384 */ 385 static int i8042_start(struct serio *serio) 386 { 387 struct i8042_port *port = serio->port_data; 388 389 port->exists = true; 390 mb(); 391 return 0; 392 } 393 394 /* 395 * i8042_stop() marks serio port as non-existing so i8042_interrupt 396 * will not try to send data to the port that is about to go away. 397 * The function is called by serio core as part of unregister procedure. 398 */ 399 static void i8042_stop(struct serio *serio) 400 { 401 struct i8042_port *port = serio->port_data; 402 403 port->exists = false; 404 405 /* 406 * We synchronize with both AUX and KBD IRQs because there is 407 * a (very unlikely) chance that AUX IRQ is raised for KBD port 408 * and vice versa. 409 */ 410 synchronize_irq(I8042_AUX_IRQ); 411 synchronize_irq(I8042_KBD_IRQ); 412 port->serio = NULL; 413 } 414 415 /* 416 * i8042_filter() filters out unwanted bytes from the input data stream. 417 * It is called from i8042_interrupt and thus is running with interrupts 418 * off and i8042_lock held. 419 */ 420 static bool i8042_filter(unsigned char data, unsigned char str, 421 struct serio *serio) 422 { 423 if (unlikely(i8042_suppress_kbd_ack)) { 424 if ((~str & I8042_STR_AUXDATA) && 425 (data == 0xfa || data == 0xfe)) { 426 i8042_suppress_kbd_ack--; 427 dbg("Extra keyboard ACK - filtered out\n"); 428 return true; 429 } 430 } 431 432 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 433 dbg("Filtered out by platform filter\n"); 434 return true; 435 } 436 437 return false; 438 } 439 440 /* 441 * i8042_interrupt() is the most important function in this driver - 442 * it handles the interrupts from the i8042, and sends incoming bytes 443 * to the upper layers. 444 */ 445 446 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 447 { 448 struct i8042_port *port; 449 struct serio *serio; 450 unsigned long flags; 451 unsigned char str, data; 452 unsigned int dfl; 453 unsigned int port_no; 454 bool filtered; 455 int ret = 1; 456 457 spin_lock_irqsave(&i8042_lock, flags); 458 459 str = i8042_read_status(); 460 if (unlikely(~str & I8042_STR_OBF)) { 461 spin_unlock_irqrestore(&i8042_lock, flags); 462 if (irq) 463 dbg("Interrupt %d, without any data\n", irq); 464 ret = 0; 465 goto out; 466 } 467 468 data = i8042_read_data(); 469 470 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 471 static unsigned long last_transmit; 472 static unsigned char last_str; 473 474 dfl = 0; 475 if (str & I8042_STR_MUXERR) { 476 dbg("MUX error, status is %02x, data is %02x\n", 477 str, data); 478 /* 479 * When MUXERR condition is signalled the data register can only contain 480 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 481 * it is not always the case. Some KBCs also report 0xfc when there is 482 * nothing connected to the port while others sometimes get confused which 483 * port the data came from and signal error leaving the data intact. They 484 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 485 * to legacy mode yet, when we see one we'll add proper handling). 486 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 487 * rest assume that the data came from the same serio last byte 488 * was transmitted (if transmission happened not too long ago). 489 */ 490 491 switch (data) { 492 default: 493 if (time_before(jiffies, last_transmit + HZ/10)) { 494 str = last_str; 495 break; 496 } 497 /* fall through - report timeout */ 498 case 0xfc: 499 case 0xfd: 500 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 501 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 502 } 503 } 504 505 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 506 last_str = str; 507 last_transmit = jiffies; 508 } else { 509 510 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 511 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); 512 513 port_no = (str & I8042_STR_AUXDATA) ? 514 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 515 } 516 517 port = &i8042_ports[port_no]; 518 serio = port->exists ? port->serio : NULL; 519 520 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n", 521 data, port_no, irq, 522 dfl & SERIO_PARITY ? ", bad parity" : "", 523 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 524 525 filtered = i8042_filter(data, str, serio); 526 527 spin_unlock_irqrestore(&i8042_lock, flags); 528 529 if (likely(port->exists && !filtered)) 530 serio_interrupt(serio, data, dfl); 531 532 out: 533 return IRQ_RETVAL(ret); 534 } 535 536 /* 537 * i8042_enable_kbd_port enables keyboard port on chip 538 */ 539 540 static int i8042_enable_kbd_port(void) 541 { 542 i8042_ctr &= ~I8042_CTR_KBDDIS; 543 i8042_ctr |= I8042_CTR_KBDINT; 544 545 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 546 i8042_ctr &= ~I8042_CTR_KBDINT; 547 i8042_ctr |= I8042_CTR_KBDDIS; 548 pr_err("Failed to enable KBD port\n"); 549 return -EIO; 550 } 551 552 return 0; 553 } 554 555 /* 556 * i8042_enable_aux_port enables AUX (mouse) port on chip 557 */ 558 559 static int i8042_enable_aux_port(void) 560 { 561 i8042_ctr &= ~I8042_CTR_AUXDIS; 562 i8042_ctr |= I8042_CTR_AUXINT; 563 564 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 565 i8042_ctr &= ~I8042_CTR_AUXINT; 566 i8042_ctr |= I8042_CTR_AUXDIS; 567 pr_err("Failed to enable AUX port\n"); 568 return -EIO; 569 } 570 571 return 0; 572 } 573 574 /* 575 * i8042_enable_mux_ports enables 4 individual AUX ports after 576 * the controller has been switched into Multiplexed mode 577 */ 578 579 static int i8042_enable_mux_ports(void) 580 { 581 unsigned char param; 582 int i; 583 584 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 585 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 586 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 587 } 588 589 return i8042_enable_aux_port(); 590 } 591 592 /* 593 * i8042_set_mux_mode checks whether the controller has an 594 * active multiplexor and puts the chip into Multiplexed (true) 595 * or Legacy (false) mode. 596 */ 597 598 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 599 { 600 601 unsigned char param, val; 602 /* 603 * Get rid of bytes in the queue. 604 */ 605 606 i8042_flush(); 607 608 /* 609 * Internal loopback test - send three bytes, they should come back from the 610 * mouse interface, the last should be version. 611 */ 612 613 param = val = 0xf0; 614 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 615 return -1; 616 param = val = multiplex ? 0x56 : 0xf6; 617 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 618 return -1; 619 param = val = multiplex ? 0xa4 : 0xa5; 620 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 621 return -1; 622 623 /* 624 * Workaround for interference with USB Legacy emulation 625 * that causes a v10.12 MUX to be found. 626 */ 627 if (param == 0xac) 628 return -1; 629 630 if (mux_version) 631 *mux_version = param; 632 633 return 0; 634 } 635 636 /* 637 * i8042_check_mux() checks whether the controller supports the PS/2 Active 638 * Multiplexing specification by Synaptics, Phoenix, Insyde and 639 * LCS/Telegraphics. 640 */ 641 642 static int __init i8042_check_mux(void) 643 { 644 unsigned char mux_version; 645 646 if (i8042_set_mux_mode(true, &mux_version)) 647 return -1; 648 649 pr_info("Detected active multiplexing controller, rev %d.%d\n", 650 (mux_version >> 4) & 0xf, mux_version & 0xf); 651 652 /* 653 * Disable all muxed ports by disabling AUX. 654 */ 655 i8042_ctr |= I8042_CTR_AUXDIS; 656 i8042_ctr &= ~I8042_CTR_AUXINT; 657 658 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 659 pr_err("Failed to disable AUX port, can't use MUX\n"); 660 return -EIO; 661 } 662 663 i8042_mux_present = true; 664 665 return 0; 666 } 667 668 /* 669 * The following is used to test AUX IRQ delivery. 670 */ 671 static struct completion i8042_aux_irq_delivered __initdata; 672 static bool i8042_irq_being_tested __initdata; 673 674 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 675 { 676 unsigned long flags; 677 unsigned char str, data; 678 int ret = 0; 679 680 spin_lock_irqsave(&i8042_lock, flags); 681 str = i8042_read_status(); 682 if (str & I8042_STR_OBF) { 683 data = i8042_read_data(); 684 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 685 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 686 if (i8042_irq_being_tested && 687 data == 0xa5 && (str & I8042_STR_AUXDATA)) 688 complete(&i8042_aux_irq_delivered); 689 ret = 1; 690 } 691 spin_unlock_irqrestore(&i8042_lock, flags); 692 693 return IRQ_RETVAL(ret); 694 } 695 696 /* 697 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 698 * verifies success by readinng CTR. Used when testing for presence of AUX 699 * port. 700 */ 701 static int __init i8042_toggle_aux(bool on) 702 { 703 unsigned char param; 704 int i; 705 706 if (i8042_command(¶m, 707 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 708 return -1; 709 710 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 711 for (i = 0; i < 100; i++) { 712 udelay(50); 713 714 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 715 return -1; 716 717 if (!(param & I8042_CTR_AUXDIS) == on) 718 return 0; 719 } 720 721 return -1; 722 } 723 724 /* 725 * i8042_check_aux() applies as much paranoia as it can at detecting 726 * the presence of an AUX interface. 727 */ 728 729 static int __init i8042_check_aux(void) 730 { 731 int retval = -1; 732 bool irq_registered = false; 733 bool aux_loop_broken = false; 734 unsigned long flags; 735 unsigned char param; 736 737 /* 738 * Get rid of bytes in the queue. 739 */ 740 741 i8042_flush(); 742 743 /* 744 * Internal loopback test - filters out AT-type i8042's. Unfortunately 745 * SiS screwed up and their 5597 doesn't support the LOOP command even 746 * though it has an AUX port. 747 */ 748 749 param = 0x5a; 750 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 751 if (retval || param != 0x5a) { 752 753 /* 754 * External connection test - filters out AT-soldered PS/2 i8042's 755 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 756 * 0xfa - no error on some notebooks which ignore the spec 757 * Because it's common for chipsets to return error on perfectly functioning 758 * AUX ports, we test for this only when the LOOP command failed. 759 */ 760 761 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 762 (param && param != 0xfa && param != 0xff)) 763 return -1; 764 765 /* 766 * If AUX_LOOP completed without error but returned unexpected data 767 * mark it as broken 768 */ 769 if (!retval) 770 aux_loop_broken = true; 771 } 772 773 /* 774 * Bit assignment test - filters out PS/2 i8042's in AT mode 775 */ 776 777 if (i8042_toggle_aux(false)) { 778 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 779 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 780 } 781 782 if (i8042_toggle_aux(true)) 783 return -1; 784 785 /* 786 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 787 * used it for a PCI card or somethig else. 788 */ 789 790 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 791 /* 792 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 793 * is working and hope we are right. 794 */ 795 retval = 0; 796 goto out; 797 } 798 799 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 800 "i8042", i8042_platform_device)) 801 goto out; 802 803 irq_registered = true; 804 805 if (i8042_enable_aux_port()) 806 goto out; 807 808 spin_lock_irqsave(&i8042_lock, flags); 809 810 init_completion(&i8042_aux_irq_delivered); 811 i8042_irq_being_tested = true; 812 813 param = 0xa5; 814 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 815 816 spin_unlock_irqrestore(&i8042_lock, flags); 817 818 if (retval) 819 goto out; 820 821 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 822 msecs_to_jiffies(250)) == 0) { 823 /* 824 * AUX IRQ was never delivered so we need to flush the controller to 825 * get rid of the byte we put there; otherwise keyboard may not work. 826 */ 827 dbg(" -- i8042 (aux irq test timeout)\n"); 828 i8042_flush(); 829 retval = -1; 830 } 831 832 out: 833 834 /* 835 * Disable the interface. 836 */ 837 838 i8042_ctr |= I8042_CTR_AUXDIS; 839 i8042_ctr &= ~I8042_CTR_AUXINT; 840 841 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 842 retval = -1; 843 844 if (irq_registered) 845 free_irq(I8042_AUX_IRQ, i8042_platform_device); 846 847 return retval; 848 } 849 850 static int i8042_controller_check(void) 851 { 852 if (i8042_flush() == I8042_BUFFER_SIZE) { 853 pr_err("No controller found\n"); 854 return -ENODEV; 855 } 856 857 return 0; 858 } 859 860 static int i8042_controller_selftest(void) 861 { 862 unsigned char param; 863 int i = 0; 864 865 /* 866 * We try this 5 times; on some really fragile systems this does not 867 * take the first time... 868 */ 869 do { 870 871 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 872 pr_err("i8042 controller self test timeout\n"); 873 return -ENODEV; 874 } 875 876 if (param == I8042_RET_CTL_TEST) 877 return 0; 878 879 pr_err("i8042 controller selftest failed. (%#x != %#x)\n", 880 param, I8042_RET_CTL_TEST); 881 msleep(50); 882 } while (i++ < 5); 883 884 #ifdef CONFIG_X86 885 /* 886 * On x86, we don't fail entire i8042 initialization if controller 887 * reset fails in hopes that keyboard port will still be functional 888 * and user will still get a working keyboard. This is especially 889 * important on netbooks. On other arches we trust hardware more. 890 */ 891 pr_info("giving up on controller selftest, continuing anyway...\n"); 892 return 0; 893 #else 894 return -EIO; 895 #endif 896 } 897 898 /* 899 * i8042_controller init initializes the i8042 controller, and, 900 * most importantly, sets it into non-xlated mode if that's 901 * desired. 902 */ 903 904 static int i8042_controller_init(void) 905 { 906 unsigned long flags; 907 int n = 0; 908 unsigned char ctr[2]; 909 910 /* 911 * Save the CTR for restore on unload / reboot. 912 */ 913 914 do { 915 if (n >= 10) { 916 pr_err("Unable to get stable CTR read\n"); 917 return -EIO; 918 } 919 920 if (n != 0) 921 udelay(50); 922 923 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 924 pr_err("Can't read CTR while initializing i8042\n"); 925 return -EIO; 926 } 927 928 } while (n < 2 || ctr[0] != ctr[1]); 929 930 i8042_initial_ctr = i8042_ctr = ctr[0]; 931 932 /* 933 * Disable the keyboard interface and interrupt. 934 */ 935 936 i8042_ctr |= I8042_CTR_KBDDIS; 937 i8042_ctr &= ~I8042_CTR_KBDINT; 938 939 /* 940 * Handle keylock. 941 */ 942 943 spin_lock_irqsave(&i8042_lock, flags); 944 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 945 if (i8042_unlock) 946 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 947 else 948 pr_warn("Warning: Keylock active\n"); 949 } 950 spin_unlock_irqrestore(&i8042_lock, flags); 951 952 /* 953 * If the chip is configured into nontranslated mode by the BIOS, don't 954 * bother enabling translating and be happy. 955 */ 956 957 if (~i8042_ctr & I8042_CTR_XLATE) 958 i8042_direct = true; 959 960 /* 961 * Set nontranslated mode for the kbd interface if requested by an option. 962 * After this the kbd interface becomes a simple serial in/out, like the aux 963 * interface is. We don't do this by default, since it can confuse notebook 964 * BIOSes. 965 */ 966 967 if (i8042_direct) 968 i8042_ctr &= ~I8042_CTR_XLATE; 969 970 /* 971 * Write CTR back. 972 */ 973 974 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 975 pr_err("Can't write CTR while initializing i8042\n"); 976 return -EIO; 977 } 978 979 /* 980 * Flush whatever accumulated while we were disabling keyboard port. 981 */ 982 983 i8042_flush(); 984 985 return 0; 986 } 987 988 989 /* 990 * Reset the controller and reset CRT to the original value set by BIOS. 991 */ 992 993 static void i8042_controller_reset(void) 994 { 995 i8042_flush(); 996 997 /* 998 * Disable both KBD and AUX interfaces so they don't get in the way 999 */ 1000 1001 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1002 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1003 1004 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1005 pr_warn("Can't write CTR while resetting\n"); 1006 1007 /* 1008 * Disable MUX mode if present. 1009 */ 1010 1011 if (i8042_mux_present) 1012 i8042_set_mux_mode(false, NULL); 1013 1014 /* 1015 * Reset the controller if requested. 1016 */ 1017 1018 if (i8042_reset) 1019 i8042_controller_selftest(); 1020 1021 /* 1022 * Restore the original control register setting. 1023 */ 1024 1025 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1026 pr_warn("Can't restore CTR\n"); 1027 } 1028 1029 1030 /* 1031 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1032 * when kernel panics. Flashing LEDs is useful for users running X who may 1033 * not see the console and will help distingushing panics from "real" 1034 * lockups. 1035 * 1036 * Note that DELAY has a limit of 10ms so we will not get stuck here 1037 * waiting for KBC to free up even if KBD interrupt is off 1038 */ 1039 1040 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1041 1042 static long i8042_panic_blink(int state) 1043 { 1044 long delay = 0; 1045 char led; 1046 1047 led = (state) ? 0x01 | 0x04 : 0; 1048 while (i8042_read_status() & I8042_STR_IBF) 1049 DELAY; 1050 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1051 i8042_suppress_kbd_ack = 2; 1052 i8042_write_data(0xed); /* set leds */ 1053 DELAY; 1054 while (i8042_read_status() & I8042_STR_IBF) 1055 DELAY; 1056 DELAY; 1057 dbg("%02x -> i8042 (panic blink)\n", led); 1058 i8042_write_data(led); 1059 DELAY; 1060 return delay; 1061 } 1062 1063 #undef DELAY 1064 1065 #ifdef CONFIG_X86 1066 static void i8042_dritek_enable(void) 1067 { 1068 unsigned char param = 0x90; 1069 int error; 1070 1071 error = i8042_command(¶m, 0x1059); 1072 if (error) 1073 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1074 } 1075 #endif 1076 1077 #ifdef CONFIG_PM 1078 1079 /* 1080 * Here we try to reset everything back to a state we had 1081 * before suspending. 1082 */ 1083 1084 static int i8042_controller_resume(bool force_reset) 1085 { 1086 int error; 1087 1088 error = i8042_controller_check(); 1089 if (error) 1090 return error; 1091 1092 if (i8042_reset || force_reset) { 1093 error = i8042_controller_selftest(); 1094 if (error) 1095 return error; 1096 } 1097 1098 /* 1099 * Restore original CTR value and disable all ports 1100 */ 1101 1102 i8042_ctr = i8042_initial_ctr; 1103 if (i8042_direct) 1104 i8042_ctr &= ~I8042_CTR_XLATE; 1105 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1106 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1107 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1108 pr_warn("Can't write CTR to resume, retrying...\n"); 1109 msleep(50); 1110 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1111 pr_err("CTR write retry failed\n"); 1112 return -EIO; 1113 } 1114 } 1115 1116 1117 #ifdef CONFIG_X86 1118 if (i8042_dritek) 1119 i8042_dritek_enable(); 1120 #endif 1121 1122 if (i8042_mux_present) { 1123 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1124 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1125 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1126 i8042_enable_aux_port(); 1127 1128 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1129 i8042_enable_kbd_port(); 1130 1131 i8042_interrupt(0, NULL); 1132 1133 return 0; 1134 } 1135 1136 /* 1137 * Here we try to restore the original BIOS settings to avoid 1138 * upsetting it. 1139 */ 1140 1141 static int i8042_pm_reset(struct device *dev) 1142 { 1143 i8042_controller_reset(); 1144 1145 return 0; 1146 } 1147 1148 static int i8042_pm_resume(struct device *dev) 1149 { 1150 /* 1151 * On resume from S2R we always try to reset the controller 1152 * to bring it in a sane state. (In case of S2D we expect 1153 * BIOS to reset the controller for us.) 1154 */ 1155 return i8042_controller_resume(true); 1156 } 1157 1158 static int i8042_pm_thaw(struct device *dev) 1159 { 1160 i8042_interrupt(0, NULL); 1161 1162 return 0; 1163 } 1164 1165 static int i8042_pm_restore(struct device *dev) 1166 { 1167 return i8042_controller_resume(false); 1168 } 1169 1170 static const struct dev_pm_ops i8042_pm_ops = { 1171 .suspend = i8042_pm_reset, 1172 .resume = i8042_pm_resume, 1173 .thaw = i8042_pm_thaw, 1174 .poweroff = i8042_pm_reset, 1175 .restore = i8042_pm_restore, 1176 }; 1177 1178 #endif /* CONFIG_PM */ 1179 1180 /* 1181 * We need to reset the 8042 back to original mode on system shutdown, 1182 * because otherwise BIOSes will be confused. 1183 */ 1184 1185 static void i8042_shutdown(struct platform_device *dev) 1186 { 1187 i8042_controller_reset(); 1188 } 1189 1190 static int __init i8042_create_kbd_port(void) 1191 { 1192 struct serio *serio; 1193 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1194 1195 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1196 if (!serio) 1197 return -ENOMEM; 1198 1199 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1200 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1201 serio->start = i8042_start; 1202 serio->stop = i8042_stop; 1203 serio->close = i8042_port_close; 1204 serio->port_data = port; 1205 serio->dev.parent = &i8042_platform_device->dev; 1206 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1207 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1208 1209 port->serio = serio; 1210 port->irq = I8042_KBD_IRQ; 1211 1212 return 0; 1213 } 1214 1215 static int __init i8042_create_aux_port(int idx) 1216 { 1217 struct serio *serio; 1218 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1219 struct i8042_port *port = &i8042_ports[port_no]; 1220 1221 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1222 if (!serio) 1223 return -ENOMEM; 1224 1225 serio->id.type = SERIO_8042; 1226 serio->write = i8042_aux_write; 1227 serio->start = i8042_start; 1228 serio->stop = i8042_stop; 1229 serio->port_data = port; 1230 serio->dev.parent = &i8042_platform_device->dev; 1231 if (idx < 0) { 1232 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1233 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1234 serio->close = i8042_port_close; 1235 } else { 1236 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1237 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1238 } 1239 1240 port->serio = serio; 1241 port->mux = idx; 1242 port->irq = I8042_AUX_IRQ; 1243 1244 return 0; 1245 } 1246 1247 static void __init i8042_free_kbd_port(void) 1248 { 1249 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1250 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1251 } 1252 1253 static void __init i8042_free_aux_ports(void) 1254 { 1255 int i; 1256 1257 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1258 kfree(i8042_ports[i].serio); 1259 i8042_ports[i].serio = NULL; 1260 } 1261 } 1262 1263 static void __init i8042_register_ports(void) 1264 { 1265 int i; 1266 1267 for (i = 0; i < I8042_NUM_PORTS; i++) { 1268 if (i8042_ports[i].serio) { 1269 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1270 i8042_ports[i].serio->name, 1271 (unsigned long) I8042_DATA_REG, 1272 (unsigned long) I8042_COMMAND_REG, 1273 i8042_ports[i].irq); 1274 serio_register_port(i8042_ports[i].serio); 1275 } 1276 } 1277 } 1278 1279 static void __devexit i8042_unregister_ports(void) 1280 { 1281 int i; 1282 1283 for (i = 0; i < I8042_NUM_PORTS; i++) { 1284 if (i8042_ports[i].serio) { 1285 serio_unregister_port(i8042_ports[i].serio); 1286 i8042_ports[i].serio = NULL; 1287 } 1288 } 1289 } 1290 1291 /* 1292 * Checks whether port belongs to i8042 controller. 1293 */ 1294 bool i8042_check_port_owner(const struct serio *port) 1295 { 1296 int i; 1297 1298 for (i = 0; i < I8042_NUM_PORTS; i++) 1299 if (i8042_ports[i].serio == port) 1300 return true; 1301 1302 return false; 1303 } 1304 EXPORT_SYMBOL(i8042_check_port_owner); 1305 1306 static void i8042_free_irqs(void) 1307 { 1308 if (i8042_aux_irq_registered) 1309 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1310 if (i8042_kbd_irq_registered) 1311 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1312 1313 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1314 } 1315 1316 static int __init i8042_setup_aux(void) 1317 { 1318 int (*aux_enable)(void); 1319 int error; 1320 int i; 1321 1322 if (i8042_check_aux()) 1323 return -ENODEV; 1324 1325 if (i8042_nomux || i8042_check_mux()) { 1326 error = i8042_create_aux_port(-1); 1327 if (error) 1328 goto err_free_ports; 1329 aux_enable = i8042_enable_aux_port; 1330 } else { 1331 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1332 error = i8042_create_aux_port(i); 1333 if (error) 1334 goto err_free_ports; 1335 } 1336 aux_enable = i8042_enable_mux_ports; 1337 } 1338 1339 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1340 "i8042", i8042_platform_device); 1341 if (error) 1342 goto err_free_ports; 1343 1344 if (aux_enable()) 1345 goto err_free_irq; 1346 1347 i8042_aux_irq_registered = true; 1348 return 0; 1349 1350 err_free_irq: 1351 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1352 err_free_ports: 1353 i8042_free_aux_ports(); 1354 return error; 1355 } 1356 1357 static int __init i8042_setup_kbd(void) 1358 { 1359 int error; 1360 1361 error = i8042_create_kbd_port(); 1362 if (error) 1363 return error; 1364 1365 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1366 "i8042", i8042_platform_device); 1367 if (error) 1368 goto err_free_port; 1369 1370 error = i8042_enable_kbd_port(); 1371 if (error) 1372 goto err_free_irq; 1373 1374 i8042_kbd_irq_registered = true; 1375 return 0; 1376 1377 err_free_irq: 1378 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1379 err_free_port: 1380 i8042_free_kbd_port(); 1381 return error; 1382 } 1383 1384 static int __init i8042_probe(struct platform_device *dev) 1385 { 1386 int error; 1387 1388 i8042_platform_device = dev; 1389 1390 if (i8042_reset) { 1391 error = i8042_controller_selftest(); 1392 if (error) 1393 return error; 1394 } 1395 1396 error = i8042_controller_init(); 1397 if (error) 1398 return error; 1399 1400 #ifdef CONFIG_X86 1401 if (i8042_dritek) 1402 i8042_dritek_enable(); 1403 #endif 1404 1405 if (!i8042_noaux) { 1406 error = i8042_setup_aux(); 1407 if (error && error != -ENODEV && error != -EBUSY) 1408 goto out_fail; 1409 } 1410 1411 if (!i8042_nokbd) { 1412 error = i8042_setup_kbd(); 1413 if (error) 1414 goto out_fail; 1415 } 1416 /* 1417 * Ok, everything is ready, let's register all serio ports 1418 */ 1419 i8042_register_ports(); 1420 1421 return 0; 1422 1423 out_fail: 1424 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1425 i8042_free_irqs(); 1426 i8042_controller_reset(); 1427 i8042_platform_device = NULL; 1428 1429 return error; 1430 } 1431 1432 static int __devexit i8042_remove(struct platform_device *dev) 1433 { 1434 i8042_unregister_ports(); 1435 i8042_free_irqs(); 1436 i8042_controller_reset(); 1437 i8042_platform_device = NULL; 1438 1439 return 0; 1440 } 1441 1442 static struct platform_driver i8042_driver = { 1443 .driver = { 1444 .name = "i8042", 1445 .owner = THIS_MODULE, 1446 #ifdef CONFIG_PM 1447 .pm = &i8042_pm_ops, 1448 #endif 1449 }, 1450 .remove = __devexit_p(i8042_remove), 1451 .shutdown = i8042_shutdown, 1452 }; 1453 1454 static int __init i8042_init(void) 1455 { 1456 struct platform_device *pdev; 1457 int err; 1458 1459 dbg_init(); 1460 1461 err = i8042_platform_init(); 1462 if (err) 1463 return err; 1464 1465 err = i8042_controller_check(); 1466 if (err) 1467 goto err_platform_exit; 1468 1469 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1470 if (IS_ERR(pdev)) { 1471 err = PTR_ERR(pdev); 1472 goto err_platform_exit; 1473 } 1474 1475 panic_blink = i8042_panic_blink; 1476 1477 return 0; 1478 1479 err_platform_exit: 1480 i8042_platform_exit(); 1481 return err; 1482 } 1483 1484 static void __exit i8042_exit(void) 1485 { 1486 platform_device_unregister(i8042_platform_device); 1487 platform_driver_unregister(&i8042_driver); 1488 i8042_platform_exit(); 1489 1490 panic_blink = NULL; 1491 } 1492 1493 module_init(i8042_init); 1494 module_exit(i8042_exit); 1495