1 /* 2 * Copyright (c) 2016, Zodiac Inflight Innovations 3 * Copyright (c) 2007-2016, Synaptics Incorporated 4 * Copyright (C) 2012 Alexandra Chin <alexandra.chin@tw.synaptics.com> 5 * Copyright (C) 2012 Scott Lin <scott.lin@tw.synaptics.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/rmi.h> 14 #include <linux/firmware.h> 15 #include <asm/unaligned.h> 16 #include <linux/delay.h> 17 #include <linux/slab.h> 18 #include <linux/jiffies.h> 19 20 #include "rmi_driver.h" 21 #include "rmi_f34.h" 22 23 static int rmi_f34v7_read_flash_status(struct f34_data *f34) 24 { 25 u8 status; 26 u8 command; 27 int ret; 28 29 ret = rmi_read_block(f34->fn->rmi_dev, 30 f34->fn->fd.data_base_addr + f34->v7.off.flash_status, 31 &status, 32 sizeof(status)); 33 if (ret < 0) { 34 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 35 "%s: Error %d reading flash status\n", __func__, ret); 36 return ret; 37 } 38 39 f34->v7.in_bl_mode = status >> 7; 40 f34->v7.flash_status = status & 0x1f; 41 42 if (f34->v7.flash_status != 0x00) { 43 dev_err(&f34->fn->dev, "%s: status=%d, command=0x%02x\n", 44 __func__, f34->v7.flash_status, f34->v7.command); 45 } 46 47 ret = rmi_read_block(f34->fn->rmi_dev, 48 f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd, 49 &command, 50 sizeof(command)); 51 if (ret < 0) { 52 dev_err(&f34->fn->dev, "%s: Failed to read flash command\n", 53 __func__); 54 return ret; 55 } 56 57 f34->v7.command = command; 58 59 return 0; 60 } 61 62 static int rmi_f34v7_wait_for_idle(struct f34_data *f34, int timeout_ms) 63 { 64 unsigned long timeout; 65 66 timeout = msecs_to_jiffies(timeout_ms); 67 68 if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) { 69 dev_warn(&f34->fn->dev, "%s: Timed out waiting for idle status\n", 70 __func__); 71 return -ETIMEDOUT; 72 } 73 74 return 0; 75 } 76 77 static int rmi_f34v7_write_command_single_transaction(struct f34_data *f34, 78 u8 cmd) 79 { 80 int ret; 81 u8 base; 82 struct f34v7_data_1_5 data_1_5; 83 84 base = f34->fn->fd.data_base_addr; 85 86 memset(&data_1_5, 0, sizeof(data_1_5)); 87 88 switch (cmd) { 89 case v7_CMD_ERASE_ALL: 90 data_1_5.partition_id = CORE_CODE_PARTITION; 91 data_1_5.command = CMD_V7_ERASE_AP; 92 break; 93 case v7_CMD_ERASE_UI_FIRMWARE: 94 data_1_5.partition_id = CORE_CODE_PARTITION; 95 data_1_5.command = CMD_V7_ERASE; 96 break; 97 case v7_CMD_ERASE_BL_CONFIG: 98 data_1_5.partition_id = GLOBAL_PARAMETERS_PARTITION; 99 data_1_5.command = CMD_V7_ERASE; 100 break; 101 case v7_CMD_ERASE_UI_CONFIG: 102 data_1_5.partition_id = CORE_CONFIG_PARTITION; 103 data_1_5.command = CMD_V7_ERASE; 104 break; 105 case v7_CMD_ERASE_DISP_CONFIG: 106 data_1_5.partition_id = DISPLAY_CONFIG_PARTITION; 107 data_1_5.command = CMD_V7_ERASE; 108 break; 109 case v7_CMD_ERASE_FLASH_CONFIG: 110 data_1_5.partition_id = FLASH_CONFIG_PARTITION; 111 data_1_5.command = CMD_V7_ERASE; 112 break; 113 case v7_CMD_ERASE_GUEST_CODE: 114 data_1_5.partition_id = GUEST_CODE_PARTITION; 115 data_1_5.command = CMD_V7_ERASE; 116 break; 117 case v7_CMD_ENABLE_FLASH_PROG: 118 data_1_5.partition_id = BOOTLOADER_PARTITION; 119 data_1_5.command = CMD_V7_ENTER_BL; 120 break; 121 } 122 123 data_1_5.payload[0] = f34->bootloader_id[0]; 124 data_1_5.payload[1] = f34->bootloader_id[1]; 125 126 ret = rmi_write_block(f34->fn->rmi_dev, 127 base + f34->v7.off.partition_id, 128 &data_1_5, sizeof(data_1_5)); 129 if (ret < 0) { 130 dev_err(&f34->fn->dev, 131 "%s: Failed to write single transaction command\n", 132 __func__); 133 return ret; 134 } 135 136 return 0; 137 } 138 139 static int rmi_f34v7_write_command(struct f34_data *f34, u8 cmd) 140 { 141 int ret; 142 u8 base; 143 u8 command; 144 145 base = f34->fn->fd.data_base_addr; 146 147 switch (cmd) { 148 case v7_CMD_WRITE_FW: 149 case v7_CMD_WRITE_CONFIG: 150 case v7_CMD_WRITE_GUEST_CODE: 151 command = CMD_V7_WRITE; 152 break; 153 case v7_CMD_READ_CONFIG: 154 command = CMD_V7_READ; 155 break; 156 case v7_CMD_ERASE_ALL: 157 command = CMD_V7_ERASE_AP; 158 break; 159 case v7_CMD_ERASE_UI_FIRMWARE: 160 case v7_CMD_ERASE_BL_CONFIG: 161 case v7_CMD_ERASE_UI_CONFIG: 162 case v7_CMD_ERASE_DISP_CONFIG: 163 case v7_CMD_ERASE_FLASH_CONFIG: 164 case v7_CMD_ERASE_GUEST_CODE: 165 command = CMD_V7_ERASE; 166 break; 167 case v7_CMD_ENABLE_FLASH_PROG: 168 command = CMD_V7_ENTER_BL; 169 break; 170 default: 171 dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n", 172 __func__, cmd); 173 return -EINVAL; 174 } 175 176 f34->v7.command = command; 177 178 switch (cmd) { 179 case v7_CMD_ERASE_ALL: 180 case v7_CMD_ERASE_UI_FIRMWARE: 181 case v7_CMD_ERASE_BL_CONFIG: 182 case v7_CMD_ERASE_UI_CONFIG: 183 case v7_CMD_ERASE_DISP_CONFIG: 184 case v7_CMD_ERASE_FLASH_CONFIG: 185 case v7_CMD_ERASE_GUEST_CODE: 186 case v7_CMD_ENABLE_FLASH_PROG: 187 ret = rmi_f34v7_write_command_single_transaction(f34, cmd); 188 if (ret < 0) 189 return ret; 190 else 191 return 0; 192 default: 193 break; 194 } 195 196 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: writing cmd %02X\n", 197 __func__, command); 198 199 ret = rmi_write_block(f34->fn->rmi_dev, 200 base + f34->v7.off.flash_cmd, 201 &command, sizeof(command)); 202 if (ret < 0) { 203 dev_err(&f34->fn->dev, "%s: Failed to write flash command\n", 204 __func__); 205 return ret; 206 } 207 208 return 0; 209 } 210 211 static int rmi_f34v7_write_partition_id(struct f34_data *f34, u8 cmd) 212 { 213 int ret; 214 u8 base; 215 u8 partition; 216 217 base = f34->fn->fd.data_base_addr; 218 219 switch (cmd) { 220 case v7_CMD_WRITE_FW: 221 partition = CORE_CODE_PARTITION; 222 break; 223 case v7_CMD_WRITE_CONFIG: 224 case v7_CMD_READ_CONFIG: 225 if (f34->v7.config_area == v7_UI_CONFIG_AREA) 226 partition = CORE_CONFIG_PARTITION; 227 else if (f34->v7.config_area == v7_DP_CONFIG_AREA) 228 partition = DISPLAY_CONFIG_PARTITION; 229 else if (f34->v7.config_area == v7_PM_CONFIG_AREA) 230 partition = GUEST_SERIALIZATION_PARTITION; 231 else if (f34->v7.config_area == v7_BL_CONFIG_AREA) 232 partition = GLOBAL_PARAMETERS_PARTITION; 233 else if (f34->v7.config_area == v7_FLASH_CONFIG_AREA) 234 partition = FLASH_CONFIG_PARTITION; 235 break; 236 case v7_CMD_WRITE_GUEST_CODE: 237 partition = GUEST_CODE_PARTITION; 238 break; 239 case v7_CMD_ERASE_ALL: 240 partition = CORE_CODE_PARTITION; 241 break; 242 case v7_CMD_ERASE_BL_CONFIG: 243 partition = GLOBAL_PARAMETERS_PARTITION; 244 break; 245 case v7_CMD_ERASE_UI_CONFIG: 246 partition = CORE_CONFIG_PARTITION; 247 break; 248 case v7_CMD_ERASE_DISP_CONFIG: 249 partition = DISPLAY_CONFIG_PARTITION; 250 break; 251 case v7_CMD_ERASE_FLASH_CONFIG: 252 partition = FLASH_CONFIG_PARTITION; 253 break; 254 case v7_CMD_ERASE_GUEST_CODE: 255 partition = GUEST_CODE_PARTITION; 256 break; 257 case v7_CMD_ENABLE_FLASH_PROG: 258 partition = BOOTLOADER_PARTITION; 259 break; 260 default: 261 dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n", 262 __func__, cmd); 263 return -EINVAL; 264 } 265 266 ret = rmi_write_block(f34->fn->rmi_dev, 267 base + f34->v7.off.partition_id, 268 &partition, sizeof(partition)); 269 if (ret < 0) { 270 dev_err(&f34->fn->dev, "%s: Failed to write partition ID\n", 271 __func__); 272 return ret; 273 } 274 275 return 0; 276 } 277 278 static int rmi_f34v7_read_partition_table(struct f34_data *f34) 279 { 280 int ret; 281 unsigned long timeout; 282 u8 base; 283 __le16 length; 284 u16 block_number = 0; 285 286 base = f34->fn->fd.data_base_addr; 287 288 f34->v7.config_area = v7_FLASH_CONFIG_AREA; 289 290 ret = rmi_f34v7_write_partition_id(f34, v7_CMD_READ_CONFIG); 291 if (ret < 0) 292 return ret; 293 294 ret = rmi_write_block(f34->fn->rmi_dev, 295 base + f34->v7.off.block_number, 296 &block_number, sizeof(block_number)); 297 if (ret < 0) { 298 dev_err(&f34->fn->dev, "%s: Failed to write block number\n", 299 __func__); 300 return ret; 301 } 302 303 put_unaligned_le16(f34->v7.flash_config_length, &length); 304 305 ret = rmi_write_block(f34->fn->rmi_dev, 306 base + f34->v7.off.transfer_length, 307 &length, sizeof(length)); 308 if (ret < 0) { 309 dev_err(&f34->fn->dev, "%s: Failed to write transfer length\n", 310 __func__); 311 return ret; 312 } 313 314 init_completion(&f34->v7.cmd_done); 315 316 ret = rmi_f34v7_write_command(f34, v7_CMD_READ_CONFIG); 317 if (ret < 0) { 318 dev_err(&f34->fn->dev, "%s: Failed to write command\n", 319 __func__); 320 return ret; 321 } 322 323 timeout = msecs_to_jiffies(F34_WRITE_WAIT_MS); 324 while (time_before(jiffies, timeout)) { 325 usleep_range(5000, 6000); 326 rmi_f34v7_read_flash_status(f34); 327 328 if (f34->v7.command == v7_CMD_IDLE && 329 f34->v7.flash_status == 0x00) { 330 break; 331 } 332 } 333 334 ret = rmi_read_block(f34->fn->rmi_dev, 335 base + f34->v7.off.payload, 336 f34->v7.read_config_buf, 337 f34->v7.partition_table_bytes); 338 if (ret < 0) { 339 dev_err(&f34->fn->dev, "%s: Failed to read block data\n", 340 __func__); 341 return ret; 342 } 343 344 return 0; 345 } 346 347 static void rmi_f34v7_parse_partition_table(struct f34_data *f34, 348 const void *partition_table, 349 struct block_count *blkcount, 350 struct physical_address *phyaddr) 351 { 352 int i; 353 int index; 354 u16 partition_length; 355 u16 physical_address; 356 const struct partition_table *ptable; 357 358 for (i = 0; i < f34->v7.partitions; i++) { 359 index = i * 8 + 2; 360 ptable = partition_table + index; 361 partition_length = le16_to_cpu(ptable->partition_length); 362 physical_address = le16_to_cpu(ptable->start_physical_address); 363 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 364 "%s: Partition entry %d: %*ph\n", 365 __func__, i, sizeof(struct partition_table), ptable); 366 switch (ptable->partition_id & 0x1f) { 367 case CORE_CODE_PARTITION: 368 blkcount->ui_firmware = partition_length; 369 phyaddr->ui_firmware = physical_address; 370 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 371 "%s: Core code block count: %d\n", 372 __func__, blkcount->ui_firmware); 373 break; 374 case CORE_CONFIG_PARTITION: 375 blkcount->ui_config = partition_length; 376 phyaddr->ui_config = physical_address; 377 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 378 "%s: Core config block count: %d\n", 379 __func__, blkcount->ui_config); 380 break; 381 case DISPLAY_CONFIG_PARTITION: 382 blkcount->dp_config = partition_length; 383 phyaddr->dp_config = physical_address; 384 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 385 "%s: Display config block count: %d\n", 386 __func__, blkcount->dp_config); 387 break; 388 case FLASH_CONFIG_PARTITION: 389 blkcount->fl_config = partition_length; 390 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 391 "%s: Flash config block count: %d\n", 392 __func__, blkcount->fl_config); 393 break; 394 case GUEST_CODE_PARTITION: 395 blkcount->guest_code = partition_length; 396 phyaddr->guest_code = physical_address; 397 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 398 "%s: Guest code block count: %d\n", 399 __func__, blkcount->guest_code); 400 break; 401 case GUEST_SERIALIZATION_PARTITION: 402 blkcount->pm_config = partition_length; 403 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 404 "%s: Guest serialization block count: %d\n", 405 __func__, blkcount->pm_config); 406 break; 407 case GLOBAL_PARAMETERS_PARTITION: 408 blkcount->bl_config = partition_length; 409 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 410 "%s: Global parameters block count: %d\n", 411 __func__, blkcount->bl_config); 412 break; 413 case DEVICE_CONFIG_PARTITION: 414 blkcount->lockdown = partition_length; 415 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 416 "%s: Device config block count: %d\n", 417 __func__, blkcount->lockdown); 418 break; 419 } 420 } 421 } 422 423 static int rmi_f34v7_read_queries_bl_version(struct f34_data *f34) 424 { 425 int ret; 426 u8 base; 427 int offset; 428 u8 query_0; 429 struct f34v7_query_1_7 query_1_7; 430 431 base = f34->fn->fd.query_base_addr; 432 433 ret = rmi_read_block(f34->fn->rmi_dev, 434 base, 435 &query_0, 436 sizeof(query_0)); 437 if (ret < 0) { 438 dev_err(&f34->fn->dev, 439 "%s: Failed to read query 0\n", __func__); 440 return ret; 441 } 442 443 offset = (query_0 & 0x7) + 1; 444 445 ret = rmi_read_block(f34->fn->rmi_dev, 446 base + offset, 447 &query_1_7, 448 sizeof(query_1_7)); 449 if (ret < 0) { 450 dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n", 451 __func__); 452 return ret; 453 } 454 455 f34->bootloader_id[0] = query_1_7.bl_minor_revision; 456 f34->bootloader_id[1] = query_1_7.bl_major_revision; 457 458 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Bootloader V%d.%d\n", 459 f34->bootloader_id[1], f34->bootloader_id[0]); 460 461 return 0; 462 } 463 464 static int rmi_f34v7_read_queries(struct f34_data *f34) 465 { 466 int ret; 467 int i, j; 468 u8 base; 469 int offset; 470 u8 *ptable; 471 u8 query_0; 472 struct f34v7_query_1_7 query_1_7; 473 474 base = f34->fn->fd.query_base_addr; 475 476 ret = rmi_read_block(f34->fn->rmi_dev, 477 base, 478 &query_0, 479 sizeof(query_0)); 480 if (ret < 0) { 481 dev_err(&f34->fn->dev, 482 "%s: Failed to read query 0\n", __func__); 483 return ret; 484 } 485 486 offset = (query_0 & 0x07) + 1; 487 488 ret = rmi_read_block(f34->fn->rmi_dev, 489 base + offset, 490 &query_1_7, 491 sizeof(query_1_7)); 492 if (ret < 0) { 493 dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n", 494 __func__); 495 return ret; 496 } 497 498 f34->bootloader_id[0] = query_1_7.bl_minor_revision; 499 f34->bootloader_id[1] = query_1_7.bl_major_revision; 500 501 f34->v7.block_size = le16_to_cpu(query_1_7.block_size); 502 f34->v7.flash_config_length = 503 le16_to_cpu(query_1_7.flash_config_length); 504 f34->v7.payload_length = le16_to_cpu(query_1_7.payload_length); 505 506 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.block_size = %d\n", 507 __func__, f34->v7.block_size); 508 509 f34->v7.off.flash_status = V7_FLASH_STATUS_OFFSET; 510 f34->v7.off.partition_id = V7_PARTITION_ID_OFFSET; 511 f34->v7.off.block_number = V7_BLOCK_NUMBER_OFFSET; 512 f34->v7.off.transfer_length = V7_TRANSFER_LENGTH_OFFSET; 513 f34->v7.off.flash_cmd = V7_COMMAND_OFFSET; 514 f34->v7.off.payload = V7_PAYLOAD_OFFSET; 515 516 f34->v7.has_display_cfg = query_1_7.partition_support[1] & HAS_DISP_CFG; 517 f34->v7.has_guest_code = 518 query_1_7.partition_support[1] & HAS_GUEST_CODE; 519 520 if (query_0 & HAS_CONFIG_ID) { 521 char f34_ctrl[CONFIG_ID_SIZE]; 522 int i = 0; 523 u8 *p = f34->configuration_id; 524 *p = '\0'; 525 526 ret = rmi_read_block(f34->fn->rmi_dev, 527 f34->fn->fd.control_base_addr, 528 f34_ctrl, 529 sizeof(f34_ctrl)); 530 if (ret) 531 return ret; 532 533 /* Eat leading zeros */ 534 while (i < sizeof(f34_ctrl) && !f34_ctrl[i]) 535 i++; 536 537 for (; i < sizeof(f34_ctrl); i++) 538 p += snprintf(p, f34->configuration_id 539 + sizeof(f34->configuration_id) - p, 540 "%02X", f34_ctrl[i]); 541 542 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Configuration ID: %s\n", 543 f34->configuration_id); 544 } 545 546 f34->v7.partitions = 0; 547 for (i = 0; i < sizeof(query_1_7.partition_support); i++) 548 for (j = 0; j < 8; j++) 549 if (query_1_7.partition_support[i] & (1 << j)) 550 f34->v7.partitions++; 551 552 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: Supported partitions: %*ph\n", 553 __func__, sizeof(query_1_7.partition_support), 554 query_1_7.partition_support); 555 556 557 f34->v7.partition_table_bytes = f34->v7.partitions * 8 + 2; 558 559 f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev, 560 f34->v7.partition_table_bytes, 561 GFP_KERNEL); 562 if (!f34->v7.read_config_buf) { 563 f34->v7.read_config_buf_size = 0; 564 return -ENOMEM; 565 } 566 567 f34->v7.read_config_buf_size = f34->v7.partition_table_bytes; 568 ptable = f34->v7.read_config_buf; 569 570 ret = rmi_f34v7_read_partition_table(f34); 571 if (ret < 0) { 572 dev_err(&f34->fn->dev, "%s: Failed to read partition table\n", 573 __func__); 574 return ret; 575 } 576 577 rmi_f34v7_parse_partition_table(f34, ptable, 578 &f34->v7.blkcount, &f34->v7.phyaddr); 579 580 return 0; 581 } 582 583 static int rmi_f34v7_check_ui_firmware_size(struct f34_data *f34) 584 { 585 u16 block_count; 586 587 block_count = f34->v7.img.ui_firmware.size / f34->v7.block_size; 588 f34->update_size += block_count; 589 590 if (block_count != f34->v7.blkcount.ui_firmware) { 591 dev_err(&f34->fn->dev, 592 "UI firmware size mismatch: %d != %d\n", 593 block_count, f34->v7.blkcount.ui_firmware); 594 return -EINVAL; 595 } 596 597 return 0; 598 } 599 600 static int rmi_f34v7_check_ui_config_size(struct f34_data *f34) 601 { 602 u16 block_count; 603 604 block_count = f34->v7.img.ui_config.size / f34->v7.block_size; 605 f34->update_size += block_count; 606 607 if (block_count != f34->v7.blkcount.ui_config) { 608 dev_err(&f34->fn->dev, "UI config size mismatch\n"); 609 return -EINVAL; 610 } 611 612 return 0; 613 } 614 615 static int rmi_f34v7_check_dp_config_size(struct f34_data *f34) 616 { 617 u16 block_count; 618 619 block_count = f34->v7.img.dp_config.size / f34->v7.block_size; 620 f34->update_size += block_count; 621 622 if (block_count != f34->v7.blkcount.dp_config) { 623 dev_err(&f34->fn->dev, "Display config size mismatch\n"); 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 static int rmi_f34v7_check_guest_code_size(struct f34_data *f34) 631 { 632 u16 block_count; 633 634 block_count = f34->v7.img.guest_code.size / f34->v7.block_size; 635 f34->update_size += block_count; 636 637 if (block_count != f34->v7.blkcount.guest_code) { 638 dev_err(&f34->fn->dev, "Guest code size mismatch\n"); 639 return -EINVAL; 640 } 641 642 return 0; 643 } 644 645 static int rmi_f34v7_check_bl_config_size(struct f34_data *f34) 646 { 647 u16 block_count; 648 649 block_count = f34->v7.img.bl_config.size / f34->v7.block_size; 650 f34->update_size += block_count; 651 652 if (block_count != f34->v7.blkcount.bl_config) { 653 dev_err(&f34->fn->dev, "Bootloader config size mismatch\n"); 654 return -EINVAL; 655 } 656 657 return 0; 658 } 659 660 static int rmi_f34v7_erase_config(struct f34_data *f34) 661 { 662 int ret; 663 664 dev_info(&f34->fn->dev, "Erasing config...\n"); 665 666 init_completion(&f34->v7.cmd_done); 667 668 switch (f34->v7.config_area) { 669 case v7_UI_CONFIG_AREA: 670 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_CONFIG); 671 if (ret < 0) 672 return ret; 673 break; 674 case v7_DP_CONFIG_AREA: 675 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_DISP_CONFIG); 676 if (ret < 0) 677 return ret; 678 break; 679 case v7_BL_CONFIG_AREA: 680 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_BL_CONFIG); 681 if (ret < 0) 682 return ret; 683 break; 684 } 685 686 ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS); 687 if (ret < 0) 688 return ret; 689 690 return 0; 691 } 692 693 static int rmi_f34v7_erase_guest_code(struct f34_data *f34) 694 { 695 int ret; 696 697 dev_info(&f34->fn->dev, "Erasing guest code...\n"); 698 699 init_completion(&f34->v7.cmd_done); 700 701 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_GUEST_CODE); 702 if (ret < 0) 703 return ret; 704 705 ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS); 706 if (ret < 0) 707 return ret; 708 709 return 0; 710 } 711 712 static int rmi_f34v7_erase_all(struct f34_data *f34) 713 { 714 int ret; 715 716 dev_info(&f34->fn->dev, "Erasing firmware...\n"); 717 718 init_completion(&f34->v7.cmd_done); 719 720 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_FIRMWARE); 721 if (ret < 0) 722 return ret; 723 724 ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS); 725 if (ret < 0) 726 return ret; 727 728 f34->v7.config_area = v7_UI_CONFIG_AREA; 729 ret = rmi_f34v7_erase_config(f34); 730 if (ret < 0) 731 return ret; 732 733 if (f34->v7.has_display_cfg) { 734 f34->v7.config_area = v7_DP_CONFIG_AREA; 735 ret = rmi_f34v7_erase_config(f34); 736 if (ret < 0) 737 return ret; 738 } 739 740 if (f34->v7.new_partition_table && f34->v7.has_guest_code) { 741 ret = rmi_f34v7_erase_guest_code(f34); 742 if (ret < 0) 743 return ret; 744 } 745 746 return 0; 747 } 748 749 static int rmi_f34v7_read_blocks(struct f34_data *f34, 750 u16 block_cnt, u8 command) 751 { 752 int ret; 753 u8 base; 754 __le16 length; 755 u16 transfer; 756 u16 max_transfer; 757 u16 remaining = block_cnt; 758 u16 block_number = 0; 759 u16 index = 0; 760 761 base = f34->fn->fd.data_base_addr; 762 763 ret = rmi_f34v7_write_partition_id(f34, command); 764 if (ret < 0) 765 return ret; 766 767 ret = rmi_write_block(f34->fn->rmi_dev, 768 base + f34->v7.off.block_number, 769 &block_number, sizeof(block_number)); 770 if (ret < 0) { 771 dev_err(&f34->fn->dev, "%s: Failed to write block number\n", 772 __func__); 773 return ret; 774 } 775 776 max_transfer = min(f34->v7.payload_length, 777 (u16)(PAGE_SIZE / f34->v7.block_size)); 778 779 do { 780 transfer = min(remaining, max_transfer); 781 put_unaligned_le16(transfer, &length); 782 783 ret = rmi_write_block(f34->fn->rmi_dev, 784 base + f34->v7.off.transfer_length, 785 &length, sizeof(length)); 786 if (ret < 0) { 787 dev_err(&f34->fn->dev, 788 "%s: Write transfer length fail (%d remaining)\n", 789 __func__, remaining); 790 return ret; 791 } 792 793 init_completion(&f34->v7.cmd_done); 794 795 ret = rmi_f34v7_write_command(f34, command); 796 if (ret < 0) 797 return ret; 798 799 ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS); 800 if (ret < 0) 801 return ret; 802 803 ret = rmi_read_block(f34->fn->rmi_dev, 804 base + f34->v7.off.payload, 805 &f34->v7.read_config_buf[index], 806 transfer * f34->v7.block_size); 807 if (ret < 0) { 808 dev_err(&f34->fn->dev, 809 "%s: Read block failed (%d blks remaining)\n", 810 __func__, remaining); 811 return ret; 812 } 813 814 index += (transfer * f34->v7.block_size); 815 remaining -= transfer; 816 } while (remaining); 817 818 return 0; 819 } 820 821 static int rmi_f34v7_write_f34v7_blocks(struct f34_data *f34, 822 const void *block_ptr, u16 block_cnt, 823 u8 command) 824 { 825 int ret; 826 u8 base; 827 __le16 length; 828 u16 transfer; 829 u16 max_transfer; 830 u16 remaining = block_cnt; 831 u16 block_number = 0; 832 833 base = f34->fn->fd.data_base_addr; 834 835 ret = rmi_f34v7_write_partition_id(f34, command); 836 if (ret < 0) 837 return ret; 838 839 ret = rmi_write_block(f34->fn->rmi_dev, 840 base + f34->v7.off.block_number, 841 &block_number, sizeof(block_number)); 842 if (ret < 0) { 843 dev_err(&f34->fn->dev, "%s: Failed to write block number\n", 844 __func__); 845 return ret; 846 } 847 848 if (f34->v7.payload_length > (PAGE_SIZE / f34->v7.block_size)) 849 max_transfer = PAGE_SIZE / f34->v7.block_size; 850 else 851 max_transfer = f34->v7.payload_length; 852 853 do { 854 transfer = min(remaining, max_transfer); 855 put_unaligned_le16(transfer, &length); 856 857 init_completion(&f34->v7.cmd_done); 858 859 ret = rmi_write_block(f34->fn->rmi_dev, 860 base + f34->v7.off.transfer_length, 861 &length, sizeof(length)); 862 if (ret < 0) { 863 dev_err(&f34->fn->dev, 864 "%s: Write transfer length fail (%d remaining)\n", 865 __func__, remaining); 866 return ret; 867 } 868 869 ret = rmi_f34v7_write_command(f34, command); 870 if (ret < 0) 871 return ret; 872 873 ret = rmi_write_block(f34->fn->rmi_dev, 874 base + f34->v7.off.payload, 875 block_ptr, transfer * f34->v7.block_size); 876 if (ret < 0) { 877 dev_err(&f34->fn->dev, 878 "%s: Failed writing data (%d blks remaining)\n", 879 __func__, remaining); 880 return ret; 881 } 882 883 ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS); 884 if (ret < 0) 885 return ret; 886 887 block_ptr += (transfer * f34->v7.block_size); 888 remaining -= transfer; 889 f34->update_progress += transfer; 890 f34->update_status = (f34->update_progress * 100) / 891 f34->update_size; 892 } while (remaining); 893 894 return 0; 895 } 896 897 static int rmi_f34v7_write_config(struct f34_data *f34) 898 { 899 return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.config_data, 900 f34->v7.config_block_count, 901 v7_CMD_WRITE_CONFIG); 902 } 903 904 static int rmi_f34v7_write_ui_config(struct f34_data *f34) 905 { 906 f34->v7.config_area = v7_UI_CONFIG_AREA; 907 f34->v7.config_data = f34->v7.img.ui_config.data; 908 f34->v7.config_size = f34->v7.img.ui_config.size; 909 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size; 910 911 return rmi_f34v7_write_config(f34); 912 } 913 914 static int rmi_f34v7_write_dp_config(struct f34_data *f34) 915 { 916 f34->v7.config_area = v7_DP_CONFIG_AREA; 917 f34->v7.config_data = f34->v7.img.dp_config.data; 918 f34->v7.config_size = f34->v7.img.dp_config.size; 919 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size; 920 921 return rmi_f34v7_write_config(f34); 922 } 923 924 static int rmi_f34v7_write_guest_code(struct f34_data *f34) 925 { 926 return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.guest_code.data, 927 f34->v7.img.guest_code.size / 928 f34->v7.block_size, 929 v7_CMD_WRITE_GUEST_CODE); 930 } 931 932 static int rmi_f34v7_write_flash_config(struct f34_data *f34) 933 { 934 int ret; 935 936 f34->v7.config_area = v7_FLASH_CONFIG_AREA; 937 f34->v7.config_data = f34->v7.img.fl_config.data; 938 f34->v7.config_size = f34->v7.img.fl_config.size; 939 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size; 940 941 if (f34->v7.config_block_count != f34->v7.blkcount.fl_config) { 942 dev_err(&f34->fn->dev, "%s: Flash config size mismatch\n", 943 __func__); 944 return -EINVAL; 945 } 946 947 init_completion(&f34->v7.cmd_done); 948 949 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_FLASH_CONFIG); 950 if (ret < 0) 951 return ret; 952 953 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 954 "%s: Erase flash config command written\n", __func__); 955 956 ret = rmi_f34v7_wait_for_idle(f34, F34_WRITE_WAIT_MS); 957 if (ret < 0) 958 return ret; 959 960 ret = rmi_f34v7_write_config(f34); 961 if (ret < 0) 962 return ret; 963 964 return 0; 965 } 966 967 static int rmi_f34v7_write_partition_table(struct f34_data *f34) 968 { 969 u16 block_count; 970 int ret; 971 972 block_count = f34->v7.blkcount.bl_config; 973 f34->v7.config_area = v7_BL_CONFIG_AREA; 974 f34->v7.config_size = f34->v7.block_size * block_count; 975 devm_kfree(&f34->fn->dev, f34->v7.read_config_buf); 976 f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev, 977 f34->v7.config_size, GFP_KERNEL); 978 if (!f34->v7.read_config_buf) { 979 f34->v7.read_config_buf_size = 0; 980 return -ENOMEM; 981 } 982 983 f34->v7.read_config_buf_size = f34->v7.config_size; 984 985 ret = rmi_f34v7_read_blocks(f34, block_count, v7_CMD_READ_CONFIG); 986 if (ret < 0) 987 return ret; 988 989 ret = rmi_f34v7_erase_config(f34); 990 if (ret < 0) 991 return ret; 992 993 ret = rmi_f34v7_write_flash_config(f34); 994 if (ret < 0) 995 return ret; 996 997 f34->v7.config_area = v7_BL_CONFIG_AREA; 998 f34->v7.config_data = f34->v7.read_config_buf; 999 f34->v7.config_size = f34->v7.img.bl_config.size; 1000 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size; 1001 1002 ret = rmi_f34v7_write_config(f34); 1003 if (ret < 0) 1004 return ret; 1005 1006 return 0; 1007 } 1008 1009 static int rmi_f34v7_write_firmware(struct f34_data *f34) 1010 { 1011 u16 blk_count; 1012 1013 blk_count = f34->v7.img.ui_firmware.size / f34->v7.block_size; 1014 1015 return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.ui_firmware.data, 1016 blk_count, v7_CMD_WRITE_FW); 1017 } 1018 1019 static void rmi_f34v7_compare_partition_tables(struct f34_data *f34) 1020 { 1021 if (f34->v7.phyaddr.ui_firmware != f34->v7.img.phyaddr.ui_firmware) { 1022 f34->v7.new_partition_table = true; 1023 return; 1024 } 1025 1026 if (f34->v7.phyaddr.ui_config != f34->v7.img.phyaddr.ui_config) { 1027 f34->v7.new_partition_table = true; 1028 return; 1029 } 1030 1031 if (f34->v7.has_display_cfg && 1032 f34->v7.phyaddr.dp_config != f34->v7.img.phyaddr.dp_config) { 1033 f34->v7.new_partition_table = true; 1034 return; 1035 } 1036 1037 if (f34->v7.has_guest_code && 1038 f34->v7.phyaddr.guest_code != f34->v7.img.phyaddr.guest_code) { 1039 f34->v7.new_partition_table = true; 1040 return; 1041 } 1042 1043 f34->v7.new_partition_table = false; 1044 } 1045 1046 static void rmi_f34v7_parse_img_header_10_bl_container(struct f34_data *f34, 1047 const void *image) 1048 { 1049 int i; 1050 int num_of_containers; 1051 unsigned int addr; 1052 unsigned int container_id; 1053 unsigned int length; 1054 const void *content; 1055 const struct container_descriptor *descriptor; 1056 1057 num_of_containers = f34->v7.img.bootloader.size / 4 - 1; 1058 1059 for (i = 1; i <= num_of_containers; i++) { 1060 addr = get_unaligned_le32(f34->v7.img.bootloader.data + i * 4); 1061 descriptor = image + addr; 1062 container_id = le16_to_cpu(descriptor->container_id); 1063 content = image + le32_to_cpu(descriptor->content_address); 1064 length = le32_to_cpu(descriptor->content_length); 1065 switch (container_id) { 1066 case BL_CONFIG_CONTAINER: 1067 case GLOBAL_PARAMETERS_CONTAINER: 1068 f34->v7.img.bl_config.data = content; 1069 f34->v7.img.bl_config.size = length; 1070 break; 1071 case BL_LOCKDOWN_INFO_CONTAINER: 1072 case DEVICE_CONFIG_CONTAINER: 1073 f34->v7.img.lockdown.data = content; 1074 f34->v7.img.lockdown.size = length; 1075 break; 1076 default: 1077 break; 1078 } 1079 } 1080 } 1081 1082 static void rmi_f34v7_parse_image_header_10(struct f34_data *f34) 1083 { 1084 unsigned int i; 1085 unsigned int num_of_containers; 1086 unsigned int addr; 1087 unsigned int offset; 1088 unsigned int container_id; 1089 unsigned int length; 1090 const void *image = f34->v7.image; 1091 const u8 *content; 1092 const struct container_descriptor *descriptor; 1093 const struct image_header_10 *header = image; 1094 1095 f34->v7.img.checksum = le32_to_cpu(header->checksum); 1096 1097 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.img.checksum=%X\n", 1098 __func__, f34->v7.img.checksum); 1099 1100 /* address of top level container */ 1101 offset = le32_to_cpu(header->top_level_container_start_addr); 1102 descriptor = image + offset; 1103 1104 /* address of top level container content */ 1105 offset = le32_to_cpu(descriptor->content_address); 1106 num_of_containers = le32_to_cpu(descriptor->content_length) / 4; 1107 1108 for (i = 0; i < num_of_containers; i++) { 1109 addr = get_unaligned_le32(image + offset); 1110 offset += 4; 1111 descriptor = image + addr; 1112 container_id = le16_to_cpu(descriptor->container_id); 1113 content = image + le32_to_cpu(descriptor->content_address); 1114 length = le32_to_cpu(descriptor->content_length); 1115 1116 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 1117 "%s: container_id=%d, length=%d\n", __func__, 1118 container_id, length); 1119 1120 switch (container_id) { 1121 case UI_CONTAINER: 1122 case CORE_CODE_CONTAINER: 1123 f34->v7.img.ui_firmware.data = content; 1124 f34->v7.img.ui_firmware.size = length; 1125 break; 1126 case UI_CONFIG_CONTAINER: 1127 case CORE_CONFIG_CONTAINER: 1128 f34->v7.img.ui_config.data = content; 1129 f34->v7.img.ui_config.size = length; 1130 break; 1131 case BL_CONTAINER: 1132 f34->v7.img.bl_version = *content; 1133 f34->v7.img.bootloader.data = content; 1134 f34->v7.img.bootloader.size = length; 1135 rmi_f34v7_parse_img_header_10_bl_container(f34, image); 1136 break; 1137 case GUEST_CODE_CONTAINER: 1138 f34->v7.img.contains_guest_code = true; 1139 f34->v7.img.guest_code.data = content; 1140 f34->v7.img.guest_code.size = length; 1141 break; 1142 case DISPLAY_CONFIG_CONTAINER: 1143 f34->v7.img.contains_display_cfg = true; 1144 f34->v7.img.dp_config.data = content; 1145 f34->v7.img.dp_config.size = length; 1146 break; 1147 case FLASH_CONFIG_CONTAINER: 1148 f34->v7.img.contains_flash_config = true; 1149 f34->v7.img.fl_config.data = content; 1150 f34->v7.img.fl_config.size = length; 1151 break; 1152 case GENERAL_INFORMATION_CONTAINER: 1153 f34->v7.img.contains_firmware_id = true; 1154 f34->v7.img.firmware_id = 1155 get_unaligned_le32(content + 4); 1156 break; 1157 default: 1158 break; 1159 } 1160 } 1161 } 1162 1163 static int rmi_f34v7_parse_image_info(struct f34_data *f34) 1164 { 1165 const struct image_header_10 *header = f34->v7.image; 1166 1167 memset(&f34->v7.img, 0x00, sizeof(f34->v7.img)); 1168 1169 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, 1170 "%s: header->major_header_version = %d\n", 1171 __func__, header->major_header_version); 1172 1173 switch (header->major_header_version) { 1174 case IMAGE_HEADER_VERSION_10: 1175 rmi_f34v7_parse_image_header_10(f34); 1176 break; 1177 default: 1178 dev_err(&f34->fn->dev, "Unsupported image file format %02X\n", 1179 header->major_header_version); 1180 return -EINVAL; 1181 } 1182 1183 if (!f34->v7.img.contains_flash_config) { 1184 dev_err(&f34->fn->dev, "%s: No flash config in fw image\n", 1185 __func__); 1186 return -EINVAL; 1187 } 1188 1189 rmi_f34v7_parse_partition_table(f34, f34->v7.img.fl_config.data, 1190 &f34->v7.img.blkcount, &f34->v7.img.phyaddr); 1191 1192 rmi_f34v7_compare_partition_tables(f34); 1193 1194 return 0; 1195 } 1196 1197 int rmi_f34v7_do_reflash(struct f34_data *f34, const struct firmware *fw) 1198 { 1199 int ret; 1200 1201 rmi_f34v7_read_queries_bl_version(f34); 1202 1203 f34->v7.image = fw->data; 1204 f34->update_progress = 0; 1205 f34->update_size = 0; 1206 1207 ret = rmi_f34v7_parse_image_info(f34); 1208 if (ret < 0) 1209 goto fail; 1210 1211 if (!f34->v7.new_partition_table) { 1212 ret = rmi_f34v7_check_ui_firmware_size(f34); 1213 if (ret < 0) 1214 goto fail; 1215 1216 ret = rmi_f34v7_check_ui_config_size(f34); 1217 if (ret < 0) 1218 goto fail; 1219 1220 if (f34->v7.has_display_cfg && 1221 f34->v7.img.contains_display_cfg) { 1222 ret = rmi_f34v7_check_dp_config_size(f34); 1223 if (ret < 0) 1224 goto fail; 1225 } 1226 1227 if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) { 1228 ret = rmi_f34v7_check_guest_code_size(f34); 1229 if (ret < 0) 1230 goto fail; 1231 } 1232 } else { 1233 ret = rmi_f34v7_check_bl_config_size(f34); 1234 if (ret < 0) 1235 goto fail; 1236 } 1237 1238 ret = rmi_f34v7_erase_all(f34); 1239 if (ret < 0) 1240 goto fail; 1241 1242 if (f34->v7.new_partition_table) { 1243 ret = rmi_f34v7_write_partition_table(f34); 1244 if (ret < 0) 1245 goto fail; 1246 dev_info(&f34->fn->dev, "%s: Partition table programmed\n", 1247 __func__); 1248 } 1249 1250 dev_info(&f34->fn->dev, "Writing firmware (%d bytes)...\n", 1251 f34->v7.img.ui_firmware.size); 1252 1253 ret = rmi_f34v7_write_firmware(f34); 1254 if (ret < 0) 1255 goto fail; 1256 1257 dev_info(&f34->fn->dev, "Writing config (%d bytes)...\n", 1258 f34->v7.img.ui_config.size); 1259 1260 f34->v7.config_area = v7_UI_CONFIG_AREA; 1261 ret = rmi_f34v7_write_ui_config(f34); 1262 if (ret < 0) 1263 goto fail; 1264 1265 if (f34->v7.has_display_cfg && f34->v7.img.contains_display_cfg) { 1266 dev_info(&f34->fn->dev, "Writing display config...\n"); 1267 1268 ret = rmi_f34v7_write_dp_config(f34); 1269 if (ret < 0) 1270 goto fail; 1271 } 1272 1273 if (f34->v7.new_partition_table) { 1274 if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) { 1275 dev_info(&f34->fn->dev, "Writing guest code...\n"); 1276 1277 ret = rmi_f34v7_write_guest_code(f34); 1278 if (ret < 0) 1279 goto fail; 1280 } 1281 } 1282 1283 fail: 1284 return ret; 1285 } 1286 1287 static int rmi_f34v7_enter_flash_prog(struct f34_data *f34) 1288 { 1289 int ret; 1290 1291 f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask); 1292 1293 ret = rmi_f34v7_read_flash_status(f34); 1294 if (ret < 0) 1295 return ret; 1296 1297 if (f34->v7.in_bl_mode) 1298 return 0; 1299 1300 init_completion(&f34->v7.cmd_done); 1301 1302 ret = rmi_f34v7_write_command(f34, v7_CMD_ENABLE_FLASH_PROG); 1303 if (ret < 0) 1304 return ret; 1305 1306 ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS); 1307 if (ret < 0) 1308 return ret; 1309 1310 return 0; 1311 } 1312 1313 int rmi_f34v7_start_reflash(struct f34_data *f34, const struct firmware *fw) 1314 { 1315 int ret = 0; 1316 1317 f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask); 1318 1319 f34->v7.config_area = v7_UI_CONFIG_AREA; 1320 f34->v7.image = fw->data; 1321 1322 ret = rmi_f34v7_parse_image_info(f34); 1323 if (ret < 0) 1324 goto exit; 1325 1326 if (!f34->v7.force_update && f34->v7.new_partition_table) { 1327 dev_err(&f34->fn->dev, "%s: Partition table mismatch\n", 1328 __func__); 1329 ret = -EINVAL; 1330 goto exit; 1331 } 1332 1333 dev_info(&f34->fn->dev, "Firmware image OK\n"); 1334 1335 ret = rmi_f34v7_read_flash_status(f34); 1336 if (ret < 0) 1337 goto exit; 1338 1339 if (f34->v7.in_bl_mode) { 1340 dev_info(&f34->fn->dev, "%s: Device in bootloader mode\n", 1341 __func__); 1342 } 1343 1344 rmi_f34v7_enter_flash_prog(f34); 1345 1346 return 0; 1347 1348 exit: 1349 return ret; 1350 } 1351 1352 int rmi_f34v7_probe(struct f34_data *f34) 1353 { 1354 int ret; 1355 1356 /* Read bootloader version */ 1357 ret = rmi_read_block(f34->fn->rmi_dev, 1358 f34->fn->fd.query_base_addr + V7_BOOTLOADER_ID_OFFSET, 1359 f34->bootloader_id, 1360 sizeof(f34->bootloader_id)); 1361 if (ret < 0) { 1362 dev_err(&f34->fn->dev, "%s: Failed to read bootloader ID\n", 1363 __func__); 1364 return ret; 1365 } 1366 1367 if (f34->bootloader_id[1] == '5') { 1368 f34->bl_version = 5; 1369 } else if (f34->bootloader_id[1] == '6') { 1370 f34->bl_version = 6; 1371 } else if (f34->bootloader_id[1] == 7) { 1372 f34->bl_version = 7; 1373 } else { 1374 dev_err(&f34->fn->dev, "%s: Unrecognized bootloader version\n", 1375 __func__); 1376 return -EINVAL; 1377 } 1378 1379 memset(&f34->v7.blkcount, 0x00, sizeof(f34->v7.blkcount)); 1380 memset(&f34->v7.phyaddr, 0x00, sizeof(f34->v7.phyaddr)); 1381 1382 init_completion(&f34->v7.cmd_done); 1383 1384 ret = rmi_f34v7_read_queries(f34); 1385 if (ret < 0) 1386 return ret; 1387 1388 f34->v7.force_update = true; 1389 return 0; 1390 } 1391