1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Azoteq IQS7222A/B/C Capacitive Touch Controller 4 * 5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com> 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/i2c.h> 14 #include <linux/input.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/ktime.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 #include <asm/unaligned.h> 23 24 #define IQS7222_PROD_NUM 0x00 25 #define IQS7222_PROD_NUM_A 840 26 #define IQS7222_PROD_NUM_B 698 27 #define IQS7222_PROD_NUM_C 863 28 29 #define IQS7222_SYS_STATUS 0x10 30 #define IQS7222_SYS_STATUS_RESET BIT(3) 31 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1) 32 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0) 33 34 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14) 35 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15) 36 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14) 37 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8) 38 39 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0) 40 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8) 41 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8 42 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0) 43 #define IQS7222_SLDR_SETUP_3_CHAN_SEL_MASK GENMASK(9, 0) 44 45 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0) 46 47 #define IQS7222_SYS_SETUP 0xD0 48 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6) 49 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7) 50 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6) 51 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4) 52 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK 53 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2) 54 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0) 55 56 #define IQS7222_EVENT_MASK_ATI BIT(12) 57 58 #define IQS7222_COMMS_HOLD BIT(0) 59 #define IQS7222_COMMS_ERROR 0xEEEE 60 #define IQS7222_COMMS_RETRY_MS 50 61 #define IQS7222_COMMS_TIMEOUT_MS 100 62 #define IQS7222_RESET_TIMEOUT_MS 250 63 #define IQS7222_ATI_TIMEOUT_MS 2000 64 65 #define IQS7222_MAX_COLS_STAT 8 66 #define IQS7222_MAX_COLS_CYCLE 3 67 #define IQS7222_MAX_COLS_GLBL 3 68 #define IQS7222_MAX_COLS_BTN 3 69 #define IQS7222_MAX_COLS_CHAN 6 70 #define IQS7222_MAX_COLS_FILT 2 71 #define IQS7222_MAX_COLS_SLDR 11 72 #define IQS7222_MAX_COLS_GPIO 3 73 #define IQS7222_MAX_COLS_SYS 13 74 75 #define IQS7222_MAX_CHAN 20 76 #define IQS7222_MAX_SLDR 2 77 78 #define IQS7222_NUM_RETRIES 5 79 #define IQS7222_REG_OFFSET 0x100 80 81 enum iqs7222_reg_key_id { 82 IQS7222_REG_KEY_NONE, 83 IQS7222_REG_KEY_PROX, 84 IQS7222_REG_KEY_TOUCH, 85 IQS7222_REG_KEY_DEBOUNCE, 86 IQS7222_REG_KEY_TAP, 87 IQS7222_REG_KEY_AXIAL, 88 IQS7222_REG_KEY_WHEEL, 89 IQS7222_REG_KEY_NO_WHEEL, 90 IQS7222_REG_KEY_RESERVED 91 }; 92 93 enum iqs7222_reg_grp_id { 94 IQS7222_REG_GRP_STAT, 95 IQS7222_REG_GRP_CYCLE, 96 IQS7222_REG_GRP_GLBL, 97 IQS7222_REG_GRP_BTN, 98 IQS7222_REG_GRP_CHAN, 99 IQS7222_REG_GRP_FILT, 100 IQS7222_REG_GRP_SLDR, 101 IQS7222_REG_GRP_GPIO, 102 IQS7222_REG_GRP_SYS, 103 IQS7222_NUM_REG_GRPS 104 }; 105 106 static const char * const iqs7222_reg_grp_names[] = { 107 [IQS7222_REG_GRP_CYCLE] = "cycle", 108 [IQS7222_REG_GRP_CHAN] = "channel", 109 [IQS7222_REG_GRP_SLDR] = "slider", 110 [IQS7222_REG_GRP_GPIO] = "gpio", 111 }; 112 113 static const unsigned int iqs7222_max_cols[] = { 114 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT, 115 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE, 116 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL, 117 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN, 118 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN, 119 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT, 120 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR, 121 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO, 122 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS, 123 }; 124 125 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, }; 126 127 struct iqs7222_event_desc { 128 const char *name; 129 u16 mask; 130 u16 val; 131 u16 enable; 132 enum iqs7222_reg_key_id reg_key; 133 }; 134 135 static const struct iqs7222_event_desc iqs7222_kp_events[] = { 136 { 137 .name = "event-prox", 138 .enable = BIT(0), 139 .reg_key = IQS7222_REG_KEY_PROX, 140 }, 141 { 142 .name = "event-touch", 143 .enable = BIT(1), 144 .reg_key = IQS7222_REG_KEY_TOUCH, 145 }, 146 }; 147 148 static const struct iqs7222_event_desc iqs7222_sl_events[] = { 149 { .name = "event-press", }, 150 { 151 .name = "event-tap", 152 .mask = BIT(0), 153 .val = BIT(0), 154 .enable = BIT(0), 155 .reg_key = IQS7222_REG_KEY_TAP, 156 }, 157 { 158 .name = "event-swipe-pos", 159 .mask = BIT(5) | BIT(1), 160 .val = BIT(1), 161 .enable = BIT(1), 162 .reg_key = IQS7222_REG_KEY_AXIAL, 163 }, 164 { 165 .name = "event-swipe-neg", 166 .mask = BIT(5) | BIT(1), 167 .val = BIT(5) | BIT(1), 168 .enable = BIT(1), 169 .reg_key = IQS7222_REG_KEY_AXIAL, 170 }, 171 { 172 .name = "event-flick-pos", 173 .mask = BIT(5) | BIT(2), 174 .val = BIT(2), 175 .enable = BIT(2), 176 .reg_key = IQS7222_REG_KEY_AXIAL, 177 }, 178 { 179 .name = "event-flick-neg", 180 .mask = BIT(5) | BIT(2), 181 .val = BIT(5) | BIT(2), 182 .enable = BIT(2), 183 .reg_key = IQS7222_REG_KEY_AXIAL, 184 }, 185 }; 186 187 struct iqs7222_reg_grp_desc { 188 u16 base; 189 int num_row; 190 int num_col; 191 }; 192 193 struct iqs7222_dev_desc { 194 u16 prod_num; 195 u16 fw_major; 196 u16 fw_minor; 197 u16 sldr_res; 198 u16 touch_link; 199 u16 wheel_enable; 200 int allow_offset; 201 int event_offset; 202 int comms_offset; 203 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS]; 204 }; 205 206 static const struct iqs7222_dev_desc iqs7222_devs[] = { 207 { 208 .prod_num = IQS7222_PROD_NUM_A, 209 .fw_major = 1, 210 .fw_minor = 12, 211 .sldr_res = U8_MAX * 16, 212 .touch_link = 1768, 213 .allow_offset = 9, 214 .event_offset = 10, 215 .comms_offset = 12, 216 .reg_grps = { 217 [IQS7222_REG_GRP_STAT] = { 218 .base = IQS7222_SYS_STATUS, 219 .num_row = 1, 220 .num_col = 8, 221 }, 222 [IQS7222_REG_GRP_CYCLE] = { 223 .base = 0x8000, 224 .num_row = 7, 225 .num_col = 3, 226 }, 227 [IQS7222_REG_GRP_GLBL] = { 228 .base = 0x8700, 229 .num_row = 1, 230 .num_col = 3, 231 }, 232 [IQS7222_REG_GRP_BTN] = { 233 .base = 0x9000, 234 .num_row = 12, 235 .num_col = 3, 236 }, 237 [IQS7222_REG_GRP_CHAN] = { 238 .base = 0xA000, 239 .num_row = 12, 240 .num_col = 6, 241 }, 242 [IQS7222_REG_GRP_FILT] = { 243 .base = 0xAC00, 244 .num_row = 1, 245 .num_col = 2, 246 }, 247 [IQS7222_REG_GRP_SLDR] = { 248 .base = 0xB000, 249 .num_row = 2, 250 .num_col = 11, 251 }, 252 [IQS7222_REG_GRP_GPIO] = { 253 .base = 0xC000, 254 .num_row = 1, 255 .num_col = 3, 256 }, 257 [IQS7222_REG_GRP_SYS] = { 258 .base = IQS7222_SYS_SETUP, 259 .num_row = 1, 260 .num_col = 13, 261 }, 262 }, 263 }, 264 { 265 .prod_num = IQS7222_PROD_NUM_B, 266 .fw_major = 1, 267 .fw_minor = 43, 268 .event_offset = 10, 269 .comms_offset = 11, 270 .reg_grps = { 271 [IQS7222_REG_GRP_STAT] = { 272 .base = IQS7222_SYS_STATUS, 273 .num_row = 1, 274 .num_col = 6, 275 }, 276 [IQS7222_REG_GRP_CYCLE] = { 277 .base = 0x8000, 278 .num_row = 10, 279 .num_col = 2, 280 }, 281 [IQS7222_REG_GRP_GLBL] = { 282 .base = 0x8A00, 283 .num_row = 1, 284 .num_col = 3, 285 }, 286 [IQS7222_REG_GRP_BTN] = { 287 .base = 0x9000, 288 .num_row = 20, 289 .num_col = 2, 290 }, 291 [IQS7222_REG_GRP_CHAN] = { 292 .base = 0xB000, 293 .num_row = 20, 294 .num_col = 4, 295 }, 296 [IQS7222_REG_GRP_FILT] = { 297 .base = 0xC400, 298 .num_row = 1, 299 .num_col = 2, 300 }, 301 [IQS7222_REG_GRP_SYS] = { 302 .base = IQS7222_SYS_SETUP, 303 .num_row = 1, 304 .num_col = 13, 305 }, 306 }, 307 }, 308 { 309 .prod_num = IQS7222_PROD_NUM_B, 310 .fw_major = 1, 311 .fw_minor = 27, 312 .reg_grps = { 313 [IQS7222_REG_GRP_STAT] = { 314 .base = IQS7222_SYS_STATUS, 315 .num_row = 1, 316 .num_col = 6, 317 }, 318 [IQS7222_REG_GRP_CYCLE] = { 319 .base = 0x8000, 320 .num_row = 10, 321 .num_col = 2, 322 }, 323 [IQS7222_REG_GRP_GLBL] = { 324 .base = 0x8A00, 325 .num_row = 1, 326 .num_col = 3, 327 }, 328 [IQS7222_REG_GRP_BTN] = { 329 .base = 0x9000, 330 .num_row = 20, 331 .num_col = 2, 332 }, 333 [IQS7222_REG_GRP_CHAN] = { 334 .base = 0xB000, 335 .num_row = 20, 336 .num_col = 4, 337 }, 338 [IQS7222_REG_GRP_FILT] = { 339 .base = 0xC400, 340 .num_row = 1, 341 .num_col = 2, 342 }, 343 [IQS7222_REG_GRP_SYS] = { 344 .base = IQS7222_SYS_SETUP, 345 .num_row = 1, 346 .num_col = 10, 347 }, 348 }, 349 }, 350 { 351 .prod_num = IQS7222_PROD_NUM_C, 352 .fw_major = 2, 353 .fw_minor = 6, 354 .sldr_res = U16_MAX, 355 .touch_link = 1686, 356 .wheel_enable = BIT(3), 357 .event_offset = 9, 358 .comms_offset = 10, 359 .reg_grps = { 360 [IQS7222_REG_GRP_STAT] = { 361 .base = IQS7222_SYS_STATUS, 362 .num_row = 1, 363 .num_col = 6, 364 }, 365 [IQS7222_REG_GRP_CYCLE] = { 366 .base = 0x8000, 367 .num_row = 5, 368 .num_col = 3, 369 }, 370 [IQS7222_REG_GRP_GLBL] = { 371 .base = 0x8500, 372 .num_row = 1, 373 .num_col = 3, 374 }, 375 [IQS7222_REG_GRP_BTN] = { 376 .base = 0x9000, 377 .num_row = 10, 378 .num_col = 3, 379 }, 380 [IQS7222_REG_GRP_CHAN] = { 381 .base = 0xA000, 382 .num_row = 10, 383 .num_col = 6, 384 }, 385 [IQS7222_REG_GRP_FILT] = { 386 .base = 0xAA00, 387 .num_row = 1, 388 .num_col = 2, 389 }, 390 [IQS7222_REG_GRP_SLDR] = { 391 .base = 0xB000, 392 .num_row = 2, 393 .num_col = 10, 394 }, 395 [IQS7222_REG_GRP_GPIO] = { 396 .base = 0xC000, 397 .num_row = 3, 398 .num_col = 3, 399 }, 400 [IQS7222_REG_GRP_SYS] = { 401 .base = IQS7222_SYS_SETUP, 402 .num_row = 1, 403 .num_col = 12, 404 }, 405 }, 406 }, 407 { 408 .prod_num = IQS7222_PROD_NUM_C, 409 .fw_major = 1, 410 .fw_minor = 13, 411 .sldr_res = U16_MAX, 412 .touch_link = 1674, 413 .wheel_enable = BIT(3), 414 .event_offset = 9, 415 .comms_offset = 10, 416 .reg_grps = { 417 [IQS7222_REG_GRP_STAT] = { 418 .base = IQS7222_SYS_STATUS, 419 .num_row = 1, 420 .num_col = 6, 421 }, 422 [IQS7222_REG_GRP_CYCLE] = { 423 .base = 0x8000, 424 .num_row = 5, 425 .num_col = 3, 426 }, 427 [IQS7222_REG_GRP_GLBL] = { 428 .base = 0x8500, 429 .num_row = 1, 430 .num_col = 3, 431 }, 432 [IQS7222_REG_GRP_BTN] = { 433 .base = 0x9000, 434 .num_row = 10, 435 .num_col = 3, 436 }, 437 [IQS7222_REG_GRP_CHAN] = { 438 .base = 0xA000, 439 .num_row = 10, 440 .num_col = 6, 441 }, 442 [IQS7222_REG_GRP_FILT] = { 443 .base = 0xAA00, 444 .num_row = 1, 445 .num_col = 2, 446 }, 447 [IQS7222_REG_GRP_SLDR] = { 448 .base = 0xB000, 449 .num_row = 2, 450 .num_col = 10, 451 }, 452 [IQS7222_REG_GRP_GPIO] = { 453 .base = 0xC000, 454 .num_row = 1, 455 .num_col = 3, 456 }, 457 [IQS7222_REG_GRP_SYS] = { 458 .base = IQS7222_SYS_SETUP, 459 .num_row = 1, 460 .num_col = 11, 461 }, 462 }, 463 }, 464 }; 465 466 struct iqs7222_prop_desc { 467 const char *name; 468 enum iqs7222_reg_grp_id reg_grp; 469 enum iqs7222_reg_key_id reg_key; 470 int reg_offset; 471 int reg_shift; 472 int reg_width; 473 int val_pitch; 474 int val_min; 475 int val_max; 476 bool invert; 477 const char *label; 478 }; 479 480 static const struct iqs7222_prop_desc iqs7222_props[] = { 481 { 482 .name = "azoteq,conv-period", 483 .reg_grp = IQS7222_REG_GRP_CYCLE, 484 .reg_offset = 0, 485 .reg_shift = 8, 486 .reg_width = 8, 487 .label = "conversion period", 488 }, 489 { 490 .name = "azoteq,conv-frac", 491 .reg_grp = IQS7222_REG_GRP_CYCLE, 492 .reg_offset = 0, 493 .reg_shift = 0, 494 .reg_width = 8, 495 .label = "conversion frequency fractional divider", 496 }, 497 { 498 .name = "azoteq,rx-float-inactive", 499 .reg_grp = IQS7222_REG_GRP_CYCLE, 500 .reg_offset = 1, 501 .reg_shift = 6, 502 .reg_width = 1, 503 .invert = true, 504 }, 505 { 506 .name = "azoteq,dead-time-enable", 507 .reg_grp = IQS7222_REG_GRP_CYCLE, 508 .reg_offset = 1, 509 .reg_shift = 5, 510 .reg_width = 1, 511 }, 512 { 513 .name = "azoteq,tx-freq-fosc", 514 .reg_grp = IQS7222_REG_GRP_CYCLE, 515 .reg_offset = 1, 516 .reg_shift = 4, 517 .reg_width = 1, 518 }, 519 { 520 .name = "azoteq,vbias-enable", 521 .reg_grp = IQS7222_REG_GRP_CYCLE, 522 .reg_offset = 1, 523 .reg_shift = 3, 524 .reg_width = 1, 525 }, 526 { 527 .name = "azoteq,sense-mode", 528 .reg_grp = IQS7222_REG_GRP_CYCLE, 529 .reg_offset = 1, 530 .reg_shift = 0, 531 .reg_width = 3, 532 .val_max = 3, 533 .label = "sensing mode", 534 }, 535 { 536 .name = "azoteq,iref-enable", 537 .reg_grp = IQS7222_REG_GRP_CYCLE, 538 .reg_offset = 2, 539 .reg_shift = 10, 540 .reg_width = 1, 541 }, 542 { 543 .name = "azoteq,iref-level", 544 .reg_grp = IQS7222_REG_GRP_CYCLE, 545 .reg_offset = 2, 546 .reg_shift = 4, 547 .reg_width = 4, 548 .label = "current reference level", 549 }, 550 { 551 .name = "azoteq,iref-trim", 552 .reg_grp = IQS7222_REG_GRP_CYCLE, 553 .reg_offset = 2, 554 .reg_shift = 0, 555 .reg_width = 4, 556 .label = "current reference trim", 557 }, 558 { 559 .name = "azoteq,rf-filt-enable", 560 .reg_grp = IQS7222_REG_GRP_GLBL, 561 .reg_offset = 0, 562 .reg_shift = 15, 563 .reg_width = 1, 564 }, 565 { 566 .name = "azoteq,max-counts", 567 .reg_grp = IQS7222_REG_GRP_GLBL, 568 .reg_offset = 0, 569 .reg_shift = 13, 570 .reg_width = 2, 571 .label = "maximum counts", 572 }, 573 { 574 .name = "azoteq,auto-mode", 575 .reg_grp = IQS7222_REG_GRP_GLBL, 576 .reg_offset = 0, 577 .reg_shift = 2, 578 .reg_width = 2, 579 .label = "number of conversions", 580 }, 581 { 582 .name = "azoteq,ati-frac-div-fine", 583 .reg_grp = IQS7222_REG_GRP_GLBL, 584 .reg_offset = 1, 585 .reg_shift = 9, 586 .reg_width = 5, 587 .label = "ATI fine fractional divider", 588 }, 589 { 590 .name = "azoteq,ati-frac-div-coarse", 591 .reg_grp = IQS7222_REG_GRP_GLBL, 592 .reg_offset = 1, 593 .reg_shift = 0, 594 .reg_width = 5, 595 .label = "ATI coarse fractional divider", 596 }, 597 { 598 .name = "azoteq,ati-comp-select", 599 .reg_grp = IQS7222_REG_GRP_GLBL, 600 .reg_offset = 2, 601 .reg_shift = 0, 602 .reg_width = 10, 603 .label = "ATI compensation selection", 604 }, 605 { 606 .name = "azoteq,ati-band", 607 .reg_grp = IQS7222_REG_GRP_CHAN, 608 .reg_offset = 0, 609 .reg_shift = 12, 610 .reg_width = 2, 611 .label = "ATI band", 612 }, 613 { 614 .name = "azoteq,global-halt", 615 .reg_grp = IQS7222_REG_GRP_CHAN, 616 .reg_offset = 0, 617 .reg_shift = 11, 618 .reg_width = 1, 619 }, 620 { 621 .name = "azoteq,invert-enable", 622 .reg_grp = IQS7222_REG_GRP_CHAN, 623 .reg_offset = 0, 624 .reg_shift = 10, 625 .reg_width = 1, 626 }, 627 { 628 .name = "azoteq,dual-direction", 629 .reg_grp = IQS7222_REG_GRP_CHAN, 630 .reg_offset = 0, 631 .reg_shift = 9, 632 .reg_width = 1, 633 }, 634 { 635 .name = "azoteq,samp-cap-double", 636 .reg_grp = IQS7222_REG_GRP_CHAN, 637 .reg_offset = 0, 638 .reg_shift = 3, 639 .reg_width = 1, 640 }, 641 { 642 .name = "azoteq,vref-half", 643 .reg_grp = IQS7222_REG_GRP_CHAN, 644 .reg_offset = 0, 645 .reg_shift = 2, 646 .reg_width = 1, 647 }, 648 { 649 .name = "azoteq,proj-bias", 650 .reg_grp = IQS7222_REG_GRP_CHAN, 651 .reg_offset = 0, 652 .reg_shift = 0, 653 .reg_width = 2, 654 .label = "projected bias current", 655 }, 656 { 657 .name = "azoteq,ati-target", 658 .reg_grp = IQS7222_REG_GRP_CHAN, 659 .reg_offset = 1, 660 .reg_shift = 8, 661 .reg_width = 8, 662 .val_pitch = 8, 663 .label = "ATI target", 664 }, 665 { 666 .name = "azoteq,ati-base", 667 .reg_grp = IQS7222_REG_GRP_CHAN, 668 .reg_offset = 1, 669 .reg_shift = 3, 670 .reg_width = 5, 671 .val_pitch = 16, 672 .label = "ATI base", 673 }, 674 { 675 .name = "azoteq,ati-mode", 676 .reg_grp = IQS7222_REG_GRP_CHAN, 677 .reg_offset = 1, 678 .reg_shift = 0, 679 .reg_width = 3, 680 .val_max = 5, 681 .label = "ATI mode", 682 }, 683 { 684 .name = "azoteq,ati-frac-div-fine", 685 .reg_grp = IQS7222_REG_GRP_CHAN, 686 .reg_offset = 2, 687 .reg_shift = 9, 688 .reg_width = 5, 689 .label = "ATI fine fractional divider", 690 }, 691 { 692 .name = "azoteq,ati-frac-mult-coarse", 693 .reg_grp = IQS7222_REG_GRP_CHAN, 694 .reg_offset = 2, 695 .reg_shift = 5, 696 .reg_width = 4, 697 .label = "ATI coarse fractional multiplier", 698 }, 699 { 700 .name = "azoteq,ati-frac-div-coarse", 701 .reg_grp = IQS7222_REG_GRP_CHAN, 702 .reg_offset = 2, 703 .reg_shift = 0, 704 .reg_width = 5, 705 .label = "ATI coarse fractional divider", 706 }, 707 { 708 .name = "azoteq,ati-comp-div", 709 .reg_grp = IQS7222_REG_GRP_CHAN, 710 .reg_offset = 3, 711 .reg_shift = 11, 712 .reg_width = 5, 713 .label = "ATI compensation divider", 714 }, 715 { 716 .name = "azoteq,ati-comp-select", 717 .reg_grp = IQS7222_REG_GRP_CHAN, 718 .reg_offset = 3, 719 .reg_shift = 0, 720 .reg_width = 10, 721 .label = "ATI compensation selection", 722 }, 723 { 724 .name = "azoteq,debounce-exit", 725 .reg_grp = IQS7222_REG_GRP_BTN, 726 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 727 .reg_offset = 0, 728 .reg_shift = 12, 729 .reg_width = 4, 730 .label = "debounce exit factor", 731 }, 732 { 733 .name = "azoteq,debounce-enter", 734 .reg_grp = IQS7222_REG_GRP_BTN, 735 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 736 .reg_offset = 0, 737 .reg_shift = 8, 738 .reg_width = 4, 739 .label = "debounce entrance factor", 740 }, 741 { 742 .name = "azoteq,thresh", 743 .reg_grp = IQS7222_REG_GRP_BTN, 744 .reg_key = IQS7222_REG_KEY_PROX, 745 .reg_offset = 0, 746 .reg_shift = 0, 747 .reg_width = 8, 748 .val_max = 127, 749 .label = "threshold", 750 }, 751 { 752 .name = "azoteq,thresh", 753 .reg_grp = IQS7222_REG_GRP_BTN, 754 .reg_key = IQS7222_REG_KEY_TOUCH, 755 .reg_offset = 1, 756 .reg_shift = 0, 757 .reg_width = 8, 758 .label = "threshold", 759 }, 760 { 761 .name = "azoteq,hyst", 762 .reg_grp = IQS7222_REG_GRP_BTN, 763 .reg_key = IQS7222_REG_KEY_TOUCH, 764 .reg_offset = 1, 765 .reg_shift = 8, 766 .reg_width = 8, 767 .label = "hysteresis", 768 }, 769 { 770 .name = "azoteq,lta-beta-lp", 771 .reg_grp = IQS7222_REG_GRP_FILT, 772 .reg_offset = 0, 773 .reg_shift = 12, 774 .reg_width = 4, 775 .label = "low-power mode long-term average beta", 776 }, 777 { 778 .name = "azoteq,lta-beta-np", 779 .reg_grp = IQS7222_REG_GRP_FILT, 780 .reg_offset = 0, 781 .reg_shift = 8, 782 .reg_width = 4, 783 .label = "normal-power mode long-term average beta", 784 }, 785 { 786 .name = "azoteq,counts-beta-lp", 787 .reg_grp = IQS7222_REG_GRP_FILT, 788 .reg_offset = 0, 789 .reg_shift = 4, 790 .reg_width = 4, 791 .label = "low-power mode counts beta", 792 }, 793 { 794 .name = "azoteq,counts-beta-np", 795 .reg_grp = IQS7222_REG_GRP_FILT, 796 .reg_offset = 0, 797 .reg_shift = 0, 798 .reg_width = 4, 799 .label = "normal-power mode counts beta", 800 }, 801 { 802 .name = "azoteq,lta-fast-beta-lp", 803 .reg_grp = IQS7222_REG_GRP_FILT, 804 .reg_offset = 1, 805 .reg_shift = 4, 806 .reg_width = 4, 807 .label = "low-power mode long-term average fast beta", 808 }, 809 { 810 .name = "azoteq,lta-fast-beta-np", 811 .reg_grp = IQS7222_REG_GRP_FILT, 812 .reg_offset = 1, 813 .reg_shift = 0, 814 .reg_width = 4, 815 .label = "normal-power mode long-term average fast beta", 816 }, 817 { 818 .name = "azoteq,lower-cal", 819 .reg_grp = IQS7222_REG_GRP_SLDR, 820 .reg_offset = 0, 821 .reg_shift = 8, 822 .reg_width = 8, 823 .label = "lower calibration", 824 }, 825 { 826 .name = "azoteq,static-beta", 827 .reg_grp = IQS7222_REG_GRP_SLDR, 828 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 829 .reg_offset = 0, 830 .reg_shift = 6, 831 .reg_width = 1, 832 }, 833 { 834 .name = "azoteq,bottom-beta", 835 .reg_grp = IQS7222_REG_GRP_SLDR, 836 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 837 .reg_offset = 0, 838 .reg_shift = 3, 839 .reg_width = 3, 840 .label = "bottom beta", 841 }, 842 { 843 .name = "azoteq,static-beta", 844 .reg_grp = IQS7222_REG_GRP_SLDR, 845 .reg_key = IQS7222_REG_KEY_WHEEL, 846 .reg_offset = 0, 847 .reg_shift = 7, 848 .reg_width = 1, 849 }, 850 { 851 .name = "azoteq,bottom-beta", 852 .reg_grp = IQS7222_REG_GRP_SLDR, 853 .reg_key = IQS7222_REG_KEY_WHEEL, 854 .reg_offset = 0, 855 .reg_shift = 4, 856 .reg_width = 3, 857 .label = "bottom beta", 858 }, 859 { 860 .name = "azoteq,bottom-speed", 861 .reg_grp = IQS7222_REG_GRP_SLDR, 862 .reg_offset = 1, 863 .reg_shift = 8, 864 .reg_width = 8, 865 .label = "bottom speed", 866 }, 867 { 868 .name = "azoteq,upper-cal", 869 .reg_grp = IQS7222_REG_GRP_SLDR, 870 .reg_offset = 1, 871 .reg_shift = 0, 872 .reg_width = 8, 873 .label = "upper calibration", 874 }, 875 { 876 .name = "azoteq,gesture-max-ms", 877 .reg_grp = IQS7222_REG_GRP_SLDR, 878 .reg_key = IQS7222_REG_KEY_TAP, 879 .reg_offset = 9, 880 .reg_shift = 8, 881 .reg_width = 8, 882 .val_pitch = 4, 883 .label = "maximum gesture time", 884 }, 885 { 886 .name = "azoteq,gesture-min-ms", 887 .reg_grp = IQS7222_REG_GRP_SLDR, 888 .reg_key = IQS7222_REG_KEY_TAP, 889 .reg_offset = 9, 890 .reg_shift = 3, 891 .reg_width = 5, 892 .val_pitch = 4, 893 .label = "minimum gesture time", 894 }, 895 { 896 .name = "azoteq,gesture-dist", 897 .reg_grp = IQS7222_REG_GRP_SLDR, 898 .reg_key = IQS7222_REG_KEY_AXIAL, 899 .reg_offset = 10, 900 .reg_shift = 8, 901 .reg_width = 8, 902 .val_pitch = 16, 903 .label = "gesture distance", 904 }, 905 { 906 .name = "azoteq,gesture-max-ms", 907 .reg_grp = IQS7222_REG_GRP_SLDR, 908 .reg_key = IQS7222_REG_KEY_AXIAL, 909 .reg_offset = 10, 910 .reg_shift = 0, 911 .reg_width = 8, 912 .val_pitch = 4, 913 .label = "maximum gesture time", 914 }, 915 { 916 .name = "drive-open-drain", 917 .reg_grp = IQS7222_REG_GRP_GPIO, 918 .reg_offset = 0, 919 .reg_shift = 1, 920 .reg_width = 1, 921 }, 922 { 923 .name = "azoteq,timeout-ati-ms", 924 .reg_grp = IQS7222_REG_GRP_SYS, 925 .reg_offset = 1, 926 .reg_shift = 0, 927 .reg_width = 16, 928 .val_pitch = 500, 929 .label = "ATI error timeout", 930 }, 931 { 932 .name = "azoteq,rate-ati-ms", 933 .reg_grp = IQS7222_REG_GRP_SYS, 934 .reg_offset = 2, 935 .reg_shift = 0, 936 .reg_width = 16, 937 .label = "ATI report rate", 938 }, 939 { 940 .name = "azoteq,timeout-np-ms", 941 .reg_grp = IQS7222_REG_GRP_SYS, 942 .reg_offset = 3, 943 .reg_shift = 0, 944 .reg_width = 16, 945 .label = "normal-power mode timeout", 946 }, 947 { 948 .name = "azoteq,rate-np-ms", 949 .reg_grp = IQS7222_REG_GRP_SYS, 950 .reg_offset = 4, 951 .reg_shift = 0, 952 .reg_width = 16, 953 .val_max = 3000, 954 .label = "normal-power mode report rate", 955 }, 956 { 957 .name = "azoteq,timeout-lp-ms", 958 .reg_grp = IQS7222_REG_GRP_SYS, 959 .reg_offset = 5, 960 .reg_shift = 0, 961 .reg_width = 16, 962 .label = "low-power mode timeout", 963 }, 964 { 965 .name = "azoteq,rate-lp-ms", 966 .reg_grp = IQS7222_REG_GRP_SYS, 967 .reg_offset = 6, 968 .reg_shift = 0, 969 .reg_width = 16, 970 .val_max = 3000, 971 .label = "low-power mode report rate", 972 }, 973 { 974 .name = "azoteq,timeout-ulp-ms", 975 .reg_grp = IQS7222_REG_GRP_SYS, 976 .reg_offset = 7, 977 .reg_shift = 0, 978 .reg_width = 16, 979 .label = "ultra-low-power mode timeout", 980 }, 981 { 982 .name = "azoteq,rate-ulp-ms", 983 .reg_grp = IQS7222_REG_GRP_SYS, 984 .reg_offset = 8, 985 .reg_shift = 0, 986 .reg_width = 16, 987 .val_max = 3000, 988 .label = "ultra-low-power mode report rate", 989 }, 990 }; 991 992 struct iqs7222_private { 993 const struct iqs7222_dev_desc *dev_desc; 994 struct gpio_desc *reset_gpio; 995 struct gpio_desc *irq_gpio; 996 struct i2c_client *client; 997 struct input_dev *keypad; 998 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 999 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 1000 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)]; 1001 unsigned int sl_axis[IQS7222_MAX_SLDR]; 1002 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE]; 1003 u16 glbl_setup[IQS7222_MAX_COLS_GLBL]; 1004 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN]; 1005 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN]; 1006 u16 filt_setup[IQS7222_MAX_COLS_FILT]; 1007 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR]; 1008 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO]; 1009 u16 sys_setup[IQS7222_MAX_COLS_SYS]; 1010 }; 1011 1012 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222, 1013 enum iqs7222_reg_grp_id reg_grp, int row) 1014 { 1015 switch (reg_grp) { 1016 case IQS7222_REG_GRP_CYCLE: 1017 return iqs7222->cycle_setup[row]; 1018 1019 case IQS7222_REG_GRP_GLBL: 1020 return iqs7222->glbl_setup; 1021 1022 case IQS7222_REG_GRP_BTN: 1023 return iqs7222->btn_setup[row]; 1024 1025 case IQS7222_REG_GRP_CHAN: 1026 return iqs7222->chan_setup[row]; 1027 1028 case IQS7222_REG_GRP_FILT: 1029 return iqs7222->filt_setup; 1030 1031 case IQS7222_REG_GRP_SLDR: 1032 return iqs7222->sldr_setup[row]; 1033 1034 case IQS7222_REG_GRP_GPIO: 1035 return iqs7222->gpio_setup[row]; 1036 1037 case IQS7222_REG_GRP_SYS: 1038 return iqs7222->sys_setup; 1039 1040 default: 1041 return NULL; 1042 } 1043 } 1044 1045 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms) 1046 { 1047 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms); 1048 int ret; 1049 1050 do { 1051 usleep_range(1000, 1100); 1052 1053 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1054 if (ret < 0) 1055 return ret; 1056 else if (ret > 0) 1057 return 0; 1058 } while (ktime_compare(ktime_get(), irq_timeout) < 0); 1059 1060 return -EBUSY; 1061 } 1062 1063 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222) 1064 { 1065 struct i2c_client *client = iqs7222->client; 1066 int error; 1067 1068 if (!iqs7222->reset_gpio) 1069 return 0; 1070 1071 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1); 1072 usleep_range(1000, 1100); 1073 1074 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); 1075 1076 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS); 1077 if (error) 1078 dev_err(&client->dev, "Failed to reset device: %d\n", error); 1079 1080 return error; 1081 } 1082 1083 static int iqs7222_force_comms(struct iqs7222_private *iqs7222) 1084 { 1085 u8 msg_buf[] = { 0xFF, 0x00, }; 1086 int ret; 1087 1088 /* 1089 * The device cannot communicate until it asserts its interrupt (RDY) 1090 * pin. Attempts to do so while RDY is deasserted return an ACK; how- 1091 * ever all write data is ignored, and all read data returns 0xEE. 1092 * 1093 * Unsolicited communication must be preceded by a special force com- 1094 * munication command, after which the device eventually asserts its 1095 * RDY pin and agrees to communicate. 1096 * 1097 * Regardless of whether communication is forced or the result of an 1098 * interrupt, the device automatically deasserts its RDY pin once it 1099 * detects an I2C stop condition, or a timeout expires. 1100 */ 1101 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1102 if (ret < 0) 1103 return ret; 1104 else if (ret > 0) 1105 return 0; 1106 1107 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf)); 1108 if (ret < (int)sizeof(msg_buf)) { 1109 if (ret >= 0) 1110 ret = -EIO; 1111 1112 /* 1113 * The datasheet states that the host must wait to retry any 1114 * failed attempt to communicate over I2C. 1115 */ 1116 msleep(IQS7222_COMMS_RETRY_MS); 1117 return ret; 1118 } 1119 1120 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS); 1121 } 1122 1123 static int iqs7222_read_burst(struct iqs7222_private *iqs7222, 1124 u16 reg, void *val, u16 num_val) 1125 { 1126 u8 reg_buf[sizeof(__be16)]; 1127 int ret, i; 1128 struct i2c_client *client = iqs7222->client; 1129 struct i2c_msg msg[] = { 1130 { 1131 .addr = client->addr, 1132 .flags = 0, 1133 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8), 1134 .buf = reg_buf, 1135 }, 1136 { 1137 .addr = client->addr, 1138 .flags = I2C_M_RD, 1139 .len = num_val * sizeof(__le16), 1140 .buf = (u8 *)val, 1141 }, 1142 }; 1143 1144 if (reg > U8_MAX) 1145 put_unaligned_be16(reg, reg_buf); 1146 else 1147 *reg_buf = (u8)reg; 1148 1149 /* 1150 * The following loop protects against an edge case in which the RDY 1151 * pin is automatically deasserted just as the read is initiated. In 1152 * that case, the read must be retried using forced communication. 1153 */ 1154 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1155 ret = iqs7222_force_comms(iqs7222); 1156 if (ret < 0) 1157 continue; 1158 1159 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); 1160 if (ret < (int)ARRAY_SIZE(msg)) { 1161 if (ret >= 0) 1162 ret = -EIO; 1163 1164 msleep(IQS7222_COMMS_RETRY_MS); 1165 continue; 1166 } 1167 1168 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) { 1169 ret = -ENODATA; 1170 continue; 1171 } 1172 1173 ret = 0; 1174 break; 1175 } 1176 1177 /* 1178 * The following delay ensures the device has deasserted the RDY pin 1179 * following the I2C stop condition. 1180 */ 1181 usleep_range(50, 100); 1182 1183 if (ret < 0) 1184 dev_err(&client->dev, 1185 "Failed to read from address 0x%04X: %d\n", reg, ret); 1186 1187 return ret; 1188 } 1189 1190 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val) 1191 { 1192 __le16 val_buf; 1193 int error; 1194 1195 error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1); 1196 if (error) 1197 return error; 1198 1199 *val = le16_to_cpu(val_buf); 1200 1201 return 0; 1202 } 1203 1204 static int iqs7222_write_burst(struct iqs7222_private *iqs7222, 1205 u16 reg, const void *val, u16 num_val) 1206 { 1207 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8); 1208 int val_len = num_val * sizeof(__le16); 1209 int msg_len = reg_len + val_len; 1210 int ret, i; 1211 struct i2c_client *client = iqs7222->client; 1212 u8 *msg_buf; 1213 1214 msg_buf = kzalloc(msg_len, GFP_KERNEL); 1215 if (!msg_buf) 1216 return -ENOMEM; 1217 1218 if (reg > U8_MAX) 1219 put_unaligned_be16(reg, msg_buf); 1220 else 1221 *msg_buf = (u8)reg; 1222 1223 memcpy(msg_buf + reg_len, val, val_len); 1224 1225 /* 1226 * The following loop protects against an edge case in which the RDY 1227 * pin is automatically asserted just before the force communication 1228 * command is sent. 1229 * 1230 * In that case, the subsequent I2C stop condition tricks the device 1231 * into preemptively deasserting the RDY pin and the command must be 1232 * sent again. 1233 */ 1234 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1235 ret = iqs7222_force_comms(iqs7222); 1236 if (ret < 0) 1237 continue; 1238 1239 ret = i2c_master_send(client, msg_buf, msg_len); 1240 if (ret < msg_len) { 1241 if (ret >= 0) 1242 ret = -EIO; 1243 1244 msleep(IQS7222_COMMS_RETRY_MS); 1245 continue; 1246 } 1247 1248 ret = 0; 1249 break; 1250 } 1251 1252 kfree(msg_buf); 1253 1254 usleep_range(50, 100); 1255 1256 if (ret < 0) 1257 dev_err(&client->dev, 1258 "Failed to write to address 0x%04X: %d\n", reg, ret); 1259 1260 return ret; 1261 } 1262 1263 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val) 1264 { 1265 __le16 val_buf = cpu_to_le16(val); 1266 1267 return iqs7222_write_burst(iqs7222, reg, &val_buf, 1); 1268 } 1269 1270 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222) 1271 { 1272 struct i2c_client *client = iqs7222->client; 1273 ktime_t ati_timeout; 1274 u16 sys_status = 0; 1275 u16 sys_setup = iqs7222->sys_setup[0] & ~IQS7222_SYS_SETUP_ACK_RESET; 1276 int error, i; 1277 1278 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1279 /* 1280 * Trigger ATI from streaming and normal-power modes so that 1281 * the RDY pin continues to be asserted during ATI. 1282 */ 1283 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1284 sys_setup | 1285 IQS7222_SYS_SETUP_REDO_ATI); 1286 if (error) 1287 return error; 1288 1289 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS); 1290 1291 do { 1292 error = iqs7222_irq_poll(iqs7222, 1293 IQS7222_COMMS_TIMEOUT_MS); 1294 if (error) 1295 continue; 1296 1297 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS, 1298 &sys_status); 1299 if (error) 1300 return error; 1301 1302 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE) 1303 continue; 1304 1305 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR) 1306 break; 1307 1308 /* 1309 * Use stream-in-touch mode if either slider reports 1310 * absolute position. 1311 */ 1312 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit) 1313 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH 1314 : IQS7222_SYS_SETUP_INTF_MODE_EVENT; 1315 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO; 1316 1317 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1318 sys_setup); 1319 } while (ktime_compare(ktime_get(), ati_timeout) < 0); 1320 1321 dev_err(&client->dev, 1322 "ATI attempt %d of %d failed with status 0x%02X, %s\n", 1323 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status, 1324 i < IQS7222_NUM_RETRIES ? "retrying..." : "stopping"); 1325 } 1326 1327 return -ETIMEDOUT; 1328 } 1329 1330 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir) 1331 { 1332 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1333 int comms_offset = dev_desc->comms_offset; 1334 int error, i, j, k; 1335 1336 /* 1337 * Take advantage of the stop-bit disable function, if available, to 1338 * save the trouble of having to reopen a communication window after 1339 * each burst read or write. 1340 */ 1341 if (comms_offset) { 1342 u16 comms_setup; 1343 1344 error = iqs7222_read_word(iqs7222, 1345 IQS7222_SYS_SETUP + comms_offset, 1346 &comms_setup); 1347 if (error) 1348 return error; 1349 1350 error = iqs7222_write_word(iqs7222, 1351 IQS7222_SYS_SETUP + comms_offset, 1352 comms_setup | IQS7222_COMMS_HOLD); 1353 if (error) 1354 return error; 1355 } 1356 1357 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { 1358 int num_row = dev_desc->reg_grps[i].num_row; 1359 int num_col = dev_desc->reg_grps[i].num_col; 1360 u16 reg = dev_desc->reg_grps[i].base; 1361 __le16 *val_buf; 1362 u16 *val; 1363 1364 if (!num_col) 1365 continue; 1366 1367 val = iqs7222_setup(iqs7222, i, 0); 1368 if (!val) 1369 continue; 1370 1371 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL); 1372 if (!val_buf) 1373 return -ENOMEM; 1374 1375 for (j = 0; j < num_row; j++) { 1376 switch (dir) { 1377 case READ: 1378 error = iqs7222_read_burst(iqs7222, reg, 1379 val_buf, num_col); 1380 for (k = 0; k < num_col; k++) 1381 val[k] = le16_to_cpu(val_buf[k]); 1382 break; 1383 1384 case WRITE: 1385 for (k = 0; k < num_col; k++) 1386 val_buf[k] = cpu_to_le16(val[k]); 1387 error = iqs7222_write_burst(iqs7222, reg, 1388 val_buf, num_col); 1389 break; 1390 1391 default: 1392 error = -EINVAL; 1393 } 1394 1395 if (error) 1396 break; 1397 1398 reg += IQS7222_REG_OFFSET; 1399 val += iqs7222_max_cols[i]; 1400 } 1401 1402 kfree(val_buf); 1403 1404 if (error) 1405 return error; 1406 } 1407 1408 if (comms_offset) { 1409 u16 comms_setup; 1410 1411 error = iqs7222_read_word(iqs7222, 1412 IQS7222_SYS_SETUP + comms_offset, 1413 &comms_setup); 1414 if (error) 1415 return error; 1416 1417 error = iqs7222_write_word(iqs7222, 1418 IQS7222_SYS_SETUP + comms_offset, 1419 comms_setup & ~IQS7222_COMMS_HOLD); 1420 if (error) 1421 return error; 1422 } 1423 1424 if (dir == READ) 1425 return 0; 1426 1427 return iqs7222_ati_trigger(iqs7222); 1428 } 1429 1430 static int iqs7222_dev_info(struct iqs7222_private *iqs7222) 1431 { 1432 struct i2c_client *client = iqs7222->client; 1433 bool prod_num_valid = false; 1434 __le16 dev_id[3]; 1435 int error, i; 1436 1437 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id, 1438 ARRAY_SIZE(dev_id)); 1439 if (error) 1440 return error; 1441 1442 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { 1443 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) 1444 continue; 1445 1446 prod_num_valid = true; 1447 1448 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major) 1449 continue; 1450 1451 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor) 1452 continue; 1453 1454 iqs7222->dev_desc = &iqs7222_devs[i]; 1455 return 0; 1456 } 1457 1458 if (prod_num_valid) 1459 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n", 1460 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2])); 1461 else 1462 dev_err(&client->dev, "Unrecognized product number: %u\n", 1463 le16_to_cpu(dev_id[0])); 1464 1465 return -EINVAL; 1466 } 1467 1468 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222, 1469 struct fwnode_handle *child_node, 1470 int child_enable, u16 child_link) 1471 { 1472 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1473 struct i2c_client *client = iqs7222->client; 1474 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row; 1475 int error, count, i; 1476 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)]; 1477 1478 if (!num_gpio) 1479 return 0; 1480 1481 if (!fwnode_property_present(child_node, "azoteq,gpio-select")) 1482 return 0; 1483 1484 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select"); 1485 if (count > num_gpio) { 1486 dev_err(&client->dev, "Invalid number of %s GPIOs\n", 1487 fwnode_get_name(child_node)); 1488 return -EINVAL; 1489 } else if (count < 0) { 1490 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n", 1491 fwnode_get_name(child_node), count); 1492 return count; 1493 } 1494 1495 error = fwnode_property_read_u32_array(child_node, 1496 "azoteq,gpio-select", 1497 gpio_sel, count); 1498 if (error) { 1499 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n", 1500 fwnode_get_name(child_node), error); 1501 return error; 1502 } 1503 1504 for (i = 0; i < count; i++) { 1505 u16 *gpio_setup; 1506 1507 if (gpio_sel[i] >= num_gpio) { 1508 dev_err(&client->dev, "Invalid %s GPIO: %u\n", 1509 fwnode_get_name(child_node), gpio_sel[i]); 1510 return -EINVAL; 1511 } 1512 1513 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]]; 1514 1515 if (gpio_setup[2] && child_link != gpio_setup[2]) { 1516 dev_err(&client->dev, 1517 "Conflicting GPIO %u event types\n", 1518 gpio_sel[i]); 1519 return -EINVAL; 1520 } 1521 1522 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; 1523 gpio_setup[1] |= child_enable; 1524 gpio_setup[2] = child_link; 1525 } 1526 1527 return 0; 1528 } 1529 1530 static int iqs7222_parse_props(struct iqs7222_private *iqs7222, 1531 struct fwnode_handle **child_node, 1532 int child_index, 1533 enum iqs7222_reg_grp_id reg_grp, 1534 enum iqs7222_reg_key_id reg_key) 1535 { 1536 u16 *setup = iqs7222_setup(iqs7222, reg_grp, child_index); 1537 struct fwnode_handle *reg_grp_node = *child_node; 1538 struct i2c_client *client = iqs7222->client; 1539 char reg_grp_name[16]; 1540 int i; 1541 1542 switch (reg_grp) { 1543 case IQS7222_REG_GRP_CYCLE: 1544 case IQS7222_REG_GRP_CHAN: 1545 case IQS7222_REG_GRP_SLDR: 1546 case IQS7222_REG_GRP_GPIO: 1547 case IQS7222_REG_GRP_BTN: 1548 /* 1549 * These groups derive a child node and return it to the caller 1550 * for additional group-specific processing. In some cases, the 1551 * child node may have already been derived. 1552 */ 1553 if (*child_node) 1554 break; 1555 1556 snprintf(reg_grp_name, sizeof(reg_grp_name), "%s-%d", 1557 iqs7222_reg_grp_names[reg_grp], child_index); 1558 1559 reg_grp_node = device_get_named_child_node(&client->dev, 1560 reg_grp_name); 1561 if (!reg_grp_node) 1562 return 0; 1563 1564 *child_node = reg_grp_node; 1565 break; 1566 1567 case IQS7222_REG_GRP_GLBL: 1568 case IQS7222_REG_GRP_FILT: 1569 case IQS7222_REG_GRP_SYS: 1570 /* 1571 * These groups are not organized beneath a child node, nor are 1572 * they subject to any additional processing by the caller. 1573 */ 1574 reg_grp_node = dev_fwnode(&client->dev); 1575 break; 1576 1577 default: 1578 return -EINVAL; 1579 } 1580 1581 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { 1582 const char *name = iqs7222_props[i].name; 1583 int reg_offset = iqs7222_props[i].reg_offset; 1584 int reg_shift = iqs7222_props[i].reg_shift; 1585 int reg_width = iqs7222_props[i].reg_width; 1586 int val_pitch = iqs7222_props[i].val_pitch ? : 1; 1587 int val_min = iqs7222_props[i].val_min; 1588 int val_max = iqs7222_props[i].val_max; 1589 bool invert = iqs7222_props[i].invert; 1590 const char *label = iqs7222_props[i].label ? : name; 1591 unsigned int val; 1592 int error; 1593 1594 if (iqs7222_props[i].reg_grp != reg_grp || 1595 iqs7222_props[i].reg_key != reg_key) 1596 continue; 1597 1598 /* 1599 * Boolean register fields are one bit wide; they are forcibly 1600 * reset to provide a means to undo changes by a bootloader if 1601 * necessary. 1602 * 1603 * Scalar fields, on the other hand, are left untouched unless 1604 * their corresponding properties are present. 1605 */ 1606 if (reg_width == 1) { 1607 if (invert) 1608 setup[reg_offset] |= BIT(reg_shift); 1609 else 1610 setup[reg_offset] &= ~BIT(reg_shift); 1611 } 1612 1613 if (!fwnode_property_present(reg_grp_node, name)) 1614 continue; 1615 1616 if (reg_width == 1) { 1617 if (invert) 1618 setup[reg_offset] &= ~BIT(reg_shift); 1619 else 1620 setup[reg_offset] |= BIT(reg_shift); 1621 1622 continue; 1623 } 1624 1625 error = fwnode_property_read_u32(reg_grp_node, name, &val); 1626 if (error) { 1627 dev_err(&client->dev, "Failed to read %s %s: %d\n", 1628 fwnode_get_name(reg_grp_node), label, error); 1629 return error; 1630 } 1631 1632 if (!val_max) 1633 val_max = GENMASK(reg_width - 1, 0) * val_pitch; 1634 1635 if (val < val_min || val > val_max) { 1636 dev_err(&client->dev, "Invalid %s %s: %u\n", 1637 fwnode_get_name(reg_grp_node), label, val); 1638 return -EINVAL; 1639 } 1640 1641 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, 1642 reg_shift); 1643 setup[reg_offset] |= (val / val_pitch << reg_shift); 1644 } 1645 1646 return 0; 1647 } 1648 1649 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222, int cycle_index) 1650 { 1651 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index]; 1652 struct i2c_client *client = iqs7222->client; 1653 struct fwnode_handle *cycle_node = NULL; 1654 unsigned int pins[9]; 1655 int error, count, i; 1656 1657 /* 1658 * Each channel shares a cycle with one other channel; the mapping of 1659 * channels to cycles is fixed. Properties defined for a cycle impact 1660 * both channels tied to the cycle. 1661 */ 1662 error = iqs7222_parse_props(iqs7222, &cycle_node, cycle_index, 1663 IQS7222_REG_GRP_CYCLE, 1664 IQS7222_REG_KEY_NONE); 1665 if (error) 1666 return error; 1667 1668 if (!cycle_node) 1669 return 0; 1670 1671 /* 1672 * Unlike channels which are restricted to a select range of CRx pins 1673 * based on channel number, any cycle can claim any of the device's 9 1674 * CTx pins (CTx0-8). 1675 */ 1676 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable")) 1677 return 0; 1678 1679 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable"); 1680 if (count < 0) { 1681 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n", 1682 fwnode_get_name(cycle_node), count); 1683 return count; 1684 } else if (count > ARRAY_SIZE(pins)) { 1685 dev_err(&client->dev, "Invalid number of %s CTx pins\n", 1686 fwnode_get_name(cycle_node)); 1687 return -EINVAL; 1688 } 1689 1690 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable", 1691 pins, count); 1692 if (error) { 1693 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n", 1694 fwnode_get_name(cycle_node), error); 1695 return error; 1696 } 1697 1698 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7); 1699 1700 for (i = 0; i < count; i++) { 1701 if (pins[i] > 8) { 1702 dev_err(&client->dev, "Invalid %s CTx pin: %u\n", 1703 fwnode_get_name(cycle_node), pins[i]); 1704 return -EINVAL; 1705 } 1706 1707 cycle_setup[1] |= BIT(pins[i] + 7); 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222, int chan_index) 1714 { 1715 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1716 struct i2c_client *client = iqs7222->client; 1717 struct fwnode_handle *chan_node = NULL; 1718 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 1719 int ext_chan = rounddown(num_chan, 10); 1720 int error, i; 1721 u16 *chan_setup = iqs7222->chan_setup[chan_index]; 1722 u16 *sys_setup = iqs7222->sys_setup; 1723 unsigned int val; 1724 1725 error = iqs7222_parse_props(iqs7222, &chan_node, chan_index, 1726 IQS7222_REG_GRP_CHAN, 1727 IQS7222_REG_KEY_NONE); 1728 if (error) 1729 return error; 1730 1731 if (!chan_node) 1732 return 0; 1733 1734 if (dev_desc->allow_offset) { 1735 sys_setup[dev_desc->allow_offset] |= BIT(chan_index); 1736 if (fwnode_property_present(chan_node, "azoteq,ulp-allow")) 1737 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index); 1738 } 1739 1740 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; 1741 1742 /* 1743 * The reference channel function allows for differential measurements 1744 * and is only available in the case of IQS7222A or IQS7222C. 1745 */ 1746 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 && 1747 fwnode_property_present(chan_node, "azoteq,ref-select")) { 1748 u16 *ref_setup; 1749 1750 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select", 1751 &val); 1752 if (error) { 1753 dev_err(&client->dev, 1754 "Failed to read %s reference channel: %d\n", 1755 fwnode_get_name(chan_node), error); 1756 return error; 1757 } 1758 1759 if (val >= ext_chan) { 1760 dev_err(&client->dev, 1761 "Invalid %s reference channel: %u\n", 1762 fwnode_get_name(chan_node), val); 1763 return -EINVAL; 1764 } 1765 1766 ref_setup = iqs7222->chan_setup[val]; 1767 1768 /* 1769 * Configure the current channel as a follower of the selected 1770 * reference channel. 1771 */ 1772 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; 1773 chan_setup[4] = val * 42 + 1048; 1774 1775 if (!fwnode_property_read_u32(chan_node, "azoteq,ref-weight", 1776 &val)) { 1777 if (val > U16_MAX) { 1778 dev_err(&client->dev, 1779 "Invalid %s reference weight: %u\n", 1780 fwnode_get_name(chan_node), val); 1781 return -EINVAL; 1782 } 1783 1784 chan_setup[5] = val; 1785 } 1786 1787 /* 1788 * Configure the selected channel as a reference channel which 1789 * serves the current channel. 1790 */ 1791 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; 1792 ref_setup[5] |= BIT(chan_index); 1793 1794 ref_setup[4] = dev_desc->touch_link; 1795 if (fwnode_property_present(chan_node, "azoteq,use-prox")) 1796 ref_setup[4] -= 2; 1797 } 1798 1799 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) { 1800 /* 1801 * Each channel can claim up to 4 CRx pins. The first half of 1802 * the channels can use CRx0-3, while the second half can use 1803 * CRx4-7. 1804 */ 1805 unsigned int pins[4]; 1806 int count; 1807 1808 count = fwnode_property_count_u32(chan_node, 1809 "azoteq,rx-enable"); 1810 if (count < 0) { 1811 dev_err(&client->dev, 1812 "Failed to count %s CRx pins: %d\n", 1813 fwnode_get_name(chan_node), count); 1814 return count; 1815 } else if (count > ARRAY_SIZE(pins)) { 1816 dev_err(&client->dev, 1817 "Invalid number of %s CRx pins\n", 1818 fwnode_get_name(chan_node)); 1819 return -EINVAL; 1820 } 1821 1822 error = fwnode_property_read_u32_array(chan_node, 1823 "azoteq,rx-enable", 1824 pins, count); 1825 if (error) { 1826 dev_err(&client->dev, 1827 "Failed to read %s CRx pins: %d\n", 1828 fwnode_get_name(chan_node), error); 1829 return error; 1830 } 1831 1832 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); 1833 1834 for (i = 0; i < count; i++) { 1835 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; 1836 1837 if (pins[i] < min_crx || pins[i] > min_crx + 3) { 1838 dev_err(&client->dev, 1839 "Invalid %s CRx pin: %u\n", 1840 fwnode_get_name(chan_node), pins[i]); 1841 return -EINVAL; 1842 } 1843 1844 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); 1845 } 1846 } 1847 1848 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { 1849 const char *event_name = iqs7222_kp_events[i].name; 1850 u16 event_enable = iqs7222_kp_events[i].enable; 1851 struct fwnode_handle *event_node; 1852 1853 event_node = fwnode_get_named_child_node(chan_node, event_name); 1854 if (!event_node) 1855 continue; 1856 1857 error = iqs7222_parse_props(iqs7222, &event_node, chan_index, 1858 IQS7222_REG_GRP_BTN, 1859 iqs7222_kp_events[i].reg_key); 1860 if (error) 1861 return error; 1862 1863 error = iqs7222_gpio_select(iqs7222, event_node, 1864 BIT(chan_index), 1865 dev_desc->touch_link - (i ? 0 : 2)); 1866 if (error) 1867 return error; 1868 1869 if (!fwnode_property_read_u32(event_node, 1870 "azoteq,timeout-press-ms", 1871 &val)) { 1872 /* 1873 * The IQS7222B employs a global pair of press timeout 1874 * registers as opposed to channel-specific registers. 1875 */ 1876 u16 *setup = dev_desc->reg_grps 1877 [IQS7222_REG_GRP_BTN].num_col > 2 ? 1878 &iqs7222->btn_setup[chan_index][2] : 1879 &sys_setup[9]; 1880 1881 if (val > U8_MAX * 500) { 1882 dev_err(&client->dev, 1883 "Invalid %s press timeout: %u\n", 1884 fwnode_get_name(chan_node), val); 1885 return -EINVAL; 1886 } 1887 1888 *setup &= ~(U8_MAX << i * 8); 1889 *setup |= (val / 500 << i * 8); 1890 } 1891 1892 error = fwnode_property_read_u32(event_node, "linux,code", 1893 &val); 1894 if (error) { 1895 dev_err(&client->dev, "Failed to read %s code: %d\n", 1896 fwnode_get_name(chan_node), error); 1897 return error; 1898 } 1899 1900 iqs7222->kp_code[chan_index][i] = val; 1901 iqs7222->kp_type[chan_index][i] = EV_KEY; 1902 1903 if (fwnode_property_present(event_node, "linux,input-type")) { 1904 error = fwnode_property_read_u32(event_node, 1905 "linux,input-type", 1906 &val); 1907 if (error) { 1908 dev_err(&client->dev, 1909 "Failed to read %s input type: %d\n", 1910 fwnode_get_name(chan_node), error); 1911 return error; 1912 } 1913 1914 if (val != EV_KEY && val != EV_SW) { 1915 dev_err(&client->dev, 1916 "Invalid %s input type: %u\n", 1917 fwnode_get_name(chan_node), val); 1918 return -EINVAL; 1919 } 1920 1921 iqs7222->kp_type[chan_index][i] = val; 1922 } 1923 1924 /* 1925 * Reference channels can opt out of event reporting by using 1926 * KEY_RESERVED in place of a true key or switch code. 1927 */ 1928 if (iqs7222->kp_type[chan_index][i] == EV_KEY && 1929 iqs7222->kp_code[chan_index][i] == KEY_RESERVED) 1930 continue; 1931 1932 input_set_capability(iqs7222->keypad, 1933 iqs7222->kp_type[chan_index][i], 1934 iqs7222->kp_code[chan_index][i]); 1935 1936 if (!dev_desc->event_offset) 1937 continue; 1938 1939 sys_setup[dev_desc->event_offset] |= event_enable; 1940 } 1941 1942 /* 1943 * The following call handles a special pair of properties that apply 1944 * to a channel node, but reside within the button (event) group. 1945 */ 1946 return iqs7222_parse_props(iqs7222, &chan_node, chan_index, 1947 IQS7222_REG_GRP_BTN, 1948 IQS7222_REG_KEY_DEBOUNCE); 1949 } 1950 1951 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222, int sldr_index) 1952 { 1953 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1954 struct i2c_client *client = iqs7222->client; 1955 struct fwnode_handle *sldr_node = NULL; 1956 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 1957 int ext_chan = rounddown(num_chan, 10); 1958 int count, error, reg_offset, i; 1959 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index]; 1960 u16 *sys_setup = iqs7222->sys_setup; 1961 unsigned int chan_sel[4], val; 1962 1963 error = iqs7222_parse_props(iqs7222, &sldr_node, sldr_index, 1964 IQS7222_REG_GRP_SLDR, 1965 IQS7222_REG_KEY_NONE); 1966 if (error) 1967 return error; 1968 1969 if (!sldr_node) 1970 return 0; 1971 1972 /* 1973 * Each slider can be spread across 3 to 4 channels. It is possible to 1974 * select only 2 channels, but doing so prevents the slider from using 1975 * the specified resolution. 1976 */ 1977 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select"); 1978 if (count < 0) { 1979 dev_err(&client->dev, "Failed to count %s channels: %d\n", 1980 fwnode_get_name(sldr_node), count); 1981 return count; 1982 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) { 1983 dev_err(&client->dev, "Invalid number of %s channels\n", 1984 fwnode_get_name(sldr_node)); 1985 return -EINVAL; 1986 } 1987 1988 error = fwnode_property_read_u32_array(sldr_node, 1989 "azoteq,channel-select", 1990 chan_sel, count); 1991 if (error) { 1992 dev_err(&client->dev, "Failed to read %s channels: %d\n", 1993 fwnode_get_name(sldr_node), error); 1994 return error; 1995 } 1996 1997 /* 1998 * Resolution and top speed, if small enough, are packed into a single 1999 * register. Otherwise, each occupies its own register and the rest of 2000 * the slider-related register addresses are offset by one. 2001 */ 2002 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; 2003 2004 sldr_setup[0] |= count; 2005 sldr_setup[3 + reg_offset] &= ~IQS7222_SLDR_SETUP_3_CHAN_SEL_MASK; 2006 2007 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { 2008 sldr_setup[5 + reg_offset + i] = 0; 2009 if (i >= count) 2010 continue; 2011 2012 if (chan_sel[i] >= ext_chan) { 2013 dev_err(&client->dev, "Invalid %s channel: %u\n", 2014 fwnode_get_name(sldr_node), chan_sel[i]); 2015 return -EINVAL; 2016 } 2017 2018 /* 2019 * The following fields indicate which channels participate in 2020 * the slider, as well as each channel's relative placement. 2021 */ 2022 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]); 2023 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080; 2024 } 2025 2026 sldr_setup[4 + reg_offset] = dev_desc->touch_link; 2027 if (fwnode_property_present(sldr_node, "azoteq,use-prox")) 2028 sldr_setup[4 + reg_offset] -= 2; 2029 2030 if (!fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val)) { 2031 if (!val || val > dev_desc->sldr_res) { 2032 dev_err(&client->dev, "Invalid %s size: %u\n", 2033 fwnode_get_name(sldr_node), val); 2034 return -EINVAL; 2035 } 2036 2037 if (reg_offset) { 2038 sldr_setup[3] = val; 2039 } else { 2040 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK; 2041 sldr_setup[2] |= (val / 16 << 2042 IQS7222_SLDR_SETUP_2_RES_SHIFT); 2043 } 2044 } 2045 2046 if (!fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val)) { 2047 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) { 2048 dev_err(&client->dev, "Invalid %s top speed: %u\n", 2049 fwnode_get_name(sldr_node), val); 2050 return -EINVAL; 2051 } 2052 2053 if (reg_offset) { 2054 sldr_setup[2] = val; 2055 } else { 2056 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK; 2057 sldr_setup[2] |= (val / 4); 2058 } 2059 } 2060 2061 if (!fwnode_property_read_u32(sldr_node, "linux,axis", &val)) { 2062 u16 sldr_max = sldr_setup[3] - 1; 2063 2064 if (!reg_offset) { 2065 sldr_max = sldr_setup[2]; 2066 2067 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK; 2068 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT; 2069 2070 sldr_max = sldr_max * 16 - 1; 2071 } 2072 2073 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); 2074 iqs7222->sl_axis[sldr_index] = val; 2075 } 2076 2077 if (dev_desc->wheel_enable) { 2078 sldr_setup[0] &= ~dev_desc->wheel_enable; 2079 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL) 2080 sldr_setup[0] |= dev_desc->wheel_enable; 2081 } 2082 2083 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { 2084 const char *event_name = iqs7222_sl_events[i].name; 2085 struct fwnode_handle *event_node; 2086 2087 /* 2088 * The absence of a register offset means the remaining fields 2089 * in the group represent gesture settings. 2090 */ 2091 if (iqs7222_sl_events[i].enable && !reg_offset) 2092 sldr_setup[9] &= ~iqs7222_sl_events[i].enable; 2093 2094 event_node = fwnode_get_named_child_node(sldr_node, event_name); 2095 if (!event_node) 2096 continue; 2097 2098 error = iqs7222_parse_props(iqs7222, &event_node, sldr_index, 2099 IQS7222_REG_GRP_SLDR, 2100 reg_offset ? 2101 IQS7222_REG_KEY_RESERVED : 2102 iqs7222_sl_events[i].reg_key); 2103 if (error) 2104 return error; 2105 2106 error = fwnode_property_read_u32(event_node, "linux,code", 2107 &val); 2108 if (error) { 2109 dev_err(&client->dev, "Failed to read %s code: %d\n", 2110 fwnode_get_name(sldr_node), error); 2111 return error; 2112 } 2113 2114 iqs7222->sl_code[sldr_index][i] = val; 2115 input_set_capability(iqs7222->keypad, EV_KEY, val); 2116 2117 /* 2118 * The press/release event is determined based on whether the 2119 * coordinate field reports 0xFFFF and has no explicit enable 2120 * control. 2121 */ 2122 if (!iqs7222_sl_events[i].enable || reg_offset) 2123 continue; 2124 2125 sldr_setup[9] |= iqs7222_sl_events[i].enable; 2126 2127 error = iqs7222_gpio_select(iqs7222, event_node, 2128 iqs7222_sl_events[i].enable, 2129 1568 + sldr_index * 30); 2130 if (error) 2131 return error; 2132 2133 if (!dev_desc->event_offset) 2134 continue; 2135 2136 sys_setup[dev_desc->event_offset] |= BIT(10 + sldr_index); 2137 } 2138 2139 /* 2140 * The following call handles a special pair of properties that shift 2141 * to make room for a wheel enable control in the case of IQS7222C. 2142 */ 2143 return iqs7222_parse_props(iqs7222, &sldr_node, sldr_index, 2144 IQS7222_REG_GRP_SLDR, 2145 dev_desc->wheel_enable ? 2146 IQS7222_REG_KEY_WHEEL : 2147 IQS7222_REG_KEY_NO_WHEEL); 2148 } 2149 2150 static int iqs7222_parse_all(struct iqs7222_private *iqs7222) 2151 { 2152 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2153 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps; 2154 u16 *sys_setup = iqs7222->sys_setup; 2155 int error, i; 2156 2157 if (dev_desc->event_offset) 2158 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI; 2159 2160 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CYCLE].num_row; i++) { 2161 error = iqs7222_parse_cycle(iqs7222, i); 2162 if (error) 2163 return error; 2164 } 2165 2166 error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_GLBL, 2167 IQS7222_REG_KEY_NONE); 2168 if (error) 2169 return error; 2170 2171 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { 2172 struct fwnode_handle *gpio_node = NULL; 2173 u16 *gpio_setup = iqs7222->gpio_setup[i]; 2174 int j; 2175 2176 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; 2177 gpio_setup[1] = 0; 2178 gpio_setup[2] = 0; 2179 2180 error = iqs7222_parse_props(iqs7222, &gpio_node, i, 2181 IQS7222_REG_GRP_GPIO, 2182 IQS7222_REG_KEY_NONE); 2183 if (error) 2184 return error; 2185 2186 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1) 2187 continue; 2188 2189 /* 2190 * The IQS7222C exposes multiple GPIO and must be informed 2191 * as to which GPIO this group represents. 2192 */ 2193 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) 2194 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); 2195 2196 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); 2197 } 2198 2199 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { 2200 u16 *chan_setup = iqs7222->chan_setup[i]; 2201 2202 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; 2203 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; 2204 2205 chan_setup[5] = 0; 2206 } 2207 2208 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { 2209 error = iqs7222_parse_chan(iqs7222, i); 2210 if (error) 2211 return error; 2212 } 2213 2214 error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_FILT, 2215 IQS7222_REG_KEY_NONE); 2216 if (error) 2217 return error; 2218 2219 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2220 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2221 2222 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; 2223 2224 error = iqs7222_parse_sldr(iqs7222, i); 2225 if (error) 2226 return error; 2227 } 2228 2229 sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; 2230 sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; 2231 2232 sys_setup[0] |= IQS7222_SYS_SETUP_ACK_RESET; 2233 2234 return iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_SYS, 2235 IQS7222_REG_KEY_NONE); 2236 } 2237 2238 static int iqs7222_report(struct iqs7222_private *iqs7222) 2239 { 2240 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2241 struct i2c_client *client = iqs7222->client; 2242 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 2243 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col; 2244 int error, i, j; 2245 __le16 status[IQS7222_MAX_COLS_STAT]; 2246 2247 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status, 2248 num_stat); 2249 if (error) 2250 return error; 2251 2252 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { 2253 dev_err(&client->dev, "Unexpected device reset\n"); 2254 return iqs7222_dev_init(iqs7222, WRITE); 2255 } 2256 2257 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { 2258 dev_err(&client->dev, "Unexpected ATI error\n"); 2259 return iqs7222_ati_trigger(iqs7222); 2260 } 2261 2262 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) 2263 return 0; 2264 2265 for (i = 0; i < num_chan; i++) { 2266 u16 *chan_setup = iqs7222->chan_setup[i]; 2267 2268 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) 2269 continue; 2270 2271 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { 2272 /* 2273 * Proximity state begins at offset 2 and spills into 2274 * offset 3 for devices with more than 16 channels. 2275 * 2276 * Touch state begins at the first offset immediately 2277 * following proximity state. 2278 */ 2279 int k = 2 + j * (num_chan > 16 ? 2 : 1); 2280 u16 state = le16_to_cpu(status[k + i / 16]); 2281 2282 input_event(iqs7222->keypad, 2283 iqs7222->kp_type[i][j], 2284 iqs7222->kp_code[i][j], 2285 !!(state & BIT(i % 16))); 2286 } 2287 } 2288 2289 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2290 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2291 u16 sldr_pos = le16_to_cpu(status[4 + i]); 2292 u16 state = le16_to_cpu(status[6 + i]); 2293 2294 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) 2295 continue; 2296 2297 if (sldr_pos < dev_desc->sldr_res) 2298 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i], 2299 sldr_pos); 2300 2301 for (j = 0; j < ARRAY_SIZE(iqs7222_sl_events); j++) { 2302 u16 mask = iqs7222_sl_events[j].mask; 2303 u16 val = iqs7222_sl_events[j].val; 2304 2305 if (!iqs7222_sl_events[j].enable) { 2306 input_report_key(iqs7222->keypad, 2307 iqs7222->sl_code[i][j], 2308 sldr_pos < dev_desc->sldr_res); 2309 continue; 2310 } 2311 2312 /* 2313 * The remaining offsets represent gesture state, and 2314 * are discarded in the case of IQS7222C because only 2315 * absolute position is reported. 2316 */ 2317 if (num_stat < IQS7222_MAX_COLS_STAT) 2318 continue; 2319 2320 input_report_key(iqs7222->keypad, 2321 iqs7222->sl_code[i][j], 2322 (state & mask) == val); 2323 } 2324 } 2325 2326 input_sync(iqs7222->keypad); 2327 2328 return 0; 2329 } 2330 2331 static irqreturn_t iqs7222_irq(int irq, void *context) 2332 { 2333 struct iqs7222_private *iqs7222 = context; 2334 2335 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED; 2336 } 2337 2338 static int iqs7222_probe(struct i2c_client *client) 2339 { 2340 struct iqs7222_private *iqs7222; 2341 unsigned long irq_flags; 2342 int error, irq; 2343 2344 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL); 2345 if (!iqs7222) 2346 return -ENOMEM; 2347 2348 i2c_set_clientdata(client, iqs7222); 2349 iqs7222->client = client; 2350 2351 iqs7222->keypad = devm_input_allocate_device(&client->dev); 2352 if (!iqs7222->keypad) 2353 return -ENOMEM; 2354 2355 iqs7222->keypad->name = client->name; 2356 iqs7222->keypad->id.bustype = BUS_I2C; 2357 2358 /* 2359 * The RDY pin behaves as an interrupt, but must also be polled ahead 2360 * of unsolicited I2C communication. As such, it is first opened as a 2361 * GPIO and then passed to gpiod_to_irq() to register the interrupt. 2362 */ 2363 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN); 2364 if (IS_ERR(iqs7222->irq_gpio)) { 2365 error = PTR_ERR(iqs7222->irq_gpio); 2366 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n", 2367 error); 2368 return error; 2369 } 2370 2371 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 2372 GPIOD_OUT_HIGH); 2373 if (IS_ERR(iqs7222->reset_gpio)) { 2374 error = PTR_ERR(iqs7222->reset_gpio); 2375 dev_err(&client->dev, "Failed to request reset GPIO: %d\n", 2376 error); 2377 return error; 2378 } 2379 2380 error = iqs7222_hard_reset(iqs7222); 2381 if (error) 2382 return error; 2383 2384 error = iqs7222_dev_info(iqs7222); 2385 if (error) 2386 return error; 2387 2388 error = iqs7222_dev_init(iqs7222, READ); 2389 if (error) 2390 return error; 2391 2392 error = iqs7222_parse_all(iqs7222); 2393 if (error) 2394 return error; 2395 2396 error = iqs7222_dev_init(iqs7222, WRITE); 2397 if (error) 2398 return error; 2399 2400 error = iqs7222_report(iqs7222); 2401 if (error) 2402 return error; 2403 2404 error = input_register_device(iqs7222->keypad); 2405 if (error) { 2406 dev_err(&client->dev, "Failed to register device: %d\n", error); 2407 return error; 2408 } 2409 2410 irq = gpiod_to_irq(iqs7222->irq_gpio); 2411 if (irq < 0) 2412 return irq; 2413 2414 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW 2415 : IRQF_TRIGGER_HIGH; 2416 irq_flags |= IRQF_ONESHOT; 2417 2418 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq, 2419 irq_flags, client->name, iqs7222); 2420 if (error) 2421 dev_err(&client->dev, "Failed to request IRQ: %d\n", error); 2422 2423 return error; 2424 } 2425 2426 static const struct of_device_id iqs7222_of_match[] = { 2427 { .compatible = "azoteq,iqs7222a" }, 2428 { .compatible = "azoteq,iqs7222b" }, 2429 { .compatible = "azoteq,iqs7222c" }, 2430 { } 2431 }; 2432 MODULE_DEVICE_TABLE(of, iqs7222_of_match); 2433 2434 static struct i2c_driver iqs7222_i2c_driver = { 2435 .driver = { 2436 .name = "iqs7222", 2437 .of_match_table = iqs7222_of_match, 2438 }, 2439 .probe_new = iqs7222_probe, 2440 }; 2441 module_i2c_driver(iqs7222_i2c_driver); 2442 2443 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>"); 2444 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C Capacitive Touch Controller"); 2445 MODULE_LICENSE("GPL"); 2446