1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Azoteq IQS7222A/B/C Capacitive Touch Controller 4 * 5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com> 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/i2c.h> 14 #include <linux/input.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/ktime.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 #include <asm/unaligned.h> 23 24 #define IQS7222_PROD_NUM 0x00 25 #define IQS7222_PROD_NUM_A 840 26 #define IQS7222_PROD_NUM_B 698 27 #define IQS7222_PROD_NUM_C 863 28 29 #define IQS7222_SYS_STATUS 0x10 30 #define IQS7222_SYS_STATUS_RESET BIT(3) 31 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1) 32 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0) 33 34 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14) 35 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15) 36 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14) 37 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8) 38 39 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0) 40 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8) 41 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8 42 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0) 43 44 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0) 45 46 #define IQS7222_SYS_SETUP 0xD0 47 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6) 48 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7) 49 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6) 50 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4) 51 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK 52 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2) 53 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0) 54 55 #define IQS7222_EVENT_MASK_ATI BIT(12) 56 #define IQS7222_EVENT_MASK_SLDR BIT(10) 57 #define IQS7222_EVENT_MASK_TOUCH BIT(1) 58 #define IQS7222_EVENT_MASK_PROX BIT(0) 59 60 #define IQS7222_COMMS_HOLD BIT(0) 61 #define IQS7222_COMMS_ERROR 0xEEEE 62 #define IQS7222_COMMS_RETRY_MS 50 63 #define IQS7222_COMMS_TIMEOUT_MS 100 64 #define IQS7222_RESET_TIMEOUT_MS 250 65 #define IQS7222_ATI_TIMEOUT_MS 2000 66 67 #define IQS7222_MAX_COLS_STAT 8 68 #define IQS7222_MAX_COLS_CYCLE 3 69 #define IQS7222_MAX_COLS_GLBL 3 70 #define IQS7222_MAX_COLS_BTN 3 71 #define IQS7222_MAX_COLS_CHAN 6 72 #define IQS7222_MAX_COLS_FILT 2 73 #define IQS7222_MAX_COLS_SLDR 11 74 #define IQS7222_MAX_COLS_GPIO 3 75 #define IQS7222_MAX_COLS_SYS 13 76 77 #define IQS7222_MAX_CHAN 20 78 #define IQS7222_MAX_SLDR 2 79 80 #define IQS7222_NUM_RETRIES 5 81 #define IQS7222_REG_OFFSET 0x100 82 83 enum iqs7222_reg_key_id { 84 IQS7222_REG_KEY_NONE, 85 IQS7222_REG_KEY_PROX, 86 IQS7222_REG_KEY_TOUCH, 87 IQS7222_REG_KEY_DEBOUNCE, 88 IQS7222_REG_KEY_TAP, 89 IQS7222_REG_KEY_AXIAL, 90 IQS7222_REG_KEY_WHEEL, 91 IQS7222_REG_KEY_NO_WHEEL, 92 IQS7222_REG_KEY_RESERVED 93 }; 94 95 enum iqs7222_reg_grp_id { 96 IQS7222_REG_GRP_STAT, 97 IQS7222_REG_GRP_FILT, 98 IQS7222_REG_GRP_CYCLE, 99 IQS7222_REG_GRP_GLBL, 100 IQS7222_REG_GRP_BTN, 101 IQS7222_REG_GRP_CHAN, 102 IQS7222_REG_GRP_SLDR, 103 IQS7222_REG_GRP_GPIO, 104 IQS7222_REG_GRP_SYS, 105 IQS7222_NUM_REG_GRPS 106 }; 107 108 static const char * const iqs7222_reg_grp_names[] = { 109 [IQS7222_REG_GRP_CYCLE] = "cycle", 110 [IQS7222_REG_GRP_CHAN] = "channel", 111 [IQS7222_REG_GRP_SLDR] = "slider", 112 [IQS7222_REG_GRP_GPIO] = "gpio", 113 }; 114 115 static const unsigned int iqs7222_max_cols[] = { 116 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT, 117 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE, 118 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL, 119 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN, 120 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN, 121 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT, 122 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR, 123 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO, 124 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS, 125 }; 126 127 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, }; 128 129 struct iqs7222_event_desc { 130 const char *name; 131 u16 mask; 132 u16 val; 133 u16 enable; 134 enum iqs7222_reg_key_id reg_key; 135 }; 136 137 static const struct iqs7222_event_desc iqs7222_kp_events[] = { 138 { 139 .name = "event-prox", 140 .enable = IQS7222_EVENT_MASK_PROX, 141 .reg_key = IQS7222_REG_KEY_PROX, 142 }, 143 { 144 .name = "event-touch", 145 .enable = IQS7222_EVENT_MASK_TOUCH, 146 .reg_key = IQS7222_REG_KEY_TOUCH, 147 }, 148 }; 149 150 static const struct iqs7222_event_desc iqs7222_sl_events[] = { 151 { .name = "event-press", }, 152 { 153 .name = "event-tap", 154 .mask = BIT(0), 155 .val = BIT(0), 156 .enable = BIT(0), 157 .reg_key = IQS7222_REG_KEY_TAP, 158 }, 159 { 160 .name = "event-swipe-pos", 161 .mask = BIT(5) | BIT(1), 162 .val = BIT(1), 163 .enable = BIT(1), 164 .reg_key = IQS7222_REG_KEY_AXIAL, 165 }, 166 { 167 .name = "event-swipe-neg", 168 .mask = BIT(5) | BIT(1), 169 .val = BIT(5) | BIT(1), 170 .enable = BIT(1), 171 .reg_key = IQS7222_REG_KEY_AXIAL, 172 }, 173 { 174 .name = "event-flick-pos", 175 .mask = BIT(5) | BIT(2), 176 .val = BIT(2), 177 .enable = BIT(2), 178 .reg_key = IQS7222_REG_KEY_AXIAL, 179 }, 180 { 181 .name = "event-flick-neg", 182 .mask = BIT(5) | BIT(2), 183 .val = BIT(5) | BIT(2), 184 .enable = BIT(2), 185 .reg_key = IQS7222_REG_KEY_AXIAL, 186 }, 187 }; 188 189 struct iqs7222_reg_grp_desc { 190 u16 base; 191 int num_row; 192 int num_col; 193 }; 194 195 struct iqs7222_dev_desc { 196 u16 prod_num; 197 u16 fw_major; 198 u16 fw_minor; 199 u16 sldr_res; 200 u16 touch_link; 201 u16 wheel_enable; 202 int allow_offset; 203 int event_offset; 204 int comms_offset; 205 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS]; 206 }; 207 208 static const struct iqs7222_dev_desc iqs7222_devs[] = { 209 { 210 .prod_num = IQS7222_PROD_NUM_A, 211 .fw_major = 1, 212 .fw_minor = 12, 213 .sldr_res = U8_MAX * 16, 214 .touch_link = 1768, 215 .allow_offset = 9, 216 .event_offset = 10, 217 .comms_offset = 12, 218 .reg_grps = { 219 [IQS7222_REG_GRP_STAT] = { 220 .base = IQS7222_SYS_STATUS, 221 .num_row = 1, 222 .num_col = 8, 223 }, 224 [IQS7222_REG_GRP_CYCLE] = { 225 .base = 0x8000, 226 .num_row = 7, 227 .num_col = 3, 228 }, 229 [IQS7222_REG_GRP_GLBL] = { 230 .base = 0x8700, 231 .num_row = 1, 232 .num_col = 3, 233 }, 234 [IQS7222_REG_GRP_BTN] = { 235 .base = 0x9000, 236 .num_row = 12, 237 .num_col = 3, 238 }, 239 [IQS7222_REG_GRP_CHAN] = { 240 .base = 0xA000, 241 .num_row = 12, 242 .num_col = 6, 243 }, 244 [IQS7222_REG_GRP_FILT] = { 245 .base = 0xAC00, 246 .num_row = 1, 247 .num_col = 2, 248 }, 249 [IQS7222_REG_GRP_SLDR] = { 250 .base = 0xB000, 251 .num_row = 2, 252 .num_col = 11, 253 }, 254 [IQS7222_REG_GRP_GPIO] = { 255 .base = 0xC000, 256 .num_row = 1, 257 .num_col = 3, 258 }, 259 [IQS7222_REG_GRP_SYS] = { 260 .base = IQS7222_SYS_SETUP, 261 .num_row = 1, 262 .num_col = 13, 263 }, 264 }, 265 }, 266 { 267 .prod_num = IQS7222_PROD_NUM_B, 268 .fw_major = 1, 269 .fw_minor = 43, 270 .event_offset = 10, 271 .comms_offset = 11, 272 .reg_grps = { 273 [IQS7222_REG_GRP_STAT] = { 274 .base = IQS7222_SYS_STATUS, 275 .num_row = 1, 276 .num_col = 6, 277 }, 278 [IQS7222_REG_GRP_CYCLE] = { 279 .base = 0x8000, 280 .num_row = 10, 281 .num_col = 2, 282 }, 283 [IQS7222_REG_GRP_GLBL] = { 284 .base = 0x8A00, 285 .num_row = 1, 286 .num_col = 3, 287 }, 288 [IQS7222_REG_GRP_BTN] = { 289 .base = 0x9000, 290 .num_row = 20, 291 .num_col = 2, 292 }, 293 [IQS7222_REG_GRP_CHAN] = { 294 .base = 0xB000, 295 .num_row = 20, 296 .num_col = 4, 297 }, 298 [IQS7222_REG_GRP_FILT] = { 299 .base = 0xC400, 300 .num_row = 1, 301 .num_col = 2, 302 }, 303 [IQS7222_REG_GRP_SYS] = { 304 .base = IQS7222_SYS_SETUP, 305 .num_row = 1, 306 .num_col = 13, 307 }, 308 }, 309 }, 310 { 311 .prod_num = IQS7222_PROD_NUM_B, 312 .fw_major = 1, 313 .fw_minor = 27, 314 .reg_grps = { 315 [IQS7222_REG_GRP_STAT] = { 316 .base = IQS7222_SYS_STATUS, 317 .num_row = 1, 318 .num_col = 6, 319 }, 320 [IQS7222_REG_GRP_CYCLE] = { 321 .base = 0x8000, 322 .num_row = 10, 323 .num_col = 2, 324 }, 325 [IQS7222_REG_GRP_GLBL] = { 326 .base = 0x8A00, 327 .num_row = 1, 328 .num_col = 3, 329 }, 330 [IQS7222_REG_GRP_BTN] = { 331 .base = 0x9000, 332 .num_row = 20, 333 .num_col = 2, 334 }, 335 [IQS7222_REG_GRP_CHAN] = { 336 .base = 0xB000, 337 .num_row = 20, 338 .num_col = 4, 339 }, 340 [IQS7222_REG_GRP_FILT] = { 341 .base = 0xC400, 342 .num_row = 1, 343 .num_col = 2, 344 }, 345 [IQS7222_REG_GRP_SYS] = { 346 .base = IQS7222_SYS_SETUP, 347 .num_row = 1, 348 .num_col = 10, 349 }, 350 }, 351 }, 352 { 353 .prod_num = IQS7222_PROD_NUM_C, 354 .fw_major = 2, 355 .fw_minor = 6, 356 .sldr_res = U16_MAX, 357 .touch_link = 1686, 358 .wheel_enable = BIT(3), 359 .event_offset = 9, 360 .comms_offset = 10, 361 .reg_grps = { 362 [IQS7222_REG_GRP_STAT] = { 363 .base = IQS7222_SYS_STATUS, 364 .num_row = 1, 365 .num_col = 6, 366 }, 367 [IQS7222_REG_GRP_CYCLE] = { 368 .base = 0x8000, 369 .num_row = 5, 370 .num_col = 3, 371 }, 372 [IQS7222_REG_GRP_GLBL] = { 373 .base = 0x8500, 374 .num_row = 1, 375 .num_col = 3, 376 }, 377 [IQS7222_REG_GRP_BTN] = { 378 .base = 0x9000, 379 .num_row = 10, 380 .num_col = 3, 381 }, 382 [IQS7222_REG_GRP_CHAN] = { 383 .base = 0xA000, 384 .num_row = 10, 385 .num_col = 6, 386 }, 387 [IQS7222_REG_GRP_FILT] = { 388 .base = 0xAA00, 389 .num_row = 1, 390 .num_col = 2, 391 }, 392 [IQS7222_REG_GRP_SLDR] = { 393 .base = 0xB000, 394 .num_row = 2, 395 .num_col = 10, 396 }, 397 [IQS7222_REG_GRP_GPIO] = { 398 .base = 0xC000, 399 .num_row = 3, 400 .num_col = 3, 401 }, 402 [IQS7222_REG_GRP_SYS] = { 403 .base = IQS7222_SYS_SETUP, 404 .num_row = 1, 405 .num_col = 12, 406 }, 407 }, 408 }, 409 { 410 .prod_num = IQS7222_PROD_NUM_C, 411 .fw_major = 1, 412 .fw_minor = 13, 413 .sldr_res = U16_MAX, 414 .touch_link = 1674, 415 .wheel_enable = BIT(3), 416 .event_offset = 9, 417 .comms_offset = 10, 418 .reg_grps = { 419 [IQS7222_REG_GRP_STAT] = { 420 .base = IQS7222_SYS_STATUS, 421 .num_row = 1, 422 .num_col = 6, 423 }, 424 [IQS7222_REG_GRP_CYCLE] = { 425 .base = 0x8000, 426 .num_row = 5, 427 .num_col = 3, 428 }, 429 [IQS7222_REG_GRP_GLBL] = { 430 .base = 0x8500, 431 .num_row = 1, 432 .num_col = 3, 433 }, 434 [IQS7222_REG_GRP_BTN] = { 435 .base = 0x9000, 436 .num_row = 10, 437 .num_col = 3, 438 }, 439 [IQS7222_REG_GRP_CHAN] = { 440 .base = 0xA000, 441 .num_row = 10, 442 .num_col = 6, 443 }, 444 [IQS7222_REG_GRP_FILT] = { 445 .base = 0xAA00, 446 .num_row = 1, 447 .num_col = 2, 448 }, 449 [IQS7222_REG_GRP_SLDR] = { 450 .base = 0xB000, 451 .num_row = 2, 452 .num_col = 10, 453 }, 454 [IQS7222_REG_GRP_GPIO] = { 455 .base = 0xC000, 456 .num_row = 1, 457 .num_col = 3, 458 }, 459 [IQS7222_REG_GRP_SYS] = { 460 .base = IQS7222_SYS_SETUP, 461 .num_row = 1, 462 .num_col = 11, 463 }, 464 }, 465 }, 466 }; 467 468 struct iqs7222_prop_desc { 469 const char *name; 470 enum iqs7222_reg_grp_id reg_grp; 471 enum iqs7222_reg_key_id reg_key; 472 int reg_offset; 473 int reg_shift; 474 int reg_width; 475 int val_pitch; 476 int val_min; 477 int val_max; 478 bool invert; 479 const char *label; 480 }; 481 482 static const struct iqs7222_prop_desc iqs7222_props[] = { 483 { 484 .name = "azoteq,conv-period", 485 .reg_grp = IQS7222_REG_GRP_CYCLE, 486 .reg_offset = 0, 487 .reg_shift = 8, 488 .reg_width = 8, 489 .label = "conversion period", 490 }, 491 { 492 .name = "azoteq,conv-frac", 493 .reg_grp = IQS7222_REG_GRP_CYCLE, 494 .reg_offset = 0, 495 .reg_shift = 0, 496 .reg_width = 8, 497 .label = "conversion frequency fractional divider", 498 }, 499 { 500 .name = "azoteq,rx-float-inactive", 501 .reg_grp = IQS7222_REG_GRP_CYCLE, 502 .reg_offset = 1, 503 .reg_shift = 6, 504 .reg_width = 1, 505 .invert = true, 506 }, 507 { 508 .name = "azoteq,dead-time-enable", 509 .reg_grp = IQS7222_REG_GRP_CYCLE, 510 .reg_offset = 1, 511 .reg_shift = 5, 512 .reg_width = 1, 513 }, 514 { 515 .name = "azoteq,tx-freq-fosc", 516 .reg_grp = IQS7222_REG_GRP_CYCLE, 517 .reg_offset = 1, 518 .reg_shift = 4, 519 .reg_width = 1, 520 }, 521 { 522 .name = "azoteq,vbias-enable", 523 .reg_grp = IQS7222_REG_GRP_CYCLE, 524 .reg_offset = 1, 525 .reg_shift = 3, 526 .reg_width = 1, 527 }, 528 { 529 .name = "azoteq,sense-mode", 530 .reg_grp = IQS7222_REG_GRP_CYCLE, 531 .reg_offset = 1, 532 .reg_shift = 0, 533 .reg_width = 3, 534 .val_max = 3, 535 .label = "sensing mode", 536 }, 537 { 538 .name = "azoteq,iref-enable", 539 .reg_grp = IQS7222_REG_GRP_CYCLE, 540 .reg_offset = 2, 541 .reg_shift = 10, 542 .reg_width = 1, 543 }, 544 { 545 .name = "azoteq,iref-level", 546 .reg_grp = IQS7222_REG_GRP_CYCLE, 547 .reg_offset = 2, 548 .reg_shift = 4, 549 .reg_width = 4, 550 .label = "current reference level", 551 }, 552 { 553 .name = "azoteq,iref-trim", 554 .reg_grp = IQS7222_REG_GRP_CYCLE, 555 .reg_offset = 2, 556 .reg_shift = 0, 557 .reg_width = 4, 558 .label = "current reference trim", 559 }, 560 { 561 .name = "azoteq,rf-filt-enable", 562 .reg_grp = IQS7222_REG_GRP_GLBL, 563 .reg_offset = 0, 564 .reg_shift = 15, 565 .reg_width = 1, 566 }, 567 { 568 .name = "azoteq,max-counts", 569 .reg_grp = IQS7222_REG_GRP_GLBL, 570 .reg_offset = 0, 571 .reg_shift = 13, 572 .reg_width = 2, 573 .label = "maximum counts", 574 }, 575 { 576 .name = "azoteq,auto-mode", 577 .reg_grp = IQS7222_REG_GRP_GLBL, 578 .reg_offset = 0, 579 .reg_shift = 2, 580 .reg_width = 2, 581 .label = "number of conversions", 582 }, 583 { 584 .name = "azoteq,ati-frac-div-fine", 585 .reg_grp = IQS7222_REG_GRP_GLBL, 586 .reg_offset = 1, 587 .reg_shift = 9, 588 .reg_width = 5, 589 .label = "ATI fine fractional divider", 590 }, 591 { 592 .name = "azoteq,ati-frac-div-coarse", 593 .reg_grp = IQS7222_REG_GRP_GLBL, 594 .reg_offset = 1, 595 .reg_shift = 0, 596 .reg_width = 5, 597 .label = "ATI coarse fractional divider", 598 }, 599 { 600 .name = "azoteq,ati-comp-select", 601 .reg_grp = IQS7222_REG_GRP_GLBL, 602 .reg_offset = 2, 603 .reg_shift = 0, 604 .reg_width = 10, 605 .label = "ATI compensation selection", 606 }, 607 { 608 .name = "azoteq,ati-band", 609 .reg_grp = IQS7222_REG_GRP_CHAN, 610 .reg_offset = 0, 611 .reg_shift = 12, 612 .reg_width = 2, 613 .label = "ATI band", 614 }, 615 { 616 .name = "azoteq,global-halt", 617 .reg_grp = IQS7222_REG_GRP_CHAN, 618 .reg_offset = 0, 619 .reg_shift = 11, 620 .reg_width = 1, 621 }, 622 { 623 .name = "azoteq,invert-enable", 624 .reg_grp = IQS7222_REG_GRP_CHAN, 625 .reg_offset = 0, 626 .reg_shift = 10, 627 .reg_width = 1, 628 }, 629 { 630 .name = "azoteq,dual-direction", 631 .reg_grp = IQS7222_REG_GRP_CHAN, 632 .reg_offset = 0, 633 .reg_shift = 9, 634 .reg_width = 1, 635 }, 636 { 637 .name = "azoteq,samp-cap-double", 638 .reg_grp = IQS7222_REG_GRP_CHAN, 639 .reg_offset = 0, 640 .reg_shift = 3, 641 .reg_width = 1, 642 }, 643 { 644 .name = "azoteq,vref-half", 645 .reg_grp = IQS7222_REG_GRP_CHAN, 646 .reg_offset = 0, 647 .reg_shift = 2, 648 .reg_width = 1, 649 }, 650 { 651 .name = "azoteq,proj-bias", 652 .reg_grp = IQS7222_REG_GRP_CHAN, 653 .reg_offset = 0, 654 .reg_shift = 0, 655 .reg_width = 2, 656 .label = "projected bias current", 657 }, 658 { 659 .name = "azoteq,ati-target", 660 .reg_grp = IQS7222_REG_GRP_CHAN, 661 .reg_offset = 1, 662 .reg_shift = 8, 663 .reg_width = 8, 664 .val_pitch = 8, 665 .label = "ATI target", 666 }, 667 { 668 .name = "azoteq,ati-base", 669 .reg_grp = IQS7222_REG_GRP_CHAN, 670 .reg_offset = 1, 671 .reg_shift = 3, 672 .reg_width = 5, 673 .val_pitch = 16, 674 .label = "ATI base", 675 }, 676 { 677 .name = "azoteq,ati-mode", 678 .reg_grp = IQS7222_REG_GRP_CHAN, 679 .reg_offset = 1, 680 .reg_shift = 0, 681 .reg_width = 3, 682 .val_max = 5, 683 .label = "ATI mode", 684 }, 685 { 686 .name = "azoteq,ati-frac-div-fine", 687 .reg_grp = IQS7222_REG_GRP_CHAN, 688 .reg_offset = 2, 689 .reg_shift = 9, 690 .reg_width = 5, 691 .label = "ATI fine fractional divider", 692 }, 693 { 694 .name = "azoteq,ati-frac-mult-coarse", 695 .reg_grp = IQS7222_REG_GRP_CHAN, 696 .reg_offset = 2, 697 .reg_shift = 5, 698 .reg_width = 4, 699 .label = "ATI coarse fractional multiplier", 700 }, 701 { 702 .name = "azoteq,ati-frac-div-coarse", 703 .reg_grp = IQS7222_REG_GRP_CHAN, 704 .reg_offset = 2, 705 .reg_shift = 0, 706 .reg_width = 5, 707 .label = "ATI coarse fractional divider", 708 }, 709 { 710 .name = "azoteq,ati-comp-div", 711 .reg_grp = IQS7222_REG_GRP_CHAN, 712 .reg_offset = 3, 713 .reg_shift = 11, 714 .reg_width = 5, 715 .label = "ATI compensation divider", 716 }, 717 { 718 .name = "azoteq,ati-comp-select", 719 .reg_grp = IQS7222_REG_GRP_CHAN, 720 .reg_offset = 3, 721 .reg_shift = 0, 722 .reg_width = 10, 723 .label = "ATI compensation selection", 724 }, 725 { 726 .name = "azoteq,debounce-exit", 727 .reg_grp = IQS7222_REG_GRP_BTN, 728 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 729 .reg_offset = 0, 730 .reg_shift = 12, 731 .reg_width = 4, 732 .label = "debounce exit factor", 733 }, 734 { 735 .name = "azoteq,debounce-enter", 736 .reg_grp = IQS7222_REG_GRP_BTN, 737 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 738 .reg_offset = 0, 739 .reg_shift = 8, 740 .reg_width = 4, 741 .label = "debounce entrance factor", 742 }, 743 { 744 .name = "azoteq,thresh", 745 .reg_grp = IQS7222_REG_GRP_BTN, 746 .reg_key = IQS7222_REG_KEY_PROX, 747 .reg_offset = 0, 748 .reg_shift = 0, 749 .reg_width = 8, 750 .val_max = 127, 751 .label = "threshold", 752 }, 753 { 754 .name = "azoteq,thresh", 755 .reg_grp = IQS7222_REG_GRP_BTN, 756 .reg_key = IQS7222_REG_KEY_TOUCH, 757 .reg_offset = 1, 758 .reg_shift = 0, 759 .reg_width = 8, 760 .label = "threshold", 761 }, 762 { 763 .name = "azoteq,hyst", 764 .reg_grp = IQS7222_REG_GRP_BTN, 765 .reg_key = IQS7222_REG_KEY_TOUCH, 766 .reg_offset = 1, 767 .reg_shift = 8, 768 .reg_width = 8, 769 .label = "hysteresis", 770 }, 771 { 772 .name = "azoteq,lta-beta-lp", 773 .reg_grp = IQS7222_REG_GRP_FILT, 774 .reg_offset = 0, 775 .reg_shift = 12, 776 .reg_width = 4, 777 .label = "low-power mode long-term average beta", 778 }, 779 { 780 .name = "azoteq,lta-beta-np", 781 .reg_grp = IQS7222_REG_GRP_FILT, 782 .reg_offset = 0, 783 .reg_shift = 8, 784 .reg_width = 4, 785 .label = "normal-power mode long-term average beta", 786 }, 787 { 788 .name = "azoteq,counts-beta-lp", 789 .reg_grp = IQS7222_REG_GRP_FILT, 790 .reg_offset = 0, 791 .reg_shift = 4, 792 .reg_width = 4, 793 .label = "low-power mode counts beta", 794 }, 795 { 796 .name = "azoteq,counts-beta-np", 797 .reg_grp = IQS7222_REG_GRP_FILT, 798 .reg_offset = 0, 799 .reg_shift = 0, 800 .reg_width = 4, 801 .label = "normal-power mode counts beta", 802 }, 803 { 804 .name = "azoteq,lta-fast-beta-lp", 805 .reg_grp = IQS7222_REG_GRP_FILT, 806 .reg_offset = 1, 807 .reg_shift = 4, 808 .reg_width = 4, 809 .label = "low-power mode long-term average fast beta", 810 }, 811 { 812 .name = "azoteq,lta-fast-beta-np", 813 .reg_grp = IQS7222_REG_GRP_FILT, 814 .reg_offset = 1, 815 .reg_shift = 0, 816 .reg_width = 4, 817 .label = "normal-power mode long-term average fast beta", 818 }, 819 { 820 .name = "azoteq,lower-cal", 821 .reg_grp = IQS7222_REG_GRP_SLDR, 822 .reg_offset = 0, 823 .reg_shift = 8, 824 .reg_width = 8, 825 .label = "lower calibration", 826 }, 827 { 828 .name = "azoteq,static-beta", 829 .reg_grp = IQS7222_REG_GRP_SLDR, 830 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 831 .reg_offset = 0, 832 .reg_shift = 6, 833 .reg_width = 1, 834 }, 835 { 836 .name = "azoteq,bottom-beta", 837 .reg_grp = IQS7222_REG_GRP_SLDR, 838 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 839 .reg_offset = 0, 840 .reg_shift = 3, 841 .reg_width = 3, 842 .label = "bottom beta", 843 }, 844 { 845 .name = "azoteq,static-beta", 846 .reg_grp = IQS7222_REG_GRP_SLDR, 847 .reg_key = IQS7222_REG_KEY_WHEEL, 848 .reg_offset = 0, 849 .reg_shift = 7, 850 .reg_width = 1, 851 }, 852 { 853 .name = "azoteq,bottom-beta", 854 .reg_grp = IQS7222_REG_GRP_SLDR, 855 .reg_key = IQS7222_REG_KEY_WHEEL, 856 .reg_offset = 0, 857 .reg_shift = 4, 858 .reg_width = 3, 859 .label = "bottom beta", 860 }, 861 { 862 .name = "azoteq,bottom-speed", 863 .reg_grp = IQS7222_REG_GRP_SLDR, 864 .reg_offset = 1, 865 .reg_shift = 8, 866 .reg_width = 8, 867 .label = "bottom speed", 868 }, 869 { 870 .name = "azoteq,upper-cal", 871 .reg_grp = IQS7222_REG_GRP_SLDR, 872 .reg_offset = 1, 873 .reg_shift = 0, 874 .reg_width = 8, 875 .label = "upper calibration", 876 }, 877 { 878 .name = "azoteq,gesture-max-ms", 879 .reg_grp = IQS7222_REG_GRP_SLDR, 880 .reg_key = IQS7222_REG_KEY_TAP, 881 .reg_offset = 9, 882 .reg_shift = 8, 883 .reg_width = 8, 884 .val_pitch = 4, 885 .label = "maximum gesture time", 886 }, 887 { 888 .name = "azoteq,gesture-min-ms", 889 .reg_grp = IQS7222_REG_GRP_SLDR, 890 .reg_key = IQS7222_REG_KEY_TAP, 891 .reg_offset = 9, 892 .reg_shift = 3, 893 .reg_width = 5, 894 .val_pitch = 4, 895 .label = "minimum gesture time", 896 }, 897 { 898 .name = "azoteq,gesture-dist", 899 .reg_grp = IQS7222_REG_GRP_SLDR, 900 .reg_key = IQS7222_REG_KEY_AXIAL, 901 .reg_offset = 10, 902 .reg_shift = 8, 903 .reg_width = 8, 904 .val_pitch = 16, 905 .label = "gesture distance", 906 }, 907 { 908 .name = "azoteq,gesture-max-ms", 909 .reg_grp = IQS7222_REG_GRP_SLDR, 910 .reg_key = IQS7222_REG_KEY_AXIAL, 911 .reg_offset = 10, 912 .reg_shift = 0, 913 .reg_width = 8, 914 .val_pitch = 4, 915 .label = "maximum gesture time", 916 }, 917 { 918 .name = "drive-open-drain", 919 .reg_grp = IQS7222_REG_GRP_GPIO, 920 .reg_offset = 0, 921 .reg_shift = 1, 922 .reg_width = 1, 923 }, 924 { 925 .name = "azoteq,timeout-ati-ms", 926 .reg_grp = IQS7222_REG_GRP_SYS, 927 .reg_offset = 1, 928 .reg_shift = 0, 929 .reg_width = 16, 930 .val_pitch = 500, 931 .label = "ATI error timeout", 932 }, 933 { 934 .name = "azoteq,rate-ati-ms", 935 .reg_grp = IQS7222_REG_GRP_SYS, 936 .reg_offset = 2, 937 .reg_shift = 0, 938 .reg_width = 16, 939 .label = "ATI report rate", 940 }, 941 { 942 .name = "azoteq,timeout-np-ms", 943 .reg_grp = IQS7222_REG_GRP_SYS, 944 .reg_offset = 3, 945 .reg_shift = 0, 946 .reg_width = 16, 947 .label = "normal-power mode timeout", 948 }, 949 { 950 .name = "azoteq,rate-np-ms", 951 .reg_grp = IQS7222_REG_GRP_SYS, 952 .reg_offset = 4, 953 .reg_shift = 0, 954 .reg_width = 16, 955 .val_max = 3000, 956 .label = "normal-power mode report rate", 957 }, 958 { 959 .name = "azoteq,timeout-lp-ms", 960 .reg_grp = IQS7222_REG_GRP_SYS, 961 .reg_offset = 5, 962 .reg_shift = 0, 963 .reg_width = 16, 964 .label = "low-power mode timeout", 965 }, 966 { 967 .name = "azoteq,rate-lp-ms", 968 .reg_grp = IQS7222_REG_GRP_SYS, 969 .reg_offset = 6, 970 .reg_shift = 0, 971 .reg_width = 16, 972 .val_max = 3000, 973 .label = "low-power mode report rate", 974 }, 975 { 976 .name = "azoteq,timeout-ulp-ms", 977 .reg_grp = IQS7222_REG_GRP_SYS, 978 .reg_offset = 7, 979 .reg_shift = 0, 980 .reg_width = 16, 981 .label = "ultra-low-power mode timeout", 982 }, 983 { 984 .name = "azoteq,rate-ulp-ms", 985 .reg_grp = IQS7222_REG_GRP_SYS, 986 .reg_offset = 8, 987 .reg_shift = 0, 988 .reg_width = 16, 989 .val_max = 3000, 990 .label = "ultra-low-power mode report rate", 991 }, 992 }; 993 994 struct iqs7222_private { 995 const struct iqs7222_dev_desc *dev_desc; 996 struct gpio_desc *reset_gpio; 997 struct gpio_desc *irq_gpio; 998 struct i2c_client *client; 999 struct input_dev *keypad; 1000 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 1001 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 1002 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)]; 1003 unsigned int sl_axis[IQS7222_MAX_SLDR]; 1004 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE]; 1005 u16 glbl_setup[IQS7222_MAX_COLS_GLBL]; 1006 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN]; 1007 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN]; 1008 u16 filt_setup[IQS7222_MAX_COLS_FILT]; 1009 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR]; 1010 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO]; 1011 u16 sys_setup[IQS7222_MAX_COLS_SYS]; 1012 }; 1013 1014 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222, 1015 enum iqs7222_reg_grp_id reg_grp, int row) 1016 { 1017 switch (reg_grp) { 1018 case IQS7222_REG_GRP_CYCLE: 1019 return iqs7222->cycle_setup[row]; 1020 1021 case IQS7222_REG_GRP_GLBL: 1022 return iqs7222->glbl_setup; 1023 1024 case IQS7222_REG_GRP_BTN: 1025 return iqs7222->btn_setup[row]; 1026 1027 case IQS7222_REG_GRP_CHAN: 1028 return iqs7222->chan_setup[row]; 1029 1030 case IQS7222_REG_GRP_FILT: 1031 return iqs7222->filt_setup; 1032 1033 case IQS7222_REG_GRP_SLDR: 1034 return iqs7222->sldr_setup[row]; 1035 1036 case IQS7222_REG_GRP_GPIO: 1037 return iqs7222->gpio_setup[row]; 1038 1039 case IQS7222_REG_GRP_SYS: 1040 return iqs7222->sys_setup; 1041 1042 default: 1043 return NULL; 1044 } 1045 } 1046 1047 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms) 1048 { 1049 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms); 1050 int ret; 1051 1052 do { 1053 usleep_range(1000, 1100); 1054 1055 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1056 if (ret < 0) 1057 return ret; 1058 else if (ret > 0) 1059 return 0; 1060 } while (ktime_compare(ktime_get(), irq_timeout) < 0); 1061 1062 return -EBUSY; 1063 } 1064 1065 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222) 1066 { 1067 struct i2c_client *client = iqs7222->client; 1068 int error; 1069 1070 if (!iqs7222->reset_gpio) 1071 return 0; 1072 1073 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1); 1074 usleep_range(1000, 1100); 1075 1076 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); 1077 1078 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS); 1079 if (error) 1080 dev_err(&client->dev, "Failed to reset device: %d\n", error); 1081 1082 return error; 1083 } 1084 1085 static int iqs7222_force_comms(struct iqs7222_private *iqs7222) 1086 { 1087 u8 msg_buf[] = { 0xFF, 0x00, }; 1088 int ret; 1089 1090 /* 1091 * The device cannot communicate until it asserts its interrupt (RDY) 1092 * pin. Attempts to do so while RDY is deasserted return an ACK; how- 1093 * ever all write data is ignored, and all read data returns 0xEE. 1094 * 1095 * Unsolicited communication must be preceded by a special force com- 1096 * munication command, after which the device eventually asserts its 1097 * RDY pin and agrees to communicate. 1098 * 1099 * Regardless of whether communication is forced or the result of an 1100 * interrupt, the device automatically deasserts its RDY pin once it 1101 * detects an I2C stop condition, or a timeout expires. 1102 */ 1103 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1104 if (ret < 0) 1105 return ret; 1106 else if (ret > 0) 1107 return 0; 1108 1109 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf)); 1110 if (ret < (int)sizeof(msg_buf)) { 1111 if (ret >= 0) 1112 ret = -EIO; 1113 1114 /* 1115 * The datasheet states that the host must wait to retry any 1116 * failed attempt to communicate over I2C. 1117 */ 1118 msleep(IQS7222_COMMS_RETRY_MS); 1119 return ret; 1120 } 1121 1122 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS); 1123 } 1124 1125 static int iqs7222_read_burst(struct iqs7222_private *iqs7222, 1126 u16 reg, void *val, u16 num_val) 1127 { 1128 u8 reg_buf[sizeof(__be16)]; 1129 int ret, i; 1130 struct i2c_client *client = iqs7222->client; 1131 struct i2c_msg msg[] = { 1132 { 1133 .addr = client->addr, 1134 .flags = 0, 1135 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8), 1136 .buf = reg_buf, 1137 }, 1138 { 1139 .addr = client->addr, 1140 .flags = I2C_M_RD, 1141 .len = num_val * sizeof(__le16), 1142 .buf = (u8 *)val, 1143 }, 1144 }; 1145 1146 if (reg > U8_MAX) 1147 put_unaligned_be16(reg, reg_buf); 1148 else 1149 *reg_buf = (u8)reg; 1150 1151 /* 1152 * The following loop protects against an edge case in which the RDY 1153 * pin is automatically deasserted just as the read is initiated. In 1154 * that case, the read must be retried using forced communication. 1155 */ 1156 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1157 ret = iqs7222_force_comms(iqs7222); 1158 if (ret < 0) 1159 continue; 1160 1161 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); 1162 if (ret < (int)ARRAY_SIZE(msg)) { 1163 if (ret >= 0) 1164 ret = -EIO; 1165 1166 msleep(IQS7222_COMMS_RETRY_MS); 1167 continue; 1168 } 1169 1170 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) { 1171 ret = -ENODATA; 1172 continue; 1173 } 1174 1175 ret = 0; 1176 break; 1177 } 1178 1179 /* 1180 * The following delay ensures the device has deasserted the RDY pin 1181 * following the I2C stop condition. 1182 */ 1183 usleep_range(50, 100); 1184 1185 if (ret < 0) 1186 dev_err(&client->dev, 1187 "Failed to read from address 0x%04X: %d\n", reg, ret); 1188 1189 return ret; 1190 } 1191 1192 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val) 1193 { 1194 __le16 val_buf; 1195 int error; 1196 1197 error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1); 1198 if (error) 1199 return error; 1200 1201 *val = le16_to_cpu(val_buf); 1202 1203 return 0; 1204 } 1205 1206 static int iqs7222_write_burst(struct iqs7222_private *iqs7222, 1207 u16 reg, const void *val, u16 num_val) 1208 { 1209 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8); 1210 int val_len = num_val * sizeof(__le16); 1211 int msg_len = reg_len + val_len; 1212 int ret, i; 1213 struct i2c_client *client = iqs7222->client; 1214 u8 *msg_buf; 1215 1216 msg_buf = kzalloc(msg_len, GFP_KERNEL); 1217 if (!msg_buf) 1218 return -ENOMEM; 1219 1220 if (reg > U8_MAX) 1221 put_unaligned_be16(reg, msg_buf); 1222 else 1223 *msg_buf = (u8)reg; 1224 1225 memcpy(msg_buf + reg_len, val, val_len); 1226 1227 /* 1228 * The following loop protects against an edge case in which the RDY 1229 * pin is automatically asserted just before the force communication 1230 * command is sent. 1231 * 1232 * In that case, the subsequent I2C stop condition tricks the device 1233 * into preemptively deasserting the RDY pin and the command must be 1234 * sent again. 1235 */ 1236 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1237 ret = iqs7222_force_comms(iqs7222); 1238 if (ret < 0) 1239 continue; 1240 1241 ret = i2c_master_send(client, msg_buf, msg_len); 1242 if (ret < msg_len) { 1243 if (ret >= 0) 1244 ret = -EIO; 1245 1246 msleep(IQS7222_COMMS_RETRY_MS); 1247 continue; 1248 } 1249 1250 ret = 0; 1251 break; 1252 } 1253 1254 kfree(msg_buf); 1255 1256 usleep_range(50, 100); 1257 1258 if (ret < 0) 1259 dev_err(&client->dev, 1260 "Failed to write to address 0x%04X: %d\n", reg, ret); 1261 1262 return ret; 1263 } 1264 1265 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val) 1266 { 1267 __le16 val_buf = cpu_to_le16(val); 1268 1269 return iqs7222_write_burst(iqs7222, reg, &val_buf, 1); 1270 } 1271 1272 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222) 1273 { 1274 struct i2c_client *client = iqs7222->client; 1275 ktime_t ati_timeout; 1276 u16 sys_status = 0; 1277 u16 sys_setup; 1278 int error, i; 1279 1280 /* 1281 * The reserved fields of the system setup register may have changed 1282 * as a result of other registers having been written. As such, read 1283 * the register's latest value to avoid unexpected behavior when the 1284 * register is written in the loop that follows. 1285 */ 1286 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup); 1287 if (error) 1288 return error; 1289 1290 sys_setup &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; 1291 sys_setup &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; 1292 1293 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1294 /* 1295 * Trigger ATI from streaming and normal-power modes so that 1296 * the RDY pin continues to be asserted during ATI. 1297 */ 1298 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1299 sys_setup | 1300 IQS7222_SYS_SETUP_REDO_ATI); 1301 if (error) 1302 return error; 1303 1304 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS); 1305 1306 do { 1307 error = iqs7222_irq_poll(iqs7222, 1308 IQS7222_COMMS_TIMEOUT_MS); 1309 if (error) 1310 continue; 1311 1312 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS, 1313 &sys_status); 1314 if (error) 1315 return error; 1316 1317 if (sys_status & IQS7222_SYS_STATUS_RESET) 1318 return 0; 1319 1320 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR) 1321 break; 1322 1323 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE) 1324 continue; 1325 1326 /* 1327 * Use stream-in-touch mode if either slider reports 1328 * absolute position. 1329 */ 1330 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit) 1331 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH 1332 : IQS7222_SYS_SETUP_INTF_MODE_EVENT; 1333 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO; 1334 1335 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1336 sys_setup); 1337 } while (ktime_compare(ktime_get(), ati_timeout) < 0); 1338 1339 dev_err(&client->dev, 1340 "ATI attempt %d of %d failed with status 0x%02X, %s\n", 1341 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status, 1342 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping"); 1343 } 1344 1345 return -ETIMEDOUT; 1346 } 1347 1348 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir) 1349 { 1350 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1351 int comms_offset = dev_desc->comms_offset; 1352 int error, i, j, k; 1353 1354 /* 1355 * Acknowledge reset before writing any registers in case the device 1356 * suffers a spurious reset during initialization. Because this step 1357 * may change the reserved fields of the second filter beta register, 1358 * its cache must be updated. 1359 * 1360 * Writing the second filter beta register, in turn, may clobber the 1361 * system status register. As such, the filter beta register pair is 1362 * written first to protect against this hazard. 1363 */ 1364 if (dir == WRITE) { 1365 u16 reg = dev_desc->reg_grps[IQS7222_REG_GRP_FILT].base + 1; 1366 u16 filt_setup; 1367 1368 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1369 iqs7222->sys_setup[0] | 1370 IQS7222_SYS_SETUP_ACK_RESET); 1371 if (error) 1372 return error; 1373 1374 error = iqs7222_read_word(iqs7222, reg, &filt_setup); 1375 if (error) 1376 return error; 1377 1378 iqs7222->filt_setup[1] &= GENMASK(7, 0); 1379 iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0)); 1380 } 1381 1382 /* 1383 * Take advantage of the stop-bit disable function, if available, to 1384 * save the trouble of having to reopen a communication window after 1385 * each burst read or write. 1386 */ 1387 if (comms_offset) { 1388 u16 comms_setup; 1389 1390 error = iqs7222_read_word(iqs7222, 1391 IQS7222_SYS_SETUP + comms_offset, 1392 &comms_setup); 1393 if (error) 1394 return error; 1395 1396 error = iqs7222_write_word(iqs7222, 1397 IQS7222_SYS_SETUP + comms_offset, 1398 comms_setup | IQS7222_COMMS_HOLD); 1399 if (error) 1400 return error; 1401 } 1402 1403 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { 1404 int num_row = dev_desc->reg_grps[i].num_row; 1405 int num_col = dev_desc->reg_grps[i].num_col; 1406 u16 reg = dev_desc->reg_grps[i].base; 1407 __le16 *val_buf; 1408 u16 *val; 1409 1410 if (!num_col) 1411 continue; 1412 1413 val = iqs7222_setup(iqs7222, i, 0); 1414 if (!val) 1415 continue; 1416 1417 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL); 1418 if (!val_buf) 1419 return -ENOMEM; 1420 1421 for (j = 0; j < num_row; j++) { 1422 switch (dir) { 1423 case READ: 1424 error = iqs7222_read_burst(iqs7222, reg, 1425 val_buf, num_col); 1426 for (k = 0; k < num_col; k++) 1427 val[k] = le16_to_cpu(val_buf[k]); 1428 break; 1429 1430 case WRITE: 1431 for (k = 0; k < num_col; k++) 1432 val_buf[k] = cpu_to_le16(val[k]); 1433 error = iqs7222_write_burst(iqs7222, reg, 1434 val_buf, num_col); 1435 break; 1436 1437 default: 1438 error = -EINVAL; 1439 } 1440 1441 if (error) 1442 break; 1443 1444 reg += IQS7222_REG_OFFSET; 1445 val += iqs7222_max_cols[i]; 1446 } 1447 1448 kfree(val_buf); 1449 1450 if (error) 1451 return error; 1452 } 1453 1454 if (comms_offset) { 1455 u16 comms_setup; 1456 1457 error = iqs7222_read_word(iqs7222, 1458 IQS7222_SYS_SETUP + comms_offset, 1459 &comms_setup); 1460 if (error) 1461 return error; 1462 1463 error = iqs7222_write_word(iqs7222, 1464 IQS7222_SYS_SETUP + comms_offset, 1465 comms_setup & ~IQS7222_COMMS_HOLD); 1466 if (error) 1467 return error; 1468 } 1469 1470 if (dir == READ) 1471 return 0; 1472 1473 return iqs7222_ati_trigger(iqs7222); 1474 } 1475 1476 static int iqs7222_dev_info(struct iqs7222_private *iqs7222) 1477 { 1478 struct i2c_client *client = iqs7222->client; 1479 bool prod_num_valid = false; 1480 __le16 dev_id[3]; 1481 int error, i; 1482 1483 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id, 1484 ARRAY_SIZE(dev_id)); 1485 if (error) 1486 return error; 1487 1488 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { 1489 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) 1490 continue; 1491 1492 prod_num_valid = true; 1493 1494 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major) 1495 continue; 1496 1497 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor) 1498 continue; 1499 1500 iqs7222->dev_desc = &iqs7222_devs[i]; 1501 return 0; 1502 } 1503 1504 if (prod_num_valid) 1505 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n", 1506 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2])); 1507 else 1508 dev_err(&client->dev, "Unrecognized product number: %u\n", 1509 le16_to_cpu(dev_id[0])); 1510 1511 return -EINVAL; 1512 } 1513 1514 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222, 1515 struct fwnode_handle *child_node, 1516 int child_enable, u16 child_link) 1517 { 1518 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1519 struct i2c_client *client = iqs7222->client; 1520 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row; 1521 int error, count, i; 1522 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)]; 1523 1524 if (!num_gpio) 1525 return 0; 1526 1527 if (!fwnode_property_present(child_node, "azoteq,gpio-select")) 1528 return 0; 1529 1530 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select"); 1531 if (count > num_gpio) { 1532 dev_err(&client->dev, "Invalid number of %s GPIOs\n", 1533 fwnode_get_name(child_node)); 1534 return -EINVAL; 1535 } else if (count < 0) { 1536 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n", 1537 fwnode_get_name(child_node), count); 1538 return count; 1539 } 1540 1541 error = fwnode_property_read_u32_array(child_node, 1542 "azoteq,gpio-select", 1543 gpio_sel, count); 1544 if (error) { 1545 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n", 1546 fwnode_get_name(child_node), error); 1547 return error; 1548 } 1549 1550 for (i = 0; i < count; i++) { 1551 u16 *gpio_setup; 1552 1553 if (gpio_sel[i] >= num_gpio) { 1554 dev_err(&client->dev, "Invalid %s GPIO: %u\n", 1555 fwnode_get_name(child_node), gpio_sel[i]); 1556 return -EINVAL; 1557 } 1558 1559 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]]; 1560 1561 if (gpio_setup[2] && child_link != gpio_setup[2]) { 1562 dev_err(&client->dev, 1563 "Conflicting GPIO %u event types\n", 1564 gpio_sel[i]); 1565 return -EINVAL; 1566 } 1567 1568 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; 1569 gpio_setup[1] |= child_enable; 1570 gpio_setup[2] = child_link; 1571 } 1572 1573 return 0; 1574 } 1575 1576 static int iqs7222_parse_props(struct iqs7222_private *iqs7222, 1577 struct fwnode_handle **child_node, 1578 int child_index, 1579 enum iqs7222_reg_grp_id reg_grp, 1580 enum iqs7222_reg_key_id reg_key) 1581 { 1582 u16 *setup = iqs7222_setup(iqs7222, reg_grp, child_index); 1583 struct i2c_client *client = iqs7222->client; 1584 struct fwnode_handle *reg_grp_node; 1585 char reg_grp_name[16]; 1586 int i; 1587 1588 switch (reg_grp) { 1589 case IQS7222_REG_GRP_CYCLE: 1590 case IQS7222_REG_GRP_CHAN: 1591 case IQS7222_REG_GRP_SLDR: 1592 case IQS7222_REG_GRP_GPIO: 1593 case IQS7222_REG_GRP_BTN: 1594 /* 1595 * These groups derive a child node and return it to the caller 1596 * for additional group-specific processing. In some cases, the 1597 * child node may have already been derived. 1598 */ 1599 reg_grp_node = *child_node; 1600 if (reg_grp_node) 1601 break; 1602 1603 snprintf(reg_grp_name, sizeof(reg_grp_name), "%s-%d", 1604 iqs7222_reg_grp_names[reg_grp], child_index); 1605 1606 reg_grp_node = device_get_named_child_node(&client->dev, 1607 reg_grp_name); 1608 if (!reg_grp_node) 1609 return 0; 1610 1611 *child_node = reg_grp_node; 1612 break; 1613 1614 case IQS7222_REG_GRP_GLBL: 1615 case IQS7222_REG_GRP_FILT: 1616 case IQS7222_REG_GRP_SYS: 1617 /* 1618 * These groups are not organized beneath a child node, nor are 1619 * they subject to any additional processing by the caller. 1620 */ 1621 reg_grp_node = dev_fwnode(&client->dev); 1622 break; 1623 1624 default: 1625 return -EINVAL; 1626 } 1627 1628 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { 1629 const char *name = iqs7222_props[i].name; 1630 int reg_offset = iqs7222_props[i].reg_offset; 1631 int reg_shift = iqs7222_props[i].reg_shift; 1632 int reg_width = iqs7222_props[i].reg_width; 1633 int val_pitch = iqs7222_props[i].val_pitch ? : 1; 1634 int val_min = iqs7222_props[i].val_min; 1635 int val_max = iqs7222_props[i].val_max; 1636 bool invert = iqs7222_props[i].invert; 1637 const char *label = iqs7222_props[i].label ? : name; 1638 unsigned int val; 1639 int error; 1640 1641 if (iqs7222_props[i].reg_grp != reg_grp || 1642 iqs7222_props[i].reg_key != reg_key) 1643 continue; 1644 1645 /* 1646 * Boolean register fields are one bit wide; they are forcibly 1647 * reset to provide a means to undo changes by a bootloader if 1648 * necessary. 1649 * 1650 * Scalar fields, on the other hand, are left untouched unless 1651 * their corresponding properties are present. 1652 */ 1653 if (reg_width == 1) { 1654 if (invert) 1655 setup[reg_offset] |= BIT(reg_shift); 1656 else 1657 setup[reg_offset] &= ~BIT(reg_shift); 1658 } 1659 1660 if (!fwnode_property_present(reg_grp_node, name)) 1661 continue; 1662 1663 if (reg_width == 1) { 1664 if (invert) 1665 setup[reg_offset] &= ~BIT(reg_shift); 1666 else 1667 setup[reg_offset] |= BIT(reg_shift); 1668 1669 continue; 1670 } 1671 1672 error = fwnode_property_read_u32(reg_grp_node, name, &val); 1673 if (error) { 1674 dev_err(&client->dev, "Failed to read %s %s: %d\n", 1675 fwnode_get_name(reg_grp_node), label, error); 1676 return error; 1677 } 1678 1679 if (!val_max) 1680 val_max = GENMASK(reg_width - 1, 0) * val_pitch; 1681 1682 if (val < val_min || val > val_max) { 1683 dev_err(&client->dev, "Invalid %s %s: %u\n", 1684 fwnode_get_name(reg_grp_node), label, val); 1685 return -EINVAL; 1686 } 1687 1688 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, 1689 reg_shift); 1690 setup[reg_offset] |= (val / val_pitch << reg_shift); 1691 } 1692 1693 return 0; 1694 } 1695 1696 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222, int cycle_index) 1697 { 1698 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index]; 1699 struct i2c_client *client = iqs7222->client; 1700 struct fwnode_handle *cycle_node = NULL; 1701 unsigned int pins[9]; 1702 int error, count, i; 1703 1704 /* 1705 * Each channel shares a cycle with one other channel; the mapping of 1706 * channels to cycles is fixed. Properties defined for a cycle impact 1707 * both channels tied to the cycle. 1708 */ 1709 error = iqs7222_parse_props(iqs7222, &cycle_node, cycle_index, 1710 IQS7222_REG_GRP_CYCLE, 1711 IQS7222_REG_KEY_NONE); 1712 if (error) 1713 return error; 1714 1715 if (!cycle_node) 1716 return 0; 1717 1718 /* 1719 * Unlike channels which are restricted to a select range of CRx pins 1720 * based on channel number, any cycle can claim any of the device's 9 1721 * CTx pins (CTx0-8). 1722 */ 1723 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable")) 1724 return 0; 1725 1726 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable"); 1727 if (count < 0) { 1728 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n", 1729 fwnode_get_name(cycle_node), count); 1730 return count; 1731 } else if (count > ARRAY_SIZE(pins)) { 1732 dev_err(&client->dev, "Invalid number of %s CTx pins\n", 1733 fwnode_get_name(cycle_node)); 1734 return -EINVAL; 1735 } 1736 1737 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable", 1738 pins, count); 1739 if (error) { 1740 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n", 1741 fwnode_get_name(cycle_node), error); 1742 return error; 1743 } 1744 1745 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7); 1746 1747 for (i = 0; i < count; i++) { 1748 if (pins[i] > 8) { 1749 dev_err(&client->dev, "Invalid %s CTx pin: %u\n", 1750 fwnode_get_name(cycle_node), pins[i]); 1751 return -EINVAL; 1752 } 1753 1754 cycle_setup[1] |= BIT(pins[i] + 7); 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222, int chan_index) 1761 { 1762 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1763 struct i2c_client *client = iqs7222->client; 1764 struct fwnode_handle *chan_node = NULL; 1765 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 1766 int ext_chan = rounddown(num_chan, 10); 1767 int error, i; 1768 u16 *chan_setup = iqs7222->chan_setup[chan_index]; 1769 u16 *sys_setup = iqs7222->sys_setup; 1770 unsigned int val; 1771 1772 error = iqs7222_parse_props(iqs7222, &chan_node, chan_index, 1773 IQS7222_REG_GRP_CHAN, 1774 IQS7222_REG_KEY_NONE); 1775 if (error) 1776 return error; 1777 1778 if (!chan_node) 1779 return 0; 1780 1781 if (dev_desc->allow_offset) { 1782 sys_setup[dev_desc->allow_offset] |= BIT(chan_index); 1783 if (fwnode_property_present(chan_node, "azoteq,ulp-allow")) 1784 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index); 1785 } 1786 1787 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; 1788 1789 /* 1790 * The reference channel function allows for differential measurements 1791 * and is only available in the case of IQS7222A or IQS7222C. 1792 */ 1793 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 && 1794 fwnode_property_present(chan_node, "azoteq,ref-select")) { 1795 u16 *ref_setup; 1796 1797 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select", 1798 &val); 1799 if (error) { 1800 dev_err(&client->dev, 1801 "Failed to read %s reference channel: %d\n", 1802 fwnode_get_name(chan_node), error); 1803 return error; 1804 } 1805 1806 if (val >= ext_chan) { 1807 dev_err(&client->dev, 1808 "Invalid %s reference channel: %u\n", 1809 fwnode_get_name(chan_node), val); 1810 return -EINVAL; 1811 } 1812 1813 ref_setup = iqs7222->chan_setup[val]; 1814 1815 /* 1816 * Configure the current channel as a follower of the selected 1817 * reference channel. 1818 */ 1819 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; 1820 chan_setup[4] = val * 42 + 1048; 1821 1822 if (!fwnode_property_read_u32(chan_node, "azoteq,ref-weight", 1823 &val)) { 1824 if (val > U16_MAX) { 1825 dev_err(&client->dev, 1826 "Invalid %s reference weight: %u\n", 1827 fwnode_get_name(chan_node), val); 1828 return -EINVAL; 1829 } 1830 1831 chan_setup[5] = val; 1832 } 1833 1834 /* 1835 * Configure the selected channel as a reference channel which 1836 * serves the current channel. 1837 */ 1838 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; 1839 ref_setup[5] |= BIT(chan_index); 1840 1841 ref_setup[4] = dev_desc->touch_link; 1842 if (fwnode_property_present(chan_node, "azoteq,use-prox")) 1843 ref_setup[4] -= 2; 1844 } 1845 1846 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) { 1847 /* 1848 * Each channel can claim up to 4 CRx pins. The first half of 1849 * the channels can use CRx0-3, while the second half can use 1850 * CRx4-7. 1851 */ 1852 unsigned int pins[4]; 1853 int count; 1854 1855 count = fwnode_property_count_u32(chan_node, 1856 "azoteq,rx-enable"); 1857 if (count < 0) { 1858 dev_err(&client->dev, 1859 "Failed to count %s CRx pins: %d\n", 1860 fwnode_get_name(chan_node), count); 1861 return count; 1862 } else if (count > ARRAY_SIZE(pins)) { 1863 dev_err(&client->dev, 1864 "Invalid number of %s CRx pins\n", 1865 fwnode_get_name(chan_node)); 1866 return -EINVAL; 1867 } 1868 1869 error = fwnode_property_read_u32_array(chan_node, 1870 "azoteq,rx-enable", 1871 pins, count); 1872 if (error) { 1873 dev_err(&client->dev, 1874 "Failed to read %s CRx pins: %d\n", 1875 fwnode_get_name(chan_node), error); 1876 return error; 1877 } 1878 1879 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); 1880 1881 for (i = 0; i < count; i++) { 1882 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; 1883 1884 if (pins[i] < min_crx || pins[i] > min_crx + 3) { 1885 dev_err(&client->dev, 1886 "Invalid %s CRx pin: %u\n", 1887 fwnode_get_name(chan_node), pins[i]); 1888 return -EINVAL; 1889 } 1890 1891 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); 1892 } 1893 } 1894 1895 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { 1896 const char *event_name = iqs7222_kp_events[i].name; 1897 u16 event_enable = iqs7222_kp_events[i].enable; 1898 struct fwnode_handle *event_node; 1899 1900 event_node = fwnode_get_named_child_node(chan_node, event_name); 1901 if (!event_node) 1902 continue; 1903 1904 error = iqs7222_parse_props(iqs7222, &event_node, chan_index, 1905 IQS7222_REG_GRP_BTN, 1906 iqs7222_kp_events[i].reg_key); 1907 if (error) 1908 return error; 1909 1910 error = iqs7222_gpio_select(iqs7222, event_node, 1911 BIT(chan_index), 1912 dev_desc->touch_link - (i ? 0 : 2)); 1913 if (error) 1914 return error; 1915 1916 if (!fwnode_property_read_u32(event_node, 1917 "azoteq,timeout-press-ms", 1918 &val)) { 1919 /* 1920 * The IQS7222B employs a global pair of press timeout 1921 * registers as opposed to channel-specific registers. 1922 */ 1923 u16 *setup = dev_desc->reg_grps 1924 [IQS7222_REG_GRP_BTN].num_col > 2 ? 1925 &iqs7222->btn_setup[chan_index][2] : 1926 &sys_setup[9]; 1927 1928 if (val > U8_MAX * 500) { 1929 dev_err(&client->dev, 1930 "Invalid %s press timeout: %u\n", 1931 fwnode_get_name(chan_node), val); 1932 return -EINVAL; 1933 } 1934 1935 *setup &= ~(U8_MAX << i * 8); 1936 *setup |= (val / 500 << i * 8); 1937 } 1938 1939 error = fwnode_property_read_u32(event_node, "linux,code", 1940 &val); 1941 if (error) { 1942 dev_err(&client->dev, "Failed to read %s code: %d\n", 1943 fwnode_get_name(chan_node), error); 1944 return error; 1945 } 1946 1947 iqs7222->kp_code[chan_index][i] = val; 1948 iqs7222->kp_type[chan_index][i] = EV_KEY; 1949 1950 if (fwnode_property_present(event_node, "linux,input-type")) { 1951 error = fwnode_property_read_u32(event_node, 1952 "linux,input-type", 1953 &val); 1954 if (error) { 1955 dev_err(&client->dev, 1956 "Failed to read %s input type: %d\n", 1957 fwnode_get_name(chan_node), error); 1958 return error; 1959 } 1960 1961 if (val != EV_KEY && val != EV_SW) { 1962 dev_err(&client->dev, 1963 "Invalid %s input type: %u\n", 1964 fwnode_get_name(chan_node), val); 1965 return -EINVAL; 1966 } 1967 1968 iqs7222->kp_type[chan_index][i] = val; 1969 } 1970 1971 /* 1972 * Reference channels can opt out of event reporting by using 1973 * KEY_RESERVED in place of a true key or switch code. 1974 */ 1975 if (iqs7222->kp_type[chan_index][i] == EV_KEY && 1976 iqs7222->kp_code[chan_index][i] == KEY_RESERVED) 1977 continue; 1978 1979 input_set_capability(iqs7222->keypad, 1980 iqs7222->kp_type[chan_index][i], 1981 iqs7222->kp_code[chan_index][i]); 1982 1983 if (!dev_desc->event_offset) 1984 continue; 1985 1986 sys_setup[dev_desc->event_offset] |= event_enable; 1987 } 1988 1989 /* 1990 * The following call handles a special pair of properties that apply 1991 * to a channel node, but reside within the button (event) group. 1992 */ 1993 return iqs7222_parse_props(iqs7222, &chan_node, chan_index, 1994 IQS7222_REG_GRP_BTN, 1995 IQS7222_REG_KEY_DEBOUNCE); 1996 } 1997 1998 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222, int sldr_index) 1999 { 2000 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2001 struct i2c_client *client = iqs7222->client; 2002 struct fwnode_handle *sldr_node = NULL; 2003 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 2004 int ext_chan = rounddown(num_chan, 10); 2005 int count, error, reg_offset, i; 2006 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset]; 2007 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index]; 2008 unsigned int chan_sel[4], val; 2009 2010 error = iqs7222_parse_props(iqs7222, &sldr_node, sldr_index, 2011 IQS7222_REG_GRP_SLDR, 2012 IQS7222_REG_KEY_NONE); 2013 if (error) 2014 return error; 2015 2016 if (!sldr_node) 2017 return 0; 2018 2019 /* 2020 * Each slider can be spread across 3 to 4 channels. It is possible to 2021 * select only 2 channels, but doing so prevents the slider from using 2022 * the specified resolution. 2023 */ 2024 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select"); 2025 if (count < 0) { 2026 dev_err(&client->dev, "Failed to count %s channels: %d\n", 2027 fwnode_get_name(sldr_node), count); 2028 return count; 2029 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) { 2030 dev_err(&client->dev, "Invalid number of %s channels\n", 2031 fwnode_get_name(sldr_node)); 2032 return -EINVAL; 2033 } 2034 2035 error = fwnode_property_read_u32_array(sldr_node, 2036 "azoteq,channel-select", 2037 chan_sel, count); 2038 if (error) { 2039 dev_err(&client->dev, "Failed to read %s channels: %d\n", 2040 fwnode_get_name(sldr_node), error); 2041 return error; 2042 } 2043 2044 /* 2045 * Resolution and top speed, if small enough, are packed into a single 2046 * register. Otherwise, each occupies its own register and the rest of 2047 * the slider-related register addresses are offset by one. 2048 */ 2049 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; 2050 2051 sldr_setup[0] |= count; 2052 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0); 2053 2054 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { 2055 sldr_setup[5 + reg_offset + i] = 0; 2056 if (i >= count) 2057 continue; 2058 2059 if (chan_sel[i] >= ext_chan) { 2060 dev_err(&client->dev, "Invalid %s channel: %u\n", 2061 fwnode_get_name(sldr_node), chan_sel[i]); 2062 return -EINVAL; 2063 } 2064 2065 /* 2066 * The following fields indicate which channels participate in 2067 * the slider, as well as each channel's relative placement. 2068 */ 2069 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]); 2070 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080; 2071 } 2072 2073 sldr_setup[4 + reg_offset] = dev_desc->touch_link; 2074 if (fwnode_property_present(sldr_node, "azoteq,use-prox")) 2075 sldr_setup[4 + reg_offset] -= 2; 2076 2077 if (!fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val)) { 2078 if (!val || val > dev_desc->sldr_res) { 2079 dev_err(&client->dev, "Invalid %s size: %u\n", 2080 fwnode_get_name(sldr_node), val); 2081 return -EINVAL; 2082 } 2083 2084 if (reg_offset) { 2085 sldr_setup[3] = val; 2086 } else { 2087 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK; 2088 sldr_setup[2] |= (val / 16 << 2089 IQS7222_SLDR_SETUP_2_RES_SHIFT); 2090 } 2091 } 2092 2093 if (!fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val)) { 2094 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) { 2095 dev_err(&client->dev, "Invalid %s top speed: %u\n", 2096 fwnode_get_name(sldr_node), val); 2097 return -EINVAL; 2098 } 2099 2100 if (reg_offset) { 2101 sldr_setup[2] = val; 2102 } else { 2103 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK; 2104 sldr_setup[2] |= (val / 4); 2105 } 2106 } 2107 2108 if (!fwnode_property_read_u32(sldr_node, "linux,axis", &val)) { 2109 u16 sldr_max = sldr_setup[3] - 1; 2110 2111 if (!reg_offset) { 2112 sldr_max = sldr_setup[2]; 2113 2114 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK; 2115 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT; 2116 2117 sldr_max = sldr_max * 16 - 1; 2118 } 2119 2120 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); 2121 iqs7222->sl_axis[sldr_index] = val; 2122 } 2123 2124 if (dev_desc->wheel_enable) { 2125 sldr_setup[0] &= ~dev_desc->wheel_enable; 2126 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL) 2127 sldr_setup[0] |= dev_desc->wheel_enable; 2128 } 2129 2130 /* 2131 * The absence of a register offset makes it safe to assume the device 2132 * supports gestures, each of which is first disabled until explicitly 2133 * enabled. 2134 */ 2135 if (!reg_offset) 2136 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) 2137 sldr_setup[9] &= ~iqs7222_sl_events[i].enable; 2138 2139 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { 2140 const char *event_name = iqs7222_sl_events[i].name; 2141 struct fwnode_handle *event_node; 2142 2143 event_node = fwnode_get_named_child_node(sldr_node, event_name); 2144 if (!event_node) 2145 continue; 2146 2147 error = iqs7222_parse_props(iqs7222, &event_node, sldr_index, 2148 IQS7222_REG_GRP_SLDR, 2149 reg_offset ? 2150 IQS7222_REG_KEY_RESERVED : 2151 iqs7222_sl_events[i].reg_key); 2152 if (error) 2153 return error; 2154 2155 /* 2156 * The press/release event does not expose a direct GPIO link, 2157 * but one can be emulated by tying each of the participating 2158 * channels to the same GPIO. 2159 */ 2160 error = iqs7222_gpio_select(iqs7222, event_node, 2161 i ? iqs7222_sl_events[i].enable 2162 : sldr_setup[3 + reg_offset], 2163 i ? 1568 + sldr_index * 30 2164 : sldr_setup[4 + reg_offset]); 2165 if (error) 2166 return error; 2167 2168 if (!reg_offset) 2169 sldr_setup[9] |= iqs7222_sl_events[i].enable; 2170 2171 error = fwnode_property_read_u32(event_node, "linux,code", 2172 &val); 2173 if (error) { 2174 dev_err(&client->dev, "Failed to read %s code: %d\n", 2175 fwnode_get_name(sldr_node), error); 2176 return error; 2177 } 2178 2179 iqs7222->sl_code[sldr_index][i] = val; 2180 input_set_capability(iqs7222->keypad, EV_KEY, val); 2181 2182 if (!dev_desc->event_offset) 2183 continue; 2184 2185 /* 2186 * The press/release event is determined based on whether the 2187 * coordinate field reports 0xFFFF and solely relies on touch 2188 * or proximity interrupts to be unmasked. 2189 */ 2190 if (i && !reg_offset) 2191 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index); 2192 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link) 2193 *event_mask |= IQS7222_EVENT_MASK_TOUCH; 2194 else 2195 *event_mask |= IQS7222_EVENT_MASK_PROX; 2196 } 2197 2198 /* 2199 * The following call handles a special pair of properties that shift 2200 * to make room for a wheel enable control in the case of IQS7222C. 2201 */ 2202 return iqs7222_parse_props(iqs7222, &sldr_node, sldr_index, 2203 IQS7222_REG_GRP_SLDR, 2204 dev_desc->wheel_enable ? 2205 IQS7222_REG_KEY_WHEEL : 2206 IQS7222_REG_KEY_NO_WHEEL); 2207 } 2208 2209 static int iqs7222_parse_all(struct iqs7222_private *iqs7222) 2210 { 2211 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2212 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps; 2213 u16 *sys_setup = iqs7222->sys_setup; 2214 int error, i; 2215 2216 if (dev_desc->event_offset) 2217 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI; 2218 2219 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CYCLE].num_row; i++) { 2220 error = iqs7222_parse_cycle(iqs7222, i); 2221 if (error) 2222 return error; 2223 } 2224 2225 error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_GLBL, 2226 IQS7222_REG_KEY_NONE); 2227 if (error) 2228 return error; 2229 2230 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { 2231 struct fwnode_handle *gpio_node = NULL; 2232 u16 *gpio_setup = iqs7222->gpio_setup[i]; 2233 int j; 2234 2235 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; 2236 gpio_setup[1] = 0; 2237 gpio_setup[2] = 0; 2238 2239 error = iqs7222_parse_props(iqs7222, &gpio_node, i, 2240 IQS7222_REG_GRP_GPIO, 2241 IQS7222_REG_KEY_NONE); 2242 if (error) 2243 return error; 2244 2245 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1) 2246 continue; 2247 2248 /* 2249 * The IQS7222C exposes multiple GPIO and must be informed 2250 * as to which GPIO this group represents. 2251 */ 2252 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) 2253 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); 2254 2255 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); 2256 } 2257 2258 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { 2259 u16 *chan_setup = iqs7222->chan_setup[i]; 2260 2261 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; 2262 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; 2263 2264 chan_setup[5] = 0; 2265 } 2266 2267 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { 2268 error = iqs7222_parse_chan(iqs7222, i); 2269 if (error) 2270 return error; 2271 } 2272 2273 error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_FILT, 2274 IQS7222_REG_KEY_NONE); 2275 if (error) 2276 return error; 2277 2278 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2279 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2280 2281 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; 2282 2283 error = iqs7222_parse_sldr(iqs7222, i); 2284 if (error) 2285 return error; 2286 } 2287 2288 return iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_SYS, 2289 IQS7222_REG_KEY_NONE); 2290 } 2291 2292 static int iqs7222_report(struct iqs7222_private *iqs7222) 2293 { 2294 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2295 struct i2c_client *client = iqs7222->client; 2296 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 2297 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col; 2298 int error, i, j; 2299 __le16 status[IQS7222_MAX_COLS_STAT]; 2300 2301 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status, 2302 num_stat); 2303 if (error) 2304 return error; 2305 2306 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { 2307 dev_err(&client->dev, "Unexpected device reset\n"); 2308 return iqs7222_dev_init(iqs7222, WRITE); 2309 } 2310 2311 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { 2312 dev_err(&client->dev, "Unexpected ATI error\n"); 2313 return iqs7222_ati_trigger(iqs7222); 2314 } 2315 2316 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) 2317 return 0; 2318 2319 for (i = 0; i < num_chan; i++) { 2320 u16 *chan_setup = iqs7222->chan_setup[i]; 2321 2322 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) 2323 continue; 2324 2325 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { 2326 /* 2327 * Proximity state begins at offset 2 and spills into 2328 * offset 3 for devices with more than 16 channels. 2329 * 2330 * Touch state begins at the first offset immediately 2331 * following proximity state. 2332 */ 2333 int k = 2 + j * (num_chan > 16 ? 2 : 1); 2334 u16 state = le16_to_cpu(status[k + i / 16]); 2335 2336 input_event(iqs7222->keypad, 2337 iqs7222->kp_type[i][j], 2338 iqs7222->kp_code[i][j], 2339 !!(state & BIT(i % 16))); 2340 } 2341 } 2342 2343 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2344 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2345 u16 sldr_pos = le16_to_cpu(status[4 + i]); 2346 u16 state = le16_to_cpu(status[6 + i]); 2347 2348 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) 2349 continue; 2350 2351 if (sldr_pos < dev_desc->sldr_res) 2352 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i], 2353 sldr_pos); 2354 2355 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0], 2356 sldr_pos < dev_desc->sldr_res); 2357 2358 /* 2359 * A maximum resolution indicates the device does not support 2360 * gestures, in which case the remaining fields are ignored. 2361 */ 2362 if (dev_desc->sldr_res == U16_MAX) 2363 continue; 2364 2365 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i)) 2366 continue; 2367 2368 /* 2369 * Skip the press/release event, as it does not have separate 2370 * status fields and is handled separately. 2371 */ 2372 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) { 2373 u16 mask = iqs7222_sl_events[j].mask; 2374 u16 val = iqs7222_sl_events[j].val; 2375 2376 input_report_key(iqs7222->keypad, 2377 iqs7222->sl_code[i][j], 2378 (state & mask) == val); 2379 } 2380 2381 input_sync(iqs7222->keypad); 2382 2383 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) 2384 input_report_key(iqs7222->keypad, 2385 iqs7222->sl_code[i][j], 0); 2386 } 2387 2388 input_sync(iqs7222->keypad); 2389 2390 return 0; 2391 } 2392 2393 static irqreturn_t iqs7222_irq(int irq, void *context) 2394 { 2395 struct iqs7222_private *iqs7222 = context; 2396 2397 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED; 2398 } 2399 2400 static int iqs7222_probe(struct i2c_client *client) 2401 { 2402 struct iqs7222_private *iqs7222; 2403 unsigned long irq_flags; 2404 int error, irq; 2405 2406 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL); 2407 if (!iqs7222) 2408 return -ENOMEM; 2409 2410 i2c_set_clientdata(client, iqs7222); 2411 iqs7222->client = client; 2412 2413 iqs7222->keypad = devm_input_allocate_device(&client->dev); 2414 if (!iqs7222->keypad) 2415 return -ENOMEM; 2416 2417 iqs7222->keypad->name = client->name; 2418 iqs7222->keypad->id.bustype = BUS_I2C; 2419 2420 /* 2421 * The RDY pin behaves as an interrupt, but must also be polled ahead 2422 * of unsolicited I2C communication. As such, it is first opened as a 2423 * GPIO and then passed to gpiod_to_irq() to register the interrupt. 2424 */ 2425 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN); 2426 if (IS_ERR(iqs7222->irq_gpio)) { 2427 error = PTR_ERR(iqs7222->irq_gpio); 2428 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n", 2429 error); 2430 return error; 2431 } 2432 2433 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 2434 GPIOD_OUT_HIGH); 2435 if (IS_ERR(iqs7222->reset_gpio)) { 2436 error = PTR_ERR(iqs7222->reset_gpio); 2437 dev_err(&client->dev, "Failed to request reset GPIO: %d\n", 2438 error); 2439 return error; 2440 } 2441 2442 error = iqs7222_hard_reset(iqs7222); 2443 if (error) 2444 return error; 2445 2446 error = iqs7222_dev_info(iqs7222); 2447 if (error) 2448 return error; 2449 2450 error = iqs7222_dev_init(iqs7222, READ); 2451 if (error) 2452 return error; 2453 2454 error = iqs7222_parse_all(iqs7222); 2455 if (error) 2456 return error; 2457 2458 error = iqs7222_dev_init(iqs7222, WRITE); 2459 if (error) 2460 return error; 2461 2462 error = iqs7222_report(iqs7222); 2463 if (error) 2464 return error; 2465 2466 error = input_register_device(iqs7222->keypad); 2467 if (error) { 2468 dev_err(&client->dev, "Failed to register device: %d\n", error); 2469 return error; 2470 } 2471 2472 irq = gpiod_to_irq(iqs7222->irq_gpio); 2473 if (irq < 0) 2474 return irq; 2475 2476 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW 2477 : IRQF_TRIGGER_HIGH; 2478 irq_flags |= IRQF_ONESHOT; 2479 2480 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq, 2481 irq_flags, client->name, iqs7222); 2482 if (error) 2483 dev_err(&client->dev, "Failed to request IRQ: %d\n", error); 2484 2485 return error; 2486 } 2487 2488 static const struct of_device_id iqs7222_of_match[] = { 2489 { .compatible = "azoteq,iqs7222a" }, 2490 { .compatible = "azoteq,iqs7222b" }, 2491 { .compatible = "azoteq,iqs7222c" }, 2492 { } 2493 }; 2494 MODULE_DEVICE_TABLE(of, iqs7222_of_match); 2495 2496 static struct i2c_driver iqs7222_i2c_driver = { 2497 .driver = { 2498 .name = "iqs7222", 2499 .of_match_table = iqs7222_of_match, 2500 }, 2501 .probe_new = iqs7222_probe, 2502 }; 2503 module_i2c_driver(iqs7222_i2c_driver); 2504 2505 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>"); 2506 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C Capacitive Touch Controller"); 2507 MODULE_LICENSE("GPL"); 2508