1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Azoteq IQS7222A/B/C Capacitive Touch Controller 4 * 5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com> 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/i2c.h> 14 #include <linux/input.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/ktime.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 #include <asm/unaligned.h> 23 24 #define IQS7222_PROD_NUM 0x00 25 #define IQS7222_PROD_NUM_A 840 26 #define IQS7222_PROD_NUM_B 698 27 #define IQS7222_PROD_NUM_C 863 28 29 #define IQS7222_SYS_STATUS 0x10 30 #define IQS7222_SYS_STATUS_RESET BIT(3) 31 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1) 32 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0) 33 34 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14) 35 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15) 36 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14) 37 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8) 38 39 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0) 40 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8) 41 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8 42 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0) 43 44 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0) 45 46 #define IQS7222_SYS_SETUP 0xD0 47 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6) 48 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7) 49 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6) 50 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4) 51 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK 52 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2) 53 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0) 54 55 #define IQS7222_EVENT_MASK_ATI BIT(12) 56 #define IQS7222_EVENT_MASK_SLDR BIT(10) 57 #define IQS7222_EVENT_MASK_TOUCH BIT(1) 58 #define IQS7222_EVENT_MASK_PROX BIT(0) 59 60 #define IQS7222_COMMS_HOLD BIT(0) 61 #define IQS7222_COMMS_ERROR 0xEEEE 62 #define IQS7222_COMMS_RETRY_MS 50 63 #define IQS7222_COMMS_TIMEOUT_MS 100 64 #define IQS7222_RESET_TIMEOUT_MS 250 65 #define IQS7222_ATI_TIMEOUT_MS 2000 66 67 #define IQS7222_MAX_COLS_STAT 8 68 #define IQS7222_MAX_COLS_CYCLE 3 69 #define IQS7222_MAX_COLS_GLBL 3 70 #define IQS7222_MAX_COLS_BTN 3 71 #define IQS7222_MAX_COLS_CHAN 6 72 #define IQS7222_MAX_COLS_FILT 2 73 #define IQS7222_MAX_COLS_SLDR 11 74 #define IQS7222_MAX_COLS_GPIO 3 75 #define IQS7222_MAX_COLS_SYS 13 76 77 #define IQS7222_MAX_CHAN 20 78 #define IQS7222_MAX_SLDR 2 79 80 #define IQS7222_NUM_RETRIES 5 81 #define IQS7222_REG_OFFSET 0x100 82 83 enum iqs7222_reg_key_id { 84 IQS7222_REG_KEY_NONE, 85 IQS7222_REG_KEY_PROX, 86 IQS7222_REG_KEY_TOUCH, 87 IQS7222_REG_KEY_DEBOUNCE, 88 IQS7222_REG_KEY_TAP, 89 IQS7222_REG_KEY_AXIAL, 90 IQS7222_REG_KEY_WHEEL, 91 IQS7222_REG_KEY_NO_WHEEL, 92 IQS7222_REG_KEY_RESERVED 93 }; 94 95 enum iqs7222_reg_grp_id { 96 IQS7222_REG_GRP_STAT, 97 IQS7222_REG_GRP_FILT, 98 IQS7222_REG_GRP_CYCLE, 99 IQS7222_REG_GRP_GLBL, 100 IQS7222_REG_GRP_BTN, 101 IQS7222_REG_GRP_CHAN, 102 IQS7222_REG_GRP_SLDR, 103 IQS7222_REG_GRP_GPIO, 104 IQS7222_REG_GRP_SYS, 105 IQS7222_NUM_REG_GRPS 106 }; 107 108 static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = { 109 [IQS7222_REG_GRP_CYCLE] = "cycle", 110 [IQS7222_REG_GRP_CHAN] = "channel", 111 [IQS7222_REG_GRP_SLDR] = "slider", 112 [IQS7222_REG_GRP_GPIO] = "gpio", 113 }; 114 115 static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = { 116 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT, 117 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE, 118 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL, 119 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN, 120 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN, 121 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT, 122 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR, 123 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO, 124 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS, 125 }; 126 127 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, }; 128 129 struct iqs7222_event_desc { 130 const char *name; 131 u16 mask; 132 u16 val; 133 u16 enable; 134 enum iqs7222_reg_key_id reg_key; 135 }; 136 137 static const struct iqs7222_event_desc iqs7222_kp_events[] = { 138 { 139 .name = "event-prox", 140 .enable = IQS7222_EVENT_MASK_PROX, 141 .reg_key = IQS7222_REG_KEY_PROX, 142 }, 143 { 144 .name = "event-touch", 145 .enable = IQS7222_EVENT_MASK_TOUCH, 146 .reg_key = IQS7222_REG_KEY_TOUCH, 147 }, 148 }; 149 150 static const struct iqs7222_event_desc iqs7222_sl_events[] = { 151 { .name = "event-press", }, 152 { 153 .name = "event-tap", 154 .mask = BIT(0), 155 .val = BIT(0), 156 .enable = BIT(0), 157 .reg_key = IQS7222_REG_KEY_TAP, 158 }, 159 { 160 .name = "event-swipe-pos", 161 .mask = BIT(5) | BIT(1), 162 .val = BIT(1), 163 .enable = BIT(1), 164 .reg_key = IQS7222_REG_KEY_AXIAL, 165 }, 166 { 167 .name = "event-swipe-neg", 168 .mask = BIT(5) | BIT(1), 169 .val = BIT(5) | BIT(1), 170 .enable = BIT(1), 171 .reg_key = IQS7222_REG_KEY_AXIAL, 172 }, 173 { 174 .name = "event-flick-pos", 175 .mask = BIT(5) | BIT(2), 176 .val = BIT(2), 177 .enable = BIT(2), 178 .reg_key = IQS7222_REG_KEY_AXIAL, 179 }, 180 { 181 .name = "event-flick-neg", 182 .mask = BIT(5) | BIT(2), 183 .val = BIT(5) | BIT(2), 184 .enable = BIT(2), 185 .reg_key = IQS7222_REG_KEY_AXIAL, 186 }, 187 }; 188 189 struct iqs7222_reg_grp_desc { 190 u16 base; 191 int num_row; 192 int num_col; 193 }; 194 195 struct iqs7222_dev_desc { 196 u16 prod_num; 197 u16 fw_major; 198 u16 fw_minor; 199 u16 sldr_res; 200 u16 touch_link; 201 u16 wheel_enable; 202 int allow_offset; 203 int event_offset; 204 int comms_offset; 205 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS]; 206 }; 207 208 static const struct iqs7222_dev_desc iqs7222_devs[] = { 209 { 210 .prod_num = IQS7222_PROD_NUM_A, 211 .fw_major = 1, 212 .fw_minor = 12, 213 .sldr_res = U8_MAX * 16, 214 .touch_link = 1768, 215 .allow_offset = 9, 216 .event_offset = 10, 217 .comms_offset = 12, 218 .reg_grps = { 219 [IQS7222_REG_GRP_STAT] = { 220 .base = IQS7222_SYS_STATUS, 221 .num_row = 1, 222 .num_col = 8, 223 }, 224 [IQS7222_REG_GRP_CYCLE] = { 225 .base = 0x8000, 226 .num_row = 7, 227 .num_col = 3, 228 }, 229 [IQS7222_REG_GRP_GLBL] = { 230 .base = 0x8700, 231 .num_row = 1, 232 .num_col = 3, 233 }, 234 [IQS7222_REG_GRP_BTN] = { 235 .base = 0x9000, 236 .num_row = 12, 237 .num_col = 3, 238 }, 239 [IQS7222_REG_GRP_CHAN] = { 240 .base = 0xA000, 241 .num_row = 12, 242 .num_col = 6, 243 }, 244 [IQS7222_REG_GRP_FILT] = { 245 .base = 0xAC00, 246 .num_row = 1, 247 .num_col = 2, 248 }, 249 [IQS7222_REG_GRP_SLDR] = { 250 .base = 0xB000, 251 .num_row = 2, 252 .num_col = 11, 253 }, 254 [IQS7222_REG_GRP_GPIO] = { 255 .base = 0xC000, 256 .num_row = 1, 257 .num_col = 3, 258 }, 259 [IQS7222_REG_GRP_SYS] = { 260 .base = IQS7222_SYS_SETUP, 261 .num_row = 1, 262 .num_col = 13, 263 }, 264 }, 265 }, 266 { 267 .prod_num = IQS7222_PROD_NUM_B, 268 .fw_major = 1, 269 .fw_minor = 43, 270 .event_offset = 10, 271 .comms_offset = 11, 272 .reg_grps = { 273 [IQS7222_REG_GRP_STAT] = { 274 .base = IQS7222_SYS_STATUS, 275 .num_row = 1, 276 .num_col = 6, 277 }, 278 [IQS7222_REG_GRP_CYCLE] = { 279 .base = 0x8000, 280 .num_row = 10, 281 .num_col = 2, 282 }, 283 [IQS7222_REG_GRP_GLBL] = { 284 .base = 0x8A00, 285 .num_row = 1, 286 .num_col = 3, 287 }, 288 [IQS7222_REG_GRP_BTN] = { 289 .base = 0x9000, 290 .num_row = 20, 291 .num_col = 2, 292 }, 293 [IQS7222_REG_GRP_CHAN] = { 294 .base = 0xB000, 295 .num_row = 20, 296 .num_col = 4, 297 }, 298 [IQS7222_REG_GRP_FILT] = { 299 .base = 0xC400, 300 .num_row = 1, 301 .num_col = 2, 302 }, 303 [IQS7222_REG_GRP_SYS] = { 304 .base = IQS7222_SYS_SETUP, 305 .num_row = 1, 306 .num_col = 13, 307 }, 308 }, 309 }, 310 { 311 .prod_num = IQS7222_PROD_NUM_B, 312 .fw_major = 1, 313 .fw_minor = 27, 314 .reg_grps = { 315 [IQS7222_REG_GRP_STAT] = { 316 .base = IQS7222_SYS_STATUS, 317 .num_row = 1, 318 .num_col = 6, 319 }, 320 [IQS7222_REG_GRP_CYCLE] = { 321 .base = 0x8000, 322 .num_row = 10, 323 .num_col = 2, 324 }, 325 [IQS7222_REG_GRP_GLBL] = { 326 .base = 0x8A00, 327 .num_row = 1, 328 .num_col = 3, 329 }, 330 [IQS7222_REG_GRP_BTN] = { 331 .base = 0x9000, 332 .num_row = 20, 333 .num_col = 2, 334 }, 335 [IQS7222_REG_GRP_CHAN] = { 336 .base = 0xB000, 337 .num_row = 20, 338 .num_col = 4, 339 }, 340 [IQS7222_REG_GRP_FILT] = { 341 .base = 0xC400, 342 .num_row = 1, 343 .num_col = 2, 344 }, 345 [IQS7222_REG_GRP_SYS] = { 346 .base = IQS7222_SYS_SETUP, 347 .num_row = 1, 348 .num_col = 10, 349 }, 350 }, 351 }, 352 { 353 .prod_num = IQS7222_PROD_NUM_C, 354 .fw_major = 2, 355 .fw_minor = 6, 356 .sldr_res = U16_MAX, 357 .touch_link = 1686, 358 .wheel_enable = BIT(3), 359 .event_offset = 9, 360 .comms_offset = 10, 361 .reg_grps = { 362 [IQS7222_REG_GRP_STAT] = { 363 .base = IQS7222_SYS_STATUS, 364 .num_row = 1, 365 .num_col = 6, 366 }, 367 [IQS7222_REG_GRP_CYCLE] = { 368 .base = 0x8000, 369 .num_row = 5, 370 .num_col = 3, 371 }, 372 [IQS7222_REG_GRP_GLBL] = { 373 .base = 0x8500, 374 .num_row = 1, 375 .num_col = 3, 376 }, 377 [IQS7222_REG_GRP_BTN] = { 378 .base = 0x9000, 379 .num_row = 10, 380 .num_col = 3, 381 }, 382 [IQS7222_REG_GRP_CHAN] = { 383 .base = 0xA000, 384 .num_row = 10, 385 .num_col = 6, 386 }, 387 [IQS7222_REG_GRP_FILT] = { 388 .base = 0xAA00, 389 .num_row = 1, 390 .num_col = 2, 391 }, 392 [IQS7222_REG_GRP_SLDR] = { 393 .base = 0xB000, 394 .num_row = 2, 395 .num_col = 10, 396 }, 397 [IQS7222_REG_GRP_GPIO] = { 398 .base = 0xC000, 399 .num_row = 3, 400 .num_col = 3, 401 }, 402 [IQS7222_REG_GRP_SYS] = { 403 .base = IQS7222_SYS_SETUP, 404 .num_row = 1, 405 .num_col = 12, 406 }, 407 }, 408 }, 409 { 410 .prod_num = IQS7222_PROD_NUM_C, 411 .fw_major = 1, 412 .fw_minor = 13, 413 .sldr_res = U16_MAX, 414 .touch_link = 1674, 415 .wheel_enable = BIT(3), 416 .event_offset = 9, 417 .comms_offset = 10, 418 .reg_grps = { 419 [IQS7222_REG_GRP_STAT] = { 420 .base = IQS7222_SYS_STATUS, 421 .num_row = 1, 422 .num_col = 6, 423 }, 424 [IQS7222_REG_GRP_CYCLE] = { 425 .base = 0x8000, 426 .num_row = 5, 427 .num_col = 3, 428 }, 429 [IQS7222_REG_GRP_GLBL] = { 430 .base = 0x8500, 431 .num_row = 1, 432 .num_col = 3, 433 }, 434 [IQS7222_REG_GRP_BTN] = { 435 .base = 0x9000, 436 .num_row = 10, 437 .num_col = 3, 438 }, 439 [IQS7222_REG_GRP_CHAN] = { 440 .base = 0xA000, 441 .num_row = 10, 442 .num_col = 6, 443 }, 444 [IQS7222_REG_GRP_FILT] = { 445 .base = 0xAA00, 446 .num_row = 1, 447 .num_col = 2, 448 }, 449 [IQS7222_REG_GRP_SLDR] = { 450 .base = 0xB000, 451 .num_row = 2, 452 .num_col = 10, 453 }, 454 [IQS7222_REG_GRP_GPIO] = { 455 .base = 0xC000, 456 .num_row = 1, 457 .num_col = 3, 458 }, 459 [IQS7222_REG_GRP_SYS] = { 460 .base = IQS7222_SYS_SETUP, 461 .num_row = 1, 462 .num_col = 11, 463 }, 464 }, 465 }, 466 }; 467 468 struct iqs7222_prop_desc { 469 const char *name; 470 enum iqs7222_reg_grp_id reg_grp; 471 enum iqs7222_reg_key_id reg_key; 472 int reg_offset; 473 int reg_shift; 474 int reg_width; 475 int val_pitch; 476 int val_min; 477 int val_max; 478 bool invert; 479 const char *label; 480 }; 481 482 static const struct iqs7222_prop_desc iqs7222_props[] = { 483 { 484 .name = "azoteq,conv-period", 485 .reg_grp = IQS7222_REG_GRP_CYCLE, 486 .reg_offset = 0, 487 .reg_shift = 8, 488 .reg_width = 8, 489 .label = "conversion period", 490 }, 491 { 492 .name = "azoteq,conv-frac", 493 .reg_grp = IQS7222_REG_GRP_CYCLE, 494 .reg_offset = 0, 495 .reg_shift = 0, 496 .reg_width = 8, 497 .label = "conversion frequency fractional divider", 498 }, 499 { 500 .name = "azoteq,rx-float-inactive", 501 .reg_grp = IQS7222_REG_GRP_CYCLE, 502 .reg_offset = 1, 503 .reg_shift = 6, 504 .reg_width = 1, 505 .invert = true, 506 }, 507 { 508 .name = "azoteq,dead-time-enable", 509 .reg_grp = IQS7222_REG_GRP_CYCLE, 510 .reg_offset = 1, 511 .reg_shift = 5, 512 .reg_width = 1, 513 }, 514 { 515 .name = "azoteq,tx-freq-fosc", 516 .reg_grp = IQS7222_REG_GRP_CYCLE, 517 .reg_offset = 1, 518 .reg_shift = 4, 519 .reg_width = 1, 520 }, 521 { 522 .name = "azoteq,vbias-enable", 523 .reg_grp = IQS7222_REG_GRP_CYCLE, 524 .reg_offset = 1, 525 .reg_shift = 3, 526 .reg_width = 1, 527 }, 528 { 529 .name = "azoteq,sense-mode", 530 .reg_grp = IQS7222_REG_GRP_CYCLE, 531 .reg_offset = 1, 532 .reg_shift = 0, 533 .reg_width = 3, 534 .val_max = 3, 535 .label = "sensing mode", 536 }, 537 { 538 .name = "azoteq,iref-enable", 539 .reg_grp = IQS7222_REG_GRP_CYCLE, 540 .reg_offset = 2, 541 .reg_shift = 10, 542 .reg_width = 1, 543 }, 544 { 545 .name = "azoteq,iref-level", 546 .reg_grp = IQS7222_REG_GRP_CYCLE, 547 .reg_offset = 2, 548 .reg_shift = 4, 549 .reg_width = 4, 550 .label = "current reference level", 551 }, 552 { 553 .name = "azoteq,iref-trim", 554 .reg_grp = IQS7222_REG_GRP_CYCLE, 555 .reg_offset = 2, 556 .reg_shift = 0, 557 .reg_width = 4, 558 .label = "current reference trim", 559 }, 560 { 561 .name = "azoteq,max-counts", 562 .reg_grp = IQS7222_REG_GRP_GLBL, 563 .reg_offset = 0, 564 .reg_shift = 13, 565 .reg_width = 2, 566 .label = "maximum counts", 567 }, 568 { 569 .name = "azoteq,auto-mode", 570 .reg_grp = IQS7222_REG_GRP_GLBL, 571 .reg_offset = 0, 572 .reg_shift = 2, 573 .reg_width = 2, 574 .label = "number of conversions", 575 }, 576 { 577 .name = "azoteq,ati-frac-div-fine", 578 .reg_grp = IQS7222_REG_GRP_GLBL, 579 .reg_offset = 1, 580 .reg_shift = 9, 581 .reg_width = 5, 582 .label = "ATI fine fractional divider", 583 }, 584 { 585 .name = "azoteq,ati-frac-div-coarse", 586 .reg_grp = IQS7222_REG_GRP_GLBL, 587 .reg_offset = 1, 588 .reg_shift = 0, 589 .reg_width = 5, 590 .label = "ATI coarse fractional divider", 591 }, 592 { 593 .name = "azoteq,ati-comp-select", 594 .reg_grp = IQS7222_REG_GRP_GLBL, 595 .reg_offset = 2, 596 .reg_shift = 0, 597 .reg_width = 10, 598 .label = "ATI compensation selection", 599 }, 600 { 601 .name = "azoteq,ati-band", 602 .reg_grp = IQS7222_REG_GRP_CHAN, 603 .reg_offset = 0, 604 .reg_shift = 12, 605 .reg_width = 2, 606 .label = "ATI band", 607 }, 608 { 609 .name = "azoteq,global-halt", 610 .reg_grp = IQS7222_REG_GRP_CHAN, 611 .reg_offset = 0, 612 .reg_shift = 11, 613 .reg_width = 1, 614 }, 615 { 616 .name = "azoteq,invert-enable", 617 .reg_grp = IQS7222_REG_GRP_CHAN, 618 .reg_offset = 0, 619 .reg_shift = 10, 620 .reg_width = 1, 621 }, 622 { 623 .name = "azoteq,dual-direction", 624 .reg_grp = IQS7222_REG_GRP_CHAN, 625 .reg_offset = 0, 626 .reg_shift = 9, 627 .reg_width = 1, 628 }, 629 { 630 .name = "azoteq,samp-cap-double", 631 .reg_grp = IQS7222_REG_GRP_CHAN, 632 .reg_offset = 0, 633 .reg_shift = 3, 634 .reg_width = 1, 635 }, 636 { 637 .name = "azoteq,vref-half", 638 .reg_grp = IQS7222_REG_GRP_CHAN, 639 .reg_offset = 0, 640 .reg_shift = 2, 641 .reg_width = 1, 642 }, 643 { 644 .name = "azoteq,proj-bias", 645 .reg_grp = IQS7222_REG_GRP_CHAN, 646 .reg_offset = 0, 647 .reg_shift = 0, 648 .reg_width = 2, 649 .label = "projected bias current", 650 }, 651 { 652 .name = "azoteq,ati-target", 653 .reg_grp = IQS7222_REG_GRP_CHAN, 654 .reg_offset = 1, 655 .reg_shift = 8, 656 .reg_width = 8, 657 .val_pitch = 8, 658 .label = "ATI target", 659 }, 660 { 661 .name = "azoteq,ati-base", 662 .reg_grp = IQS7222_REG_GRP_CHAN, 663 .reg_offset = 1, 664 .reg_shift = 3, 665 .reg_width = 5, 666 .val_pitch = 16, 667 .label = "ATI base", 668 }, 669 { 670 .name = "azoteq,ati-mode", 671 .reg_grp = IQS7222_REG_GRP_CHAN, 672 .reg_offset = 1, 673 .reg_shift = 0, 674 .reg_width = 3, 675 .val_max = 5, 676 .label = "ATI mode", 677 }, 678 { 679 .name = "azoteq,ati-frac-div-fine", 680 .reg_grp = IQS7222_REG_GRP_CHAN, 681 .reg_offset = 2, 682 .reg_shift = 9, 683 .reg_width = 5, 684 .label = "ATI fine fractional divider", 685 }, 686 { 687 .name = "azoteq,ati-frac-mult-coarse", 688 .reg_grp = IQS7222_REG_GRP_CHAN, 689 .reg_offset = 2, 690 .reg_shift = 5, 691 .reg_width = 4, 692 .label = "ATI coarse fractional multiplier", 693 }, 694 { 695 .name = "azoteq,ati-frac-div-coarse", 696 .reg_grp = IQS7222_REG_GRP_CHAN, 697 .reg_offset = 2, 698 .reg_shift = 0, 699 .reg_width = 5, 700 .label = "ATI coarse fractional divider", 701 }, 702 { 703 .name = "azoteq,ati-comp-div", 704 .reg_grp = IQS7222_REG_GRP_CHAN, 705 .reg_offset = 3, 706 .reg_shift = 11, 707 .reg_width = 5, 708 .label = "ATI compensation divider", 709 }, 710 { 711 .name = "azoteq,ati-comp-select", 712 .reg_grp = IQS7222_REG_GRP_CHAN, 713 .reg_offset = 3, 714 .reg_shift = 0, 715 .reg_width = 10, 716 .label = "ATI compensation selection", 717 }, 718 { 719 .name = "azoteq,debounce-exit", 720 .reg_grp = IQS7222_REG_GRP_BTN, 721 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 722 .reg_offset = 0, 723 .reg_shift = 12, 724 .reg_width = 4, 725 .label = "debounce exit factor", 726 }, 727 { 728 .name = "azoteq,debounce-enter", 729 .reg_grp = IQS7222_REG_GRP_BTN, 730 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 731 .reg_offset = 0, 732 .reg_shift = 8, 733 .reg_width = 4, 734 .label = "debounce entrance factor", 735 }, 736 { 737 .name = "azoteq,thresh", 738 .reg_grp = IQS7222_REG_GRP_BTN, 739 .reg_key = IQS7222_REG_KEY_PROX, 740 .reg_offset = 0, 741 .reg_shift = 0, 742 .reg_width = 8, 743 .val_max = 127, 744 .label = "threshold", 745 }, 746 { 747 .name = "azoteq,thresh", 748 .reg_grp = IQS7222_REG_GRP_BTN, 749 .reg_key = IQS7222_REG_KEY_TOUCH, 750 .reg_offset = 1, 751 .reg_shift = 0, 752 .reg_width = 8, 753 .label = "threshold", 754 }, 755 { 756 .name = "azoteq,hyst", 757 .reg_grp = IQS7222_REG_GRP_BTN, 758 .reg_key = IQS7222_REG_KEY_TOUCH, 759 .reg_offset = 1, 760 .reg_shift = 8, 761 .reg_width = 8, 762 .label = "hysteresis", 763 }, 764 { 765 .name = "azoteq,lta-beta-lp", 766 .reg_grp = IQS7222_REG_GRP_FILT, 767 .reg_offset = 0, 768 .reg_shift = 12, 769 .reg_width = 4, 770 .label = "low-power mode long-term average beta", 771 }, 772 { 773 .name = "azoteq,lta-beta-np", 774 .reg_grp = IQS7222_REG_GRP_FILT, 775 .reg_offset = 0, 776 .reg_shift = 8, 777 .reg_width = 4, 778 .label = "normal-power mode long-term average beta", 779 }, 780 { 781 .name = "azoteq,counts-beta-lp", 782 .reg_grp = IQS7222_REG_GRP_FILT, 783 .reg_offset = 0, 784 .reg_shift = 4, 785 .reg_width = 4, 786 .label = "low-power mode counts beta", 787 }, 788 { 789 .name = "azoteq,counts-beta-np", 790 .reg_grp = IQS7222_REG_GRP_FILT, 791 .reg_offset = 0, 792 .reg_shift = 0, 793 .reg_width = 4, 794 .label = "normal-power mode counts beta", 795 }, 796 { 797 .name = "azoteq,lta-fast-beta-lp", 798 .reg_grp = IQS7222_REG_GRP_FILT, 799 .reg_offset = 1, 800 .reg_shift = 4, 801 .reg_width = 4, 802 .label = "low-power mode long-term average fast beta", 803 }, 804 { 805 .name = "azoteq,lta-fast-beta-np", 806 .reg_grp = IQS7222_REG_GRP_FILT, 807 .reg_offset = 1, 808 .reg_shift = 0, 809 .reg_width = 4, 810 .label = "normal-power mode long-term average fast beta", 811 }, 812 { 813 .name = "azoteq,lower-cal", 814 .reg_grp = IQS7222_REG_GRP_SLDR, 815 .reg_offset = 0, 816 .reg_shift = 8, 817 .reg_width = 8, 818 .label = "lower calibration", 819 }, 820 { 821 .name = "azoteq,static-beta", 822 .reg_grp = IQS7222_REG_GRP_SLDR, 823 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 824 .reg_offset = 0, 825 .reg_shift = 6, 826 .reg_width = 1, 827 }, 828 { 829 .name = "azoteq,bottom-beta", 830 .reg_grp = IQS7222_REG_GRP_SLDR, 831 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 832 .reg_offset = 0, 833 .reg_shift = 3, 834 .reg_width = 3, 835 .label = "bottom beta", 836 }, 837 { 838 .name = "azoteq,static-beta", 839 .reg_grp = IQS7222_REG_GRP_SLDR, 840 .reg_key = IQS7222_REG_KEY_WHEEL, 841 .reg_offset = 0, 842 .reg_shift = 7, 843 .reg_width = 1, 844 }, 845 { 846 .name = "azoteq,bottom-beta", 847 .reg_grp = IQS7222_REG_GRP_SLDR, 848 .reg_key = IQS7222_REG_KEY_WHEEL, 849 .reg_offset = 0, 850 .reg_shift = 4, 851 .reg_width = 3, 852 .label = "bottom beta", 853 }, 854 { 855 .name = "azoteq,bottom-speed", 856 .reg_grp = IQS7222_REG_GRP_SLDR, 857 .reg_offset = 1, 858 .reg_shift = 8, 859 .reg_width = 8, 860 .label = "bottom speed", 861 }, 862 { 863 .name = "azoteq,upper-cal", 864 .reg_grp = IQS7222_REG_GRP_SLDR, 865 .reg_offset = 1, 866 .reg_shift = 0, 867 .reg_width = 8, 868 .label = "upper calibration", 869 }, 870 { 871 .name = "azoteq,gesture-max-ms", 872 .reg_grp = IQS7222_REG_GRP_SLDR, 873 .reg_key = IQS7222_REG_KEY_TAP, 874 .reg_offset = 9, 875 .reg_shift = 8, 876 .reg_width = 8, 877 .val_pitch = 4, 878 .label = "maximum gesture time", 879 }, 880 { 881 .name = "azoteq,gesture-min-ms", 882 .reg_grp = IQS7222_REG_GRP_SLDR, 883 .reg_key = IQS7222_REG_KEY_TAP, 884 .reg_offset = 9, 885 .reg_shift = 3, 886 .reg_width = 5, 887 .val_pitch = 4, 888 .label = "minimum gesture time", 889 }, 890 { 891 .name = "azoteq,gesture-dist", 892 .reg_grp = IQS7222_REG_GRP_SLDR, 893 .reg_key = IQS7222_REG_KEY_AXIAL, 894 .reg_offset = 10, 895 .reg_shift = 8, 896 .reg_width = 8, 897 .val_pitch = 16, 898 .label = "gesture distance", 899 }, 900 { 901 .name = "azoteq,gesture-max-ms", 902 .reg_grp = IQS7222_REG_GRP_SLDR, 903 .reg_key = IQS7222_REG_KEY_AXIAL, 904 .reg_offset = 10, 905 .reg_shift = 0, 906 .reg_width = 8, 907 .val_pitch = 4, 908 .label = "maximum gesture time", 909 }, 910 { 911 .name = "drive-open-drain", 912 .reg_grp = IQS7222_REG_GRP_GPIO, 913 .reg_offset = 0, 914 .reg_shift = 1, 915 .reg_width = 1, 916 }, 917 { 918 .name = "azoteq,timeout-ati-ms", 919 .reg_grp = IQS7222_REG_GRP_SYS, 920 .reg_offset = 1, 921 .reg_shift = 0, 922 .reg_width = 16, 923 .val_pitch = 500, 924 .label = "ATI error timeout", 925 }, 926 { 927 .name = "azoteq,rate-ati-ms", 928 .reg_grp = IQS7222_REG_GRP_SYS, 929 .reg_offset = 2, 930 .reg_shift = 0, 931 .reg_width = 16, 932 .label = "ATI report rate", 933 }, 934 { 935 .name = "azoteq,timeout-np-ms", 936 .reg_grp = IQS7222_REG_GRP_SYS, 937 .reg_offset = 3, 938 .reg_shift = 0, 939 .reg_width = 16, 940 .label = "normal-power mode timeout", 941 }, 942 { 943 .name = "azoteq,rate-np-ms", 944 .reg_grp = IQS7222_REG_GRP_SYS, 945 .reg_offset = 4, 946 .reg_shift = 0, 947 .reg_width = 16, 948 .val_max = 3000, 949 .label = "normal-power mode report rate", 950 }, 951 { 952 .name = "azoteq,timeout-lp-ms", 953 .reg_grp = IQS7222_REG_GRP_SYS, 954 .reg_offset = 5, 955 .reg_shift = 0, 956 .reg_width = 16, 957 .label = "low-power mode timeout", 958 }, 959 { 960 .name = "azoteq,rate-lp-ms", 961 .reg_grp = IQS7222_REG_GRP_SYS, 962 .reg_offset = 6, 963 .reg_shift = 0, 964 .reg_width = 16, 965 .val_max = 3000, 966 .label = "low-power mode report rate", 967 }, 968 { 969 .name = "azoteq,timeout-ulp-ms", 970 .reg_grp = IQS7222_REG_GRP_SYS, 971 .reg_offset = 7, 972 .reg_shift = 0, 973 .reg_width = 16, 974 .label = "ultra-low-power mode timeout", 975 }, 976 { 977 .name = "azoteq,rate-ulp-ms", 978 .reg_grp = IQS7222_REG_GRP_SYS, 979 .reg_offset = 8, 980 .reg_shift = 0, 981 .reg_width = 16, 982 .val_max = 3000, 983 .label = "ultra-low-power mode report rate", 984 }, 985 }; 986 987 struct iqs7222_private { 988 const struct iqs7222_dev_desc *dev_desc; 989 struct gpio_desc *reset_gpio; 990 struct gpio_desc *irq_gpio; 991 struct i2c_client *client; 992 struct input_dev *keypad; 993 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 994 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 995 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)]; 996 unsigned int sl_axis[IQS7222_MAX_SLDR]; 997 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE]; 998 u16 glbl_setup[IQS7222_MAX_COLS_GLBL]; 999 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN]; 1000 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN]; 1001 u16 filt_setup[IQS7222_MAX_COLS_FILT]; 1002 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR]; 1003 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO]; 1004 u16 sys_setup[IQS7222_MAX_COLS_SYS]; 1005 }; 1006 1007 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222, 1008 enum iqs7222_reg_grp_id reg_grp, int row) 1009 { 1010 switch (reg_grp) { 1011 case IQS7222_REG_GRP_CYCLE: 1012 return iqs7222->cycle_setup[row]; 1013 1014 case IQS7222_REG_GRP_GLBL: 1015 return iqs7222->glbl_setup; 1016 1017 case IQS7222_REG_GRP_BTN: 1018 return iqs7222->btn_setup[row]; 1019 1020 case IQS7222_REG_GRP_CHAN: 1021 return iqs7222->chan_setup[row]; 1022 1023 case IQS7222_REG_GRP_FILT: 1024 return iqs7222->filt_setup; 1025 1026 case IQS7222_REG_GRP_SLDR: 1027 return iqs7222->sldr_setup[row]; 1028 1029 case IQS7222_REG_GRP_GPIO: 1030 return iqs7222->gpio_setup[row]; 1031 1032 case IQS7222_REG_GRP_SYS: 1033 return iqs7222->sys_setup; 1034 1035 default: 1036 return NULL; 1037 } 1038 } 1039 1040 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms) 1041 { 1042 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms); 1043 int ret; 1044 1045 do { 1046 usleep_range(1000, 1100); 1047 1048 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1049 if (ret < 0) 1050 return ret; 1051 else if (ret > 0) 1052 return 0; 1053 } while (ktime_compare(ktime_get(), irq_timeout) < 0); 1054 1055 return -EBUSY; 1056 } 1057 1058 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222) 1059 { 1060 struct i2c_client *client = iqs7222->client; 1061 int error; 1062 1063 if (!iqs7222->reset_gpio) 1064 return 0; 1065 1066 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1); 1067 usleep_range(1000, 1100); 1068 1069 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); 1070 1071 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS); 1072 if (error) 1073 dev_err(&client->dev, "Failed to reset device: %d\n", error); 1074 1075 return error; 1076 } 1077 1078 static int iqs7222_force_comms(struct iqs7222_private *iqs7222) 1079 { 1080 u8 msg_buf[] = { 0xFF, }; 1081 int ret; 1082 1083 /* 1084 * The device cannot communicate until it asserts its interrupt (RDY) 1085 * pin. Attempts to do so while RDY is deasserted return an ACK; how- 1086 * ever all write data is ignored, and all read data returns 0xEE. 1087 * 1088 * Unsolicited communication must be preceded by a special force com- 1089 * munication command, after which the device eventually asserts its 1090 * RDY pin and agrees to communicate. 1091 * 1092 * Regardless of whether communication is forced or the result of an 1093 * interrupt, the device automatically deasserts its RDY pin once it 1094 * detects an I2C stop condition, or a timeout expires. 1095 */ 1096 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1097 if (ret < 0) 1098 return ret; 1099 else if (ret > 0) 1100 return 0; 1101 1102 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf)); 1103 if (ret < (int)sizeof(msg_buf)) { 1104 if (ret >= 0) 1105 ret = -EIO; 1106 1107 /* 1108 * The datasheet states that the host must wait to retry any 1109 * failed attempt to communicate over I2C. 1110 */ 1111 msleep(IQS7222_COMMS_RETRY_MS); 1112 return ret; 1113 } 1114 1115 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS); 1116 } 1117 1118 static int iqs7222_read_burst(struct iqs7222_private *iqs7222, 1119 u16 reg, void *val, u16 num_val) 1120 { 1121 u8 reg_buf[sizeof(__be16)]; 1122 int ret, i; 1123 struct i2c_client *client = iqs7222->client; 1124 struct i2c_msg msg[] = { 1125 { 1126 .addr = client->addr, 1127 .flags = 0, 1128 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8), 1129 .buf = reg_buf, 1130 }, 1131 { 1132 .addr = client->addr, 1133 .flags = I2C_M_RD, 1134 .len = num_val * sizeof(__le16), 1135 .buf = (u8 *)val, 1136 }, 1137 }; 1138 1139 if (reg > U8_MAX) 1140 put_unaligned_be16(reg, reg_buf); 1141 else 1142 *reg_buf = (u8)reg; 1143 1144 /* 1145 * The following loop protects against an edge case in which the RDY 1146 * pin is automatically deasserted just as the read is initiated. In 1147 * that case, the read must be retried using forced communication. 1148 */ 1149 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1150 ret = iqs7222_force_comms(iqs7222); 1151 if (ret < 0) 1152 continue; 1153 1154 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); 1155 if (ret < (int)ARRAY_SIZE(msg)) { 1156 if (ret >= 0) 1157 ret = -EIO; 1158 1159 msleep(IQS7222_COMMS_RETRY_MS); 1160 continue; 1161 } 1162 1163 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) { 1164 ret = -ENODATA; 1165 continue; 1166 } 1167 1168 ret = 0; 1169 break; 1170 } 1171 1172 /* 1173 * The following delay ensures the device has deasserted the RDY pin 1174 * following the I2C stop condition. 1175 */ 1176 usleep_range(50, 100); 1177 1178 if (ret < 0) 1179 dev_err(&client->dev, 1180 "Failed to read from address 0x%04X: %d\n", reg, ret); 1181 1182 return ret; 1183 } 1184 1185 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val) 1186 { 1187 __le16 val_buf; 1188 int error; 1189 1190 error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1); 1191 if (error) 1192 return error; 1193 1194 *val = le16_to_cpu(val_buf); 1195 1196 return 0; 1197 } 1198 1199 static int iqs7222_write_burst(struct iqs7222_private *iqs7222, 1200 u16 reg, const void *val, u16 num_val) 1201 { 1202 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8); 1203 int val_len = num_val * sizeof(__le16); 1204 int msg_len = reg_len + val_len; 1205 int ret, i; 1206 struct i2c_client *client = iqs7222->client; 1207 u8 *msg_buf; 1208 1209 msg_buf = kzalloc(msg_len, GFP_KERNEL); 1210 if (!msg_buf) 1211 return -ENOMEM; 1212 1213 if (reg > U8_MAX) 1214 put_unaligned_be16(reg, msg_buf); 1215 else 1216 *msg_buf = (u8)reg; 1217 1218 memcpy(msg_buf + reg_len, val, val_len); 1219 1220 /* 1221 * The following loop protects against an edge case in which the RDY 1222 * pin is automatically asserted just before the force communication 1223 * command is sent. 1224 * 1225 * In that case, the subsequent I2C stop condition tricks the device 1226 * into preemptively deasserting the RDY pin and the command must be 1227 * sent again. 1228 */ 1229 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1230 ret = iqs7222_force_comms(iqs7222); 1231 if (ret < 0) 1232 continue; 1233 1234 ret = i2c_master_send(client, msg_buf, msg_len); 1235 if (ret < msg_len) { 1236 if (ret >= 0) 1237 ret = -EIO; 1238 1239 msleep(IQS7222_COMMS_RETRY_MS); 1240 continue; 1241 } 1242 1243 ret = 0; 1244 break; 1245 } 1246 1247 kfree(msg_buf); 1248 1249 usleep_range(50, 100); 1250 1251 if (ret < 0) 1252 dev_err(&client->dev, 1253 "Failed to write to address 0x%04X: %d\n", reg, ret); 1254 1255 return ret; 1256 } 1257 1258 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val) 1259 { 1260 __le16 val_buf = cpu_to_le16(val); 1261 1262 return iqs7222_write_burst(iqs7222, reg, &val_buf, 1); 1263 } 1264 1265 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222) 1266 { 1267 struct i2c_client *client = iqs7222->client; 1268 ktime_t ati_timeout; 1269 u16 sys_status = 0; 1270 u16 sys_setup; 1271 int error, i; 1272 1273 /* 1274 * The reserved fields of the system setup register may have changed 1275 * as a result of other registers having been written. As such, read 1276 * the register's latest value to avoid unexpected behavior when the 1277 * register is written in the loop that follows. 1278 */ 1279 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup); 1280 if (error) 1281 return error; 1282 1283 sys_setup &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; 1284 sys_setup &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; 1285 1286 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1287 /* 1288 * Trigger ATI from streaming and normal-power modes so that 1289 * the RDY pin continues to be asserted during ATI. 1290 */ 1291 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1292 sys_setup | 1293 IQS7222_SYS_SETUP_REDO_ATI); 1294 if (error) 1295 return error; 1296 1297 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS); 1298 1299 do { 1300 error = iqs7222_irq_poll(iqs7222, 1301 IQS7222_COMMS_TIMEOUT_MS); 1302 if (error) 1303 continue; 1304 1305 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS, 1306 &sys_status); 1307 if (error) 1308 return error; 1309 1310 if (sys_status & IQS7222_SYS_STATUS_RESET) 1311 return 0; 1312 1313 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR) 1314 break; 1315 1316 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE) 1317 continue; 1318 1319 /* 1320 * Use stream-in-touch mode if either slider reports 1321 * absolute position. 1322 */ 1323 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit) 1324 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH 1325 : IQS7222_SYS_SETUP_INTF_MODE_EVENT; 1326 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO; 1327 1328 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1329 sys_setup); 1330 } while (ktime_compare(ktime_get(), ati_timeout) < 0); 1331 1332 dev_err(&client->dev, 1333 "ATI attempt %d of %d failed with status 0x%02X, %s\n", 1334 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status, 1335 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping"); 1336 } 1337 1338 return -ETIMEDOUT; 1339 } 1340 1341 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir) 1342 { 1343 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1344 int comms_offset = dev_desc->comms_offset; 1345 int error, i, j, k; 1346 1347 /* 1348 * Acknowledge reset before writing any registers in case the device 1349 * suffers a spurious reset during initialization. Because this step 1350 * may change the reserved fields of the second filter beta register, 1351 * its cache must be updated. 1352 * 1353 * Writing the second filter beta register, in turn, may clobber the 1354 * system status register. As such, the filter beta register pair is 1355 * written first to protect against this hazard. 1356 */ 1357 if (dir == WRITE) { 1358 u16 reg = dev_desc->reg_grps[IQS7222_REG_GRP_FILT].base + 1; 1359 u16 filt_setup; 1360 1361 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1362 iqs7222->sys_setup[0] | 1363 IQS7222_SYS_SETUP_ACK_RESET); 1364 if (error) 1365 return error; 1366 1367 error = iqs7222_read_word(iqs7222, reg, &filt_setup); 1368 if (error) 1369 return error; 1370 1371 iqs7222->filt_setup[1] &= GENMASK(7, 0); 1372 iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0)); 1373 } 1374 1375 /* 1376 * Take advantage of the stop-bit disable function, if available, to 1377 * save the trouble of having to reopen a communication window after 1378 * each burst read or write. 1379 */ 1380 if (comms_offset) { 1381 u16 comms_setup; 1382 1383 error = iqs7222_read_word(iqs7222, 1384 IQS7222_SYS_SETUP + comms_offset, 1385 &comms_setup); 1386 if (error) 1387 return error; 1388 1389 error = iqs7222_write_word(iqs7222, 1390 IQS7222_SYS_SETUP + comms_offset, 1391 comms_setup | IQS7222_COMMS_HOLD); 1392 if (error) 1393 return error; 1394 } 1395 1396 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { 1397 int num_row = dev_desc->reg_grps[i].num_row; 1398 int num_col = dev_desc->reg_grps[i].num_col; 1399 u16 reg = dev_desc->reg_grps[i].base; 1400 __le16 *val_buf; 1401 u16 *val; 1402 1403 if (!num_col) 1404 continue; 1405 1406 val = iqs7222_setup(iqs7222, i, 0); 1407 if (!val) 1408 continue; 1409 1410 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL); 1411 if (!val_buf) 1412 return -ENOMEM; 1413 1414 for (j = 0; j < num_row; j++) { 1415 switch (dir) { 1416 case READ: 1417 error = iqs7222_read_burst(iqs7222, reg, 1418 val_buf, num_col); 1419 for (k = 0; k < num_col; k++) 1420 val[k] = le16_to_cpu(val_buf[k]); 1421 break; 1422 1423 case WRITE: 1424 for (k = 0; k < num_col; k++) 1425 val_buf[k] = cpu_to_le16(val[k]); 1426 error = iqs7222_write_burst(iqs7222, reg, 1427 val_buf, num_col); 1428 break; 1429 1430 default: 1431 error = -EINVAL; 1432 } 1433 1434 if (error) 1435 break; 1436 1437 reg += IQS7222_REG_OFFSET; 1438 val += iqs7222_max_cols[i]; 1439 } 1440 1441 kfree(val_buf); 1442 1443 if (error) 1444 return error; 1445 } 1446 1447 if (comms_offset) { 1448 u16 comms_setup; 1449 1450 error = iqs7222_read_word(iqs7222, 1451 IQS7222_SYS_SETUP + comms_offset, 1452 &comms_setup); 1453 if (error) 1454 return error; 1455 1456 error = iqs7222_write_word(iqs7222, 1457 IQS7222_SYS_SETUP + comms_offset, 1458 comms_setup & ~IQS7222_COMMS_HOLD); 1459 if (error) 1460 return error; 1461 } 1462 1463 if (dir == READ) 1464 return 0; 1465 1466 return iqs7222_ati_trigger(iqs7222); 1467 } 1468 1469 static int iqs7222_dev_info(struct iqs7222_private *iqs7222) 1470 { 1471 struct i2c_client *client = iqs7222->client; 1472 bool prod_num_valid = false; 1473 __le16 dev_id[3]; 1474 int error, i; 1475 1476 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id, 1477 ARRAY_SIZE(dev_id)); 1478 if (error) 1479 return error; 1480 1481 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { 1482 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) 1483 continue; 1484 1485 prod_num_valid = true; 1486 1487 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major) 1488 continue; 1489 1490 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor) 1491 continue; 1492 1493 iqs7222->dev_desc = &iqs7222_devs[i]; 1494 return 0; 1495 } 1496 1497 if (prod_num_valid) 1498 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n", 1499 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2])); 1500 else 1501 dev_err(&client->dev, "Unrecognized product number: %u\n", 1502 le16_to_cpu(dev_id[0])); 1503 1504 return -EINVAL; 1505 } 1506 1507 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222, 1508 struct fwnode_handle *child_node, 1509 int child_enable, u16 child_link) 1510 { 1511 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1512 struct i2c_client *client = iqs7222->client; 1513 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row; 1514 int error, count, i; 1515 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)]; 1516 1517 if (!num_gpio) 1518 return 0; 1519 1520 if (!fwnode_property_present(child_node, "azoteq,gpio-select")) 1521 return 0; 1522 1523 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select"); 1524 if (count > num_gpio) { 1525 dev_err(&client->dev, "Invalid number of %s GPIOs\n", 1526 fwnode_get_name(child_node)); 1527 return -EINVAL; 1528 } else if (count < 0) { 1529 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n", 1530 fwnode_get_name(child_node), count); 1531 return count; 1532 } 1533 1534 error = fwnode_property_read_u32_array(child_node, 1535 "azoteq,gpio-select", 1536 gpio_sel, count); 1537 if (error) { 1538 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n", 1539 fwnode_get_name(child_node), error); 1540 return error; 1541 } 1542 1543 for (i = 0; i < count; i++) { 1544 u16 *gpio_setup; 1545 1546 if (gpio_sel[i] >= num_gpio) { 1547 dev_err(&client->dev, "Invalid %s GPIO: %u\n", 1548 fwnode_get_name(child_node), gpio_sel[i]); 1549 return -EINVAL; 1550 } 1551 1552 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]]; 1553 1554 if (gpio_setup[2] && child_link != gpio_setup[2]) { 1555 dev_err(&client->dev, 1556 "Conflicting GPIO %u event types\n", 1557 gpio_sel[i]); 1558 return -EINVAL; 1559 } 1560 1561 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; 1562 gpio_setup[1] |= child_enable; 1563 gpio_setup[2] = child_link; 1564 } 1565 1566 return 0; 1567 } 1568 1569 static int iqs7222_parse_props(struct iqs7222_private *iqs7222, 1570 struct fwnode_handle *reg_grp_node, 1571 int reg_grp_index, 1572 enum iqs7222_reg_grp_id reg_grp, 1573 enum iqs7222_reg_key_id reg_key) 1574 { 1575 u16 *setup = iqs7222_setup(iqs7222, reg_grp, reg_grp_index); 1576 struct i2c_client *client = iqs7222->client; 1577 int i; 1578 1579 if (!setup) 1580 return 0; 1581 1582 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { 1583 const char *name = iqs7222_props[i].name; 1584 int reg_offset = iqs7222_props[i].reg_offset; 1585 int reg_shift = iqs7222_props[i].reg_shift; 1586 int reg_width = iqs7222_props[i].reg_width; 1587 int val_pitch = iqs7222_props[i].val_pitch ? : 1; 1588 int val_min = iqs7222_props[i].val_min; 1589 int val_max = iqs7222_props[i].val_max; 1590 bool invert = iqs7222_props[i].invert; 1591 const char *label = iqs7222_props[i].label ? : name; 1592 unsigned int val; 1593 int error; 1594 1595 if (iqs7222_props[i].reg_grp != reg_grp || 1596 iqs7222_props[i].reg_key != reg_key) 1597 continue; 1598 1599 /* 1600 * Boolean register fields are one bit wide; they are forcibly 1601 * reset to provide a means to undo changes by a bootloader if 1602 * necessary. 1603 * 1604 * Scalar fields, on the other hand, are left untouched unless 1605 * their corresponding properties are present. 1606 */ 1607 if (reg_width == 1) { 1608 if (invert) 1609 setup[reg_offset] |= BIT(reg_shift); 1610 else 1611 setup[reg_offset] &= ~BIT(reg_shift); 1612 } 1613 1614 if (!fwnode_property_present(reg_grp_node, name)) 1615 continue; 1616 1617 if (reg_width == 1) { 1618 if (invert) 1619 setup[reg_offset] &= ~BIT(reg_shift); 1620 else 1621 setup[reg_offset] |= BIT(reg_shift); 1622 1623 continue; 1624 } 1625 1626 error = fwnode_property_read_u32(reg_grp_node, name, &val); 1627 if (error) { 1628 dev_err(&client->dev, "Failed to read %s %s: %d\n", 1629 fwnode_get_name(reg_grp_node), label, error); 1630 return error; 1631 } 1632 1633 if (!val_max) 1634 val_max = GENMASK(reg_width - 1, 0) * val_pitch; 1635 1636 if (val < val_min || val > val_max) { 1637 dev_err(&client->dev, "Invalid %s %s: %u\n", 1638 fwnode_get_name(reg_grp_node), label, val); 1639 return -EINVAL; 1640 } 1641 1642 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, 1643 reg_shift); 1644 setup[reg_offset] |= (val / val_pitch << reg_shift); 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int iqs7222_parse_event(struct iqs7222_private *iqs7222, 1651 struct fwnode_handle *event_node, 1652 int reg_grp_index, 1653 enum iqs7222_reg_grp_id reg_grp, 1654 enum iqs7222_reg_key_id reg_key, 1655 u16 event_enable, u16 event_link, 1656 unsigned int *event_type, 1657 unsigned int *event_code) 1658 { 1659 struct i2c_client *client = iqs7222->client; 1660 int error; 1661 1662 error = iqs7222_parse_props(iqs7222, event_node, reg_grp_index, 1663 reg_grp, reg_key); 1664 if (error) 1665 return error; 1666 1667 error = iqs7222_gpio_select(iqs7222, event_node, event_enable, 1668 event_link); 1669 if (error) 1670 return error; 1671 1672 error = fwnode_property_read_u32(event_node, "linux,code", event_code); 1673 if (error == -EINVAL) { 1674 return 0; 1675 } else if (error) { 1676 dev_err(&client->dev, "Failed to read %s code: %d\n", 1677 fwnode_get_name(event_node), error); 1678 return error; 1679 } 1680 1681 if (!event_type) { 1682 input_set_capability(iqs7222->keypad, EV_KEY, *event_code); 1683 return 0; 1684 } 1685 1686 error = fwnode_property_read_u32(event_node, "linux,input-type", 1687 event_type); 1688 if (error == -EINVAL) { 1689 *event_type = EV_KEY; 1690 } else if (error) { 1691 dev_err(&client->dev, "Failed to read %s input type: %d\n", 1692 fwnode_get_name(event_node), error); 1693 return error; 1694 } else if (*event_type != EV_KEY && *event_type != EV_SW) { 1695 dev_err(&client->dev, "Invalid %s input type: %d\n", 1696 fwnode_get_name(event_node), *event_type); 1697 return -EINVAL; 1698 } 1699 1700 input_set_capability(iqs7222->keypad, *event_type, *event_code); 1701 1702 return 0; 1703 } 1704 1705 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222, 1706 struct fwnode_handle *cycle_node, int cycle_index) 1707 { 1708 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index]; 1709 struct i2c_client *client = iqs7222->client; 1710 unsigned int pins[9]; 1711 int error, count, i; 1712 1713 /* 1714 * Each channel shares a cycle with one other channel; the mapping of 1715 * channels to cycles is fixed. Properties defined for a cycle impact 1716 * both channels tied to the cycle. 1717 * 1718 * Unlike channels which are restricted to a select range of CRx pins 1719 * based on channel number, any cycle can claim any of the device's 9 1720 * CTx pins (CTx0-8). 1721 */ 1722 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable")) 1723 return 0; 1724 1725 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable"); 1726 if (count < 0) { 1727 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n", 1728 fwnode_get_name(cycle_node), count); 1729 return count; 1730 } else if (count > ARRAY_SIZE(pins)) { 1731 dev_err(&client->dev, "Invalid number of %s CTx pins\n", 1732 fwnode_get_name(cycle_node)); 1733 return -EINVAL; 1734 } 1735 1736 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable", 1737 pins, count); 1738 if (error) { 1739 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n", 1740 fwnode_get_name(cycle_node), error); 1741 return error; 1742 } 1743 1744 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7); 1745 1746 for (i = 0; i < count; i++) { 1747 if (pins[i] > 8) { 1748 dev_err(&client->dev, "Invalid %s CTx pin: %u\n", 1749 fwnode_get_name(cycle_node), pins[i]); 1750 return -EINVAL; 1751 } 1752 1753 cycle_setup[1] |= BIT(pins[i] + 7); 1754 } 1755 1756 return 0; 1757 } 1758 1759 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222, 1760 struct fwnode_handle *chan_node, int chan_index) 1761 { 1762 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1763 struct i2c_client *client = iqs7222->client; 1764 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 1765 int ext_chan = rounddown(num_chan, 10); 1766 int error, i; 1767 u16 *chan_setup = iqs7222->chan_setup[chan_index]; 1768 u16 *sys_setup = iqs7222->sys_setup; 1769 unsigned int val; 1770 1771 if (dev_desc->allow_offset && 1772 fwnode_property_present(chan_node, "azoteq,ulp-allow")) 1773 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index); 1774 1775 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; 1776 1777 /* 1778 * The reference channel function allows for differential measurements 1779 * and is only available in the case of IQS7222A or IQS7222C. 1780 */ 1781 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 && 1782 fwnode_property_present(chan_node, "azoteq,ref-select")) { 1783 u16 *ref_setup; 1784 1785 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select", 1786 &val); 1787 if (error) { 1788 dev_err(&client->dev, 1789 "Failed to read %s reference channel: %d\n", 1790 fwnode_get_name(chan_node), error); 1791 return error; 1792 } 1793 1794 if (val >= ext_chan) { 1795 dev_err(&client->dev, 1796 "Invalid %s reference channel: %u\n", 1797 fwnode_get_name(chan_node), val); 1798 return -EINVAL; 1799 } 1800 1801 ref_setup = iqs7222->chan_setup[val]; 1802 1803 /* 1804 * Configure the current channel as a follower of the selected 1805 * reference channel. 1806 */ 1807 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; 1808 chan_setup[4] = val * 42 + 1048; 1809 1810 error = fwnode_property_read_u32(chan_node, "azoteq,ref-weight", 1811 &val); 1812 if (!error) { 1813 if (val > U16_MAX) { 1814 dev_err(&client->dev, 1815 "Invalid %s reference weight: %u\n", 1816 fwnode_get_name(chan_node), val); 1817 return -EINVAL; 1818 } 1819 1820 chan_setup[5] = val; 1821 } else if (error != -EINVAL) { 1822 dev_err(&client->dev, 1823 "Failed to read %s reference weight: %d\n", 1824 fwnode_get_name(chan_node), error); 1825 return error; 1826 } 1827 1828 /* 1829 * Configure the selected channel as a reference channel which 1830 * serves the current channel. 1831 */ 1832 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; 1833 ref_setup[5] |= BIT(chan_index); 1834 1835 ref_setup[4] = dev_desc->touch_link; 1836 if (fwnode_property_present(chan_node, "azoteq,use-prox")) 1837 ref_setup[4] -= 2; 1838 } 1839 1840 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) { 1841 /* 1842 * Each channel can claim up to 4 CRx pins. The first half of 1843 * the channels can use CRx0-3, while the second half can use 1844 * CRx4-7. 1845 */ 1846 unsigned int pins[4]; 1847 int count; 1848 1849 count = fwnode_property_count_u32(chan_node, 1850 "azoteq,rx-enable"); 1851 if (count < 0) { 1852 dev_err(&client->dev, 1853 "Failed to count %s CRx pins: %d\n", 1854 fwnode_get_name(chan_node), count); 1855 return count; 1856 } else if (count > ARRAY_SIZE(pins)) { 1857 dev_err(&client->dev, 1858 "Invalid number of %s CRx pins\n", 1859 fwnode_get_name(chan_node)); 1860 return -EINVAL; 1861 } 1862 1863 error = fwnode_property_read_u32_array(chan_node, 1864 "azoteq,rx-enable", 1865 pins, count); 1866 if (error) { 1867 dev_err(&client->dev, 1868 "Failed to read %s CRx pins: %d\n", 1869 fwnode_get_name(chan_node), error); 1870 return error; 1871 } 1872 1873 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); 1874 1875 for (i = 0; i < count; i++) { 1876 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; 1877 1878 if (pins[i] < min_crx || pins[i] > min_crx + 3) { 1879 dev_err(&client->dev, 1880 "Invalid %s CRx pin: %u\n", 1881 fwnode_get_name(chan_node), pins[i]); 1882 return -EINVAL; 1883 } 1884 1885 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); 1886 } 1887 } 1888 1889 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { 1890 const char *event_name = iqs7222_kp_events[i].name; 1891 u16 event_enable = iqs7222_kp_events[i].enable; 1892 struct fwnode_handle *event_node; 1893 1894 event_node = fwnode_get_named_child_node(chan_node, event_name); 1895 if (!event_node) 1896 continue; 1897 1898 error = fwnode_property_read_u32(event_node, 1899 "azoteq,timeout-press-ms", 1900 &val); 1901 if (!error) { 1902 /* 1903 * The IQS7222B employs a global pair of press timeout 1904 * registers as opposed to channel-specific registers. 1905 */ 1906 u16 *setup = dev_desc->reg_grps 1907 [IQS7222_REG_GRP_BTN].num_col > 2 ? 1908 &iqs7222->btn_setup[chan_index][2] : 1909 &sys_setup[9]; 1910 1911 if (val > U8_MAX * 500) { 1912 dev_err(&client->dev, 1913 "Invalid %s press timeout: %u\n", 1914 fwnode_get_name(event_node), val); 1915 fwnode_handle_put(event_node); 1916 return -EINVAL; 1917 } 1918 1919 *setup &= ~(U8_MAX << i * 8); 1920 *setup |= (val / 500 << i * 8); 1921 } else if (error != -EINVAL) { 1922 dev_err(&client->dev, 1923 "Failed to read %s press timeout: %d\n", 1924 fwnode_get_name(event_node), error); 1925 fwnode_handle_put(event_node); 1926 return error; 1927 } 1928 1929 error = iqs7222_parse_event(iqs7222, event_node, chan_index, 1930 IQS7222_REG_GRP_BTN, 1931 iqs7222_kp_events[i].reg_key, 1932 BIT(chan_index), 1933 dev_desc->touch_link - (i ? 0 : 2), 1934 &iqs7222->kp_type[chan_index][i], 1935 &iqs7222->kp_code[chan_index][i]); 1936 fwnode_handle_put(event_node); 1937 if (error) 1938 return error; 1939 1940 if (!dev_desc->event_offset) 1941 continue; 1942 1943 sys_setup[dev_desc->event_offset] |= event_enable; 1944 } 1945 1946 /* 1947 * The following call handles a special pair of properties that apply 1948 * to a channel node, but reside within the button (event) group. 1949 */ 1950 return iqs7222_parse_props(iqs7222, chan_node, chan_index, 1951 IQS7222_REG_GRP_BTN, 1952 IQS7222_REG_KEY_DEBOUNCE); 1953 } 1954 1955 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222, 1956 struct fwnode_handle *sldr_node, int sldr_index) 1957 { 1958 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1959 struct i2c_client *client = iqs7222->client; 1960 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 1961 int ext_chan = rounddown(num_chan, 10); 1962 int count, error, reg_offset, i; 1963 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset]; 1964 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index]; 1965 unsigned int chan_sel[4], val; 1966 1967 /* 1968 * Each slider can be spread across 3 to 4 channels. It is possible to 1969 * select only 2 channels, but doing so prevents the slider from using 1970 * the specified resolution. 1971 */ 1972 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select"); 1973 if (count < 0) { 1974 dev_err(&client->dev, "Failed to count %s channels: %d\n", 1975 fwnode_get_name(sldr_node), count); 1976 return count; 1977 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) { 1978 dev_err(&client->dev, "Invalid number of %s channels\n", 1979 fwnode_get_name(sldr_node)); 1980 return -EINVAL; 1981 } 1982 1983 error = fwnode_property_read_u32_array(sldr_node, 1984 "azoteq,channel-select", 1985 chan_sel, count); 1986 if (error) { 1987 dev_err(&client->dev, "Failed to read %s channels: %d\n", 1988 fwnode_get_name(sldr_node), error); 1989 return error; 1990 } 1991 1992 /* 1993 * Resolution and top speed, if small enough, are packed into a single 1994 * register. Otherwise, each occupies its own register and the rest of 1995 * the slider-related register addresses are offset by one. 1996 */ 1997 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; 1998 1999 sldr_setup[0] |= count; 2000 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0); 2001 2002 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { 2003 sldr_setup[5 + reg_offset + i] = 0; 2004 if (i >= count) 2005 continue; 2006 2007 if (chan_sel[i] >= ext_chan) { 2008 dev_err(&client->dev, "Invalid %s channel: %u\n", 2009 fwnode_get_name(sldr_node), chan_sel[i]); 2010 return -EINVAL; 2011 } 2012 2013 /* 2014 * The following fields indicate which channels participate in 2015 * the slider, as well as each channel's relative placement. 2016 */ 2017 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]); 2018 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080; 2019 } 2020 2021 sldr_setup[4 + reg_offset] = dev_desc->touch_link; 2022 if (fwnode_property_present(sldr_node, "azoteq,use-prox")) 2023 sldr_setup[4 + reg_offset] -= 2; 2024 2025 error = fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val); 2026 if (!error) { 2027 if (!val || val > dev_desc->sldr_res) { 2028 dev_err(&client->dev, "Invalid %s size: %u\n", 2029 fwnode_get_name(sldr_node), val); 2030 return -EINVAL; 2031 } 2032 2033 if (reg_offset) { 2034 sldr_setup[3] = val; 2035 } else { 2036 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK; 2037 sldr_setup[2] |= (val / 16 << 2038 IQS7222_SLDR_SETUP_2_RES_SHIFT); 2039 } 2040 } else if (error != -EINVAL) { 2041 dev_err(&client->dev, "Failed to read %s size: %d\n", 2042 fwnode_get_name(sldr_node), error); 2043 return error; 2044 } 2045 2046 error = fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val); 2047 if (!error) { 2048 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) { 2049 dev_err(&client->dev, "Invalid %s top speed: %u\n", 2050 fwnode_get_name(sldr_node), val); 2051 return -EINVAL; 2052 } 2053 2054 if (reg_offset) { 2055 sldr_setup[2] = val; 2056 } else { 2057 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK; 2058 sldr_setup[2] |= (val / 4); 2059 } 2060 } else if (error != -EINVAL) { 2061 dev_err(&client->dev, "Failed to read %s top speed: %d\n", 2062 fwnode_get_name(sldr_node), error); 2063 return error; 2064 } 2065 2066 error = fwnode_property_read_u32(sldr_node, "linux,axis", &val); 2067 if (!error) { 2068 u16 sldr_max = sldr_setup[3] - 1; 2069 2070 if (!reg_offset) { 2071 sldr_max = sldr_setup[2]; 2072 2073 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK; 2074 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT; 2075 2076 sldr_max = sldr_max * 16 - 1; 2077 } 2078 2079 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); 2080 iqs7222->sl_axis[sldr_index] = val; 2081 } else if (error != -EINVAL) { 2082 dev_err(&client->dev, "Failed to read %s axis: %d\n", 2083 fwnode_get_name(sldr_node), error); 2084 return error; 2085 } 2086 2087 if (dev_desc->wheel_enable) { 2088 sldr_setup[0] &= ~dev_desc->wheel_enable; 2089 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL) 2090 sldr_setup[0] |= dev_desc->wheel_enable; 2091 } 2092 2093 /* 2094 * The absence of a register offset makes it safe to assume the device 2095 * supports gestures, each of which is first disabled until explicitly 2096 * enabled. 2097 */ 2098 if (!reg_offset) 2099 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) 2100 sldr_setup[9] &= ~iqs7222_sl_events[i].enable; 2101 2102 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { 2103 const char *event_name = iqs7222_sl_events[i].name; 2104 struct fwnode_handle *event_node; 2105 enum iqs7222_reg_key_id reg_key; 2106 2107 event_node = fwnode_get_named_child_node(sldr_node, event_name); 2108 if (!event_node) 2109 continue; 2110 2111 if (reg_offset) 2112 reg_key = IQS7222_REG_KEY_RESERVED; 2113 else 2114 reg_key = iqs7222_sl_events[i].reg_key; 2115 2116 /* 2117 * The press/release event does not expose a direct GPIO link, 2118 * but one can be emulated by tying each of the participating 2119 * channels to the same GPIO. 2120 */ 2121 error = iqs7222_parse_event(iqs7222, event_node, sldr_index, 2122 IQS7222_REG_GRP_SLDR, reg_key, 2123 i ? iqs7222_sl_events[i].enable 2124 : sldr_setup[3 + reg_offset], 2125 i ? 1568 + sldr_index * 30 2126 : sldr_setup[4 + reg_offset], 2127 NULL, 2128 &iqs7222->sl_code[sldr_index][i]); 2129 fwnode_handle_put(event_node); 2130 if (error) 2131 return error; 2132 2133 if (!reg_offset) 2134 sldr_setup[9] |= iqs7222_sl_events[i].enable; 2135 2136 if (!dev_desc->event_offset) 2137 continue; 2138 2139 /* 2140 * The press/release event is determined based on whether the 2141 * coordinate field reports 0xFFFF and solely relies on touch 2142 * or proximity interrupts to be unmasked. 2143 */ 2144 if (i && !reg_offset) 2145 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index); 2146 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link) 2147 *event_mask |= IQS7222_EVENT_MASK_TOUCH; 2148 else 2149 *event_mask |= IQS7222_EVENT_MASK_PROX; 2150 } 2151 2152 /* 2153 * The following call handles a special pair of properties that shift 2154 * to make room for a wheel enable control in the case of IQS7222C. 2155 */ 2156 return iqs7222_parse_props(iqs7222, sldr_node, sldr_index, 2157 IQS7222_REG_GRP_SLDR, 2158 dev_desc->wheel_enable ? 2159 IQS7222_REG_KEY_WHEEL : 2160 IQS7222_REG_KEY_NO_WHEEL); 2161 } 2162 2163 static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS]) 2164 (struct iqs7222_private *iqs7222, 2165 struct fwnode_handle *reg_grp_node, 2166 int reg_grp_index) = { 2167 [IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle, 2168 [IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan, 2169 [IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr, 2170 }; 2171 2172 static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222, 2173 enum iqs7222_reg_grp_id reg_grp, 2174 int reg_grp_index) 2175 { 2176 struct i2c_client *client = iqs7222->client; 2177 struct fwnode_handle *reg_grp_node; 2178 int error; 2179 2180 if (iqs7222_reg_grp_names[reg_grp]) { 2181 char reg_grp_name[16]; 2182 2183 snprintf(reg_grp_name, sizeof(reg_grp_name), "%s-%d", 2184 iqs7222_reg_grp_names[reg_grp], reg_grp_index); 2185 2186 reg_grp_node = device_get_named_child_node(&client->dev, 2187 reg_grp_name); 2188 } else { 2189 reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev)); 2190 } 2191 2192 if (!reg_grp_node) 2193 return 0; 2194 2195 error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index, 2196 reg_grp, IQS7222_REG_KEY_NONE); 2197 2198 if (!error && iqs7222_parse_extra[reg_grp]) 2199 error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node, 2200 reg_grp_index); 2201 2202 fwnode_handle_put(reg_grp_node); 2203 2204 return error; 2205 } 2206 2207 static int iqs7222_parse_all(struct iqs7222_private *iqs7222) 2208 { 2209 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2210 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps; 2211 u16 *sys_setup = iqs7222->sys_setup; 2212 int error, i, j; 2213 2214 if (dev_desc->allow_offset) 2215 sys_setup[dev_desc->allow_offset] = U16_MAX; 2216 2217 if (dev_desc->event_offset) 2218 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI; 2219 2220 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { 2221 u16 *gpio_setup = iqs7222->gpio_setup[i]; 2222 2223 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; 2224 gpio_setup[1] = 0; 2225 gpio_setup[2] = 0; 2226 2227 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1) 2228 continue; 2229 2230 /* 2231 * The IQS7222C exposes multiple GPIO and must be informed 2232 * as to which GPIO this group represents. 2233 */ 2234 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) 2235 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); 2236 2237 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); 2238 } 2239 2240 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { 2241 u16 *chan_setup = iqs7222->chan_setup[i]; 2242 2243 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; 2244 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; 2245 2246 chan_setup[5] = 0; 2247 } 2248 2249 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2250 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2251 2252 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; 2253 } 2254 2255 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { 2256 for (j = 0; j < reg_grps[i].num_row; j++) { 2257 error = iqs7222_parse_reg_grp(iqs7222, i, j); 2258 if (error) 2259 return error; 2260 } 2261 } 2262 2263 return 0; 2264 } 2265 2266 static int iqs7222_report(struct iqs7222_private *iqs7222) 2267 { 2268 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2269 struct i2c_client *client = iqs7222->client; 2270 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 2271 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col; 2272 int error, i, j; 2273 __le16 status[IQS7222_MAX_COLS_STAT]; 2274 2275 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status, 2276 num_stat); 2277 if (error) 2278 return error; 2279 2280 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { 2281 dev_err(&client->dev, "Unexpected device reset\n"); 2282 return iqs7222_dev_init(iqs7222, WRITE); 2283 } 2284 2285 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { 2286 dev_err(&client->dev, "Unexpected ATI error\n"); 2287 return iqs7222_ati_trigger(iqs7222); 2288 } 2289 2290 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) 2291 return 0; 2292 2293 for (i = 0; i < num_chan; i++) { 2294 u16 *chan_setup = iqs7222->chan_setup[i]; 2295 2296 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) 2297 continue; 2298 2299 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { 2300 /* 2301 * Proximity state begins at offset 2 and spills into 2302 * offset 3 for devices with more than 16 channels. 2303 * 2304 * Touch state begins at the first offset immediately 2305 * following proximity state. 2306 */ 2307 int k = 2 + j * (num_chan > 16 ? 2 : 1); 2308 u16 state = le16_to_cpu(status[k + i / 16]); 2309 2310 if (!iqs7222->kp_type[i][j]) 2311 continue; 2312 2313 input_event(iqs7222->keypad, 2314 iqs7222->kp_type[i][j], 2315 iqs7222->kp_code[i][j], 2316 !!(state & BIT(i % 16))); 2317 } 2318 } 2319 2320 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2321 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2322 u16 sldr_pos = le16_to_cpu(status[4 + i]); 2323 u16 state = le16_to_cpu(status[6 + i]); 2324 2325 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) 2326 continue; 2327 2328 if (sldr_pos < dev_desc->sldr_res) 2329 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i], 2330 sldr_pos); 2331 2332 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0], 2333 sldr_pos < dev_desc->sldr_res); 2334 2335 /* 2336 * A maximum resolution indicates the device does not support 2337 * gestures, in which case the remaining fields are ignored. 2338 */ 2339 if (dev_desc->sldr_res == U16_MAX) 2340 continue; 2341 2342 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i)) 2343 continue; 2344 2345 /* 2346 * Skip the press/release event, as it does not have separate 2347 * status fields and is handled separately. 2348 */ 2349 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) { 2350 u16 mask = iqs7222_sl_events[j].mask; 2351 u16 val = iqs7222_sl_events[j].val; 2352 2353 input_report_key(iqs7222->keypad, 2354 iqs7222->sl_code[i][j], 2355 (state & mask) == val); 2356 } 2357 2358 input_sync(iqs7222->keypad); 2359 2360 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) 2361 input_report_key(iqs7222->keypad, 2362 iqs7222->sl_code[i][j], 0); 2363 } 2364 2365 input_sync(iqs7222->keypad); 2366 2367 return 0; 2368 } 2369 2370 static irqreturn_t iqs7222_irq(int irq, void *context) 2371 { 2372 struct iqs7222_private *iqs7222 = context; 2373 2374 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED; 2375 } 2376 2377 static int iqs7222_probe(struct i2c_client *client) 2378 { 2379 struct iqs7222_private *iqs7222; 2380 unsigned long irq_flags; 2381 int error, irq; 2382 2383 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL); 2384 if (!iqs7222) 2385 return -ENOMEM; 2386 2387 i2c_set_clientdata(client, iqs7222); 2388 iqs7222->client = client; 2389 2390 iqs7222->keypad = devm_input_allocate_device(&client->dev); 2391 if (!iqs7222->keypad) 2392 return -ENOMEM; 2393 2394 iqs7222->keypad->name = client->name; 2395 iqs7222->keypad->id.bustype = BUS_I2C; 2396 2397 /* 2398 * The RDY pin behaves as an interrupt, but must also be polled ahead 2399 * of unsolicited I2C communication. As such, it is first opened as a 2400 * GPIO and then passed to gpiod_to_irq() to register the interrupt. 2401 */ 2402 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN); 2403 if (IS_ERR(iqs7222->irq_gpio)) { 2404 error = PTR_ERR(iqs7222->irq_gpio); 2405 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n", 2406 error); 2407 return error; 2408 } 2409 2410 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 2411 GPIOD_OUT_HIGH); 2412 if (IS_ERR(iqs7222->reset_gpio)) { 2413 error = PTR_ERR(iqs7222->reset_gpio); 2414 dev_err(&client->dev, "Failed to request reset GPIO: %d\n", 2415 error); 2416 return error; 2417 } 2418 2419 error = iqs7222_hard_reset(iqs7222); 2420 if (error) 2421 return error; 2422 2423 error = iqs7222_dev_info(iqs7222); 2424 if (error) 2425 return error; 2426 2427 error = iqs7222_dev_init(iqs7222, READ); 2428 if (error) 2429 return error; 2430 2431 error = iqs7222_parse_all(iqs7222); 2432 if (error) 2433 return error; 2434 2435 error = iqs7222_dev_init(iqs7222, WRITE); 2436 if (error) 2437 return error; 2438 2439 error = iqs7222_report(iqs7222); 2440 if (error) 2441 return error; 2442 2443 error = input_register_device(iqs7222->keypad); 2444 if (error) { 2445 dev_err(&client->dev, "Failed to register device: %d\n", error); 2446 return error; 2447 } 2448 2449 irq = gpiod_to_irq(iqs7222->irq_gpio); 2450 if (irq < 0) 2451 return irq; 2452 2453 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW 2454 : IRQF_TRIGGER_HIGH; 2455 irq_flags |= IRQF_ONESHOT; 2456 2457 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq, 2458 irq_flags, client->name, iqs7222); 2459 if (error) 2460 dev_err(&client->dev, "Failed to request IRQ: %d\n", error); 2461 2462 return error; 2463 } 2464 2465 static const struct of_device_id iqs7222_of_match[] = { 2466 { .compatible = "azoteq,iqs7222a" }, 2467 { .compatible = "azoteq,iqs7222b" }, 2468 { .compatible = "azoteq,iqs7222c" }, 2469 { } 2470 }; 2471 MODULE_DEVICE_TABLE(of, iqs7222_of_match); 2472 2473 static struct i2c_driver iqs7222_i2c_driver = { 2474 .driver = { 2475 .name = "iqs7222", 2476 .of_match_table = iqs7222_of_match, 2477 }, 2478 .probe_new = iqs7222_probe, 2479 }; 2480 module_i2c_driver(iqs7222_i2c_driver); 2481 2482 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>"); 2483 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C Capacitive Touch Controller"); 2484 MODULE_LICENSE("GPL"); 2485