1 /* 2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix 3 * keyboard controller 4 * 5 * Copyright (c) 2009-2011, NVIDIA Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/input.h> 25 #include <linux/platform_device.h> 26 #include <linux/delay.h> 27 #include <linux/io.h> 28 #include <linux/interrupt.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/clk.h> 32 #include <linux/slab.h> 33 #include <linux/input/matrix_keypad.h> 34 #include <linux/reset.h> 35 #include <linux/err.h> 36 37 #define KBC_MAX_KPENT 8 38 39 /* Maximum row/column supported by Tegra KBC yet is 16x8 */ 40 #define KBC_MAX_GPIO 24 41 /* Maximum keys supported by Tegra KBC yet is 16 x 8*/ 42 #define KBC_MAX_KEY (16 * 8) 43 44 #define KBC_MAX_DEBOUNCE_CNT 0x3ffu 45 46 /* KBC row scan time and delay for beginning the row scan. */ 47 #define KBC_ROW_SCAN_TIME 16 48 #define KBC_ROW_SCAN_DLY 5 49 50 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */ 51 #define KBC_CYCLE_MS 32 52 53 /* KBC Registers */ 54 55 /* KBC Control Register */ 56 #define KBC_CONTROL_0 0x0 57 #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) 58 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) 59 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) 60 #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1) 61 #define KBC_CONTROL_KBC_EN (1 << 0) 62 63 /* KBC Interrupt Register */ 64 #define KBC_INT_0 0x4 65 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) 66 #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0) 67 68 #define KBC_ROW_CFG0_0 0x8 69 #define KBC_COL_CFG0_0 0x18 70 #define KBC_TO_CNT_0 0x24 71 #define KBC_INIT_DLY_0 0x28 72 #define KBC_RPT_DLY_0 0x2c 73 #define KBC_KP_ENT0_0 0x30 74 #define KBC_KP_ENT1_0 0x34 75 #define KBC_ROW0_MASK_0 0x38 76 77 #define KBC_ROW_SHIFT 3 78 79 enum tegra_pin_type { 80 PIN_CFG_IGNORE, 81 PIN_CFG_COL, 82 PIN_CFG_ROW, 83 }; 84 85 /* Tegra KBC hw support */ 86 struct tegra_kbc_hw_support { 87 int max_rows; 88 int max_columns; 89 }; 90 91 struct tegra_kbc_pin_cfg { 92 enum tegra_pin_type type; 93 unsigned char num; 94 }; 95 96 struct tegra_kbc { 97 struct device *dev; 98 unsigned int debounce_cnt; 99 unsigned int repeat_cnt; 100 struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; 101 const struct matrix_keymap_data *keymap_data; 102 bool wakeup; 103 void __iomem *mmio; 104 struct input_dev *idev; 105 int irq; 106 spinlock_t lock; 107 unsigned int repoll_dly; 108 unsigned long cp_dly_jiffies; 109 unsigned int cp_to_wkup_dly; 110 bool use_fn_map; 111 bool use_ghost_filter; 112 bool keypress_caused_wake; 113 unsigned short keycode[KBC_MAX_KEY * 2]; 114 unsigned short current_keys[KBC_MAX_KPENT]; 115 unsigned int num_pressed_keys; 116 u32 wakeup_key; 117 struct timer_list timer; 118 struct clk *clk; 119 struct reset_control *rst; 120 const struct tegra_kbc_hw_support *hw_support; 121 int max_keys; 122 int num_rows_and_columns; 123 }; 124 125 static void tegra_kbc_report_released_keys(struct input_dev *input, 126 unsigned short old_keycodes[], 127 unsigned int old_num_keys, 128 unsigned short new_keycodes[], 129 unsigned int new_num_keys) 130 { 131 unsigned int i, j; 132 133 for (i = 0; i < old_num_keys; i++) { 134 for (j = 0; j < new_num_keys; j++) 135 if (old_keycodes[i] == new_keycodes[j]) 136 break; 137 138 if (j == new_num_keys) 139 input_report_key(input, old_keycodes[i], 0); 140 } 141 } 142 143 static void tegra_kbc_report_pressed_keys(struct input_dev *input, 144 unsigned char scancodes[], 145 unsigned short keycodes[], 146 unsigned int num_pressed_keys) 147 { 148 unsigned int i; 149 150 for (i = 0; i < num_pressed_keys; i++) { 151 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); 152 input_report_key(input, keycodes[i], 1); 153 } 154 } 155 156 static void tegra_kbc_report_keys(struct tegra_kbc *kbc) 157 { 158 unsigned char scancodes[KBC_MAX_KPENT]; 159 unsigned short keycodes[KBC_MAX_KPENT]; 160 u32 val = 0; 161 unsigned int i; 162 unsigned int num_down = 0; 163 bool fn_keypress = false; 164 bool key_in_same_row = false; 165 bool key_in_same_col = false; 166 167 for (i = 0; i < KBC_MAX_KPENT; i++) { 168 if ((i % 4) == 0) 169 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); 170 171 if (val & 0x80) { 172 unsigned int col = val & 0x07; 173 unsigned int row = (val >> 3) & 0x0f; 174 unsigned char scancode = 175 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); 176 177 scancodes[num_down] = scancode; 178 keycodes[num_down] = kbc->keycode[scancode]; 179 /* If driver uses Fn map, do not report the Fn key. */ 180 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) 181 fn_keypress = true; 182 else 183 num_down++; 184 } 185 186 val >>= 8; 187 } 188 189 /* 190 * Matrix keyboard designs are prone to keyboard ghosting. 191 * Ghosting occurs if there are 3 keys such that - 192 * any 2 of the 3 keys share a row, and any 2 of them share a column. 193 * If so ignore the key presses for this iteration. 194 */ 195 if (kbc->use_ghost_filter && num_down >= 3) { 196 for (i = 0; i < num_down; i++) { 197 unsigned int j; 198 u8 curr_col = scancodes[i] & 0x07; 199 u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; 200 201 /* 202 * Find 2 keys such that one key is in the same row 203 * and the other is in the same column as the i-th key. 204 */ 205 for (j = i + 1; j < num_down; j++) { 206 u8 col = scancodes[j] & 0x07; 207 u8 row = scancodes[j] >> KBC_ROW_SHIFT; 208 209 if (col == curr_col) 210 key_in_same_col = true; 211 if (row == curr_row) 212 key_in_same_row = true; 213 } 214 } 215 } 216 217 /* 218 * If the platform uses Fn keymaps, translate keys on a Fn keypress. 219 * Function keycodes are max_keys apart from the plain keycodes. 220 */ 221 if (fn_keypress) { 222 for (i = 0; i < num_down; i++) { 223 scancodes[i] += kbc->max_keys; 224 keycodes[i] = kbc->keycode[scancodes[i]]; 225 } 226 } 227 228 /* Ignore the key presses for this iteration? */ 229 if (key_in_same_col && key_in_same_row) 230 return; 231 232 tegra_kbc_report_released_keys(kbc->idev, 233 kbc->current_keys, kbc->num_pressed_keys, 234 keycodes, num_down); 235 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); 236 input_sync(kbc->idev); 237 238 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); 239 kbc->num_pressed_keys = num_down; 240 } 241 242 static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) 243 { 244 u32 val; 245 246 val = readl(kbc->mmio + KBC_CONTROL_0); 247 if (enable) 248 val |= KBC_CONTROL_FIFO_CNT_INT_EN; 249 else 250 val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; 251 writel(val, kbc->mmio + KBC_CONTROL_0); 252 } 253 254 static void tegra_kbc_keypress_timer(struct timer_list *t) 255 { 256 struct tegra_kbc *kbc = from_timer(kbc, t, timer); 257 unsigned long flags; 258 u32 val; 259 unsigned int i; 260 261 spin_lock_irqsave(&kbc->lock, flags); 262 263 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; 264 if (val) { 265 unsigned long dly; 266 267 tegra_kbc_report_keys(kbc); 268 269 /* 270 * If more than one keys are pressed we need not wait 271 * for the repoll delay. 272 */ 273 dly = (val == 1) ? kbc->repoll_dly : 1; 274 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); 275 } else { 276 /* Release any pressed keys and exit the polling loop */ 277 for (i = 0; i < kbc->num_pressed_keys; i++) 278 input_report_key(kbc->idev, kbc->current_keys[i], 0); 279 input_sync(kbc->idev); 280 281 kbc->num_pressed_keys = 0; 282 283 /* All keys are released so enable the keypress interrupt */ 284 tegra_kbc_set_fifo_interrupt(kbc, true); 285 } 286 287 spin_unlock_irqrestore(&kbc->lock, flags); 288 } 289 290 static irqreturn_t tegra_kbc_isr(int irq, void *args) 291 { 292 struct tegra_kbc *kbc = args; 293 unsigned long flags; 294 u32 val; 295 296 spin_lock_irqsave(&kbc->lock, flags); 297 298 /* 299 * Quickly bail out & reenable interrupts if the fifo threshold 300 * count interrupt wasn't the interrupt source 301 */ 302 val = readl(kbc->mmio + KBC_INT_0); 303 writel(val, kbc->mmio + KBC_INT_0); 304 305 if (val & KBC_INT_FIFO_CNT_INT_STATUS) { 306 /* 307 * Until all keys are released, defer further processing to 308 * the polling loop in tegra_kbc_keypress_timer. 309 */ 310 tegra_kbc_set_fifo_interrupt(kbc, false); 311 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); 312 } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { 313 /* We can be here only through system resume path */ 314 kbc->keypress_caused_wake = true; 315 } 316 317 spin_unlock_irqrestore(&kbc->lock, flags); 318 319 return IRQ_HANDLED; 320 } 321 322 static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) 323 { 324 int i; 325 unsigned int rst_val; 326 327 /* Either mask all keys or none. */ 328 rst_val = (filter && !kbc->wakeup) ? ~0 : 0; 329 330 for (i = 0; i < kbc->hw_support->max_rows; i++) 331 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); 332 } 333 334 static void tegra_kbc_config_pins(struct tegra_kbc *kbc) 335 { 336 int i; 337 338 for (i = 0; i < KBC_MAX_GPIO; i++) { 339 u32 r_shft = 5 * (i % 6); 340 u32 c_shft = 4 * (i % 8); 341 u32 r_mask = 0x1f << r_shft; 342 u32 c_mask = 0x0f << c_shft; 343 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; 344 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; 345 u32 row_cfg = readl(kbc->mmio + r_offs); 346 u32 col_cfg = readl(kbc->mmio + c_offs); 347 348 row_cfg &= ~r_mask; 349 col_cfg &= ~c_mask; 350 351 switch (kbc->pin_cfg[i].type) { 352 case PIN_CFG_ROW: 353 row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft; 354 break; 355 356 case PIN_CFG_COL: 357 col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft; 358 break; 359 360 case PIN_CFG_IGNORE: 361 break; 362 } 363 364 writel(row_cfg, kbc->mmio + r_offs); 365 writel(col_cfg, kbc->mmio + c_offs); 366 } 367 } 368 369 static int tegra_kbc_start(struct tegra_kbc *kbc) 370 { 371 unsigned int debounce_cnt; 372 u32 val = 0; 373 int ret; 374 375 ret = clk_prepare_enable(kbc->clk); 376 if (ret) 377 return ret; 378 379 /* Reset the KBC controller to clear all previous status.*/ 380 reset_control_assert(kbc->rst); 381 udelay(100); 382 reset_control_deassert(kbc->rst); 383 udelay(100); 384 385 tegra_kbc_config_pins(kbc); 386 tegra_kbc_setup_wakekeys(kbc, false); 387 388 writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); 389 390 /* Keyboard debounce count is maximum of 12 bits. */ 391 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 392 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); 393 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ 394 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ 395 val |= KBC_CONTROL_KBC_EN; /* enable */ 396 writel(val, kbc->mmio + KBC_CONTROL_0); 397 398 /* 399 * Compute the delay(ns) from interrupt mode to continuous polling 400 * mode so the timer routine is scheduled appropriately. 401 */ 402 val = readl(kbc->mmio + KBC_INIT_DLY_0); 403 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); 404 405 kbc->num_pressed_keys = 0; 406 407 /* 408 * Atomically clear out any remaining entries in the key FIFO 409 * and enable keyboard interrupts. 410 */ 411 while (1) { 412 val = readl(kbc->mmio + KBC_INT_0); 413 val >>= 4; 414 if (!val) 415 break; 416 417 val = readl(kbc->mmio + KBC_KP_ENT0_0); 418 val = readl(kbc->mmio + KBC_KP_ENT1_0); 419 } 420 writel(0x7, kbc->mmio + KBC_INT_0); 421 422 enable_irq(kbc->irq); 423 424 return 0; 425 } 426 427 static void tegra_kbc_stop(struct tegra_kbc *kbc) 428 { 429 unsigned long flags; 430 u32 val; 431 432 spin_lock_irqsave(&kbc->lock, flags); 433 val = readl(kbc->mmio + KBC_CONTROL_0); 434 val &= ~1; 435 writel(val, kbc->mmio + KBC_CONTROL_0); 436 spin_unlock_irqrestore(&kbc->lock, flags); 437 438 disable_irq(kbc->irq); 439 del_timer_sync(&kbc->timer); 440 441 clk_disable_unprepare(kbc->clk); 442 } 443 444 static int tegra_kbc_open(struct input_dev *dev) 445 { 446 struct tegra_kbc *kbc = input_get_drvdata(dev); 447 448 return tegra_kbc_start(kbc); 449 } 450 451 static void tegra_kbc_close(struct input_dev *dev) 452 { 453 struct tegra_kbc *kbc = input_get_drvdata(dev); 454 455 return tegra_kbc_stop(kbc); 456 } 457 458 static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc, 459 unsigned int *num_rows) 460 { 461 int i; 462 463 *num_rows = 0; 464 465 for (i = 0; i < KBC_MAX_GPIO; i++) { 466 const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i]; 467 468 switch (pin_cfg->type) { 469 case PIN_CFG_ROW: 470 if (pin_cfg->num >= kbc->hw_support->max_rows) { 471 dev_err(kbc->dev, 472 "pin_cfg[%d]: invalid row number %d\n", 473 i, pin_cfg->num); 474 return false; 475 } 476 (*num_rows)++; 477 break; 478 479 case PIN_CFG_COL: 480 if (pin_cfg->num >= kbc->hw_support->max_columns) { 481 dev_err(kbc->dev, 482 "pin_cfg[%d]: invalid column number %d\n", 483 i, pin_cfg->num); 484 return false; 485 } 486 break; 487 488 case PIN_CFG_IGNORE: 489 break; 490 491 default: 492 dev_err(kbc->dev, 493 "pin_cfg[%d]: invalid entry type %d\n", 494 pin_cfg->type, pin_cfg->num); 495 return false; 496 } 497 } 498 499 return true; 500 } 501 502 static int tegra_kbc_parse_dt(struct tegra_kbc *kbc) 503 { 504 struct device_node *np = kbc->dev->of_node; 505 u32 prop; 506 int i; 507 u32 num_rows = 0; 508 u32 num_cols = 0; 509 u32 cols_cfg[KBC_MAX_GPIO]; 510 u32 rows_cfg[KBC_MAX_GPIO]; 511 int proplen; 512 int ret; 513 514 if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop)) 515 kbc->debounce_cnt = prop; 516 517 if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop)) 518 kbc->repeat_cnt = prop; 519 520 if (of_find_property(np, "nvidia,needs-ghost-filter", NULL)) 521 kbc->use_ghost_filter = true; 522 523 if (of_property_read_bool(np, "wakeup-source") || 524 of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */ 525 kbc->wakeup = true; 526 527 if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) { 528 dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n"); 529 return -ENOENT; 530 } 531 num_rows = proplen / sizeof(u32); 532 533 if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) { 534 dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n"); 535 return -ENOENT; 536 } 537 num_cols = proplen / sizeof(u32); 538 539 if (num_rows > kbc->hw_support->max_rows) { 540 dev_err(kbc->dev, 541 "Number of rows is more than supported by hardware\n"); 542 return -EINVAL; 543 } 544 545 if (num_cols > kbc->hw_support->max_columns) { 546 dev_err(kbc->dev, 547 "Number of cols is more than supported by hardware\n"); 548 return -EINVAL; 549 } 550 551 if (!of_get_property(np, "linux,keymap", &proplen)) { 552 dev_err(kbc->dev, "property linux,keymap not found\n"); 553 return -ENOENT; 554 } 555 556 if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) { 557 dev_err(kbc->dev, 558 "keypad rows/columns not properly specified\n"); 559 return -EINVAL; 560 } 561 562 /* Set all pins as non-configured */ 563 for (i = 0; i < kbc->num_rows_and_columns; i++) 564 kbc->pin_cfg[i].type = PIN_CFG_IGNORE; 565 566 ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins", 567 rows_cfg, num_rows); 568 if (ret < 0) { 569 dev_err(kbc->dev, "Rows configurations are not proper\n"); 570 return -EINVAL; 571 } 572 573 ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins", 574 cols_cfg, num_cols); 575 if (ret < 0) { 576 dev_err(kbc->dev, "Cols configurations are not proper\n"); 577 return -EINVAL; 578 } 579 580 for (i = 0; i < num_rows; i++) { 581 kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW; 582 kbc->pin_cfg[rows_cfg[i]].num = i; 583 } 584 585 for (i = 0; i < num_cols; i++) { 586 kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL; 587 kbc->pin_cfg[cols_cfg[i]].num = i; 588 } 589 590 return 0; 591 } 592 593 static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = { 594 .max_rows = 16, 595 .max_columns = 8, 596 }; 597 598 static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = { 599 .max_rows = 11, 600 .max_columns = 8, 601 }; 602 603 static const struct of_device_id tegra_kbc_of_match[] = { 604 { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support}, 605 { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support}, 606 { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support}, 607 { }, 608 }; 609 MODULE_DEVICE_TABLE(of, tegra_kbc_of_match); 610 611 static int tegra_kbc_probe(struct platform_device *pdev) 612 { 613 struct tegra_kbc *kbc; 614 struct resource *res; 615 int err; 616 int num_rows = 0; 617 unsigned int debounce_cnt; 618 unsigned int scan_time_rows; 619 unsigned int keymap_rows; 620 const struct of_device_id *match; 621 622 match = of_match_device(tegra_kbc_of_match, &pdev->dev); 623 624 kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL); 625 if (!kbc) { 626 dev_err(&pdev->dev, "failed to alloc memory for kbc\n"); 627 return -ENOMEM; 628 } 629 630 kbc->dev = &pdev->dev; 631 kbc->hw_support = match->data; 632 kbc->max_keys = kbc->hw_support->max_rows * 633 kbc->hw_support->max_columns; 634 kbc->num_rows_and_columns = kbc->hw_support->max_rows + 635 kbc->hw_support->max_columns; 636 keymap_rows = kbc->max_keys; 637 spin_lock_init(&kbc->lock); 638 639 err = tegra_kbc_parse_dt(kbc); 640 if (err) 641 return err; 642 643 if (!tegra_kbc_check_pin_cfg(kbc, &num_rows)) 644 return -EINVAL; 645 646 kbc->irq = platform_get_irq(pdev, 0); 647 if (kbc->irq < 0) { 648 dev_err(&pdev->dev, "failed to get keyboard IRQ\n"); 649 return -ENXIO; 650 } 651 652 kbc->idev = devm_input_allocate_device(&pdev->dev); 653 if (!kbc->idev) { 654 dev_err(&pdev->dev, "failed to allocate input device\n"); 655 return -ENOMEM; 656 } 657 658 timer_setup(&kbc->timer, tegra_kbc_keypress_timer, 0); 659 660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 661 kbc->mmio = devm_ioremap_resource(&pdev->dev, res); 662 if (IS_ERR(kbc->mmio)) 663 return PTR_ERR(kbc->mmio); 664 665 kbc->clk = devm_clk_get(&pdev->dev, NULL); 666 if (IS_ERR(kbc->clk)) { 667 dev_err(&pdev->dev, "failed to get keyboard clock\n"); 668 return PTR_ERR(kbc->clk); 669 } 670 671 kbc->rst = devm_reset_control_get(&pdev->dev, "kbc"); 672 if (IS_ERR(kbc->rst)) { 673 dev_err(&pdev->dev, "failed to get keyboard reset\n"); 674 return PTR_ERR(kbc->rst); 675 } 676 677 /* 678 * The time delay between two consecutive reads of the FIFO is 679 * the sum of the repeat time and the time taken for scanning 680 * the rows. There is an additional delay before the row scanning 681 * starts. The repoll delay is computed in milliseconds. 682 */ 683 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 684 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; 685 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt; 686 kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); 687 688 kbc->idev->name = pdev->name; 689 kbc->idev->id.bustype = BUS_HOST; 690 kbc->idev->dev.parent = &pdev->dev; 691 kbc->idev->open = tegra_kbc_open; 692 kbc->idev->close = tegra_kbc_close; 693 694 if (kbc->keymap_data && kbc->use_fn_map) 695 keymap_rows *= 2; 696 697 err = matrix_keypad_build_keymap(kbc->keymap_data, NULL, 698 keymap_rows, 699 kbc->hw_support->max_columns, 700 kbc->keycode, kbc->idev); 701 if (err) { 702 dev_err(&pdev->dev, "failed to setup keymap\n"); 703 return err; 704 } 705 706 __set_bit(EV_REP, kbc->idev->evbit); 707 input_set_capability(kbc->idev, EV_MSC, MSC_SCAN); 708 709 input_set_drvdata(kbc->idev, kbc); 710 711 err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr, 712 IRQF_TRIGGER_HIGH, pdev->name, kbc); 713 if (err) { 714 dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); 715 return err; 716 } 717 718 disable_irq(kbc->irq); 719 720 err = input_register_device(kbc->idev); 721 if (err) { 722 dev_err(&pdev->dev, "failed to register input device\n"); 723 return err; 724 } 725 726 platform_set_drvdata(pdev, kbc); 727 device_init_wakeup(&pdev->dev, kbc->wakeup); 728 729 return 0; 730 } 731 732 #ifdef CONFIG_PM_SLEEP 733 static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable) 734 { 735 u32 val; 736 737 val = readl(kbc->mmio + KBC_CONTROL_0); 738 if (enable) 739 val |= KBC_CONTROL_KEYPRESS_INT_EN; 740 else 741 val &= ~KBC_CONTROL_KEYPRESS_INT_EN; 742 writel(val, kbc->mmio + KBC_CONTROL_0); 743 } 744 745 static int tegra_kbc_suspend(struct device *dev) 746 { 747 struct platform_device *pdev = to_platform_device(dev); 748 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 749 750 mutex_lock(&kbc->idev->mutex); 751 if (device_may_wakeup(&pdev->dev)) { 752 disable_irq(kbc->irq); 753 del_timer_sync(&kbc->timer); 754 tegra_kbc_set_fifo_interrupt(kbc, false); 755 756 /* Forcefully clear the interrupt status */ 757 writel(0x7, kbc->mmio + KBC_INT_0); 758 /* 759 * Store the previous resident time of continuous polling mode. 760 * Force the keyboard into interrupt mode. 761 */ 762 kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); 763 writel(0, kbc->mmio + KBC_TO_CNT_0); 764 765 tegra_kbc_setup_wakekeys(kbc, true); 766 msleep(30); 767 768 kbc->keypress_caused_wake = false; 769 /* Enable keypress interrupt before going into suspend. */ 770 tegra_kbc_set_keypress_interrupt(kbc, true); 771 enable_irq(kbc->irq); 772 enable_irq_wake(kbc->irq); 773 } else { 774 if (kbc->idev->users) 775 tegra_kbc_stop(kbc); 776 } 777 mutex_unlock(&kbc->idev->mutex); 778 779 return 0; 780 } 781 782 static int tegra_kbc_resume(struct device *dev) 783 { 784 struct platform_device *pdev = to_platform_device(dev); 785 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 786 int err = 0; 787 788 mutex_lock(&kbc->idev->mutex); 789 if (device_may_wakeup(&pdev->dev)) { 790 disable_irq_wake(kbc->irq); 791 tegra_kbc_setup_wakekeys(kbc, false); 792 /* We will use fifo interrupts for key detection. */ 793 tegra_kbc_set_keypress_interrupt(kbc, false); 794 795 /* Restore the resident time of continuous polling mode. */ 796 writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); 797 798 tegra_kbc_set_fifo_interrupt(kbc, true); 799 800 if (kbc->keypress_caused_wake && kbc->wakeup_key) { 801 /* 802 * We can't report events directly from the ISR 803 * because timekeeping is stopped when processing 804 * wakeup request and we get a nasty warning when 805 * we try to call do_gettimeofday() in evdev 806 * handler. 807 */ 808 input_report_key(kbc->idev, kbc->wakeup_key, 1); 809 input_sync(kbc->idev); 810 input_report_key(kbc->idev, kbc->wakeup_key, 0); 811 input_sync(kbc->idev); 812 } 813 } else { 814 if (kbc->idev->users) 815 err = tegra_kbc_start(kbc); 816 } 817 mutex_unlock(&kbc->idev->mutex); 818 819 return err; 820 } 821 #endif 822 823 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume); 824 825 static struct platform_driver tegra_kbc_driver = { 826 .probe = tegra_kbc_probe, 827 .driver = { 828 .name = "tegra-kbc", 829 .pm = &tegra_kbc_pm_ops, 830 .of_match_table = tegra_kbc_of_match, 831 }, 832 }; 833 module_platform_driver(tegra_kbc_driver); 834 835 MODULE_LICENSE("GPL"); 836 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); 837 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); 838 MODULE_ALIAS("platform:tegra-kbc"); 839