1 /* 2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix 3 * keyboard controller 4 * 5 * Copyright (c) 2009-2011, NVIDIA Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/input.h> 25 #include <linux/platform_device.h> 26 #include <linux/delay.h> 27 #include <linux/io.h> 28 #include <linux/interrupt.h> 29 #include <linux/of.h> 30 #include <linux/clk.h> 31 #include <linux/slab.h> 32 #include <linux/input/matrix_keypad.h> 33 #include <linux/clk/tegra.h> 34 35 #define KBC_MAX_GPIO 24 36 #define KBC_MAX_KPENT 8 37 38 #define KBC_MAX_ROW 16 39 #define KBC_MAX_COL 8 40 #define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL) 41 42 #define KBC_MAX_DEBOUNCE_CNT 0x3ffu 43 44 /* KBC row scan time and delay for beginning the row scan. */ 45 #define KBC_ROW_SCAN_TIME 16 46 #define KBC_ROW_SCAN_DLY 5 47 48 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */ 49 #define KBC_CYCLE_MS 32 50 51 /* KBC Registers */ 52 53 /* KBC Control Register */ 54 #define KBC_CONTROL_0 0x0 55 #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) 56 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) 57 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) 58 #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1) 59 #define KBC_CONTROL_KBC_EN (1 << 0) 60 61 /* KBC Interrupt Register */ 62 #define KBC_INT_0 0x4 63 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) 64 #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0) 65 66 #define KBC_ROW_CFG0_0 0x8 67 #define KBC_COL_CFG0_0 0x18 68 #define KBC_TO_CNT_0 0x24 69 #define KBC_INIT_DLY_0 0x28 70 #define KBC_RPT_DLY_0 0x2c 71 #define KBC_KP_ENT0_0 0x30 72 #define KBC_KP_ENT1_0 0x34 73 #define KBC_ROW0_MASK_0 0x38 74 75 #define KBC_ROW_SHIFT 3 76 77 enum tegra_pin_type { 78 PIN_CFG_IGNORE, 79 PIN_CFG_COL, 80 PIN_CFG_ROW, 81 }; 82 83 struct tegra_kbc_pin_cfg { 84 enum tegra_pin_type type; 85 unsigned char num; 86 }; 87 88 struct tegra_kbc { 89 struct device *dev; 90 unsigned int debounce_cnt; 91 unsigned int repeat_cnt; 92 struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; 93 const struct matrix_keymap_data *keymap_data; 94 bool wakeup; 95 void __iomem *mmio; 96 struct input_dev *idev; 97 int irq; 98 spinlock_t lock; 99 unsigned int repoll_dly; 100 unsigned long cp_dly_jiffies; 101 unsigned int cp_to_wkup_dly; 102 bool use_fn_map; 103 bool use_ghost_filter; 104 bool keypress_caused_wake; 105 unsigned short keycode[KBC_MAX_KEY * 2]; 106 unsigned short current_keys[KBC_MAX_KPENT]; 107 unsigned int num_pressed_keys; 108 u32 wakeup_key; 109 struct timer_list timer; 110 struct clk *clk; 111 }; 112 113 static void tegra_kbc_report_released_keys(struct input_dev *input, 114 unsigned short old_keycodes[], 115 unsigned int old_num_keys, 116 unsigned short new_keycodes[], 117 unsigned int new_num_keys) 118 { 119 unsigned int i, j; 120 121 for (i = 0; i < old_num_keys; i++) { 122 for (j = 0; j < new_num_keys; j++) 123 if (old_keycodes[i] == new_keycodes[j]) 124 break; 125 126 if (j == new_num_keys) 127 input_report_key(input, old_keycodes[i], 0); 128 } 129 } 130 131 static void tegra_kbc_report_pressed_keys(struct input_dev *input, 132 unsigned char scancodes[], 133 unsigned short keycodes[], 134 unsigned int num_pressed_keys) 135 { 136 unsigned int i; 137 138 for (i = 0; i < num_pressed_keys; i++) { 139 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); 140 input_report_key(input, keycodes[i], 1); 141 } 142 } 143 144 static void tegra_kbc_report_keys(struct tegra_kbc *kbc) 145 { 146 unsigned char scancodes[KBC_MAX_KPENT]; 147 unsigned short keycodes[KBC_MAX_KPENT]; 148 u32 val = 0; 149 unsigned int i; 150 unsigned int num_down = 0; 151 bool fn_keypress = false; 152 bool key_in_same_row = false; 153 bool key_in_same_col = false; 154 155 for (i = 0; i < KBC_MAX_KPENT; i++) { 156 if ((i % 4) == 0) 157 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); 158 159 if (val & 0x80) { 160 unsigned int col = val & 0x07; 161 unsigned int row = (val >> 3) & 0x0f; 162 unsigned char scancode = 163 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); 164 165 scancodes[num_down] = scancode; 166 keycodes[num_down] = kbc->keycode[scancode]; 167 /* If driver uses Fn map, do not report the Fn key. */ 168 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) 169 fn_keypress = true; 170 else 171 num_down++; 172 } 173 174 val >>= 8; 175 } 176 177 /* 178 * Matrix keyboard designs are prone to keyboard ghosting. 179 * Ghosting occurs if there are 3 keys such that - 180 * any 2 of the 3 keys share a row, and any 2 of them share a column. 181 * If so ignore the key presses for this iteration. 182 */ 183 if (kbc->use_ghost_filter && num_down >= 3) { 184 for (i = 0; i < num_down; i++) { 185 unsigned int j; 186 u8 curr_col = scancodes[i] & 0x07; 187 u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; 188 189 /* 190 * Find 2 keys such that one key is in the same row 191 * and the other is in the same column as the i-th key. 192 */ 193 for (j = i + 1; j < num_down; j++) { 194 u8 col = scancodes[j] & 0x07; 195 u8 row = scancodes[j] >> KBC_ROW_SHIFT; 196 197 if (col == curr_col) 198 key_in_same_col = true; 199 if (row == curr_row) 200 key_in_same_row = true; 201 } 202 } 203 } 204 205 /* 206 * If the platform uses Fn keymaps, translate keys on a Fn keypress. 207 * Function keycodes are KBC_MAX_KEY apart from the plain keycodes. 208 */ 209 if (fn_keypress) { 210 for (i = 0; i < num_down; i++) { 211 scancodes[i] += KBC_MAX_KEY; 212 keycodes[i] = kbc->keycode[scancodes[i]]; 213 } 214 } 215 216 /* Ignore the key presses for this iteration? */ 217 if (key_in_same_col && key_in_same_row) 218 return; 219 220 tegra_kbc_report_released_keys(kbc->idev, 221 kbc->current_keys, kbc->num_pressed_keys, 222 keycodes, num_down); 223 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); 224 input_sync(kbc->idev); 225 226 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); 227 kbc->num_pressed_keys = num_down; 228 } 229 230 static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) 231 { 232 u32 val; 233 234 val = readl(kbc->mmio + KBC_CONTROL_0); 235 if (enable) 236 val |= KBC_CONTROL_FIFO_CNT_INT_EN; 237 else 238 val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; 239 writel(val, kbc->mmio + KBC_CONTROL_0); 240 } 241 242 static void tegra_kbc_keypress_timer(unsigned long data) 243 { 244 struct tegra_kbc *kbc = (struct tegra_kbc *)data; 245 unsigned long flags; 246 u32 val; 247 unsigned int i; 248 249 spin_lock_irqsave(&kbc->lock, flags); 250 251 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; 252 if (val) { 253 unsigned long dly; 254 255 tegra_kbc_report_keys(kbc); 256 257 /* 258 * If more than one keys are pressed we need not wait 259 * for the repoll delay. 260 */ 261 dly = (val == 1) ? kbc->repoll_dly : 1; 262 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); 263 } else { 264 /* Release any pressed keys and exit the polling loop */ 265 for (i = 0; i < kbc->num_pressed_keys; i++) 266 input_report_key(kbc->idev, kbc->current_keys[i], 0); 267 input_sync(kbc->idev); 268 269 kbc->num_pressed_keys = 0; 270 271 /* All keys are released so enable the keypress interrupt */ 272 tegra_kbc_set_fifo_interrupt(kbc, true); 273 } 274 275 spin_unlock_irqrestore(&kbc->lock, flags); 276 } 277 278 static irqreturn_t tegra_kbc_isr(int irq, void *args) 279 { 280 struct tegra_kbc *kbc = args; 281 unsigned long flags; 282 u32 val; 283 284 spin_lock_irqsave(&kbc->lock, flags); 285 286 /* 287 * Quickly bail out & reenable interrupts if the fifo threshold 288 * count interrupt wasn't the interrupt source 289 */ 290 val = readl(kbc->mmio + KBC_INT_0); 291 writel(val, kbc->mmio + KBC_INT_0); 292 293 if (val & KBC_INT_FIFO_CNT_INT_STATUS) { 294 /* 295 * Until all keys are released, defer further processing to 296 * the polling loop in tegra_kbc_keypress_timer. 297 */ 298 tegra_kbc_set_fifo_interrupt(kbc, false); 299 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); 300 } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { 301 /* We can be here only through system resume path */ 302 kbc->keypress_caused_wake = true; 303 } 304 305 spin_unlock_irqrestore(&kbc->lock, flags); 306 307 return IRQ_HANDLED; 308 } 309 310 static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) 311 { 312 int i; 313 unsigned int rst_val; 314 315 /* Either mask all keys or none. */ 316 rst_val = (filter && !kbc->wakeup) ? ~0 : 0; 317 318 for (i = 0; i < KBC_MAX_ROW; i++) 319 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); 320 } 321 322 static void tegra_kbc_config_pins(struct tegra_kbc *kbc) 323 { 324 int i; 325 326 for (i = 0; i < KBC_MAX_GPIO; i++) { 327 u32 r_shft = 5 * (i % 6); 328 u32 c_shft = 4 * (i % 8); 329 u32 r_mask = 0x1f << r_shft; 330 u32 c_mask = 0x0f << c_shft; 331 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; 332 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; 333 u32 row_cfg = readl(kbc->mmio + r_offs); 334 u32 col_cfg = readl(kbc->mmio + c_offs); 335 336 row_cfg &= ~r_mask; 337 col_cfg &= ~c_mask; 338 339 switch (kbc->pin_cfg[i].type) { 340 case PIN_CFG_ROW: 341 row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft; 342 break; 343 344 case PIN_CFG_COL: 345 col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft; 346 break; 347 348 case PIN_CFG_IGNORE: 349 break; 350 } 351 352 writel(row_cfg, kbc->mmio + r_offs); 353 writel(col_cfg, kbc->mmio + c_offs); 354 } 355 } 356 357 static int tegra_kbc_start(struct tegra_kbc *kbc) 358 { 359 unsigned int debounce_cnt; 360 u32 val = 0; 361 362 clk_prepare_enable(kbc->clk); 363 364 /* Reset the KBC controller to clear all previous status.*/ 365 tegra_periph_reset_assert(kbc->clk); 366 udelay(100); 367 tegra_periph_reset_deassert(kbc->clk); 368 udelay(100); 369 370 tegra_kbc_config_pins(kbc); 371 tegra_kbc_setup_wakekeys(kbc, false); 372 373 writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); 374 375 /* Keyboard debounce count is maximum of 12 bits. */ 376 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 377 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); 378 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ 379 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ 380 val |= KBC_CONTROL_KBC_EN; /* enable */ 381 writel(val, kbc->mmio + KBC_CONTROL_0); 382 383 /* 384 * Compute the delay(ns) from interrupt mode to continuous polling 385 * mode so the timer routine is scheduled appropriately. 386 */ 387 val = readl(kbc->mmio + KBC_INIT_DLY_0); 388 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); 389 390 kbc->num_pressed_keys = 0; 391 392 /* 393 * Atomically clear out any remaining entries in the key FIFO 394 * and enable keyboard interrupts. 395 */ 396 while (1) { 397 val = readl(kbc->mmio + KBC_INT_0); 398 val >>= 4; 399 if (!val) 400 break; 401 402 val = readl(kbc->mmio + KBC_KP_ENT0_0); 403 val = readl(kbc->mmio + KBC_KP_ENT1_0); 404 } 405 writel(0x7, kbc->mmio + KBC_INT_0); 406 407 enable_irq(kbc->irq); 408 409 return 0; 410 } 411 412 static void tegra_kbc_stop(struct tegra_kbc *kbc) 413 { 414 unsigned long flags; 415 u32 val; 416 417 spin_lock_irqsave(&kbc->lock, flags); 418 val = readl(kbc->mmio + KBC_CONTROL_0); 419 val &= ~1; 420 writel(val, kbc->mmio + KBC_CONTROL_0); 421 spin_unlock_irqrestore(&kbc->lock, flags); 422 423 disable_irq(kbc->irq); 424 del_timer_sync(&kbc->timer); 425 426 clk_disable_unprepare(kbc->clk); 427 } 428 429 static int tegra_kbc_open(struct input_dev *dev) 430 { 431 struct tegra_kbc *kbc = input_get_drvdata(dev); 432 433 return tegra_kbc_start(kbc); 434 } 435 436 static void tegra_kbc_close(struct input_dev *dev) 437 { 438 struct tegra_kbc *kbc = input_get_drvdata(dev); 439 440 return tegra_kbc_stop(kbc); 441 } 442 443 static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc, 444 unsigned int *num_rows) 445 { 446 int i; 447 448 *num_rows = 0; 449 450 for (i = 0; i < KBC_MAX_GPIO; i++) { 451 const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i]; 452 453 switch (pin_cfg->type) { 454 case PIN_CFG_ROW: 455 if (pin_cfg->num >= KBC_MAX_ROW) { 456 dev_err(kbc->dev, 457 "pin_cfg[%d]: invalid row number %d\n", 458 i, pin_cfg->num); 459 return false; 460 } 461 (*num_rows)++; 462 break; 463 464 case PIN_CFG_COL: 465 if (pin_cfg->num >= KBC_MAX_COL) { 466 dev_err(kbc->dev, 467 "pin_cfg[%d]: invalid column number %d\n", 468 i, pin_cfg->num); 469 return false; 470 } 471 break; 472 473 case PIN_CFG_IGNORE: 474 break; 475 476 default: 477 dev_err(kbc->dev, 478 "pin_cfg[%d]: invalid entry type %d\n", 479 pin_cfg->type, pin_cfg->num); 480 return false; 481 } 482 } 483 484 return true; 485 } 486 487 static int tegra_kbc_parse_dt(struct tegra_kbc *kbc) 488 { 489 struct device_node *np = kbc->dev->of_node; 490 u32 prop; 491 int i; 492 u32 num_rows = 0; 493 u32 num_cols = 0; 494 u32 cols_cfg[KBC_MAX_GPIO]; 495 u32 rows_cfg[KBC_MAX_GPIO]; 496 int proplen; 497 int ret; 498 499 if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop)) 500 kbc->debounce_cnt = prop; 501 502 if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop)) 503 kbc->repeat_cnt = prop; 504 505 if (of_find_property(np, "nvidia,needs-ghost-filter", NULL)) 506 kbc->use_ghost_filter = true; 507 508 if (of_find_property(np, "nvidia,wakeup-source", NULL)) 509 kbc->wakeup = true; 510 511 if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) { 512 dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n"); 513 return -ENOENT; 514 } 515 num_rows = proplen / sizeof(u32); 516 517 if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) { 518 dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n"); 519 return -ENOENT; 520 } 521 num_cols = proplen / sizeof(u32); 522 523 if (!of_get_property(np, "linux,keymap", &proplen)) { 524 dev_err(kbc->dev, "property linux,keymap not found\n"); 525 return -ENOENT; 526 } 527 528 if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) { 529 dev_err(kbc->dev, 530 "keypad rows/columns not porperly specified\n"); 531 return -EINVAL; 532 } 533 534 /* Set all pins as non-configured */ 535 for (i = 0; i < KBC_MAX_GPIO; i++) 536 kbc->pin_cfg[i].type = PIN_CFG_IGNORE; 537 538 ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins", 539 rows_cfg, num_rows); 540 if (ret < 0) { 541 dev_err(kbc->dev, "Rows configurations are not proper\n"); 542 return -EINVAL; 543 } 544 545 ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins", 546 cols_cfg, num_cols); 547 if (ret < 0) { 548 dev_err(kbc->dev, "Cols configurations are not proper\n"); 549 return -EINVAL; 550 } 551 552 for (i = 0; i < num_rows; i++) { 553 kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW; 554 kbc->pin_cfg[rows_cfg[i]].num = i; 555 } 556 557 for (i = 0; i < num_cols; i++) { 558 kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL; 559 kbc->pin_cfg[cols_cfg[i]].num = i; 560 } 561 562 return 0; 563 } 564 565 static int tegra_kbc_probe(struct platform_device *pdev) 566 { 567 struct tegra_kbc *kbc; 568 struct resource *res; 569 int err; 570 int num_rows = 0; 571 unsigned int debounce_cnt; 572 unsigned int scan_time_rows; 573 unsigned int keymap_rows = KBC_MAX_KEY; 574 575 kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL); 576 if (!kbc) { 577 dev_err(&pdev->dev, "failed to alloc memory for kbc\n"); 578 return -ENOMEM; 579 } 580 581 kbc->dev = &pdev->dev; 582 spin_lock_init(&kbc->lock); 583 584 err = tegra_kbc_parse_dt(kbc); 585 if (err) 586 return err; 587 588 if (!tegra_kbc_check_pin_cfg(kbc, &num_rows)) 589 return -EINVAL; 590 591 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 592 if (!res) { 593 dev_err(&pdev->dev, "failed to get I/O memory\n"); 594 return -ENXIO; 595 } 596 597 kbc->irq = platform_get_irq(pdev, 0); 598 if (kbc->irq < 0) { 599 dev_err(&pdev->dev, "failed to get keyboard IRQ\n"); 600 return -ENXIO; 601 } 602 603 kbc->idev = devm_input_allocate_device(&pdev->dev); 604 if (!kbc->idev) { 605 dev_err(&pdev->dev, "failed to allocate input device\n"); 606 return -ENOMEM; 607 } 608 609 setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc); 610 611 kbc->mmio = devm_request_and_ioremap(&pdev->dev, res); 612 if (!kbc->mmio) { 613 dev_err(&pdev->dev, "Cannot request memregion/iomap address\n"); 614 return -EBUSY; 615 } 616 617 kbc->clk = devm_clk_get(&pdev->dev, NULL); 618 if (IS_ERR(kbc->clk)) { 619 dev_err(&pdev->dev, "failed to get keyboard clock\n"); 620 return PTR_ERR(kbc->clk); 621 } 622 623 /* 624 * The time delay between two consecutive reads of the FIFO is 625 * the sum of the repeat time and the time taken for scanning 626 * the rows. There is an additional delay before the row scanning 627 * starts. The repoll delay is computed in milliseconds. 628 */ 629 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 630 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; 631 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt; 632 kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); 633 634 kbc->idev->name = pdev->name; 635 kbc->idev->id.bustype = BUS_HOST; 636 kbc->idev->dev.parent = &pdev->dev; 637 kbc->idev->open = tegra_kbc_open; 638 kbc->idev->close = tegra_kbc_close; 639 640 if (kbc->keymap_data && kbc->use_fn_map) 641 keymap_rows *= 2; 642 643 err = matrix_keypad_build_keymap(kbc->keymap_data, NULL, 644 keymap_rows, KBC_MAX_COL, 645 kbc->keycode, kbc->idev); 646 if (err) { 647 dev_err(&pdev->dev, "failed to setup keymap\n"); 648 return err; 649 } 650 651 __set_bit(EV_REP, kbc->idev->evbit); 652 input_set_capability(kbc->idev, EV_MSC, MSC_SCAN); 653 654 input_set_drvdata(kbc->idev, kbc); 655 656 err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr, 657 IRQF_NO_SUSPEND | IRQF_TRIGGER_HIGH, pdev->name, kbc); 658 if (err) { 659 dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); 660 return err; 661 } 662 663 disable_irq(kbc->irq); 664 665 err = input_register_device(kbc->idev); 666 if (err) { 667 dev_err(&pdev->dev, "failed to register input device\n"); 668 return err; 669 } 670 671 platform_set_drvdata(pdev, kbc); 672 device_init_wakeup(&pdev->dev, kbc->wakeup); 673 674 return 0; 675 } 676 677 #ifdef CONFIG_PM_SLEEP 678 static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable) 679 { 680 u32 val; 681 682 val = readl(kbc->mmio + KBC_CONTROL_0); 683 if (enable) 684 val |= KBC_CONTROL_KEYPRESS_INT_EN; 685 else 686 val &= ~KBC_CONTROL_KEYPRESS_INT_EN; 687 writel(val, kbc->mmio + KBC_CONTROL_0); 688 } 689 690 static int tegra_kbc_suspend(struct device *dev) 691 { 692 struct platform_device *pdev = to_platform_device(dev); 693 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 694 695 mutex_lock(&kbc->idev->mutex); 696 if (device_may_wakeup(&pdev->dev)) { 697 disable_irq(kbc->irq); 698 del_timer_sync(&kbc->timer); 699 tegra_kbc_set_fifo_interrupt(kbc, false); 700 701 /* Forcefully clear the interrupt status */ 702 writel(0x7, kbc->mmio + KBC_INT_0); 703 /* 704 * Store the previous resident time of continuous polling mode. 705 * Force the keyboard into interrupt mode. 706 */ 707 kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); 708 writel(0, kbc->mmio + KBC_TO_CNT_0); 709 710 tegra_kbc_setup_wakekeys(kbc, true); 711 msleep(30); 712 713 kbc->keypress_caused_wake = false; 714 /* Enable keypress interrupt before going into suspend. */ 715 tegra_kbc_set_keypress_interrupt(kbc, true); 716 enable_irq(kbc->irq); 717 enable_irq_wake(kbc->irq); 718 } else { 719 if (kbc->idev->users) 720 tegra_kbc_stop(kbc); 721 } 722 mutex_unlock(&kbc->idev->mutex); 723 724 return 0; 725 } 726 727 static int tegra_kbc_resume(struct device *dev) 728 { 729 struct platform_device *pdev = to_platform_device(dev); 730 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 731 int err = 0; 732 733 mutex_lock(&kbc->idev->mutex); 734 if (device_may_wakeup(&pdev->dev)) { 735 disable_irq_wake(kbc->irq); 736 tegra_kbc_setup_wakekeys(kbc, false); 737 /* We will use fifo interrupts for key detection. */ 738 tegra_kbc_set_keypress_interrupt(kbc, false); 739 740 /* Restore the resident time of continuous polling mode. */ 741 writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); 742 743 tegra_kbc_set_fifo_interrupt(kbc, true); 744 745 if (kbc->keypress_caused_wake && kbc->wakeup_key) { 746 /* 747 * We can't report events directly from the ISR 748 * because timekeeping is stopped when processing 749 * wakeup request and we get a nasty warning when 750 * we try to call do_gettimeofday() in evdev 751 * handler. 752 */ 753 input_report_key(kbc->idev, kbc->wakeup_key, 1); 754 input_sync(kbc->idev); 755 input_report_key(kbc->idev, kbc->wakeup_key, 0); 756 input_sync(kbc->idev); 757 } 758 } else { 759 if (kbc->idev->users) 760 err = tegra_kbc_start(kbc); 761 } 762 mutex_unlock(&kbc->idev->mutex); 763 764 return err; 765 } 766 #endif 767 768 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume); 769 770 static const struct of_device_id tegra_kbc_of_match[] = { 771 { .compatible = "nvidia,tegra20-kbc", }, 772 { }, 773 }; 774 MODULE_DEVICE_TABLE(of, tegra_kbc_of_match); 775 776 static struct platform_driver tegra_kbc_driver = { 777 .probe = tegra_kbc_probe, 778 .driver = { 779 .name = "tegra-kbc", 780 .owner = THIS_MODULE, 781 .pm = &tegra_kbc_pm_ops, 782 .of_match_table = tegra_kbc_of_match, 783 }, 784 }; 785 module_platform_driver(tegra_kbc_driver); 786 787 MODULE_LICENSE("GPL"); 788 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); 789 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); 790 MODULE_ALIAS("platform:tegra-kbc"); 791