1aef9ec39SRoland Dreier /* 2aef9ec39SRoland Dreier * Copyright (c) 2005 Cisco Systems. All rights reserved. 3aef9ec39SRoland Dreier * 4aef9ec39SRoland Dreier * This software is available to you under a choice of one of two 5aef9ec39SRoland Dreier * licenses. You may choose to be licensed under the terms of the GNU 6aef9ec39SRoland Dreier * General Public License (GPL) Version 2, available from the file 7aef9ec39SRoland Dreier * COPYING in the main directory of this source tree, or the 8aef9ec39SRoland Dreier * OpenIB.org BSD license below: 9aef9ec39SRoland Dreier * 10aef9ec39SRoland Dreier * Redistribution and use in source and binary forms, with or 11aef9ec39SRoland Dreier * without modification, are permitted provided that the following 12aef9ec39SRoland Dreier * conditions are met: 13aef9ec39SRoland Dreier * 14aef9ec39SRoland Dreier * - Redistributions of source code must retain the above 15aef9ec39SRoland Dreier * copyright notice, this list of conditions and the following 16aef9ec39SRoland Dreier * disclaimer. 17aef9ec39SRoland Dreier * 18aef9ec39SRoland Dreier * - Redistributions in binary form must reproduce the above 19aef9ec39SRoland Dreier * copyright notice, this list of conditions and the following 20aef9ec39SRoland Dreier * disclaimer in the documentation and/or other materials 21aef9ec39SRoland Dreier * provided with the distribution. 22aef9ec39SRoland Dreier * 23aef9ec39SRoland Dreier * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24aef9ec39SRoland Dreier * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25aef9ec39SRoland Dreier * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26aef9ec39SRoland Dreier * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27aef9ec39SRoland Dreier * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28aef9ec39SRoland Dreier * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29aef9ec39SRoland Dreier * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30aef9ec39SRoland Dreier * SOFTWARE. 31aef9ec39SRoland Dreier */ 32aef9ec39SRoland Dreier 33aef9ec39SRoland Dreier #ifndef IB_SRP_H 34aef9ec39SRoland Dreier #define IB_SRP_H 35aef9ec39SRoland Dreier 36aef9ec39SRoland Dreier #include <linux/types.h> 37aef9ec39SRoland Dreier #include <linux/list.h> 388e9e5f4fSIngo Molnar #include <linux/mutex.h> 39cf368713SRoland Dreier #include <linux/scatterlist.h> 40aef9ec39SRoland Dreier 41aef9ec39SRoland Dreier #include <scsi/scsi_host.h> 42aef9ec39SRoland Dreier #include <scsi/scsi_cmnd.h> 43aef9ec39SRoland Dreier 44aef9ec39SRoland Dreier #include <rdma/ib_verbs.h> 45aef9ec39SRoland Dreier #include <rdma/ib_sa.h> 46aef9ec39SRoland Dreier #include <rdma/ib_cm.h> 4719f31343SBart Van Assche #include <rdma/rdma_cm.h> 48aef9ec39SRoland Dreier 49aef9ec39SRoland Dreier enum { 50aef9ec39SRoland Dreier SRP_PATH_REC_TIMEOUT_MS = 1000, 51aef9ec39SRoland Dreier SRP_ABORT_TIMEOUT_MS = 5000, 52aef9ec39SRoland Dreier 53aef9ec39SRoland Dreier SRP_PORT_REDIRECT = 1, 54aef9ec39SRoland Dreier SRP_DLID_REDIRECT = 2, 559fe4bcf4SDavid Dillow SRP_STALE_CONN = 3, 56aef9ec39SRoland Dreier 5774b0a15bSVu Pham SRP_DEF_SG_TABLESIZE = 12, 58aef9ec39SRoland Dreier 594d73f95fSBart Van Assche SRP_DEFAULT_QUEUE_SIZE = 1 << 6, 60dd5e6e38SBart Van Assche SRP_RSP_SQ_SIZE = 1, 61dd5e6e38SBart Van Assche SRP_TSK_MGMT_SQ_SIZE = 1, 624d73f95fSBart Van Assche SRP_DEFAULT_CMD_SQ_SIZE = SRP_DEFAULT_QUEUE_SIZE - SRP_RSP_SQ_SIZE - 634d73f95fSBart Van Assche SRP_TSK_MGMT_SQ_SIZE, 64aef9ec39SRoland Dreier 65f8b6e31eSDavid Dillow SRP_TAG_NO_REQ = ~0U, 66f8b6e31eSDavid Dillow SRP_TAG_TSK_MGMT = 1U << 31, 67f5358a17SRoland Dreier 6852ede08fSBart Van Assche SRP_MAX_PAGES_PER_MR = 512, 69482fffc4SBart Van Assche 70482fffc4SBart Van Assche SRP_MAX_ADD_CDB_LEN = 16, 71882981f4SBart Van Assche 72882981f4SBart Van Assche SRP_MAX_IMM_SGE = 2, 73882981f4SBart Van Assche SRP_MAX_SGE = SRP_MAX_IMM_SGE + 1, 74882981f4SBart Van Assche /* 75882981f4SBart Van Assche * Choose the immediate data offset such that a 32 byte CDB still fits. 76882981f4SBart Van Assche */ 77882981f4SBart Van Assche SRP_IMM_DATA_OFFSET = sizeof(struct srp_cmd) + 78882981f4SBart Van Assche SRP_MAX_ADD_CDB_LEN + 79882981f4SBart Van Assche sizeof(struct srp_imm_buf), 80aef9ec39SRoland Dreier }; 81aef9ec39SRoland Dreier 82aef9ec39SRoland Dreier enum srp_target_state { 8334aa654eSBart Van Assche SRP_TARGET_SCANNING, 84aef9ec39SRoland Dreier SRP_TARGET_LIVE, 85ef6c49d8SBart Van Assche SRP_TARGET_REMOVED, 86aef9ec39SRoland Dreier }; 87aef9ec39SRoland Dreier 88bb12588aSDavid Dillow enum srp_iu_type { 89bb12588aSDavid Dillow SRP_IU_CMD, 90bb12588aSDavid Dillow SRP_IU_TSK_MGMT, 91bb12588aSDavid Dillow SRP_IU_RSP, 928cba2077SDavid Dillow }; 938cba2077SDavid Dillow 945cfb1782SBart Van Assche /* 955cfb1782SBart Van Assche * @mr_page_mask: HCA memory registration page mask. 965cfb1782SBart Van Assche * @mr_page_size: HCA memory registration page size. 97f273ad4fSMax Gurtovoy * @mr_max_size: Maximum size in bytes of a single FR registration request. 985cfb1782SBart Van Assche */ 99f5358a17SRoland Dreier struct srp_device { 100f5358a17SRoland Dreier struct list_head dev_list; 101aef9ec39SRoland Dreier struct ib_device *dev; 102aef9ec39SRoland Dreier struct ib_pd *pd; 103cee687b6SBart Van Assche u32 global_rkey; 10452ede08fSBart Van Assche u64 mr_page_mask; 10552ede08fSBart Van Assche int mr_page_size; 10652ede08fSBart Van Assche int mr_max_size; 10752ede08fSBart Van Assche int max_pages_per_mr; 1085cfb1782SBart Van Assche bool has_fr; 1095cfb1782SBart Van Assche bool use_fast_reg; 110f5358a17SRoland Dreier }; 111f5358a17SRoland Dreier 112f5358a17SRoland Dreier struct srp_host { 11305321937SGreg Kroah-Hartman struct srp_device *srp_dev; 114f5358a17SRoland Dreier u8 port; 115ee959b00STony Jones struct device dev; 116aef9ec39SRoland Dreier struct list_head target_list; 117b3589fd4SMatthew Wilcox spinlock_t target_lock; 118aef9ec39SRoland Dreier struct completion released; 119aef9ec39SRoland Dreier struct list_head list; 1202d7091bcSBart Van Assche struct mutex add_target_mutex; 121aef9ec39SRoland Dreier }; 122aef9ec39SRoland Dreier 123aef9ec39SRoland Dreier struct srp_request { 124aef9ec39SRoland Dreier struct scsi_cmnd *scmnd; 125aef9ec39SRoland Dreier struct srp_iu *cmd; 1265cfb1782SBart Van Assche struct srp_fr_desc **fr_list; 127c07d424dSDavid Dillow struct srp_direct_buf *indirect_desc; 128c07d424dSDavid Dillow dma_addr_t indirect_dma_addr; 12952ede08fSBart Van Assche short nmdesc; 1301dc7b1f1SChristoph Hellwig struct ib_cqe reg_cqe; 131aef9ec39SRoland Dreier }; 132aef9ec39SRoland Dreier 133509c07bcSBart Van Assche /** 134509c07bcSBart Van Assche * struct srp_rdma_ch 135509c07bcSBart Van Assche * @comp_vector: Completion vector used by this RDMA channel. 136513d5647SBart Van Assche * @max_it_iu_len: Maximum initiator-to-target information unit length. 1374f6d498cSBart Van Assche * @max_ti_iu_len: Maximum target-to-initiator information unit length. 138509c07bcSBart Van Assche */ 139509c07bcSBart Van Assche struct srp_rdma_ch { 1409af76271SDavid Dillow /* These are RW in the hot path, and commonly used together */ 1419af76271SDavid Dillow struct list_head free_tx; 1429af76271SDavid Dillow spinlock_t lock; 1439af76271SDavid Dillow s32 req_lim; 1449af76271SDavid Dillow 1459af76271SDavid Dillow /* These are read-only in the hot path */ 146509c07bcSBart Van Assche struct srp_target_port *target ____cacheline_aligned_in_smp; 147509c07bcSBart Van Assche struct ib_cq *send_cq; 1489af76271SDavid Dillow struct ib_cq *recv_cq; 1499af76271SDavid Dillow struct ib_qp *qp; 1505cfb1782SBart Van Assche struct srp_fr_pool *fr_pool; 151513d5647SBart Van Assche uint32_t max_it_iu_len; 1524f6d498cSBart Van Assche uint32_t max_ti_iu_len; 153bf583470SBart Van Assche u8 max_imm_sge; 154882981f4SBart Van Assche bool use_imm_data; 155509c07bcSBart Van Assche 156509c07bcSBart Van Assche /* Everything above this point is used in the hot path of 157509c07bcSBart Van Assche * command processing. Try to keep them packed into cachelines. 158509c07bcSBart Van Assche */ 159509c07bcSBart Van Assche 160509c07bcSBart Van Assche struct completion done; 161509c07bcSBart Van Assche int status; 162509c07bcSBart Van Assche 16319f31343SBart Van Assche union { 16419f31343SBart Van Assche struct ib_cm { 165c2f8fc4eSDasaratharaman Chandramouli struct sa_path_rec path; 166509c07bcSBart Van Assche struct ib_sa_query *path_query; 167509c07bcSBart Van Assche int path_query_id; 168509c07bcSBart Van Assche struct ib_cm_id *cm_id; 16919f31343SBart Van Assche } ib_cm; 17019f31343SBart Van Assche struct rdma_cm { 17119f31343SBart Van Assche struct rdma_cm_id *cm_id; 17219f31343SBart Van Assche } rdma_cm; 17319f31343SBart Van Assche }; 17419f31343SBart Van Assche 175509c07bcSBart Van Assche struct srp_iu **tx_ring; 176509c07bcSBart Van Assche struct srp_iu **rx_ring; 177509c07bcSBart Van Assche struct srp_request *req_ring; 178509c07bcSBart Van Assche int comp_vector; 179509c07bcSBart Van Assche 1800a6fdbdeSBart Van Assche u64 tsk_mgmt_tag; 181509c07bcSBart Van Assche struct completion tsk_mgmt_done; 182509c07bcSBart Van Assche u8 tsk_mgmt_status; 183c014c8cdSBart Van Assche bool connected; 184509c07bcSBart Van Assche }; 185509c07bcSBart Van Assche 186509c07bcSBart Van Assche /** 187509c07bcSBart Van Assche * struct srp_target_port 188509c07bcSBart Van Assche * @comp_vector: Completion vector used by the first RDMA channel created for 189509c07bcSBart Van Assche * this target port. 190509c07bcSBart Van Assche */ 191509c07bcSBart Van Assche struct srp_target_port { 192509c07bcSBart Van Assche /* read and written in the hot path */ 193509c07bcSBart Van Assche spinlock_t lock; 194509c07bcSBart Van Assche 195509c07bcSBart Van Assche /* read only in the hot path */ 196cee687b6SBart Van Assche u32 global_rkey; 197d92c0da7SBart Van Assche struct srp_rdma_ch *ch; 19819f31343SBart Van Assche struct net *net; 199d92c0da7SBart Van Assche u32 ch_count; 2009af76271SDavid Dillow u32 lkey; 2019af76271SDavid Dillow enum srp_target_state state; 202547ed331SHonggang Li uint32_t max_it_iu_size; 20349248644SDavid Dillow unsigned int cmd_sg_cnt; 204c07d424dSDavid Dillow unsigned int indirect_size; 205c07d424dSDavid Dillow bool allow_ext_sg; 2069af76271SDavid Dillow 207509c07bcSBart Van Assche /* other member variables */ 208747fe000SBart Van Assche union ib_gid sgid; 209aef9ec39SRoland Dreier __be64 id_ext; 210aef9ec39SRoland Dreier __be64 ioc_guid; 21101cb9bcbSIshai Rabinovitz __be64 initiator_ext; 2120c0450dbSRamachandra K u16 io_class; 213aef9ec39SRoland Dreier struct srp_host *srp_host; 214aef9ec39SRoland Dreier struct Scsi_Host *scsi_host; 2159dd69a60SBart Van Assche struct srp_rport *rport; 216aef9ec39SRoland Dreier char target_name[32]; 217aef9ec39SRoland Dreier unsigned int scsi_id; 218c07d424dSDavid Dillow unsigned int sg_tablesize; 219b0780ee5SBart Van Assche unsigned int target_can_queue; 220fa9863f8SBart Van Assche int mr_pool_size; 221509c5f33SBart Van Assche int mr_per_cmd; 2224d73f95fSBart Van Assche int queue_size; 2234d73f95fSBart Van Assche int req_ring_size; 2244b5e5f41SBart Van Assche int comp_vector; 2257bb312e4SVu Pham int tl_retry_count; 226aef9ec39SRoland Dreier 22719f31343SBart Van Assche bool using_rdma_cm; 22819f31343SBart Van Assche 22919f31343SBart Van Assche union { 23019f31343SBart Van Assche struct { 23119f31343SBart Van Assche __be64 service_id; 232747fe000SBart Van Assche union ib_gid orig_dgid; 233747fe000SBart Van Assche __be16 pkey; 23419f31343SBart Van Assche } ib_cm; 23519f31343SBart Van Assche struct { 23619f31343SBart Van Assche union { 23719f31343SBart Van Assche struct sockaddr_in ip4; 23819f31343SBart Van Assche struct sockaddr_in6 ip6; 23914673778SBart Van Assche struct sockaddr sa; 24019f31343SBart Van Assche struct sockaddr_storage ss; 24119f31343SBart Van Assche } src; 24219f31343SBart Van Assche union { 24319f31343SBart Van Assche struct sockaddr_in ip4; 24419f31343SBart Van Assche struct sockaddr_in6 ip6; 24514673778SBart Van Assche struct sockaddr sa; 24619f31343SBart Van Assche struct sockaddr_storage ss; 24719f31343SBart Van Assche } dst; 24819f31343SBart Van Assche bool src_specified; 24919f31343SBart Van Assche } rdma_cm; 25019f31343SBart Van Assche }; 251aef9ec39SRoland Dreier 252c9b03c1aSBart Van Assche u32 rq_tmo_jiffies; 253c9b03c1aSBart Van Assche 2546bfa24faSRoland Dreier int zero_req_lim; 2556bfa24faSRoland Dreier 256c1120f89SBart Van Assche struct work_struct tl_err_work; 257ef6c49d8SBart Van Assche struct work_struct remove_work; 258aef9ec39SRoland Dreier 259aef9ec39SRoland Dreier struct list_head list; 260948d1e88SBart Van Assche bool qp_in_error; 261aef9ec39SRoland Dreier }; 262aef9ec39SRoland Dreier 263aef9ec39SRoland Dreier struct srp_iu { 264dcb4cb85SBart Van Assche struct list_head list; 26585507bccSRalph Campbell u64 dma; 266aef9ec39SRoland Dreier void *buf; 267aef9ec39SRoland Dreier size_t size; 268aef9ec39SRoland Dreier enum dma_data_direction direction; 269882981f4SBart Van Assche u32 num_sge; 270882981f4SBart Van Assche struct ib_sge sge[SRP_MAX_SGE]; 2711dc7b1f1SChristoph Hellwig struct ib_cqe cqe; 272aef9ec39SRoland Dreier }; 273aef9ec39SRoland Dreier 2745cfb1782SBart Van Assche /** 2755cfb1782SBart Van Assche * struct srp_fr_desc - fast registration work request arguments 2765cfb1782SBart Van Assche * @entry: Entry in srp_fr_pool.free_list. 2775cfb1782SBart Van Assche * @mr: Memory region. 2785cfb1782SBart Van Assche * @frpl: Fast registration page list. 2795cfb1782SBart Van Assche */ 2805cfb1782SBart Van Assche struct srp_fr_desc { 2815cfb1782SBart Van Assche struct list_head entry; 2825cfb1782SBart Van Assche struct ib_mr *mr; 2835cfb1782SBart Van Assche }; 2845cfb1782SBart Van Assche 2855cfb1782SBart Van Assche /** 2865cfb1782SBart Van Assche * struct srp_fr_pool - pool of fast registration descriptors 2875cfb1782SBart Van Assche * 2885cfb1782SBart Van Assche * An entry is available for allocation if and only if it occurs in @free_list. 2895cfb1782SBart Van Assche * 2905cfb1782SBart Van Assche * @size: Number of descriptors in this pool. 2915cfb1782SBart Van Assche * @max_page_list_len: Maximum fast registration work request page list length. 2925cfb1782SBart Van Assche * @lock: Protects free_list. 2935cfb1782SBart Van Assche * @free_list: List of free descriptors. 2945cfb1782SBart Van Assche * @desc: Fast registration descriptor pool. 2955cfb1782SBart Van Assche */ 2965cfb1782SBart Van Assche struct srp_fr_pool { 2975cfb1782SBart Van Assche int size; 2985cfb1782SBart Van Assche int max_page_list_len; 2995cfb1782SBart Van Assche spinlock_t lock; 3005cfb1782SBart Van Assche struct list_head free_list; 3015b361328SGustavo A. R. Silva struct srp_fr_desc desc[]; 3025cfb1782SBart Van Assche }; 3035cfb1782SBart Van Assche 3045cfb1782SBart Van Assche /** 3055cfb1782SBart Van Assche * struct srp_map_state - per-request DMA memory mapping state 3065cfb1782SBart Van Assche * @desc: Pointer to the element of the SRP buffer descriptor array 3075cfb1782SBart Van Assche * that is being filled in. 3085cfb1782SBart Van Assche * @pages: Array with DMA addresses of pages being considered for 3095cfb1782SBart Van Assche * memory registration. 3105cfb1782SBart Van Assche * @base_dma_addr: DMA address of the first page that has not yet been mapped. 311f273ad4fSMax Gurtovoy * @dma_len: Number of bytes that will be registered with the next FR 312f273ad4fSMax Gurtovoy * memory registration call. 3135cfb1782SBart Van Assche * @total_len: Total number of bytes in the sg-list being mapped. 3145cfb1782SBart Van Assche * @npages: Number of page addresses in the pages[] array. 315f273ad4fSMax Gurtovoy * @nmdesc: Number of FR memory descriptors used for mapping. 3165cfb1782SBart Van Assche * @ndesc: Number of SRP buffer descriptors that have been filled in. 3175cfb1782SBart Van Assche */ 3188f26c9ffSDavid Dillow struct srp_map_state { 3195cfb1782SBart Van Assche union { 320f731ed62SBart Van Assche struct { 321f731ed62SBart Van Assche struct srp_fr_desc **next; 322f731ed62SBart Van Assche struct srp_fr_desc **end; 323f731ed62SBart Van Assche } fr; 324330179f2SBart Van Assche struct { 325330179f2SBart Van Assche void **next; 326330179f2SBart Van Assche void **end; 327330179f2SBart Van Assche } gen; 3285cfb1782SBart Van Assche }; 3298f26c9ffSDavid Dillow struct srp_direct_buf *desc; 330f7f7aab1SSagi Grimberg union { 3318f26c9ffSDavid Dillow u64 *pages; 332f7f7aab1SSagi Grimberg struct scatterlist *sg; 333f7f7aab1SSagi Grimberg }; 3348f26c9ffSDavid Dillow dma_addr_t base_dma_addr; 33552ede08fSBart Van Assche u32 dma_len; 3368f26c9ffSDavid Dillow u32 total_len; 3378f26c9ffSDavid Dillow unsigned int npages; 33852ede08fSBart Van Assche unsigned int nmdesc; 3398f26c9ffSDavid Dillow unsigned int ndesc; 3408f26c9ffSDavid Dillow }; 3418f26c9ffSDavid Dillow 342aef9ec39SRoland Dreier #endif /* IB_SRP_H */ 343