1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 /* Copyright (c) 2008-2019, IBM Corporation */ 5 6 #include <linux/errno.h> 7 #include <linux/types.h> 8 #include <linux/uaccess.h> 9 #include <linux/vmalloc.h> 10 #include <linux/xarray.h> 11 12 #include <rdma/iw_cm.h> 13 #include <rdma/ib_verbs.h> 14 #include <rdma/ib_user_verbs.h> 15 #include <rdma/uverbs_ioctl.h> 16 17 #include "siw.h" 18 #include "siw_verbs.h" 19 #include "siw_mem.h" 20 21 static int ib_qp_state_to_siw_qp_state[IB_QPS_ERR + 1] = { 22 [IB_QPS_RESET] = SIW_QP_STATE_IDLE, 23 [IB_QPS_INIT] = SIW_QP_STATE_IDLE, 24 [IB_QPS_RTR] = SIW_QP_STATE_RTR, 25 [IB_QPS_RTS] = SIW_QP_STATE_RTS, 26 [IB_QPS_SQD] = SIW_QP_STATE_CLOSING, 27 [IB_QPS_SQE] = SIW_QP_STATE_TERMINATE, 28 [IB_QPS_ERR] = SIW_QP_STATE_ERROR 29 }; 30 31 static char ib_qp_state_to_string[IB_QPS_ERR + 1][sizeof("RESET")] = { 32 [IB_QPS_RESET] = "RESET", [IB_QPS_INIT] = "INIT", [IB_QPS_RTR] = "RTR", 33 [IB_QPS_RTS] = "RTS", [IB_QPS_SQD] = "SQD", [IB_QPS_SQE] = "SQE", 34 [IB_QPS_ERR] = "ERR" 35 }; 36 37 void siw_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 38 { 39 struct siw_user_mmap_entry *entry = to_siw_mmap_entry(rdma_entry); 40 41 kfree(entry); 42 } 43 44 int siw_mmap(struct ib_ucontext *ctx, struct vm_area_struct *vma) 45 { 46 struct siw_ucontext *uctx = to_siw_ctx(ctx); 47 size_t size = vma->vm_end - vma->vm_start; 48 struct rdma_user_mmap_entry *rdma_entry; 49 struct siw_user_mmap_entry *entry; 50 int rv = -EINVAL; 51 52 /* 53 * Must be page aligned 54 */ 55 if (vma->vm_start & (PAGE_SIZE - 1)) { 56 pr_warn("siw: mmap not page aligned\n"); 57 return -EINVAL; 58 } 59 rdma_entry = rdma_user_mmap_entry_get(&uctx->base_ucontext, vma); 60 if (!rdma_entry) { 61 siw_dbg(&uctx->sdev->base_dev, "mmap lookup failed: %lu, %#zx\n", 62 vma->vm_pgoff, size); 63 return -EINVAL; 64 } 65 entry = to_siw_mmap_entry(rdma_entry); 66 67 rv = remap_vmalloc_range(vma, entry->address, 0); 68 if (rv) { 69 pr_warn("remap_vmalloc_range failed: %lu, %zu\n", vma->vm_pgoff, 70 size); 71 goto out; 72 } 73 out: 74 rdma_user_mmap_entry_put(rdma_entry); 75 76 return rv; 77 } 78 79 int siw_alloc_ucontext(struct ib_ucontext *base_ctx, struct ib_udata *udata) 80 { 81 struct siw_device *sdev = to_siw_dev(base_ctx->device); 82 struct siw_ucontext *ctx = to_siw_ctx(base_ctx); 83 struct siw_uresp_alloc_ctx uresp = {}; 84 int rv; 85 86 if (atomic_inc_return(&sdev->num_ctx) > SIW_MAX_CONTEXT) { 87 rv = -ENOMEM; 88 goto err_out; 89 } 90 ctx->sdev = sdev; 91 92 uresp.dev_id = sdev->vendor_part_id; 93 94 if (udata->outlen < sizeof(uresp)) { 95 rv = -EINVAL; 96 goto err_out; 97 } 98 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 99 if (rv) 100 goto err_out; 101 102 siw_dbg(base_ctx->device, "success. now %d context(s)\n", 103 atomic_read(&sdev->num_ctx)); 104 105 return 0; 106 107 err_out: 108 atomic_dec(&sdev->num_ctx); 109 siw_dbg(base_ctx->device, "failure %d. now %d context(s)\n", rv, 110 atomic_read(&sdev->num_ctx)); 111 112 return rv; 113 } 114 115 void siw_dealloc_ucontext(struct ib_ucontext *base_ctx) 116 { 117 struct siw_ucontext *uctx = to_siw_ctx(base_ctx); 118 119 atomic_dec(&uctx->sdev->num_ctx); 120 } 121 122 int siw_query_device(struct ib_device *base_dev, struct ib_device_attr *attr, 123 struct ib_udata *udata) 124 { 125 struct siw_device *sdev = to_siw_dev(base_dev); 126 127 if (udata->inlen || udata->outlen) 128 return -EINVAL; 129 130 memset(attr, 0, sizeof(*attr)); 131 132 /* Revisit atomic caps if RFC 7306 gets supported */ 133 attr->atomic_cap = 0; 134 attr->device_cap_flags = 135 IB_DEVICE_MEM_MGT_EXTENSIONS | IB_DEVICE_ALLOW_USER_UNREG; 136 attr->max_cq = sdev->attrs.max_cq; 137 attr->max_cqe = sdev->attrs.max_cqe; 138 attr->max_fast_reg_page_list_len = SIW_MAX_SGE_PBL; 139 attr->max_fmr = sdev->attrs.max_fmr; 140 attr->max_mr = sdev->attrs.max_mr; 141 attr->max_mw = sdev->attrs.max_mw; 142 attr->max_mr_size = ~0ull; 143 attr->max_pd = sdev->attrs.max_pd; 144 attr->max_qp = sdev->attrs.max_qp; 145 attr->max_qp_init_rd_atom = sdev->attrs.max_ird; 146 attr->max_qp_rd_atom = sdev->attrs.max_ord; 147 attr->max_qp_wr = sdev->attrs.max_qp_wr; 148 attr->max_recv_sge = sdev->attrs.max_sge; 149 attr->max_res_rd_atom = sdev->attrs.max_qp * sdev->attrs.max_ird; 150 attr->max_send_sge = sdev->attrs.max_sge; 151 attr->max_sge_rd = sdev->attrs.max_sge_rd; 152 attr->max_srq = sdev->attrs.max_srq; 153 attr->max_srq_sge = sdev->attrs.max_srq_sge; 154 attr->max_srq_wr = sdev->attrs.max_srq_wr; 155 attr->page_size_cap = PAGE_SIZE; 156 attr->vendor_id = SIW_VENDOR_ID; 157 attr->vendor_part_id = sdev->vendor_part_id; 158 159 memcpy(&attr->sys_image_guid, sdev->netdev->dev_addr, 6); 160 161 return 0; 162 } 163 164 int siw_query_port(struct ib_device *base_dev, u8 port, 165 struct ib_port_attr *attr) 166 { 167 struct siw_device *sdev = to_siw_dev(base_dev); 168 169 memset(attr, 0, sizeof(*attr)); 170 171 attr->active_mtu = attr->max_mtu; 172 attr->active_speed = 2; 173 attr->active_width = 2; 174 attr->gid_tbl_len = 1; 175 attr->max_msg_sz = -1; 176 attr->max_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 177 attr->phys_state = sdev->state == IB_PORT_ACTIVE ? 178 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 179 attr->pkey_tbl_len = 1; 180 attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP; 181 attr->state = sdev->state; 182 /* 183 * All zero 184 * 185 * attr->lid = 0; 186 * attr->bad_pkey_cntr = 0; 187 * attr->qkey_viol_cntr = 0; 188 * attr->sm_lid = 0; 189 * attr->lmc = 0; 190 * attr->max_vl_num = 0; 191 * attr->sm_sl = 0; 192 * attr->subnet_timeout = 0; 193 * attr->init_type_repy = 0; 194 */ 195 return 0; 196 } 197 198 int siw_get_port_immutable(struct ib_device *base_dev, u8 port, 199 struct ib_port_immutable *port_immutable) 200 { 201 struct ib_port_attr attr; 202 int rv = siw_query_port(base_dev, port, &attr); 203 204 if (rv) 205 return rv; 206 207 port_immutable->pkey_tbl_len = attr.pkey_tbl_len; 208 port_immutable->gid_tbl_len = attr.gid_tbl_len; 209 port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 210 211 return 0; 212 } 213 214 int siw_query_pkey(struct ib_device *base_dev, u8 port, u16 idx, u16 *pkey) 215 { 216 /* Report the default pkey */ 217 *pkey = 0xffff; 218 return 0; 219 } 220 221 int siw_query_gid(struct ib_device *base_dev, u8 port, int idx, 222 union ib_gid *gid) 223 { 224 struct siw_device *sdev = to_siw_dev(base_dev); 225 226 /* subnet_prefix == interface_id == 0; */ 227 memset(gid, 0, sizeof(*gid)); 228 memcpy(&gid->raw[0], sdev->netdev->dev_addr, 6); 229 230 return 0; 231 } 232 233 int siw_alloc_pd(struct ib_pd *pd, struct ib_udata *udata) 234 { 235 struct siw_device *sdev = to_siw_dev(pd->device); 236 237 if (atomic_inc_return(&sdev->num_pd) > SIW_MAX_PD) { 238 atomic_dec(&sdev->num_pd); 239 return -ENOMEM; 240 } 241 siw_dbg_pd(pd, "now %d PD's(s)\n", atomic_read(&sdev->num_pd)); 242 243 return 0; 244 } 245 246 void siw_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 247 { 248 struct siw_device *sdev = to_siw_dev(pd->device); 249 250 siw_dbg_pd(pd, "free PD\n"); 251 atomic_dec(&sdev->num_pd); 252 } 253 254 void siw_qp_get_ref(struct ib_qp *base_qp) 255 { 256 siw_qp_get(to_siw_qp(base_qp)); 257 } 258 259 void siw_qp_put_ref(struct ib_qp *base_qp) 260 { 261 siw_qp_put(to_siw_qp(base_qp)); 262 } 263 264 static struct rdma_user_mmap_entry * 265 siw_mmap_entry_insert(struct siw_ucontext *uctx, 266 void *address, size_t length, 267 u64 *offset) 268 { 269 struct siw_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); 270 int rv; 271 272 *offset = SIW_INVAL_UOBJ_KEY; 273 if (!entry) 274 return NULL; 275 276 entry->address = address; 277 278 rv = rdma_user_mmap_entry_insert(&uctx->base_ucontext, 279 &entry->rdma_entry, 280 length); 281 if (rv) { 282 kfree(entry); 283 return NULL; 284 } 285 286 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 287 288 return &entry->rdma_entry; 289 } 290 291 /* 292 * siw_create_qp() 293 * 294 * Create QP of requested size on given device. 295 * 296 * @pd: Protection Domain 297 * @attrs: Initial QP attributes. 298 * @udata: used to provide QP ID, SQ and RQ size back to user. 299 */ 300 301 struct ib_qp *siw_create_qp(struct ib_pd *pd, 302 struct ib_qp_init_attr *attrs, 303 struct ib_udata *udata) 304 { 305 struct siw_qp *qp = NULL; 306 struct siw_base_qp *siw_base_qp = NULL; 307 struct ib_device *base_dev = pd->device; 308 struct siw_device *sdev = to_siw_dev(base_dev); 309 struct siw_ucontext *uctx = 310 rdma_udata_to_drv_context(udata, struct siw_ucontext, 311 base_ucontext); 312 struct siw_cq *scq = NULL, *rcq = NULL; 313 unsigned long flags; 314 int num_sqe, num_rqe, rv = 0; 315 size_t length; 316 317 siw_dbg(base_dev, "create new QP\n"); 318 319 if (atomic_inc_return(&sdev->num_qp) > SIW_MAX_QP) { 320 siw_dbg(base_dev, "too many QP's\n"); 321 rv = -ENOMEM; 322 goto err_out; 323 } 324 if (attrs->qp_type != IB_QPT_RC) { 325 siw_dbg(base_dev, "only RC QP's supported\n"); 326 rv = -EINVAL; 327 goto err_out; 328 } 329 if ((attrs->cap.max_send_wr > SIW_MAX_QP_WR) || 330 (attrs->cap.max_recv_wr > SIW_MAX_QP_WR) || 331 (attrs->cap.max_send_sge > SIW_MAX_SGE) || 332 (attrs->cap.max_recv_sge > SIW_MAX_SGE)) { 333 siw_dbg(base_dev, "QP size error\n"); 334 rv = -EINVAL; 335 goto err_out; 336 } 337 if (attrs->cap.max_inline_data > SIW_MAX_INLINE) { 338 siw_dbg(base_dev, "max inline send: %d > %d\n", 339 attrs->cap.max_inline_data, (int)SIW_MAX_INLINE); 340 rv = -EINVAL; 341 goto err_out; 342 } 343 /* 344 * NOTE: we allow for zero element SQ and RQ WQE's SGL's 345 * but not for a QP unable to hold any WQE (SQ + RQ) 346 */ 347 if (attrs->cap.max_send_wr + attrs->cap.max_recv_wr == 0) { 348 siw_dbg(base_dev, "QP must have send or receive queue\n"); 349 rv = -EINVAL; 350 goto err_out; 351 } 352 scq = to_siw_cq(attrs->send_cq); 353 rcq = to_siw_cq(attrs->recv_cq); 354 355 if (!scq || (!rcq && !attrs->srq)) { 356 siw_dbg(base_dev, "send CQ or receive CQ invalid\n"); 357 rv = -EINVAL; 358 goto err_out; 359 } 360 siw_base_qp = kzalloc(sizeof(*siw_base_qp), GFP_KERNEL); 361 if (!siw_base_qp) { 362 rv = -ENOMEM; 363 goto err_out; 364 } 365 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 366 if (!qp) { 367 rv = -ENOMEM; 368 goto err_out; 369 } 370 siw_base_qp->qp = qp; 371 qp->ib_qp = &siw_base_qp->base_qp; 372 373 init_rwsem(&qp->state_lock); 374 spin_lock_init(&qp->sq_lock); 375 spin_lock_init(&qp->rq_lock); 376 spin_lock_init(&qp->orq_lock); 377 378 qp->kernel_verbs = !udata; 379 380 rv = siw_qp_add(sdev, qp); 381 if (rv) 382 goto err_out; 383 384 /* All queue indices are derived from modulo operations 385 * on a free running 'get' (consumer) and 'put' (producer) 386 * unsigned counter. Having queue sizes at power of two 387 * avoids handling counter wrap around. 388 */ 389 num_sqe = roundup_pow_of_two(attrs->cap.max_send_wr); 390 num_rqe = roundup_pow_of_two(attrs->cap.max_recv_wr); 391 392 if (qp->kernel_verbs) 393 qp->sendq = vzalloc(num_sqe * sizeof(struct siw_sqe)); 394 else 395 qp->sendq = vmalloc_user(num_sqe * sizeof(struct siw_sqe)); 396 397 if (qp->sendq == NULL) { 398 siw_dbg(base_dev, "SQ size %d alloc failed\n", num_sqe); 399 rv = -ENOMEM; 400 goto err_out_xa; 401 } 402 if (attrs->sq_sig_type != IB_SIGNAL_REQ_WR) { 403 if (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) 404 qp->attrs.flags |= SIW_SIGNAL_ALL_WR; 405 else { 406 rv = -EINVAL; 407 goto err_out_xa; 408 } 409 } 410 qp->pd = pd; 411 qp->scq = scq; 412 qp->rcq = rcq; 413 414 if (attrs->srq) { 415 /* 416 * SRQ support. 417 * Verbs 6.3.7: ignore RQ size, if SRQ present 418 * Verbs 6.3.5: do not check PD of SRQ against PD of QP 419 */ 420 qp->srq = to_siw_srq(attrs->srq); 421 qp->attrs.rq_size = 0; 422 siw_dbg(base_dev, "QP [%u]: SRQ attached\n", qp->qp_num); 423 } else if (num_rqe) { 424 if (qp->kernel_verbs) 425 qp->recvq = vzalloc(num_rqe * sizeof(struct siw_rqe)); 426 else 427 qp->recvq = 428 vmalloc_user(num_rqe * sizeof(struct siw_rqe)); 429 430 if (qp->recvq == NULL) { 431 siw_dbg(base_dev, "RQ size %d alloc failed\n", num_rqe); 432 rv = -ENOMEM; 433 goto err_out_xa; 434 } 435 qp->attrs.rq_size = num_rqe; 436 } 437 qp->attrs.sq_size = num_sqe; 438 qp->attrs.sq_max_sges = attrs->cap.max_send_sge; 439 qp->attrs.rq_max_sges = attrs->cap.max_recv_sge; 440 441 /* Make those two tunables fixed for now. */ 442 qp->tx_ctx.gso_seg_limit = 1; 443 qp->tx_ctx.zcopy_tx = zcopy_tx; 444 445 qp->attrs.state = SIW_QP_STATE_IDLE; 446 447 if (udata) { 448 struct siw_uresp_create_qp uresp = {}; 449 450 uresp.num_sqe = num_sqe; 451 uresp.num_rqe = num_rqe; 452 uresp.qp_id = qp_id(qp); 453 454 if (qp->sendq) { 455 length = num_sqe * sizeof(struct siw_sqe); 456 qp->sq_entry = 457 siw_mmap_entry_insert(uctx, qp->sendq, 458 length, &uresp.sq_key); 459 if (!qp->sq_entry) { 460 rv = -ENOMEM; 461 goto err_out_xa; 462 } 463 } 464 465 if (qp->recvq) { 466 length = num_rqe * sizeof(struct siw_rqe); 467 qp->rq_entry = 468 siw_mmap_entry_insert(uctx, qp->recvq, 469 length, &uresp.rq_key); 470 if (!qp->rq_entry) { 471 uresp.sq_key = SIW_INVAL_UOBJ_KEY; 472 rv = -ENOMEM; 473 goto err_out_xa; 474 } 475 } 476 477 if (udata->outlen < sizeof(uresp)) { 478 rv = -EINVAL; 479 goto err_out_xa; 480 } 481 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 482 if (rv) 483 goto err_out_xa; 484 } 485 qp->tx_cpu = siw_get_tx_cpu(sdev); 486 if (qp->tx_cpu < 0) { 487 rv = -EINVAL; 488 goto err_out_xa; 489 } 490 INIT_LIST_HEAD(&qp->devq); 491 spin_lock_irqsave(&sdev->lock, flags); 492 list_add_tail(&qp->devq, &sdev->qp_list); 493 spin_unlock_irqrestore(&sdev->lock, flags); 494 495 return qp->ib_qp; 496 497 err_out_xa: 498 xa_erase(&sdev->qp_xa, qp_id(qp)); 499 err_out: 500 kfree(siw_base_qp); 501 502 if (qp) { 503 if (uctx) { 504 rdma_user_mmap_entry_remove(qp->sq_entry); 505 rdma_user_mmap_entry_remove(qp->rq_entry); 506 } 507 vfree(qp->sendq); 508 vfree(qp->recvq); 509 kfree(qp); 510 } 511 atomic_dec(&sdev->num_qp); 512 513 return ERR_PTR(rv); 514 } 515 516 /* 517 * Minimum siw_query_qp() verb interface. 518 * 519 * @qp_attr_mask is not used but all available information is provided 520 */ 521 int siw_query_qp(struct ib_qp *base_qp, struct ib_qp_attr *qp_attr, 522 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 523 { 524 struct siw_qp *qp; 525 struct siw_device *sdev; 526 527 if (base_qp && qp_attr && qp_init_attr) { 528 qp = to_siw_qp(base_qp); 529 sdev = to_siw_dev(base_qp->device); 530 } else { 531 return -EINVAL; 532 } 533 qp_attr->cap.max_inline_data = SIW_MAX_INLINE; 534 qp_attr->cap.max_send_wr = qp->attrs.sq_size; 535 qp_attr->cap.max_send_sge = qp->attrs.sq_max_sges; 536 qp_attr->cap.max_recv_wr = qp->attrs.rq_size; 537 qp_attr->cap.max_recv_sge = qp->attrs.rq_max_sges; 538 qp_attr->path_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 539 qp_attr->max_rd_atomic = qp->attrs.irq_size; 540 qp_attr->max_dest_rd_atomic = qp->attrs.orq_size; 541 542 qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE | 543 IB_ACCESS_REMOTE_WRITE | 544 IB_ACCESS_REMOTE_READ; 545 546 qp_init_attr->qp_type = base_qp->qp_type; 547 qp_init_attr->send_cq = base_qp->send_cq; 548 qp_init_attr->recv_cq = base_qp->recv_cq; 549 qp_init_attr->srq = base_qp->srq; 550 551 qp_init_attr->cap = qp_attr->cap; 552 553 return 0; 554 } 555 556 int siw_verbs_modify_qp(struct ib_qp *base_qp, struct ib_qp_attr *attr, 557 int attr_mask, struct ib_udata *udata) 558 { 559 struct siw_qp_attrs new_attrs; 560 enum siw_qp_attr_mask siw_attr_mask = 0; 561 struct siw_qp *qp = to_siw_qp(base_qp); 562 int rv = 0; 563 564 if (!attr_mask) 565 return 0; 566 567 memset(&new_attrs, 0, sizeof(new_attrs)); 568 569 if (attr_mask & IB_QP_ACCESS_FLAGS) { 570 siw_attr_mask = SIW_QP_ATTR_ACCESS_FLAGS; 571 572 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 573 new_attrs.flags |= SIW_RDMA_READ_ENABLED; 574 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 575 new_attrs.flags |= SIW_RDMA_WRITE_ENABLED; 576 if (attr->qp_access_flags & IB_ACCESS_MW_BIND) 577 new_attrs.flags |= SIW_RDMA_BIND_ENABLED; 578 } 579 if (attr_mask & IB_QP_STATE) { 580 siw_dbg_qp(qp, "desired IB QP state: %s\n", 581 ib_qp_state_to_string[attr->qp_state]); 582 583 new_attrs.state = ib_qp_state_to_siw_qp_state[attr->qp_state]; 584 585 if (new_attrs.state > SIW_QP_STATE_RTS) 586 qp->tx_ctx.tx_suspend = 1; 587 588 siw_attr_mask |= SIW_QP_ATTR_STATE; 589 } 590 if (!siw_attr_mask) 591 goto out; 592 593 down_write(&qp->state_lock); 594 595 rv = siw_qp_modify(qp, &new_attrs, siw_attr_mask); 596 597 up_write(&qp->state_lock); 598 out: 599 return rv; 600 } 601 602 int siw_destroy_qp(struct ib_qp *base_qp, struct ib_udata *udata) 603 { 604 struct siw_qp *qp = to_siw_qp(base_qp); 605 struct siw_ucontext *uctx = 606 rdma_udata_to_drv_context(udata, struct siw_ucontext, 607 base_ucontext); 608 struct siw_qp_attrs qp_attrs; 609 610 siw_dbg_qp(qp, "state %d\n", qp->attrs.state); 611 612 /* 613 * Mark QP as in process of destruction to prevent from 614 * any async callbacks to RDMA core 615 */ 616 qp->attrs.flags |= SIW_QP_IN_DESTROY; 617 qp->rx_stream.rx_suspend = 1; 618 619 if (uctx) { 620 rdma_user_mmap_entry_remove(qp->sq_entry); 621 rdma_user_mmap_entry_remove(qp->rq_entry); 622 } 623 624 down_write(&qp->state_lock); 625 626 qp_attrs.state = SIW_QP_STATE_ERROR; 627 siw_qp_modify(qp, &qp_attrs, SIW_QP_ATTR_STATE); 628 629 if (qp->cep) { 630 siw_cep_put(qp->cep); 631 qp->cep = NULL; 632 } 633 up_write(&qp->state_lock); 634 635 kfree(qp->tx_ctx.mpa_crc_hd); 636 kfree(qp->rx_stream.mpa_crc_hd); 637 638 qp->scq = qp->rcq = NULL; 639 640 siw_qp_put(qp); 641 642 return 0; 643 } 644 645 /* 646 * siw_copy_inline_sgl() 647 * 648 * Prepare sgl of inlined data for sending. For userland callers 649 * function checks if given buffer addresses and len's are within 650 * process context bounds. 651 * Data from all provided sge's are copied together into the wqe, 652 * referenced by a single sge. 653 */ 654 static int siw_copy_inline_sgl(const struct ib_send_wr *core_wr, 655 struct siw_sqe *sqe) 656 { 657 struct ib_sge *core_sge = core_wr->sg_list; 658 void *kbuf = &sqe->sge[1]; 659 int num_sge = core_wr->num_sge, bytes = 0; 660 661 sqe->sge[0].laddr = (uintptr_t)kbuf; 662 sqe->sge[0].lkey = 0; 663 664 while (num_sge--) { 665 if (!core_sge->length) { 666 core_sge++; 667 continue; 668 } 669 bytes += core_sge->length; 670 if (bytes > SIW_MAX_INLINE) { 671 bytes = -EINVAL; 672 break; 673 } 674 memcpy(kbuf, (void *)(uintptr_t)core_sge->addr, 675 core_sge->length); 676 677 kbuf += core_sge->length; 678 core_sge++; 679 } 680 sqe->sge[0].length = bytes > 0 ? bytes : 0; 681 sqe->num_sge = bytes > 0 ? 1 : 0; 682 683 return bytes; 684 } 685 686 /* Complete SQ WR's without processing */ 687 static int siw_sq_flush_wr(struct siw_qp *qp, const struct ib_send_wr *wr, 688 const struct ib_send_wr **bad_wr) 689 { 690 struct siw_sqe sqe = {}; 691 int rv = 0; 692 693 while (wr) { 694 sqe.id = wr->wr_id; 695 sqe.opcode = wr->opcode; 696 rv = siw_sqe_complete(qp, &sqe, 0, SIW_WC_WR_FLUSH_ERR); 697 if (rv) { 698 if (bad_wr) 699 *bad_wr = wr; 700 break; 701 } 702 wr = wr->next; 703 } 704 return rv; 705 } 706 707 /* Complete RQ WR's without processing */ 708 static int siw_rq_flush_wr(struct siw_qp *qp, const struct ib_recv_wr *wr, 709 const struct ib_recv_wr **bad_wr) 710 { 711 struct siw_rqe rqe = {}; 712 int rv = 0; 713 714 while (wr) { 715 rqe.id = wr->wr_id; 716 rv = siw_rqe_complete(qp, &rqe, 0, 0, SIW_WC_WR_FLUSH_ERR); 717 if (rv) { 718 if (bad_wr) 719 *bad_wr = wr; 720 break; 721 } 722 wr = wr->next; 723 } 724 return rv; 725 } 726 727 /* 728 * siw_post_send() 729 * 730 * Post a list of S-WR's to a SQ. 731 * 732 * @base_qp: Base QP contained in siw QP 733 * @wr: Null terminated list of user WR's 734 * @bad_wr: Points to failing WR in case of synchronous failure. 735 */ 736 int siw_post_send(struct ib_qp *base_qp, const struct ib_send_wr *wr, 737 const struct ib_send_wr **bad_wr) 738 { 739 struct siw_qp *qp = to_siw_qp(base_qp); 740 struct siw_wqe *wqe = tx_wqe(qp); 741 742 unsigned long flags; 743 int rv = 0; 744 745 if (wr && !qp->kernel_verbs) { 746 siw_dbg_qp(qp, "wr must be empty for user mapped sq\n"); 747 *bad_wr = wr; 748 return -EINVAL; 749 } 750 751 /* 752 * Try to acquire QP state lock. Must be non-blocking 753 * to accommodate kernel clients needs. 754 */ 755 if (!down_read_trylock(&qp->state_lock)) { 756 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 757 /* 758 * ERROR state is final, so we can be sure 759 * this state will not change as long as the QP 760 * exists. 761 * 762 * This handles an ib_drain_sq() call with 763 * a concurrent request to set the QP state 764 * to ERROR. 765 */ 766 rv = siw_sq_flush_wr(qp, wr, bad_wr); 767 } else { 768 siw_dbg_qp(qp, "QP locked, state %d\n", 769 qp->attrs.state); 770 *bad_wr = wr; 771 rv = -ENOTCONN; 772 } 773 return rv; 774 } 775 if (unlikely(qp->attrs.state != SIW_QP_STATE_RTS)) { 776 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 777 /* 778 * Immediately flush this WR to CQ, if QP 779 * is in ERROR state. SQ is guaranteed to 780 * be empty, so WR complets in-order. 781 * 782 * Typically triggered by ib_drain_sq(). 783 */ 784 rv = siw_sq_flush_wr(qp, wr, bad_wr); 785 } else { 786 siw_dbg_qp(qp, "QP out of state %d\n", 787 qp->attrs.state); 788 *bad_wr = wr; 789 rv = -ENOTCONN; 790 } 791 up_read(&qp->state_lock); 792 return rv; 793 } 794 spin_lock_irqsave(&qp->sq_lock, flags); 795 796 while (wr) { 797 u32 idx = qp->sq_put % qp->attrs.sq_size; 798 struct siw_sqe *sqe = &qp->sendq[idx]; 799 800 if (sqe->flags) { 801 siw_dbg_qp(qp, "sq full\n"); 802 rv = -ENOMEM; 803 break; 804 } 805 if (wr->num_sge > qp->attrs.sq_max_sges) { 806 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge); 807 rv = -EINVAL; 808 break; 809 } 810 sqe->id = wr->wr_id; 811 812 if ((wr->send_flags & IB_SEND_SIGNALED) || 813 (qp->attrs.flags & SIW_SIGNAL_ALL_WR)) 814 sqe->flags |= SIW_WQE_SIGNALLED; 815 816 if (wr->send_flags & IB_SEND_FENCE) 817 sqe->flags |= SIW_WQE_READ_FENCE; 818 819 switch (wr->opcode) { 820 case IB_WR_SEND: 821 case IB_WR_SEND_WITH_INV: 822 if (wr->send_flags & IB_SEND_SOLICITED) 823 sqe->flags |= SIW_WQE_SOLICITED; 824 825 if (!(wr->send_flags & IB_SEND_INLINE)) { 826 siw_copy_sgl(wr->sg_list, sqe->sge, 827 wr->num_sge); 828 sqe->num_sge = wr->num_sge; 829 } else { 830 rv = siw_copy_inline_sgl(wr, sqe); 831 if (rv <= 0) { 832 rv = -EINVAL; 833 break; 834 } 835 sqe->flags |= SIW_WQE_INLINE; 836 sqe->num_sge = 1; 837 } 838 if (wr->opcode == IB_WR_SEND) 839 sqe->opcode = SIW_OP_SEND; 840 else { 841 sqe->opcode = SIW_OP_SEND_REMOTE_INV; 842 sqe->rkey = wr->ex.invalidate_rkey; 843 } 844 break; 845 846 case IB_WR_RDMA_READ_WITH_INV: 847 case IB_WR_RDMA_READ: 848 /* 849 * iWarp restricts RREAD sink to SGL containing 850 * 1 SGE only. we could relax to SGL with multiple 851 * elements referring the SAME ltag or even sending 852 * a private per-rreq tag referring to a checked 853 * local sgl with MULTIPLE ltag's. 854 */ 855 if (unlikely(wr->num_sge != 1)) { 856 rv = -EINVAL; 857 break; 858 } 859 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 1); 860 /* 861 * NOTE: zero length RREAD is allowed! 862 */ 863 sqe->raddr = rdma_wr(wr)->remote_addr; 864 sqe->rkey = rdma_wr(wr)->rkey; 865 sqe->num_sge = 1; 866 867 if (wr->opcode == IB_WR_RDMA_READ) 868 sqe->opcode = SIW_OP_READ; 869 else 870 sqe->opcode = SIW_OP_READ_LOCAL_INV; 871 break; 872 873 case IB_WR_RDMA_WRITE: 874 if (!(wr->send_flags & IB_SEND_INLINE)) { 875 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 876 wr->num_sge); 877 sqe->num_sge = wr->num_sge; 878 } else { 879 rv = siw_copy_inline_sgl(wr, sqe); 880 if (unlikely(rv < 0)) { 881 rv = -EINVAL; 882 break; 883 } 884 sqe->flags |= SIW_WQE_INLINE; 885 sqe->num_sge = 1; 886 } 887 sqe->raddr = rdma_wr(wr)->remote_addr; 888 sqe->rkey = rdma_wr(wr)->rkey; 889 sqe->opcode = SIW_OP_WRITE; 890 break; 891 892 case IB_WR_REG_MR: 893 sqe->base_mr = (uintptr_t)reg_wr(wr)->mr; 894 sqe->rkey = reg_wr(wr)->key; 895 sqe->access = reg_wr(wr)->access & IWARP_ACCESS_MASK; 896 sqe->opcode = SIW_OP_REG_MR; 897 break; 898 899 case IB_WR_LOCAL_INV: 900 sqe->rkey = wr->ex.invalidate_rkey; 901 sqe->opcode = SIW_OP_INVAL_STAG; 902 break; 903 904 default: 905 siw_dbg_qp(qp, "ib wr type %d unsupported\n", 906 wr->opcode); 907 rv = -EINVAL; 908 break; 909 } 910 siw_dbg_qp(qp, "opcode %d, flags 0x%x, wr_id 0x%pK\n", 911 sqe->opcode, sqe->flags, 912 (void *)(uintptr_t)sqe->id); 913 914 if (unlikely(rv < 0)) 915 break; 916 917 /* make SQE only valid after completely written */ 918 smp_wmb(); 919 sqe->flags |= SIW_WQE_VALID; 920 921 qp->sq_put++; 922 wr = wr->next; 923 } 924 925 /* 926 * Send directly if SQ processing is not in progress. 927 * Eventual immediate errors (rv < 0) do not affect the involved 928 * RI resources (Verbs, 8.3.1) and thus do not prevent from SQ 929 * processing, if new work is already pending. But rv must be passed 930 * to caller. 931 */ 932 if (wqe->wr_status != SIW_WR_IDLE) { 933 spin_unlock_irqrestore(&qp->sq_lock, flags); 934 goto skip_direct_sending; 935 } 936 rv = siw_activate_tx(qp); 937 spin_unlock_irqrestore(&qp->sq_lock, flags); 938 939 if (rv <= 0) 940 goto skip_direct_sending; 941 942 if (qp->kernel_verbs) { 943 rv = siw_sq_start(qp); 944 } else { 945 qp->tx_ctx.in_syscall = 1; 946 947 if (siw_qp_sq_process(qp) != 0 && !(qp->tx_ctx.tx_suspend)) 948 siw_qp_cm_drop(qp, 0); 949 950 qp->tx_ctx.in_syscall = 0; 951 } 952 skip_direct_sending: 953 954 up_read(&qp->state_lock); 955 956 if (rv >= 0) 957 return 0; 958 /* 959 * Immediate error 960 */ 961 siw_dbg_qp(qp, "error %d\n", rv); 962 963 *bad_wr = wr; 964 return rv; 965 } 966 967 /* 968 * siw_post_receive() 969 * 970 * Post a list of R-WR's to a RQ. 971 * 972 * @base_qp: Base QP contained in siw QP 973 * @wr: Null terminated list of user WR's 974 * @bad_wr: Points to failing WR in case of synchronous failure. 975 */ 976 int siw_post_receive(struct ib_qp *base_qp, const struct ib_recv_wr *wr, 977 const struct ib_recv_wr **bad_wr) 978 { 979 struct siw_qp *qp = to_siw_qp(base_qp); 980 unsigned long flags; 981 int rv = 0; 982 983 if (qp->srq) { 984 *bad_wr = wr; 985 return -EOPNOTSUPP; /* what else from errno.h? */ 986 } 987 if (!qp->kernel_verbs) { 988 siw_dbg_qp(qp, "no kernel post_recv for user mapped sq\n"); 989 *bad_wr = wr; 990 return -EINVAL; 991 } 992 993 /* 994 * Try to acquire QP state lock. Must be non-blocking 995 * to accommodate kernel clients needs. 996 */ 997 if (!down_read_trylock(&qp->state_lock)) { 998 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 999 /* 1000 * ERROR state is final, so we can be sure 1001 * this state will not change as long as the QP 1002 * exists. 1003 * 1004 * This handles an ib_drain_rq() call with 1005 * a concurrent request to set the QP state 1006 * to ERROR. 1007 */ 1008 rv = siw_rq_flush_wr(qp, wr, bad_wr); 1009 } else { 1010 siw_dbg_qp(qp, "QP locked, state %d\n", 1011 qp->attrs.state); 1012 *bad_wr = wr; 1013 rv = -ENOTCONN; 1014 } 1015 return rv; 1016 } 1017 if (qp->attrs.state > SIW_QP_STATE_RTS) { 1018 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 1019 /* 1020 * Immediately flush this WR to CQ, if QP 1021 * is in ERROR state. RQ is guaranteed to 1022 * be empty, so WR complets in-order. 1023 * 1024 * Typically triggered by ib_drain_rq(). 1025 */ 1026 rv = siw_rq_flush_wr(qp, wr, bad_wr); 1027 } else { 1028 siw_dbg_qp(qp, "QP out of state %d\n", 1029 qp->attrs.state); 1030 *bad_wr = wr; 1031 rv = -ENOTCONN; 1032 } 1033 up_read(&qp->state_lock); 1034 return rv; 1035 } 1036 /* 1037 * Serialize potentially multiple producers. 1038 * Not needed for single threaded consumer side. 1039 */ 1040 spin_lock_irqsave(&qp->rq_lock, flags); 1041 1042 while (wr) { 1043 u32 idx = qp->rq_put % qp->attrs.rq_size; 1044 struct siw_rqe *rqe = &qp->recvq[idx]; 1045 1046 if (rqe->flags) { 1047 siw_dbg_qp(qp, "RQ full\n"); 1048 rv = -ENOMEM; 1049 break; 1050 } 1051 if (wr->num_sge > qp->attrs.rq_max_sges) { 1052 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge); 1053 rv = -EINVAL; 1054 break; 1055 } 1056 rqe->id = wr->wr_id; 1057 rqe->num_sge = wr->num_sge; 1058 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge); 1059 1060 /* make sure RQE is completely written before valid */ 1061 smp_wmb(); 1062 1063 rqe->flags = SIW_WQE_VALID; 1064 1065 qp->rq_put++; 1066 wr = wr->next; 1067 } 1068 spin_unlock_irqrestore(&qp->rq_lock, flags); 1069 1070 up_read(&qp->state_lock); 1071 1072 if (rv < 0) { 1073 siw_dbg_qp(qp, "error %d\n", rv); 1074 *bad_wr = wr; 1075 } 1076 return rv > 0 ? 0 : rv; 1077 } 1078 1079 void siw_destroy_cq(struct ib_cq *base_cq, struct ib_udata *udata) 1080 { 1081 struct siw_cq *cq = to_siw_cq(base_cq); 1082 struct siw_device *sdev = to_siw_dev(base_cq->device); 1083 struct siw_ucontext *ctx = 1084 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1085 base_ucontext); 1086 1087 siw_dbg_cq(cq, "free CQ resources\n"); 1088 1089 siw_cq_flush(cq); 1090 1091 if (ctx) 1092 rdma_user_mmap_entry_remove(cq->cq_entry); 1093 1094 atomic_dec(&sdev->num_cq); 1095 1096 vfree(cq->queue); 1097 } 1098 1099 /* 1100 * siw_create_cq() 1101 * 1102 * Populate CQ of requested size 1103 * 1104 * @base_cq: CQ as allocated by RDMA midlayer 1105 * @attr: Initial CQ attributes 1106 * @udata: relates to user context 1107 */ 1108 1109 int siw_create_cq(struct ib_cq *base_cq, const struct ib_cq_init_attr *attr, 1110 struct ib_udata *udata) 1111 { 1112 struct siw_device *sdev = to_siw_dev(base_cq->device); 1113 struct siw_cq *cq = to_siw_cq(base_cq); 1114 int rv, size = attr->cqe; 1115 1116 if (atomic_inc_return(&sdev->num_cq) > SIW_MAX_CQ) { 1117 siw_dbg(base_cq->device, "too many CQ's\n"); 1118 rv = -ENOMEM; 1119 goto err_out; 1120 } 1121 if (size < 1 || size > sdev->attrs.max_cqe) { 1122 siw_dbg(base_cq->device, "CQ size error: %d\n", size); 1123 rv = -EINVAL; 1124 goto err_out; 1125 } 1126 size = roundup_pow_of_two(size); 1127 cq->base_cq.cqe = size; 1128 cq->num_cqe = size; 1129 1130 if (!udata) { 1131 cq->kernel_verbs = 1; 1132 cq->queue = vzalloc(size * sizeof(struct siw_cqe) + 1133 sizeof(struct siw_cq_ctrl)); 1134 } else { 1135 cq->queue = vmalloc_user(size * sizeof(struct siw_cqe) + 1136 sizeof(struct siw_cq_ctrl)); 1137 } 1138 if (cq->queue == NULL) { 1139 rv = -ENOMEM; 1140 goto err_out; 1141 } 1142 get_random_bytes(&cq->id, 4); 1143 siw_dbg(base_cq->device, "new CQ [%u]\n", cq->id); 1144 1145 spin_lock_init(&cq->lock); 1146 1147 cq->notify = (struct siw_cq_ctrl *)&cq->queue[size]; 1148 1149 if (udata) { 1150 struct siw_uresp_create_cq uresp = {}; 1151 struct siw_ucontext *ctx = 1152 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1153 base_ucontext); 1154 size_t length = size * sizeof(struct siw_cqe) + 1155 sizeof(struct siw_cq_ctrl); 1156 1157 cq->cq_entry = 1158 siw_mmap_entry_insert(ctx, cq->queue, 1159 length, &uresp.cq_key); 1160 if (!cq->cq_entry) { 1161 rv = -ENOMEM; 1162 goto err_out; 1163 } 1164 1165 uresp.cq_id = cq->id; 1166 uresp.num_cqe = size; 1167 1168 if (udata->outlen < sizeof(uresp)) { 1169 rv = -EINVAL; 1170 goto err_out; 1171 } 1172 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1173 if (rv) 1174 goto err_out; 1175 } 1176 return 0; 1177 1178 err_out: 1179 siw_dbg(base_cq->device, "CQ creation failed: %d", rv); 1180 1181 if (cq && cq->queue) { 1182 struct siw_ucontext *ctx = 1183 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1184 base_ucontext); 1185 if (ctx) 1186 rdma_user_mmap_entry_remove(cq->cq_entry); 1187 vfree(cq->queue); 1188 } 1189 atomic_dec(&sdev->num_cq); 1190 1191 return rv; 1192 } 1193 1194 /* 1195 * siw_poll_cq() 1196 * 1197 * Reap CQ entries if available and copy work completion status into 1198 * array of WC's provided by caller. Returns number of reaped CQE's. 1199 * 1200 * @base_cq: Base CQ contained in siw CQ. 1201 * @num_cqe: Maximum number of CQE's to reap. 1202 * @wc: Array of work completions to be filled by siw. 1203 */ 1204 int siw_poll_cq(struct ib_cq *base_cq, int num_cqe, struct ib_wc *wc) 1205 { 1206 struct siw_cq *cq = to_siw_cq(base_cq); 1207 int i; 1208 1209 for (i = 0; i < num_cqe; i++) { 1210 if (!siw_reap_cqe(cq, wc)) 1211 break; 1212 wc++; 1213 } 1214 return i; 1215 } 1216 1217 /* 1218 * siw_req_notify_cq() 1219 * 1220 * Request notification for new CQE's added to that CQ. 1221 * Defined flags: 1222 * o SIW_CQ_NOTIFY_SOLICITED lets siw trigger a notification 1223 * event if a WQE with notification flag set enters the CQ 1224 * o SIW_CQ_NOTIFY_NEXT_COMP lets siw trigger a notification 1225 * event if a WQE enters the CQ. 1226 * o IB_CQ_REPORT_MISSED_EVENTS: return value will provide the 1227 * number of not reaped CQE's regardless of its notification 1228 * type and current or new CQ notification settings. 1229 * 1230 * @base_cq: Base CQ contained in siw CQ. 1231 * @flags: Requested notification flags. 1232 */ 1233 int siw_req_notify_cq(struct ib_cq *base_cq, enum ib_cq_notify_flags flags) 1234 { 1235 struct siw_cq *cq = to_siw_cq(base_cq); 1236 1237 siw_dbg_cq(cq, "flags: 0x%02x\n", flags); 1238 1239 if ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED) 1240 /* 1241 * Enable CQ event for next solicited completion. 1242 * and make it visible to all associated producers. 1243 */ 1244 smp_store_mb(cq->notify->flags, SIW_NOTIFY_SOLICITED); 1245 else 1246 /* 1247 * Enable CQ event for any signalled completion. 1248 * and make it visible to all associated producers. 1249 */ 1250 smp_store_mb(cq->notify->flags, SIW_NOTIFY_ALL); 1251 1252 if (flags & IB_CQ_REPORT_MISSED_EVENTS) 1253 return cq->cq_put - cq->cq_get; 1254 1255 return 0; 1256 } 1257 1258 /* 1259 * siw_dereg_mr() 1260 * 1261 * Release Memory Region. 1262 * 1263 * @base_mr: Base MR contained in siw MR. 1264 * @udata: points to user context, unused. 1265 */ 1266 int siw_dereg_mr(struct ib_mr *base_mr, struct ib_udata *udata) 1267 { 1268 struct siw_mr *mr = to_siw_mr(base_mr); 1269 struct siw_device *sdev = to_siw_dev(base_mr->device); 1270 1271 siw_dbg_mem(mr->mem, "deregister MR\n"); 1272 1273 atomic_dec(&sdev->num_mr); 1274 1275 siw_mr_drop_mem(mr); 1276 kfree_rcu(mr, rcu); 1277 1278 return 0; 1279 } 1280 1281 /* 1282 * siw_reg_user_mr() 1283 * 1284 * Register Memory Region. 1285 * 1286 * @pd: Protection Domain 1287 * @start: starting address of MR (virtual address) 1288 * @len: len of MR 1289 * @rnic_va: not used by siw 1290 * @rights: MR access rights 1291 * @udata: user buffer to communicate STag and Key. 1292 */ 1293 struct ib_mr *siw_reg_user_mr(struct ib_pd *pd, u64 start, u64 len, 1294 u64 rnic_va, int rights, struct ib_udata *udata) 1295 { 1296 struct siw_mr *mr = NULL; 1297 struct siw_umem *umem = NULL; 1298 struct siw_ureq_reg_mr ureq; 1299 struct siw_device *sdev = to_siw_dev(pd->device); 1300 1301 unsigned long mem_limit = rlimit(RLIMIT_MEMLOCK); 1302 int rv; 1303 1304 siw_dbg_pd(pd, "start: 0x%pK, va: 0x%pK, len: %llu\n", 1305 (void *)(uintptr_t)start, (void *)(uintptr_t)rnic_va, 1306 (unsigned long long)len); 1307 1308 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1309 siw_dbg_pd(pd, "too many mr's\n"); 1310 rv = -ENOMEM; 1311 goto err_out; 1312 } 1313 if (!len) { 1314 rv = -EINVAL; 1315 goto err_out; 1316 } 1317 if (mem_limit != RLIM_INFINITY) { 1318 unsigned long num_pages = 1319 (PAGE_ALIGN(len + (start & ~PAGE_MASK))) >> PAGE_SHIFT; 1320 mem_limit >>= PAGE_SHIFT; 1321 1322 if (num_pages > mem_limit - current->mm->locked_vm) { 1323 siw_dbg_pd(pd, "pages req %lu, max %lu, lock %lu\n", 1324 num_pages, mem_limit, 1325 current->mm->locked_vm); 1326 rv = -ENOMEM; 1327 goto err_out; 1328 } 1329 } 1330 umem = siw_umem_get(start, len, ib_access_writable(rights)); 1331 if (IS_ERR(umem)) { 1332 rv = PTR_ERR(umem); 1333 siw_dbg_pd(pd, "getting user memory failed: %d\n", rv); 1334 umem = NULL; 1335 goto err_out; 1336 } 1337 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1338 if (!mr) { 1339 rv = -ENOMEM; 1340 goto err_out; 1341 } 1342 rv = siw_mr_add_mem(mr, pd, umem, start, len, rights); 1343 if (rv) 1344 goto err_out; 1345 1346 if (udata) { 1347 struct siw_uresp_reg_mr uresp = {}; 1348 struct siw_mem *mem = mr->mem; 1349 1350 if (udata->inlen < sizeof(ureq)) { 1351 rv = -EINVAL; 1352 goto err_out; 1353 } 1354 rv = ib_copy_from_udata(&ureq, udata, sizeof(ureq)); 1355 if (rv) 1356 goto err_out; 1357 1358 mr->base_mr.lkey |= ureq.stag_key; 1359 mr->base_mr.rkey |= ureq.stag_key; 1360 mem->stag |= ureq.stag_key; 1361 uresp.stag = mem->stag; 1362 1363 if (udata->outlen < sizeof(uresp)) { 1364 rv = -EINVAL; 1365 goto err_out; 1366 } 1367 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1368 if (rv) 1369 goto err_out; 1370 } 1371 mr->mem->stag_valid = 1; 1372 1373 return &mr->base_mr; 1374 1375 err_out: 1376 atomic_dec(&sdev->num_mr); 1377 if (mr) { 1378 if (mr->mem) 1379 siw_mr_drop_mem(mr); 1380 kfree_rcu(mr, rcu); 1381 } else { 1382 if (umem) 1383 siw_umem_release(umem, false); 1384 } 1385 return ERR_PTR(rv); 1386 } 1387 1388 struct ib_mr *siw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1389 u32 max_sge, struct ib_udata *udata) 1390 { 1391 struct siw_device *sdev = to_siw_dev(pd->device); 1392 struct siw_mr *mr = NULL; 1393 struct siw_pbl *pbl = NULL; 1394 int rv; 1395 1396 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1397 siw_dbg_pd(pd, "too many mr's\n"); 1398 rv = -ENOMEM; 1399 goto err_out; 1400 } 1401 if (mr_type != IB_MR_TYPE_MEM_REG) { 1402 siw_dbg_pd(pd, "mr type %d unsupported\n", mr_type); 1403 rv = -EOPNOTSUPP; 1404 goto err_out; 1405 } 1406 if (max_sge > SIW_MAX_SGE_PBL) { 1407 siw_dbg_pd(pd, "too many sge's: %d\n", max_sge); 1408 rv = -ENOMEM; 1409 goto err_out; 1410 } 1411 pbl = siw_pbl_alloc(max_sge); 1412 if (IS_ERR(pbl)) { 1413 rv = PTR_ERR(pbl); 1414 siw_dbg_pd(pd, "pbl allocation failed: %d\n", rv); 1415 pbl = NULL; 1416 goto err_out; 1417 } 1418 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1419 if (!mr) { 1420 rv = -ENOMEM; 1421 goto err_out; 1422 } 1423 rv = siw_mr_add_mem(mr, pd, pbl, 0, max_sge * PAGE_SIZE, 0); 1424 if (rv) 1425 goto err_out; 1426 1427 mr->mem->is_pbl = 1; 1428 1429 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag); 1430 1431 return &mr->base_mr; 1432 1433 err_out: 1434 atomic_dec(&sdev->num_mr); 1435 1436 if (!mr) { 1437 kfree(pbl); 1438 } else { 1439 if (mr->mem) 1440 siw_mr_drop_mem(mr); 1441 kfree_rcu(mr, rcu); 1442 } 1443 siw_dbg_pd(pd, "failed: %d\n", rv); 1444 1445 return ERR_PTR(rv); 1446 } 1447 1448 /* Just used to count number of pages being mapped */ 1449 static int siw_set_pbl_page(struct ib_mr *base_mr, u64 buf_addr) 1450 { 1451 return 0; 1452 } 1453 1454 int siw_map_mr_sg(struct ib_mr *base_mr, struct scatterlist *sl, int num_sle, 1455 unsigned int *sg_off) 1456 { 1457 struct scatterlist *slp; 1458 struct siw_mr *mr = to_siw_mr(base_mr); 1459 struct siw_mem *mem = mr->mem; 1460 struct siw_pbl *pbl = mem->pbl; 1461 struct siw_pble *pble; 1462 unsigned long pbl_size; 1463 int i, rv; 1464 1465 if (!pbl) { 1466 siw_dbg_mem(mem, "no PBL allocated\n"); 1467 return -EINVAL; 1468 } 1469 pble = pbl->pbe; 1470 1471 if (pbl->max_buf < num_sle) { 1472 siw_dbg_mem(mem, "too many SGE's: %d > %d\n", 1473 mem->pbl->max_buf, num_sle); 1474 return -ENOMEM; 1475 } 1476 for_each_sg(sl, slp, num_sle, i) { 1477 if (sg_dma_len(slp) == 0) { 1478 siw_dbg_mem(mem, "empty SGE\n"); 1479 return -EINVAL; 1480 } 1481 if (i == 0) { 1482 pble->addr = sg_dma_address(slp); 1483 pble->size = sg_dma_len(slp); 1484 pble->pbl_off = 0; 1485 pbl_size = pble->size; 1486 pbl->num_buf = 1; 1487 } else { 1488 /* Merge PBL entries if adjacent */ 1489 if (pble->addr + pble->size == sg_dma_address(slp)) { 1490 pble->size += sg_dma_len(slp); 1491 } else { 1492 pble++; 1493 pbl->num_buf++; 1494 pble->addr = sg_dma_address(slp); 1495 pble->size = sg_dma_len(slp); 1496 pble->pbl_off = pbl_size; 1497 } 1498 pbl_size += sg_dma_len(slp); 1499 } 1500 siw_dbg_mem(mem, 1501 "sge[%d], size %u, addr 0x%p, total %lu\n", 1502 i, pble->size, (void *)(uintptr_t)pble->addr, 1503 pbl_size); 1504 } 1505 rv = ib_sg_to_pages(base_mr, sl, num_sle, sg_off, siw_set_pbl_page); 1506 if (rv > 0) { 1507 mem->len = base_mr->length; 1508 mem->va = base_mr->iova; 1509 siw_dbg_mem(mem, 1510 "%llu bytes, start 0x%pK, %u SLE to %u entries\n", 1511 mem->len, (void *)(uintptr_t)mem->va, num_sle, 1512 pbl->num_buf); 1513 } 1514 return rv; 1515 } 1516 1517 /* 1518 * siw_get_dma_mr() 1519 * 1520 * Create a (empty) DMA memory region, where no umem is attached. 1521 */ 1522 struct ib_mr *siw_get_dma_mr(struct ib_pd *pd, int rights) 1523 { 1524 struct siw_device *sdev = to_siw_dev(pd->device); 1525 struct siw_mr *mr = NULL; 1526 int rv; 1527 1528 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1529 siw_dbg_pd(pd, "too many mr's\n"); 1530 rv = -ENOMEM; 1531 goto err_out; 1532 } 1533 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1534 if (!mr) { 1535 rv = -ENOMEM; 1536 goto err_out; 1537 } 1538 rv = siw_mr_add_mem(mr, pd, NULL, 0, ULONG_MAX, rights); 1539 if (rv) 1540 goto err_out; 1541 1542 mr->mem->stag_valid = 1; 1543 1544 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag); 1545 1546 return &mr->base_mr; 1547 1548 err_out: 1549 if (rv) 1550 kfree(mr); 1551 1552 atomic_dec(&sdev->num_mr); 1553 1554 return ERR_PTR(rv); 1555 } 1556 1557 /* 1558 * siw_create_srq() 1559 * 1560 * Create Shared Receive Queue of attributes @init_attrs 1561 * within protection domain given by @pd. 1562 * 1563 * @base_srq: Base SRQ contained in siw SRQ. 1564 * @init_attrs: SRQ init attributes. 1565 * @udata: points to user context 1566 */ 1567 int siw_create_srq(struct ib_srq *base_srq, 1568 struct ib_srq_init_attr *init_attrs, struct ib_udata *udata) 1569 { 1570 struct siw_srq *srq = to_siw_srq(base_srq); 1571 struct ib_srq_attr *attrs = &init_attrs->attr; 1572 struct siw_device *sdev = to_siw_dev(base_srq->device); 1573 struct siw_ucontext *ctx = 1574 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1575 base_ucontext); 1576 int rv; 1577 1578 if (atomic_inc_return(&sdev->num_srq) > SIW_MAX_SRQ) { 1579 siw_dbg_pd(base_srq->pd, "too many SRQ's\n"); 1580 rv = -ENOMEM; 1581 goto err_out; 1582 } 1583 if (attrs->max_wr == 0 || attrs->max_wr > SIW_MAX_SRQ_WR || 1584 attrs->max_sge > SIW_MAX_SGE || attrs->srq_limit > attrs->max_wr) { 1585 rv = -EINVAL; 1586 goto err_out; 1587 } 1588 srq->max_sge = attrs->max_sge; 1589 srq->num_rqe = roundup_pow_of_two(attrs->max_wr); 1590 srq->limit = attrs->srq_limit; 1591 if (srq->limit) 1592 srq->armed = 1; 1593 1594 srq->kernel_verbs = !udata; 1595 1596 if (udata) 1597 srq->recvq = 1598 vmalloc_user(srq->num_rqe * sizeof(struct siw_rqe)); 1599 else 1600 srq->recvq = vzalloc(srq->num_rqe * sizeof(struct siw_rqe)); 1601 1602 if (srq->recvq == NULL) { 1603 rv = -ENOMEM; 1604 goto err_out; 1605 } 1606 if (udata) { 1607 struct siw_uresp_create_srq uresp = {}; 1608 size_t length = srq->num_rqe * sizeof(struct siw_rqe); 1609 1610 srq->srq_entry = 1611 siw_mmap_entry_insert(ctx, srq->recvq, 1612 length, &uresp.srq_key); 1613 if (!srq->srq_entry) { 1614 rv = -ENOMEM; 1615 goto err_out; 1616 } 1617 1618 uresp.num_rqe = srq->num_rqe; 1619 1620 if (udata->outlen < sizeof(uresp)) { 1621 rv = -EINVAL; 1622 goto err_out; 1623 } 1624 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1625 if (rv) 1626 goto err_out; 1627 } 1628 spin_lock_init(&srq->lock); 1629 1630 siw_dbg_pd(base_srq->pd, "[SRQ]: success\n"); 1631 1632 return 0; 1633 1634 err_out: 1635 if (srq->recvq) { 1636 if (ctx) 1637 rdma_user_mmap_entry_remove(srq->srq_entry); 1638 vfree(srq->recvq); 1639 } 1640 atomic_dec(&sdev->num_srq); 1641 1642 return rv; 1643 } 1644 1645 /* 1646 * siw_modify_srq() 1647 * 1648 * Modify SRQ. The caller may resize SRQ and/or set/reset notification 1649 * limit and (re)arm IB_EVENT_SRQ_LIMIT_REACHED notification. 1650 * 1651 * NOTE: it is unclear if RDMA core allows for changing the MAX_SGE 1652 * parameter. siw_modify_srq() does not check the attrs->max_sge param. 1653 */ 1654 int siw_modify_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs, 1655 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata) 1656 { 1657 struct siw_srq *srq = to_siw_srq(base_srq); 1658 unsigned long flags; 1659 int rv = 0; 1660 1661 spin_lock_irqsave(&srq->lock, flags); 1662 1663 if (attr_mask & IB_SRQ_MAX_WR) { 1664 /* resize request not yet supported */ 1665 rv = -EOPNOTSUPP; 1666 goto out; 1667 } 1668 if (attr_mask & IB_SRQ_LIMIT) { 1669 if (attrs->srq_limit) { 1670 if (unlikely(attrs->srq_limit > srq->num_rqe)) { 1671 rv = -EINVAL; 1672 goto out; 1673 } 1674 srq->armed = 1; 1675 } else { 1676 srq->armed = 0; 1677 } 1678 srq->limit = attrs->srq_limit; 1679 } 1680 out: 1681 spin_unlock_irqrestore(&srq->lock, flags); 1682 1683 return rv; 1684 } 1685 1686 /* 1687 * siw_query_srq() 1688 * 1689 * Query SRQ attributes. 1690 */ 1691 int siw_query_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs) 1692 { 1693 struct siw_srq *srq = to_siw_srq(base_srq); 1694 unsigned long flags; 1695 1696 spin_lock_irqsave(&srq->lock, flags); 1697 1698 attrs->max_wr = srq->num_rqe; 1699 attrs->max_sge = srq->max_sge; 1700 attrs->srq_limit = srq->limit; 1701 1702 spin_unlock_irqrestore(&srq->lock, flags); 1703 1704 return 0; 1705 } 1706 1707 /* 1708 * siw_destroy_srq() 1709 * 1710 * Destroy SRQ. 1711 * It is assumed that the SRQ is not referenced by any 1712 * QP anymore - the code trusts the RDMA core environment to keep track 1713 * of QP references. 1714 */ 1715 void siw_destroy_srq(struct ib_srq *base_srq, struct ib_udata *udata) 1716 { 1717 struct siw_srq *srq = to_siw_srq(base_srq); 1718 struct siw_device *sdev = to_siw_dev(base_srq->device); 1719 struct siw_ucontext *ctx = 1720 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1721 base_ucontext); 1722 1723 if (ctx) 1724 rdma_user_mmap_entry_remove(srq->srq_entry); 1725 vfree(srq->recvq); 1726 atomic_dec(&sdev->num_srq); 1727 } 1728 1729 /* 1730 * siw_post_srq_recv() 1731 * 1732 * Post a list of receive queue elements to SRQ. 1733 * NOTE: The function does not check or lock a certain SRQ state 1734 * during the post operation. The code simply trusts the 1735 * RDMA core environment. 1736 * 1737 * @base_srq: Base SRQ contained in siw SRQ 1738 * @wr: List of R-WR's 1739 * @bad_wr: Updated to failing WR if posting fails. 1740 */ 1741 int siw_post_srq_recv(struct ib_srq *base_srq, const struct ib_recv_wr *wr, 1742 const struct ib_recv_wr **bad_wr) 1743 { 1744 struct siw_srq *srq = to_siw_srq(base_srq); 1745 unsigned long flags; 1746 int rv = 0; 1747 1748 if (unlikely(!srq->kernel_verbs)) { 1749 siw_dbg_pd(base_srq->pd, 1750 "[SRQ]: no kernel post_recv for mapped srq\n"); 1751 rv = -EINVAL; 1752 goto out; 1753 } 1754 /* 1755 * Serialize potentially multiple producers. 1756 * Also needed to serialize potentially multiple 1757 * consumers. 1758 */ 1759 spin_lock_irqsave(&srq->lock, flags); 1760 1761 while (wr) { 1762 u32 idx = srq->rq_put % srq->num_rqe; 1763 struct siw_rqe *rqe = &srq->recvq[idx]; 1764 1765 if (rqe->flags) { 1766 siw_dbg_pd(base_srq->pd, "SRQ full\n"); 1767 rv = -ENOMEM; 1768 break; 1769 } 1770 if (unlikely(wr->num_sge > srq->max_sge)) { 1771 siw_dbg_pd(base_srq->pd, 1772 "[SRQ]: too many sge's: %d\n", wr->num_sge); 1773 rv = -EINVAL; 1774 break; 1775 } 1776 rqe->id = wr->wr_id; 1777 rqe->num_sge = wr->num_sge; 1778 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge); 1779 1780 /* Make sure S-RQE is completely written before valid */ 1781 smp_wmb(); 1782 1783 rqe->flags = SIW_WQE_VALID; 1784 1785 srq->rq_put++; 1786 wr = wr->next; 1787 } 1788 spin_unlock_irqrestore(&srq->lock, flags); 1789 out: 1790 if (unlikely(rv < 0)) { 1791 siw_dbg_pd(base_srq->pd, "[SRQ]: error %d\n", rv); 1792 *bad_wr = wr; 1793 } 1794 return rv; 1795 } 1796 1797 void siw_qp_event(struct siw_qp *qp, enum ib_event_type etype) 1798 { 1799 struct ib_event event; 1800 struct ib_qp *base_qp = qp->ib_qp; 1801 1802 /* 1803 * Do not report asynchronous errors on QP which gets 1804 * destroyed via verbs interface (siw_destroy_qp()) 1805 */ 1806 if (qp->attrs.flags & SIW_QP_IN_DESTROY) 1807 return; 1808 1809 event.event = etype; 1810 event.device = base_qp->device; 1811 event.element.qp = base_qp; 1812 1813 if (base_qp->event_handler) { 1814 siw_dbg_qp(qp, "reporting event %d\n", etype); 1815 base_qp->event_handler(&event, base_qp->qp_context); 1816 } 1817 } 1818 1819 void siw_cq_event(struct siw_cq *cq, enum ib_event_type etype) 1820 { 1821 struct ib_event event; 1822 struct ib_cq *base_cq = &cq->base_cq; 1823 1824 event.event = etype; 1825 event.device = base_cq->device; 1826 event.element.cq = base_cq; 1827 1828 if (base_cq->event_handler) { 1829 siw_dbg_cq(cq, "reporting CQ event %d\n", etype); 1830 base_cq->event_handler(&event, base_cq->cq_context); 1831 } 1832 } 1833 1834 void siw_srq_event(struct siw_srq *srq, enum ib_event_type etype) 1835 { 1836 struct ib_event event; 1837 struct ib_srq *base_srq = &srq->base_srq; 1838 1839 event.event = etype; 1840 event.device = base_srq->device; 1841 event.element.srq = base_srq; 1842 1843 if (base_srq->event_handler) { 1844 siw_dbg_pd(srq->base_srq.pd, 1845 "reporting SRQ event %d\n", etype); 1846 base_srq->event_handler(&event, base_srq->srq_context); 1847 } 1848 } 1849 1850 void siw_port_event(struct siw_device *sdev, u8 port, enum ib_event_type etype) 1851 { 1852 struct ib_event event; 1853 1854 event.event = etype; 1855 event.device = &sdev->base_dev; 1856 event.element.port_num = port; 1857 1858 siw_dbg(&sdev->base_dev, "reporting port event %d\n", etype); 1859 1860 ib_dispatch_event(&event); 1861 } 1862