1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 /* Copyright (c) 2008-2019, IBM Corporation */ 5 6 #include <linux/errno.h> 7 #include <linux/types.h> 8 #include <linux/uaccess.h> 9 #include <linux/vmalloc.h> 10 #include <linux/xarray.h> 11 12 #include <rdma/iw_cm.h> 13 #include <rdma/ib_verbs.h> 14 #include <rdma/ib_user_verbs.h> 15 #include <rdma/uverbs_ioctl.h> 16 17 #include "siw.h" 18 #include "siw_verbs.h" 19 #include "siw_mem.h" 20 21 static int ib_qp_state_to_siw_qp_state[IB_QPS_ERR + 1] = { 22 [IB_QPS_RESET] = SIW_QP_STATE_IDLE, 23 [IB_QPS_INIT] = SIW_QP_STATE_IDLE, 24 [IB_QPS_RTR] = SIW_QP_STATE_RTR, 25 [IB_QPS_RTS] = SIW_QP_STATE_RTS, 26 [IB_QPS_SQD] = SIW_QP_STATE_CLOSING, 27 [IB_QPS_SQE] = SIW_QP_STATE_TERMINATE, 28 [IB_QPS_ERR] = SIW_QP_STATE_ERROR 29 }; 30 31 static char ib_qp_state_to_string[IB_QPS_ERR + 1][sizeof("RESET")] = { 32 [IB_QPS_RESET] = "RESET", [IB_QPS_INIT] = "INIT", [IB_QPS_RTR] = "RTR", 33 [IB_QPS_RTS] = "RTS", [IB_QPS_SQD] = "SQD", [IB_QPS_SQE] = "SQE", 34 [IB_QPS_ERR] = "ERR" 35 }; 36 37 void siw_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 38 { 39 struct siw_user_mmap_entry *entry = to_siw_mmap_entry(rdma_entry); 40 41 kfree(entry); 42 } 43 44 int siw_mmap(struct ib_ucontext *ctx, struct vm_area_struct *vma) 45 { 46 struct siw_ucontext *uctx = to_siw_ctx(ctx); 47 size_t size = vma->vm_end - vma->vm_start; 48 struct rdma_user_mmap_entry *rdma_entry; 49 struct siw_user_mmap_entry *entry; 50 int rv = -EINVAL; 51 52 /* 53 * Must be page aligned 54 */ 55 if (vma->vm_start & (PAGE_SIZE - 1)) { 56 pr_warn("siw: mmap not page aligned\n"); 57 return -EINVAL; 58 } 59 rdma_entry = rdma_user_mmap_entry_get(&uctx->base_ucontext, vma); 60 if (!rdma_entry) { 61 siw_dbg(&uctx->sdev->base_dev, "mmap lookup failed: %lu, %#zx\n", 62 vma->vm_pgoff, size); 63 return -EINVAL; 64 } 65 entry = to_siw_mmap_entry(rdma_entry); 66 67 rv = remap_vmalloc_range(vma, entry->address, 0); 68 if (rv) { 69 pr_warn("remap_vmalloc_range failed: %lu, %zu\n", vma->vm_pgoff, 70 size); 71 goto out; 72 } 73 out: 74 rdma_user_mmap_entry_put(rdma_entry); 75 76 return rv; 77 } 78 79 int siw_alloc_ucontext(struct ib_ucontext *base_ctx, struct ib_udata *udata) 80 { 81 struct siw_device *sdev = to_siw_dev(base_ctx->device); 82 struct siw_ucontext *ctx = to_siw_ctx(base_ctx); 83 struct siw_uresp_alloc_ctx uresp = {}; 84 int rv; 85 86 if (atomic_inc_return(&sdev->num_ctx) > SIW_MAX_CONTEXT) { 87 rv = -ENOMEM; 88 goto err_out; 89 } 90 ctx->sdev = sdev; 91 92 uresp.dev_id = sdev->vendor_part_id; 93 94 if (udata->outlen < sizeof(uresp)) { 95 rv = -EINVAL; 96 goto err_out; 97 } 98 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 99 if (rv) 100 goto err_out; 101 102 siw_dbg(base_ctx->device, "success. now %d context(s)\n", 103 atomic_read(&sdev->num_ctx)); 104 105 return 0; 106 107 err_out: 108 atomic_dec(&sdev->num_ctx); 109 siw_dbg(base_ctx->device, "failure %d. now %d context(s)\n", rv, 110 atomic_read(&sdev->num_ctx)); 111 112 return rv; 113 } 114 115 void siw_dealloc_ucontext(struct ib_ucontext *base_ctx) 116 { 117 struct siw_ucontext *uctx = to_siw_ctx(base_ctx); 118 119 atomic_dec(&uctx->sdev->num_ctx); 120 } 121 122 int siw_query_device(struct ib_device *base_dev, struct ib_device_attr *attr, 123 struct ib_udata *udata) 124 { 125 struct siw_device *sdev = to_siw_dev(base_dev); 126 127 if (udata->inlen || udata->outlen) 128 return -EINVAL; 129 130 memset(attr, 0, sizeof(*attr)); 131 132 /* Revisit atomic caps if RFC 7306 gets supported */ 133 attr->atomic_cap = 0; 134 attr->device_cap_flags = 135 IB_DEVICE_MEM_MGT_EXTENSIONS | IB_DEVICE_ALLOW_USER_UNREG; 136 attr->max_cq = sdev->attrs.max_cq; 137 attr->max_cqe = sdev->attrs.max_cqe; 138 attr->max_fast_reg_page_list_len = SIW_MAX_SGE_PBL; 139 attr->max_mr = sdev->attrs.max_mr; 140 attr->max_mw = sdev->attrs.max_mw; 141 attr->max_mr_size = ~0ull; 142 attr->max_pd = sdev->attrs.max_pd; 143 attr->max_qp = sdev->attrs.max_qp; 144 attr->max_qp_init_rd_atom = sdev->attrs.max_ird; 145 attr->max_qp_rd_atom = sdev->attrs.max_ord; 146 attr->max_qp_wr = sdev->attrs.max_qp_wr; 147 attr->max_recv_sge = sdev->attrs.max_sge; 148 attr->max_res_rd_atom = sdev->attrs.max_qp * sdev->attrs.max_ird; 149 attr->max_send_sge = sdev->attrs.max_sge; 150 attr->max_sge_rd = sdev->attrs.max_sge_rd; 151 attr->max_srq = sdev->attrs.max_srq; 152 attr->max_srq_sge = sdev->attrs.max_srq_sge; 153 attr->max_srq_wr = sdev->attrs.max_srq_wr; 154 attr->page_size_cap = PAGE_SIZE; 155 attr->vendor_id = SIW_VENDOR_ID; 156 attr->vendor_part_id = sdev->vendor_part_id; 157 158 memcpy(&attr->sys_image_guid, sdev->netdev->dev_addr, 6); 159 160 return 0; 161 } 162 163 int siw_query_port(struct ib_device *base_dev, u8 port, 164 struct ib_port_attr *attr) 165 { 166 struct siw_device *sdev = to_siw_dev(base_dev); 167 int rv; 168 169 memset(attr, 0, sizeof(*attr)); 170 171 rv = ib_get_eth_speed(base_dev, port, &attr->active_speed, 172 &attr->active_width); 173 attr->gid_tbl_len = 1; 174 attr->max_msg_sz = -1; 175 attr->max_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 176 attr->active_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 177 attr->phys_state = sdev->state == IB_PORT_ACTIVE ? 178 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 179 attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP; 180 attr->state = sdev->state; 181 /* 182 * All zero 183 * 184 * attr->lid = 0; 185 * attr->bad_pkey_cntr = 0; 186 * attr->qkey_viol_cntr = 0; 187 * attr->sm_lid = 0; 188 * attr->lmc = 0; 189 * attr->max_vl_num = 0; 190 * attr->sm_sl = 0; 191 * attr->subnet_timeout = 0; 192 * attr->init_type_repy = 0; 193 */ 194 return rv; 195 } 196 197 int siw_get_port_immutable(struct ib_device *base_dev, u8 port, 198 struct ib_port_immutable *port_immutable) 199 { 200 struct ib_port_attr attr; 201 int rv = siw_query_port(base_dev, port, &attr); 202 203 if (rv) 204 return rv; 205 206 port_immutable->gid_tbl_len = attr.gid_tbl_len; 207 port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 208 209 return 0; 210 } 211 212 int siw_query_gid(struct ib_device *base_dev, u8 port, int idx, 213 union ib_gid *gid) 214 { 215 struct siw_device *sdev = to_siw_dev(base_dev); 216 217 /* subnet_prefix == interface_id == 0; */ 218 memset(gid, 0, sizeof(*gid)); 219 memcpy(&gid->raw[0], sdev->netdev->dev_addr, 6); 220 221 return 0; 222 } 223 224 int siw_alloc_pd(struct ib_pd *pd, struct ib_udata *udata) 225 { 226 struct siw_device *sdev = to_siw_dev(pd->device); 227 228 if (atomic_inc_return(&sdev->num_pd) > SIW_MAX_PD) { 229 atomic_dec(&sdev->num_pd); 230 return -ENOMEM; 231 } 232 siw_dbg_pd(pd, "now %d PD's(s)\n", atomic_read(&sdev->num_pd)); 233 234 return 0; 235 } 236 237 int siw_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 238 { 239 struct siw_device *sdev = to_siw_dev(pd->device); 240 241 siw_dbg_pd(pd, "free PD\n"); 242 atomic_dec(&sdev->num_pd); 243 return 0; 244 } 245 246 void siw_qp_get_ref(struct ib_qp *base_qp) 247 { 248 siw_qp_get(to_siw_qp(base_qp)); 249 } 250 251 void siw_qp_put_ref(struct ib_qp *base_qp) 252 { 253 siw_qp_put(to_siw_qp(base_qp)); 254 } 255 256 static struct rdma_user_mmap_entry * 257 siw_mmap_entry_insert(struct siw_ucontext *uctx, 258 void *address, size_t length, 259 u64 *offset) 260 { 261 struct siw_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); 262 int rv; 263 264 *offset = SIW_INVAL_UOBJ_KEY; 265 if (!entry) 266 return NULL; 267 268 entry->address = address; 269 270 rv = rdma_user_mmap_entry_insert(&uctx->base_ucontext, 271 &entry->rdma_entry, 272 length); 273 if (rv) { 274 kfree(entry); 275 return NULL; 276 } 277 278 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 279 280 return &entry->rdma_entry; 281 } 282 283 /* 284 * siw_create_qp() 285 * 286 * Create QP of requested size on given device. 287 * 288 * @pd: Protection Domain 289 * @attrs: Initial QP attributes. 290 * @udata: used to provide QP ID, SQ and RQ size back to user. 291 */ 292 293 struct ib_qp *siw_create_qp(struct ib_pd *pd, 294 struct ib_qp_init_attr *attrs, 295 struct ib_udata *udata) 296 { 297 struct siw_qp *qp = NULL; 298 struct ib_device *base_dev = pd->device; 299 struct siw_device *sdev = to_siw_dev(base_dev); 300 struct siw_ucontext *uctx = 301 rdma_udata_to_drv_context(udata, struct siw_ucontext, 302 base_ucontext); 303 struct siw_cq *scq = NULL, *rcq = NULL; 304 unsigned long flags; 305 int num_sqe, num_rqe, rv = 0; 306 size_t length; 307 308 siw_dbg(base_dev, "create new QP\n"); 309 310 if (atomic_inc_return(&sdev->num_qp) > SIW_MAX_QP) { 311 siw_dbg(base_dev, "too many QP's\n"); 312 rv = -ENOMEM; 313 goto err_out; 314 } 315 if (attrs->qp_type != IB_QPT_RC) { 316 siw_dbg(base_dev, "only RC QP's supported\n"); 317 rv = -EOPNOTSUPP; 318 goto err_out; 319 } 320 if ((attrs->cap.max_send_wr > SIW_MAX_QP_WR) || 321 (attrs->cap.max_recv_wr > SIW_MAX_QP_WR) || 322 (attrs->cap.max_send_sge > SIW_MAX_SGE) || 323 (attrs->cap.max_recv_sge > SIW_MAX_SGE)) { 324 siw_dbg(base_dev, "QP size error\n"); 325 rv = -EINVAL; 326 goto err_out; 327 } 328 if (attrs->cap.max_inline_data > SIW_MAX_INLINE) { 329 siw_dbg(base_dev, "max inline send: %d > %d\n", 330 attrs->cap.max_inline_data, (int)SIW_MAX_INLINE); 331 rv = -EINVAL; 332 goto err_out; 333 } 334 /* 335 * NOTE: we allow for zero element SQ and RQ WQE's SGL's 336 * but not for a QP unable to hold any WQE (SQ + RQ) 337 */ 338 if (attrs->cap.max_send_wr + attrs->cap.max_recv_wr == 0) { 339 siw_dbg(base_dev, "QP must have send or receive queue\n"); 340 rv = -EINVAL; 341 goto err_out; 342 } 343 scq = to_siw_cq(attrs->send_cq); 344 rcq = to_siw_cq(attrs->recv_cq); 345 346 if (!scq || (!rcq && !attrs->srq)) { 347 siw_dbg(base_dev, "send CQ or receive CQ invalid\n"); 348 rv = -EINVAL; 349 goto err_out; 350 } 351 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 352 if (!qp) { 353 rv = -ENOMEM; 354 goto err_out; 355 } 356 init_rwsem(&qp->state_lock); 357 spin_lock_init(&qp->sq_lock); 358 spin_lock_init(&qp->rq_lock); 359 spin_lock_init(&qp->orq_lock); 360 361 rv = siw_qp_add(sdev, qp); 362 if (rv) 363 goto err_out; 364 365 /* All queue indices are derived from modulo operations 366 * on a free running 'get' (consumer) and 'put' (producer) 367 * unsigned counter. Having queue sizes at power of two 368 * avoids handling counter wrap around. 369 */ 370 num_sqe = roundup_pow_of_two(attrs->cap.max_send_wr); 371 num_rqe = roundup_pow_of_two(attrs->cap.max_recv_wr); 372 373 if (udata) 374 qp->sendq = vmalloc_user(num_sqe * sizeof(struct siw_sqe)); 375 else 376 qp->sendq = vzalloc(num_sqe * sizeof(struct siw_sqe)); 377 378 if (qp->sendq == NULL) { 379 siw_dbg(base_dev, "SQ size %d alloc failed\n", num_sqe); 380 rv = -ENOMEM; 381 goto err_out_xa; 382 } 383 if (attrs->sq_sig_type != IB_SIGNAL_REQ_WR) { 384 if (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) 385 qp->attrs.flags |= SIW_SIGNAL_ALL_WR; 386 else { 387 rv = -EINVAL; 388 goto err_out_xa; 389 } 390 } 391 qp->pd = pd; 392 qp->scq = scq; 393 qp->rcq = rcq; 394 395 if (attrs->srq) { 396 /* 397 * SRQ support. 398 * Verbs 6.3.7: ignore RQ size, if SRQ present 399 * Verbs 6.3.5: do not check PD of SRQ against PD of QP 400 */ 401 qp->srq = to_siw_srq(attrs->srq); 402 qp->attrs.rq_size = 0; 403 siw_dbg(base_dev, "QP [%u]: SRQ attached\n", 404 qp->base_qp.qp_num); 405 } else if (num_rqe) { 406 if (udata) 407 qp->recvq = 408 vmalloc_user(num_rqe * sizeof(struct siw_rqe)); 409 else 410 qp->recvq = vzalloc(num_rqe * sizeof(struct siw_rqe)); 411 412 if (qp->recvq == NULL) { 413 siw_dbg(base_dev, "RQ size %d alloc failed\n", num_rqe); 414 rv = -ENOMEM; 415 goto err_out_xa; 416 } 417 qp->attrs.rq_size = num_rqe; 418 } 419 qp->attrs.sq_size = num_sqe; 420 qp->attrs.sq_max_sges = attrs->cap.max_send_sge; 421 qp->attrs.rq_max_sges = attrs->cap.max_recv_sge; 422 423 /* Make those two tunables fixed for now. */ 424 qp->tx_ctx.gso_seg_limit = 1; 425 qp->tx_ctx.zcopy_tx = zcopy_tx; 426 427 qp->attrs.state = SIW_QP_STATE_IDLE; 428 429 if (udata) { 430 struct siw_uresp_create_qp uresp = {}; 431 432 uresp.num_sqe = num_sqe; 433 uresp.num_rqe = num_rqe; 434 uresp.qp_id = qp_id(qp); 435 436 if (qp->sendq) { 437 length = num_sqe * sizeof(struct siw_sqe); 438 qp->sq_entry = 439 siw_mmap_entry_insert(uctx, qp->sendq, 440 length, &uresp.sq_key); 441 if (!qp->sq_entry) { 442 rv = -ENOMEM; 443 goto err_out_xa; 444 } 445 } 446 447 if (qp->recvq) { 448 length = num_rqe * sizeof(struct siw_rqe); 449 qp->rq_entry = 450 siw_mmap_entry_insert(uctx, qp->recvq, 451 length, &uresp.rq_key); 452 if (!qp->rq_entry) { 453 uresp.sq_key = SIW_INVAL_UOBJ_KEY; 454 rv = -ENOMEM; 455 goto err_out_xa; 456 } 457 } 458 459 if (udata->outlen < sizeof(uresp)) { 460 rv = -EINVAL; 461 goto err_out_xa; 462 } 463 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 464 if (rv) 465 goto err_out_xa; 466 } 467 qp->tx_cpu = siw_get_tx_cpu(sdev); 468 if (qp->tx_cpu < 0) { 469 rv = -EINVAL; 470 goto err_out_xa; 471 } 472 INIT_LIST_HEAD(&qp->devq); 473 spin_lock_irqsave(&sdev->lock, flags); 474 list_add_tail(&qp->devq, &sdev->qp_list); 475 spin_unlock_irqrestore(&sdev->lock, flags); 476 477 return &qp->base_qp; 478 479 err_out_xa: 480 xa_erase(&sdev->qp_xa, qp_id(qp)); 481 err_out: 482 if (qp) { 483 if (uctx) { 484 rdma_user_mmap_entry_remove(qp->sq_entry); 485 rdma_user_mmap_entry_remove(qp->rq_entry); 486 } 487 vfree(qp->sendq); 488 vfree(qp->recvq); 489 kfree(qp); 490 } 491 atomic_dec(&sdev->num_qp); 492 493 return ERR_PTR(rv); 494 } 495 496 /* 497 * Minimum siw_query_qp() verb interface. 498 * 499 * @qp_attr_mask is not used but all available information is provided 500 */ 501 int siw_query_qp(struct ib_qp *base_qp, struct ib_qp_attr *qp_attr, 502 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 503 { 504 struct siw_qp *qp; 505 struct siw_device *sdev; 506 507 if (base_qp && qp_attr && qp_init_attr) { 508 qp = to_siw_qp(base_qp); 509 sdev = to_siw_dev(base_qp->device); 510 } else { 511 return -EINVAL; 512 } 513 qp_attr->cap.max_inline_data = SIW_MAX_INLINE; 514 qp_attr->cap.max_send_wr = qp->attrs.sq_size; 515 qp_attr->cap.max_send_sge = qp->attrs.sq_max_sges; 516 qp_attr->cap.max_recv_wr = qp->attrs.rq_size; 517 qp_attr->cap.max_recv_sge = qp->attrs.rq_max_sges; 518 qp_attr->path_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu); 519 qp_attr->max_rd_atomic = qp->attrs.irq_size; 520 qp_attr->max_dest_rd_atomic = qp->attrs.orq_size; 521 522 qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE | 523 IB_ACCESS_REMOTE_WRITE | 524 IB_ACCESS_REMOTE_READ; 525 526 qp_init_attr->qp_type = base_qp->qp_type; 527 qp_init_attr->send_cq = base_qp->send_cq; 528 qp_init_attr->recv_cq = base_qp->recv_cq; 529 qp_init_attr->srq = base_qp->srq; 530 531 qp_init_attr->cap = qp_attr->cap; 532 533 return 0; 534 } 535 536 int siw_verbs_modify_qp(struct ib_qp *base_qp, struct ib_qp_attr *attr, 537 int attr_mask, struct ib_udata *udata) 538 { 539 struct siw_qp_attrs new_attrs; 540 enum siw_qp_attr_mask siw_attr_mask = 0; 541 struct siw_qp *qp = to_siw_qp(base_qp); 542 int rv = 0; 543 544 if (!attr_mask) 545 return 0; 546 547 memset(&new_attrs, 0, sizeof(new_attrs)); 548 549 if (attr_mask & IB_QP_ACCESS_FLAGS) { 550 siw_attr_mask = SIW_QP_ATTR_ACCESS_FLAGS; 551 552 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 553 new_attrs.flags |= SIW_RDMA_READ_ENABLED; 554 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 555 new_attrs.flags |= SIW_RDMA_WRITE_ENABLED; 556 if (attr->qp_access_flags & IB_ACCESS_MW_BIND) 557 new_attrs.flags |= SIW_RDMA_BIND_ENABLED; 558 } 559 if (attr_mask & IB_QP_STATE) { 560 siw_dbg_qp(qp, "desired IB QP state: %s\n", 561 ib_qp_state_to_string[attr->qp_state]); 562 563 new_attrs.state = ib_qp_state_to_siw_qp_state[attr->qp_state]; 564 565 if (new_attrs.state > SIW_QP_STATE_RTS) 566 qp->tx_ctx.tx_suspend = 1; 567 568 siw_attr_mask |= SIW_QP_ATTR_STATE; 569 } 570 if (!siw_attr_mask) 571 goto out; 572 573 down_write(&qp->state_lock); 574 575 rv = siw_qp_modify(qp, &new_attrs, siw_attr_mask); 576 577 up_write(&qp->state_lock); 578 out: 579 return rv; 580 } 581 582 int siw_destroy_qp(struct ib_qp *base_qp, struct ib_udata *udata) 583 { 584 struct siw_qp *qp = to_siw_qp(base_qp); 585 struct siw_ucontext *uctx = 586 rdma_udata_to_drv_context(udata, struct siw_ucontext, 587 base_ucontext); 588 struct siw_qp_attrs qp_attrs; 589 590 siw_dbg_qp(qp, "state %d\n", qp->attrs.state); 591 592 /* 593 * Mark QP as in process of destruction to prevent from 594 * any async callbacks to RDMA core 595 */ 596 qp->attrs.flags |= SIW_QP_IN_DESTROY; 597 qp->rx_stream.rx_suspend = 1; 598 599 if (uctx) { 600 rdma_user_mmap_entry_remove(qp->sq_entry); 601 rdma_user_mmap_entry_remove(qp->rq_entry); 602 } 603 604 down_write(&qp->state_lock); 605 606 qp_attrs.state = SIW_QP_STATE_ERROR; 607 siw_qp_modify(qp, &qp_attrs, SIW_QP_ATTR_STATE); 608 609 if (qp->cep) { 610 siw_cep_put(qp->cep); 611 qp->cep = NULL; 612 } 613 up_write(&qp->state_lock); 614 615 kfree(qp->tx_ctx.mpa_crc_hd); 616 kfree(qp->rx_stream.mpa_crc_hd); 617 618 qp->scq = qp->rcq = NULL; 619 620 siw_qp_put(qp); 621 622 return 0; 623 } 624 625 /* 626 * siw_copy_inline_sgl() 627 * 628 * Prepare sgl of inlined data for sending. For userland callers 629 * function checks if given buffer addresses and len's are within 630 * process context bounds. 631 * Data from all provided sge's are copied together into the wqe, 632 * referenced by a single sge. 633 */ 634 static int siw_copy_inline_sgl(const struct ib_send_wr *core_wr, 635 struct siw_sqe *sqe) 636 { 637 struct ib_sge *core_sge = core_wr->sg_list; 638 void *kbuf = &sqe->sge[1]; 639 int num_sge = core_wr->num_sge, bytes = 0; 640 641 sqe->sge[0].laddr = (uintptr_t)kbuf; 642 sqe->sge[0].lkey = 0; 643 644 while (num_sge--) { 645 if (!core_sge->length) { 646 core_sge++; 647 continue; 648 } 649 bytes += core_sge->length; 650 if (bytes > SIW_MAX_INLINE) { 651 bytes = -EINVAL; 652 break; 653 } 654 memcpy(kbuf, (void *)(uintptr_t)core_sge->addr, 655 core_sge->length); 656 657 kbuf += core_sge->length; 658 core_sge++; 659 } 660 sqe->sge[0].length = bytes > 0 ? bytes : 0; 661 sqe->num_sge = bytes > 0 ? 1 : 0; 662 663 return bytes; 664 } 665 666 /* Complete SQ WR's without processing */ 667 static int siw_sq_flush_wr(struct siw_qp *qp, const struct ib_send_wr *wr, 668 const struct ib_send_wr **bad_wr) 669 { 670 struct siw_sqe sqe = {}; 671 int rv = 0; 672 673 while (wr) { 674 sqe.id = wr->wr_id; 675 sqe.opcode = wr->opcode; 676 rv = siw_sqe_complete(qp, &sqe, 0, SIW_WC_WR_FLUSH_ERR); 677 if (rv) { 678 if (bad_wr) 679 *bad_wr = wr; 680 break; 681 } 682 wr = wr->next; 683 } 684 return rv; 685 } 686 687 /* Complete RQ WR's without processing */ 688 static int siw_rq_flush_wr(struct siw_qp *qp, const struct ib_recv_wr *wr, 689 const struct ib_recv_wr **bad_wr) 690 { 691 struct siw_rqe rqe = {}; 692 int rv = 0; 693 694 while (wr) { 695 rqe.id = wr->wr_id; 696 rv = siw_rqe_complete(qp, &rqe, 0, 0, SIW_WC_WR_FLUSH_ERR); 697 if (rv) { 698 if (bad_wr) 699 *bad_wr = wr; 700 break; 701 } 702 wr = wr->next; 703 } 704 return rv; 705 } 706 707 /* 708 * siw_post_send() 709 * 710 * Post a list of S-WR's to a SQ. 711 * 712 * @base_qp: Base QP contained in siw QP 713 * @wr: Null terminated list of user WR's 714 * @bad_wr: Points to failing WR in case of synchronous failure. 715 */ 716 int siw_post_send(struct ib_qp *base_qp, const struct ib_send_wr *wr, 717 const struct ib_send_wr **bad_wr) 718 { 719 struct siw_qp *qp = to_siw_qp(base_qp); 720 struct siw_wqe *wqe = tx_wqe(qp); 721 722 unsigned long flags; 723 int rv = 0; 724 725 if (wr && !rdma_is_kernel_res(&qp->base_qp.res)) { 726 siw_dbg_qp(qp, "wr must be empty for user mapped sq\n"); 727 *bad_wr = wr; 728 return -EINVAL; 729 } 730 731 /* 732 * Try to acquire QP state lock. Must be non-blocking 733 * to accommodate kernel clients needs. 734 */ 735 if (!down_read_trylock(&qp->state_lock)) { 736 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 737 /* 738 * ERROR state is final, so we can be sure 739 * this state will not change as long as the QP 740 * exists. 741 * 742 * This handles an ib_drain_sq() call with 743 * a concurrent request to set the QP state 744 * to ERROR. 745 */ 746 rv = siw_sq_flush_wr(qp, wr, bad_wr); 747 } else { 748 siw_dbg_qp(qp, "QP locked, state %d\n", 749 qp->attrs.state); 750 *bad_wr = wr; 751 rv = -ENOTCONN; 752 } 753 return rv; 754 } 755 if (unlikely(qp->attrs.state != SIW_QP_STATE_RTS)) { 756 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 757 /* 758 * Immediately flush this WR to CQ, if QP 759 * is in ERROR state. SQ is guaranteed to 760 * be empty, so WR complets in-order. 761 * 762 * Typically triggered by ib_drain_sq(). 763 */ 764 rv = siw_sq_flush_wr(qp, wr, bad_wr); 765 } else { 766 siw_dbg_qp(qp, "QP out of state %d\n", 767 qp->attrs.state); 768 *bad_wr = wr; 769 rv = -ENOTCONN; 770 } 771 up_read(&qp->state_lock); 772 return rv; 773 } 774 spin_lock_irqsave(&qp->sq_lock, flags); 775 776 while (wr) { 777 u32 idx = qp->sq_put % qp->attrs.sq_size; 778 struct siw_sqe *sqe = &qp->sendq[idx]; 779 780 if (sqe->flags) { 781 siw_dbg_qp(qp, "sq full\n"); 782 rv = -ENOMEM; 783 break; 784 } 785 if (wr->num_sge > qp->attrs.sq_max_sges) { 786 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge); 787 rv = -EINVAL; 788 break; 789 } 790 sqe->id = wr->wr_id; 791 792 if ((wr->send_flags & IB_SEND_SIGNALED) || 793 (qp->attrs.flags & SIW_SIGNAL_ALL_WR)) 794 sqe->flags |= SIW_WQE_SIGNALLED; 795 796 if (wr->send_flags & IB_SEND_FENCE) 797 sqe->flags |= SIW_WQE_READ_FENCE; 798 799 switch (wr->opcode) { 800 case IB_WR_SEND: 801 case IB_WR_SEND_WITH_INV: 802 if (wr->send_flags & IB_SEND_SOLICITED) 803 sqe->flags |= SIW_WQE_SOLICITED; 804 805 if (!(wr->send_flags & IB_SEND_INLINE)) { 806 siw_copy_sgl(wr->sg_list, sqe->sge, 807 wr->num_sge); 808 sqe->num_sge = wr->num_sge; 809 } else { 810 rv = siw_copy_inline_sgl(wr, sqe); 811 if (rv <= 0) { 812 rv = -EINVAL; 813 break; 814 } 815 sqe->flags |= SIW_WQE_INLINE; 816 sqe->num_sge = 1; 817 } 818 if (wr->opcode == IB_WR_SEND) 819 sqe->opcode = SIW_OP_SEND; 820 else { 821 sqe->opcode = SIW_OP_SEND_REMOTE_INV; 822 sqe->rkey = wr->ex.invalidate_rkey; 823 } 824 break; 825 826 case IB_WR_RDMA_READ_WITH_INV: 827 case IB_WR_RDMA_READ: 828 /* 829 * iWarp restricts RREAD sink to SGL containing 830 * 1 SGE only. we could relax to SGL with multiple 831 * elements referring the SAME ltag or even sending 832 * a private per-rreq tag referring to a checked 833 * local sgl with MULTIPLE ltag's. 834 */ 835 if (unlikely(wr->num_sge != 1)) { 836 rv = -EINVAL; 837 break; 838 } 839 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 1); 840 /* 841 * NOTE: zero length RREAD is allowed! 842 */ 843 sqe->raddr = rdma_wr(wr)->remote_addr; 844 sqe->rkey = rdma_wr(wr)->rkey; 845 sqe->num_sge = 1; 846 847 if (wr->opcode == IB_WR_RDMA_READ) 848 sqe->opcode = SIW_OP_READ; 849 else 850 sqe->opcode = SIW_OP_READ_LOCAL_INV; 851 break; 852 853 case IB_WR_RDMA_WRITE: 854 if (!(wr->send_flags & IB_SEND_INLINE)) { 855 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 856 wr->num_sge); 857 sqe->num_sge = wr->num_sge; 858 } else { 859 rv = siw_copy_inline_sgl(wr, sqe); 860 if (unlikely(rv < 0)) { 861 rv = -EINVAL; 862 break; 863 } 864 sqe->flags |= SIW_WQE_INLINE; 865 sqe->num_sge = 1; 866 } 867 sqe->raddr = rdma_wr(wr)->remote_addr; 868 sqe->rkey = rdma_wr(wr)->rkey; 869 sqe->opcode = SIW_OP_WRITE; 870 break; 871 872 case IB_WR_REG_MR: 873 sqe->base_mr = (uintptr_t)reg_wr(wr)->mr; 874 sqe->rkey = reg_wr(wr)->key; 875 sqe->access = reg_wr(wr)->access & IWARP_ACCESS_MASK; 876 sqe->opcode = SIW_OP_REG_MR; 877 break; 878 879 case IB_WR_LOCAL_INV: 880 sqe->rkey = wr->ex.invalidate_rkey; 881 sqe->opcode = SIW_OP_INVAL_STAG; 882 break; 883 884 default: 885 siw_dbg_qp(qp, "ib wr type %d unsupported\n", 886 wr->opcode); 887 rv = -EINVAL; 888 break; 889 } 890 siw_dbg_qp(qp, "opcode %d, flags 0x%x, wr_id 0x%pK\n", 891 sqe->opcode, sqe->flags, 892 (void *)(uintptr_t)sqe->id); 893 894 if (unlikely(rv < 0)) 895 break; 896 897 /* make SQE only valid after completely written */ 898 smp_wmb(); 899 sqe->flags |= SIW_WQE_VALID; 900 901 qp->sq_put++; 902 wr = wr->next; 903 } 904 905 /* 906 * Send directly if SQ processing is not in progress. 907 * Eventual immediate errors (rv < 0) do not affect the involved 908 * RI resources (Verbs, 8.3.1) and thus do not prevent from SQ 909 * processing, if new work is already pending. But rv must be passed 910 * to caller. 911 */ 912 if (wqe->wr_status != SIW_WR_IDLE) { 913 spin_unlock_irqrestore(&qp->sq_lock, flags); 914 goto skip_direct_sending; 915 } 916 rv = siw_activate_tx(qp); 917 spin_unlock_irqrestore(&qp->sq_lock, flags); 918 919 if (rv <= 0) 920 goto skip_direct_sending; 921 922 if (rdma_is_kernel_res(&qp->base_qp.res)) { 923 rv = siw_sq_start(qp); 924 } else { 925 qp->tx_ctx.in_syscall = 1; 926 927 if (siw_qp_sq_process(qp) != 0 && !(qp->tx_ctx.tx_suspend)) 928 siw_qp_cm_drop(qp, 0); 929 930 qp->tx_ctx.in_syscall = 0; 931 } 932 skip_direct_sending: 933 934 up_read(&qp->state_lock); 935 936 if (rv >= 0) 937 return 0; 938 /* 939 * Immediate error 940 */ 941 siw_dbg_qp(qp, "error %d\n", rv); 942 943 *bad_wr = wr; 944 return rv; 945 } 946 947 /* 948 * siw_post_receive() 949 * 950 * Post a list of R-WR's to a RQ. 951 * 952 * @base_qp: Base QP contained in siw QP 953 * @wr: Null terminated list of user WR's 954 * @bad_wr: Points to failing WR in case of synchronous failure. 955 */ 956 int siw_post_receive(struct ib_qp *base_qp, const struct ib_recv_wr *wr, 957 const struct ib_recv_wr **bad_wr) 958 { 959 struct siw_qp *qp = to_siw_qp(base_qp); 960 unsigned long flags; 961 int rv = 0; 962 963 if (qp->srq) { 964 *bad_wr = wr; 965 return -EOPNOTSUPP; /* what else from errno.h? */ 966 } 967 if (!rdma_is_kernel_res(&qp->base_qp.res)) { 968 siw_dbg_qp(qp, "no kernel post_recv for user mapped rq\n"); 969 *bad_wr = wr; 970 return -EINVAL; 971 } 972 973 /* 974 * Try to acquire QP state lock. Must be non-blocking 975 * to accommodate kernel clients needs. 976 */ 977 if (!down_read_trylock(&qp->state_lock)) { 978 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 979 /* 980 * ERROR state is final, so we can be sure 981 * this state will not change as long as the QP 982 * exists. 983 * 984 * This handles an ib_drain_rq() call with 985 * a concurrent request to set the QP state 986 * to ERROR. 987 */ 988 rv = siw_rq_flush_wr(qp, wr, bad_wr); 989 } else { 990 siw_dbg_qp(qp, "QP locked, state %d\n", 991 qp->attrs.state); 992 *bad_wr = wr; 993 rv = -ENOTCONN; 994 } 995 return rv; 996 } 997 if (qp->attrs.state > SIW_QP_STATE_RTS) { 998 if (qp->attrs.state == SIW_QP_STATE_ERROR) { 999 /* 1000 * Immediately flush this WR to CQ, if QP 1001 * is in ERROR state. RQ is guaranteed to 1002 * be empty, so WR complets in-order. 1003 * 1004 * Typically triggered by ib_drain_rq(). 1005 */ 1006 rv = siw_rq_flush_wr(qp, wr, bad_wr); 1007 } else { 1008 siw_dbg_qp(qp, "QP out of state %d\n", 1009 qp->attrs.state); 1010 *bad_wr = wr; 1011 rv = -ENOTCONN; 1012 } 1013 up_read(&qp->state_lock); 1014 return rv; 1015 } 1016 /* 1017 * Serialize potentially multiple producers. 1018 * Not needed for single threaded consumer side. 1019 */ 1020 spin_lock_irqsave(&qp->rq_lock, flags); 1021 1022 while (wr) { 1023 u32 idx = qp->rq_put % qp->attrs.rq_size; 1024 struct siw_rqe *rqe = &qp->recvq[idx]; 1025 1026 if (rqe->flags) { 1027 siw_dbg_qp(qp, "RQ full\n"); 1028 rv = -ENOMEM; 1029 break; 1030 } 1031 if (wr->num_sge > qp->attrs.rq_max_sges) { 1032 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge); 1033 rv = -EINVAL; 1034 break; 1035 } 1036 rqe->id = wr->wr_id; 1037 rqe->num_sge = wr->num_sge; 1038 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge); 1039 1040 /* make sure RQE is completely written before valid */ 1041 smp_wmb(); 1042 1043 rqe->flags = SIW_WQE_VALID; 1044 1045 qp->rq_put++; 1046 wr = wr->next; 1047 } 1048 spin_unlock_irqrestore(&qp->rq_lock, flags); 1049 1050 up_read(&qp->state_lock); 1051 1052 if (rv < 0) { 1053 siw_dbg_qp(qp, "error %d\n", rv); 1054 *bad_wr = wr; 1055 } 1056 return rv > 0 ? 0 : rv; 1057 } 1058 1059 int siw_destroy_cq(struct ib_cq *base_cq, struct ib_udata *udata) 1060 { 1061 struct siw_cq *cq = to_siw_cq(base_cq); 1062 struct siw_device *sdev = to_siw_dev(base_cq->device); 1063 struct siw_ucontext *ctx = 1064 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1065 base_ucontext); 1066 1067 siw_dbg_cq(cq, "free CQ resources\n"); 1068 1069 siw_cq_flush(cq); 1070 1071 if (ctx) 1072 rdma_user_mmap_entry_remove(cq->cq_entry); 1073 1074 atomic_dec(&sdev->num_cq); 1075 1076 vfree(cq->queue); 1077 return 0; 1078 } 1079 1080 /* 1081 * siw_create_cq() 1082 * 1083 * Populate CQ of requested size 1084 * 1085 * @base_cq: CQ as allocated by RDMA midlayer 1086 * @attr: Initial CQ attributes 1087 * @udata: relates to user context 1088 */ 1089 1090 int siw_create_cq(struct ib_cq *base_cq, const struct ib_cq_init_attr *attr, 1091 struct ib_udata *udata) 1092 { 1093 struct siw_device *sdev = to_siw_dev(base_cq->device); 1094 struct siw_cq *cq = to_siw_cq(base_cq); 1095 int rv, size = attr->cqe; 1096 1097 if (atomic_inc_return(&sdev->num_cq) > SIW_MAX_CQ) { 1098 siw_dbg(base_cq->device, "too many CQ's\n"); 1099 rv = -ENOMEM; 1100 goto err_out; 1101 } 1102 if (size < 1 || size > sdev->attrs.max_cqe) { 1103 siw_dbg(base_cq->device, "CQ size error: %d\n", size); 1104 rv = -EINVAL; 1105 goto err_out; 1106 } 1107 size = roundup_pow_of_two(size); 1108 cq->base_cq.cqe = size; 1109 cq->num_cqe = size; 1110 1111 if (udata) 1112 cq->queue = vmalloc_user(size * sizeof(struct siw_cqe) + 1113 sizeof(struct siw_cq_ctrl)); 1114 else 1115 cq->queue = vzalloc(size * sizeof(struct siw_cqe) + 1116 sizeof(struct siw_cq_ctrl)); 1117 1118 if (cq->queue == NULL) { 1119 rv = -ENOMEM; 1120 goto err_out; 1121 } 1122 get_random_bytes(&cq->id, 4); 1123 siw_dbg(base_cq->device, "new CQ [%u]\n", cq->id); 1124 1125 spin_lock_init(&cq->lock); 1126 1127 cq->notify = (struct siw_cq_ctrl *)&cq->queue[size]; 1128 1129 if (udata) { 1130 struct siw_uresp_create_cq uresp = {}; 1131 struct siw_ucontext *ctx = 1132 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1133 base_ucontext); 1134 size_t length = size * sizeof(struct siw_cqe) + 1135 sizeof(struct siw_cq_ctrl); 1136 1137 cq->cq_entry = 1138 siw_mmap_entry_insert(ctx, cq->queue, 1139 length, &uresp.cq_key); 1140 if (!cq->cq_entry) { 1141 rv = -ENOMEM; 1142 goto err_out; 1143 } 1144 1145 uresp.cq_id = cq->id; 1146 uresp.num_cqe = size; 1147 1148 if (udata->outlen < sizeof(uresp)) { 1149 rv = -EINVAL; 1150 goto err_out; 1151 } 1152 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1153 if (rv) 1154 goto err_out; 1155 } 1156 return 0; 1157 1158 err_out: 1159 siw_dbg(base_cq->device, "CQ creation failed: %d", rv); 1160 1161 if (cq && cq->queue) { 1162 struct siw_ucontext *ctx = 1163 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1164 base_ucontext); 1165 if (ctx) 1166 rdma_user_mmap_entry_remove(cq->cq_entry); 1167 vfree(cq->queue); 1168 } 1169 atomic_dec(&sdev->num_cq); 1170 1171 return rv; 1172 } 1173 1174 /* 1175 * siw_poll_cq() 1176 * 1177 * Reap CQ entries if available and copy work completion status into 1178 * array of WC's provided by caller. Returns number of reaped CQE's. 1179 * 1180 * @base_cq: Base CQ contained in siw CQ. 1181 * @num_cqe: Maximum number of CQE's to reap. 1182 * @wc: Array of work completions to be filled by siw. 1183 */ 1184 int siw_poll_cq(struct ib_cq *base_cq, int num_cqe, struct ib_wc *wc) 1185 { 1186 struct siw_cq *cq = to_siw_cq(base_cq); 1187 int i; 1188 1189 for (i = 0; i < num_cqe; i++) { 1190 if (!siw_reap_cqe(cq, wc)) 1191 break; 1192 wc++; 1193 } 1194 return i; 1195 } 1196 1197 /* 1198 * siw_req_notify_cq() 1199 * 1200 * Request notification for new CQE's added to that CQ. 1201 * Defined flags: 1202 * o SIW_CQ_NOTIFY_SOLICITED lets siw trigger a notification 1203 * event if a WQE with notification flag set enters the CQ 1204 * o SIW_CQ_NOTIFY_NEXT_COMP lets siw trigger a notification 1205 * event if a WQE enters the CQ. 1206 * o IB_CQ_REPORT_MISSED_EVENTS: return value will provide the 1207 * number of not reaped CQE's regardless of its notification 1208 * type and current or new CQ notification settings. 1209 * 1210 * @base_cq: Base CQ contained in siw CQ. 1211 * @flags: Requested notification flags. 1212 */ 1213 int siw_req_notify_cq(struct ib_cq *base_cq, enum ib_cq_notify_flags flags) 1214 { 1215 struct siw_cq *cq = to_siw_cq(base_cq); 1216 1217 siw_dbg_cq(cq, "flags: 0x%02x\n", flags); 1218 1219 if ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED) 1220 /* 1221 * Enable CQ event for next solicited completion. 1222 * and make it visible to all associated producers. 1223 */ 1224 smp_store_mb(cq->notify->flags, SIW_NOTIFY_SOLICITED); 1225 else 1226 /* 1227 * Enable CQ event for any signalled completion. 1228 * and make it visible to all associated producers. 1229 */ 1230 smp_store_mb(cq->notify->flags, SIW_NOTIFY_ALL); 1231 1232 if (flags & IB_CQ_REPORT_MISSED_EVENTS) 1233 return cq->cq_put - cq->cq_get; 1234 1235 return 0; 1236 } 1237 1238 /* 1239 * siw_dereg_mr() 1240 * 1241 * Release Memory Region. 1242 * 1243 * @base_mr: Base MR contained in siw MR. 1244 * @udata: points to user context, unused. 1245 */ 1246 int siw_dereg_mr(struct ib_mr *base_mr, struct ib_udata *udata) 1247 { 1248 struct siw_mr *mr = to_siw_mr(base_mr); 1249 struct siw_device *sdev = to_siw_dev(base_mr->device); 1250 1251 siw_dbg_mem(mr->mem, "deregister MR\n"); 1252 1253 atomic_dec(&sdev->num_mr); 1254 1255 siw_mr_drop_mem(mr); 1256 kfree_rcu(mr, rcu); 1257 1258 return 0; 1259 } 1260 1261 /* 1262 * siw_reg_user_mr() 1263 * 1264 * Register Memory Region. 1265 * 1266 * @pd: Protection Domain 1267 * @start: starting address of MR (virtual address) 1268 * @len: len of MR 1269 * @rnic_va: not used by siw 1270 * @rights: MR access rights 1271 * @udata: user buffer to communicate STag and Key. 1272 */ 1273 struct ib_mr *siw_reg_user_mr(struct ib_pd *pd, u64 start, u64 len, 1274 u64 rnic_va, int rights, struct ib_udata *udata) 1275 { 1276 struct siw_mr *mr = NULL; 1277 struct siw_umem *umem = NULL; 1278 struct siw_ureq_reg_mr ureq; 1279 struct siw_device *sdev = to_siw_dev(pd->device); 1280 1281 unsigned long mem_limit = rlimit(RLIMIT_MEMLOCK); 1282 int rv; 1283 1284 siw_dbg_pd(pd, "start: 0x%pK, va: 0x%pK, len: %llu\n", 1285 (void *)(uintptr_t)start, (void *)(uintptr_t)rnic_va, 1286 (unsigned long long)len); 1287 1288 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1289 siw_dbg_pd(pd, "too many mr's\n"); 1290 rv = -ENOMEM; 1291 goto err_out; 1292 } 1293 if (!len) { 1294 rv = -EINVAL; 1295 goto err_out; 1296 } 1297 if (mem_limit != RLIM_INFINITY) { 1298 unsigned long num_pages = 1299 (PAGE_ALIGN(len + (start & ~PAGE_MASK))) >> PAGE_SHIFT; 1300 mem_limit >>= PAGE_SHIFT; 1301 1302 if (num_pages > mem_limit - current->mm->locked_vm) { 1303 siw_dbg_pd(pd, "pages req %lu, max %lu, lock %lu\n", 1304 num_pages, mem_limit, 1305 current->mm->locked_vm); 1306 rv = -ENOMEM; 1307 goto err_out; 1308 } 1309 } 1310 umem = siw_umem_get(start, len, ib_access_writable(rights)); 1311 if (IS_ERR(umem)) { 1312 rv = PTR_ERR(umem); 1313 siw_dbg_pd(pd, "getting user memory failed: %d\n", rv); 1314 umem = NULL; 1315 goto err_out; 1316 } 1317 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1318 if (!mr) { 1319 rv = -ENOMEM; 1320 goto err_out; 1321 } 1322 rv = siw_mr_add_mem(mr, pd, umem, start, len, rights); 1323 if (rv) 1324 goto err_out; 1325 1326 if (udata) { 1327 struct siw_uresp_reg_mr uresp = {}; 1328 struct siw_mem *mem = mr->mem; 1329 1330 if (udata->inlen < sizeof(ureq)) { 1331 rv = -EINVAL; 1332 goto err_out; 1333 } 1334 rv = ib_copy_from_udata(&ureq, udata, sizeof(ureq)); 1335 if (rv) 1336 goto err_out; 1337 1338 mr->base_mr.lkey |= ureq.stag_key; 1339 mr->base_mr.rkey |= ureq.stag_key; 1340 mem->stag |= ureq.stag_key; 1341 uresp.stag = mem->stag; 1342 1343 if (udata->outlen < sizeof(uresp)) { 1344 rv = -EINVAL; 1345 goto err_out; 1346 } 1347 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1348 if (rv) 1349 goto err_out; 1350 } 1351 mr->mem->stag_valid = 1; 1352 1353 return &mr->base_mr; 1354 1355 err_out: 1356 atomic_dec(&sdev->num_mr); 1357 if (mr) { 1358 if (mr->mem) 1359 siw_mr_drop_mem(mr); 1360 kfree_rcu(mr, rcu); 1361 } else { 1362 if (umem) 1363 siw_umem_release(umem, false); 1364 } 1365 return ERR_PTR(rv); 1366 } 1367 1368 struct ib_mr *siw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1369 u32 max_sge) 1370 { 1371 struct siw_device *sdev = to_siw_dev(pd->device); 1372 struct siw_mr *mr = NULL; 1373 struct siw_pbl *pbl = NULL; 1374 int rv; 1375 1376 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1377 siw_dbg_pd(pd, "too many mr's\n"); 1378 rv = -ENOMEM; 1379 goto err_out; 1380 } 1381 if (mr_type != IB_MR_TYPE_MEM_REG) { 1382 siw_dbg_pd(pd, "mr type %d unsupported\n", mr_type); 1383 rv = -EOPNOTSUPP; 1384 goto err_out; 1385 } 1386 if (max_sge > SIW_MAX_SGE_PBL) { 1387 siw_dbg_pd(pd, "too many sge's: %d\n", max_sge); 1388 rv = -ENOMEM; 1389 goto err_out; 1390 } 1391 pbl = siw_pbl_alloc(max_sge); 1392 if (IS_ERR(pbl)) { 1393 rv = PTR_ERR(pbl); 1394 siw_dbg_pd(pd, "pbl allocation failed: %d\n", rv); 1395 pbl = NULL; 1396 goto err_out; 1397 } 1398 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1399 if (!mr) { 1400 rv = -ENOMEM; 1401 goto err_out; 1402 } 1403 rv = siw_mr_add_mem(mr, pd, pbl, 0, max_sge * PAGE_SIZE, 0); 1404 if (rv) 1405 goto err_out; 1406 1407 mr->mem->is_pbl = 1; 1408 1409 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag); 1410 1411 return &mr->base_mr; 1412 1413 err_out: 1414 atomic_dec(&sdev->num_mr); 1415 1416 if (!mr) { 1417 kfree(pbl); 1418 } else { 1419 if (mr->mem) 1420 siw_mr_drop_mem(mr); 1421 kfree_rcu(mr, rcu); 1422 } 1423 siw_dbg_pd(pd, "failed: %d\n", rv); 1424 1425 return ERR_PTR(rv); 1426 } 1427 1428 /* Just used to count number of pages being mapped */ 1429 static int siw_set_pbl_page(struct ib_mr *base_mr, u64 buf_addr) 1430 { 1431 return 0; 1432 } 1433 1434 int siw_map_mr_sg(struct ib_mr *base_mr, struct scatterlist *sl, int num_sle, 1435 unsigned int *sg_off) 1436 { 1437 struct scatterlist *slp; 1438 struct siw_mr *mr = to_siw_mr(base_mr); 1439 struct siw_mem *mem = mr->mem; 1440 struct siw_pbl *pbl = mem->pbl; 1441 struct siw_pble *pble; 1442 unsigned long pbl_size; 1443 int i, rv; 1444 1445 if (!pbl) { 1446 siw_dbg_mem(mem, "no PBL allocated\n"); 1447 return -EINVAL; 1448 } 1449 pble = pbl->pbe; 1450 1451 if (pbl->max_buf < num_sle) { 1452 siw_dbg_mem(mem, "too many SGE's: %d > %d\n", 1453 mem->pbl->max_buf, num_sle); 1454 return -ENOMEM; 1455 } 1456 for_each_sg(sl, slp, num_sle, i) { 1457 if (sg_dma_len(slp) == 0) { 1458 siw_dbg_mem(mem, "empty SGE\n"); 1459 return -EINVAL; 1460 } 1461 if (i == 0) { 1462 pble->addr = sg_dma_address(slp); 1463 pble->size = sg_dma_len(slp); 1464 pble->pbl_off = 0; 1465 pbl_size = pble->size; 1466 pbl->num_buf = 1; 1467 } else { 1468 /* Merge PBL entries if adjacent */ 1469 if (pble->addr + pble->size == sg_dma_address(slp)) { 1470 pble->size += sg_dma_len(slp); 1471 } else { 1472 pble++; 1473 pbl->num_buf++; 1474 pble->addr = sg_dma_address(slp); 1475 pble->size = sg_dma_len(slp); 1476 pble->pbl_off = pbl_size; 1477 } 1478 pbl_size += sg_dma_len(slp); 1479 } 1480 siw_dbg_mem(mem, 1481 "sge[%d], size %u, addr 0x%p, total %lu\n", 1482 i, pble->size, (void *)(uintptr_t)pble->addr, 1483 pbl_size); 1484 } 1485 rv = ib_sg_to_pages(base_mr, sl, num_sle, sg_off, siw_set_pbl_page); 1486 if (rv > 0) { 1487 mem->len = base_mr->length; 1488 mem->va = base_mr->iova; 1489 siw_dbg_mem(mem, 1490 "%llu bytes, start 0x%pK, %u SLE to %u entries\n", 1491 mem->len, (void *)(uintptr_t)mem->va, num_sle, 1492 pbl->num_buf); 1493 } 1494 return rv; 1495 } 1496 1497 /* 1498 * siw_get_dma_mr() 1499 * 1500 * Create a (empty) DMA memory region, where no umem is attached. 1501 */ 1502 struct ib_mr *siw_get_dma_mr(struct ib_pd *pd, int rights) 1503 { 1504 struct siw_device *sdev = to_siw_dev(pd->device); 1505 struct siw_mr *mr = NULL; 1506 int rv; 1507 1508 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) { 1509 siw_dbg_pd(pd, "too many mr's\n"); 1510 rv = -ENOMEM; 1511 goto err_out; 1512 } 1513 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 1514 if (!mr) { 1515 rv = -ENOMEM; 1516 goto err_out; 1517 } 1518 rv = siw_mr_add_mem(mr, pd, NULL, 0, ULONG_MAX, rights); 1519 if (rv) 1520 goto err_out; 1521 1522 mr->mem->stag_valid = 1; 1523 1524 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag); 1525 1526 return &mr->base_mr; 1527 1528 err_out: 1529 if (rv) 1530 kfree(mr); 1531 1532 atomic_dec(&sdev->num_mr); 1533 1534 return ERR_PTR(rv); 1535 } 1536 1537 /* 1538 * siw_create_srq() 1539 * 1540 * Create Shared Receive Queue of attributes @init_attrs 1541 * within protection domain given by @pd. 1542 * 1543 * @base_srq: Base SRQ contained in siw SRQ. 1544 * @init_attrs: SRQ init attributes. 1545 * @udata: points to user context 1546 */ 1547 int siw_create_srq(struct ib_srq *base_srq, 1548 struct ib_srq_init_attr *init_attrs, struct ib_udata *udata) 1549 { 1550 struct siw_srq *srq = to_siw_srq(base_srq); 1551 struct ib_srq_attr *attrs = &init_attrs->attr; 1552 struct siw_device *sdev = to_siw_dev(base_srq->device); 1553 struct siw_ucontext *ctx = 1554 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1555 base_ucontext); 1556 int rv; 1557 1558 if (atomic_inc_return(&sdev->num_srq) > SIW_MAX_SRQ) { 1559 siw_dbg_pd(base_srq->pd, "too many SRQ's\n"); 1560 rv = -ENOMEM; 1561 goto err_out; 1562 } 1563 if (attrs->max_wr == 0 || attrs->max_wr > SIW_MAX_SRQ_WR || 1564 attrs->max_sge > SIW_MAX_SGE || attrs->srq_limit > attrs->max_wr) { 1565 rv = -EINVAL; 1566 goto err_out; 1567 } 1568 srq->max_sge = attrs->max_sge; 1569 srq->num_rqe = roundup_pow_of_two(attrs->max_wr); 1570 srq->limit = attrs->srq_limit; 1571 if (srq->limit) 1572 srq->armed = true; 1573 1574 srq->is_kernel_res = !udata; 1575 1576 if (udata) 1577 srq->recvq = 1578 vmalloc_user(srq->num_rqe * sizeof(struct siw_rqe)); 1579 else 1580 srq->recvq = vzalloc(srq->num_rqe * sizeof(struct siw_rqe)); 1581 1582 if (srq->recvq == NULL) { 1583 rv = -ENOMEM; 1584 goto err_out; 1585 } 1586 if (udata) { 1587 struct siw_uresp_create_srq uresp = {}; 1588 size_t length = srq->num_rqe * sizeof(struct siw_rqe); 1589 1590 srq->srq_entry = 1591 siw_mmap_entry_insert(ctx, srq->recvq, 1592 length, &uresp.srq_key); 1593 if (!srq->srq_entry) { 1594 rv = -ENOMEM; 1595 goto err_out; 1596 } 1597 1598 uresp.num_rqe = srq->num_rqe; 1599 1600 if (udata->outlen < sizeof(uresp)) { 1601 rv = -EINVAL; 1602 goto err_out; 1603 } 1604 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp)); 1605 if (rv) 1606 goto err_out; 1607 } 1608 spin_lock_init(&srq->lock); 1609 1610 siw_dbg_pd(base_srq->pd, "[SRQ]: success\n"); 1611 1612 return 0; 1613 1614 err_out: 1615 if (srq->recvq) { 1616 if (ctx) 1617 rdma_user_mmap_entry_remove(srq->srq_entry); 1618 vfree(srq->recvq); 1619 } 1620 atomic_dec(&sdev->num_srq); 1621 1622 return rv; 1623 } 1624 1625 /* 1626 * siw_modify_srq() 1627 * 1628 * Modify SRQ. The caller may resize SRQ and/or set/reset notification 1629 * limit and (re)arm IB_EVENT_SRQ_LIMIT_REACHED notification. 1630 * 1631 * NOTE: it is unclear if RDMA core allows for changing the MAX_SGE 1632 * parameter. siw_modify_srq() does not check the attrs->max_sge param. 1633 */ 1634 int siw_modify_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs, 1635 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata) 1636 { 1637 struct siw_srq *srq = to_siw_srq(base_srq); 1638 unsigned long flags; 1639 int rv = 0; 1640 1641 spin_lock_irqsave(&srq->lock, flags); 1642 1643 if (attr_mask & IB_SRQ_MAX_WR) { 1644 /* resize request not yet supported */ 1645 rv = -EOPNOTSUPP; 1646 goto out; 1647 } 1648 if (attr_mask & IB_SRQ_LIMIT) { 1649 if (attrs->srq_limit) { 1650 if (unlikely(attrs->srq_limit > srq->num_rqe)) { 1651 rv = -EINVAL; 1652 goto out; 1653 } 1654 srq->armed = true; 1655 } else { 1656 srq->armed = false; 1657 } 1658 srq->limit = attrs->srq_limit; 1659 } 1660 out: 1661 spin_unlock_irqrestore(&srq->lock, flags); 1662 1663 return rv; 1664 } 1665 1666 /* 1667 * siw_query_srq() 1668 * 1669 * Query SRQ attributes. 1670 */ 1671 int siw_query_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs) 1672 { 1673 struct siw_srq *srq = to_siw_srq(base_srq); 1674 unsigned long flags; 1675 1676 spin_lock_irqsave(&srq->lock, flags); 1677 1678 attrs->max_wr = srq->num_rqe; 1679 attrs->max_sge = srq->max_sge; 1680 attrs->srq_limit = srq->limit; 1681 1682 spin_unlock_irqrestore(&srq->lock, flags); 1683 1684 return 0; 1685 } 1686 1687 /* 1688 * siw_destroy_srq() 1689 * 1690 * Destroy SRQ. 1691 * It is assumed that the SRQ is not referenced by any 1692 * QP anymore - the code trusts the RDMA core environment to keep track 1693 * of QP references. 1694 */ 1695 int siw_destroy_srq(struct ib_srq *base_srq, struct ib_udata *udata) 1696 { 1697 struct siw_srq *srq = to_siw_srq(base_srq); 1698 struct siw_device *sdev = to_siw_dev(base_srq->device); 1699 struct siw_ucontext *ctx = 1700 rdma_udata_to_drv_context(udata, struct siw_ucontext, 1701 base_ucontext); 1702 1703 if (ctx) 1704 rdma_user_mmap_entry_remove(srq->srq_entry); 1705 vfree(srq->recvq); 1706 atomic_dec(&sdev->num_srq); 1707 return 0; 1708 } 1709 1710 /* 1711 * siw_post_srq_recv() 1712 * 1713 * Post a list of receive queue elements to SRQ. 1714 * NOTE: The function does not check or lock a certain SRQ state 1715 * during the post operation. The code simply trusts the 1716 * RDMA core environment. 1717 * 1718 * @base_srq: Base SRQ contained in siw SRQ 1719 * @wr: List of R-WR's 1720 * @bad_wr: Updated to failing WR if posting fails. 1721 */ 1722 int siw_post_srq_recv(struct ib_srq *base_srq, const struct ib_recv_wr *wr, 1723 const struct ib_recv_wr **bad_wr) 1724 { 1725 struct siw_srq *srq = to_siw_srq(base_srq); 1726 unsigned long flags; 1727 int rv = 0; 1728 1729 if (unlikely(!srq->is_kernel_res)) { 1730 siw_dbg_pd(base_srq->pd, 1731 "[SRQ]: no kernel post_recv for mapped srq\n"); 1732 rv = -EINVAL; 1733 goto out; 1734 } 1735 /* 1736 * Serialize potentially multiple producers. 1737 * Also needed to serialize potentially multiple 1738 * consumers. 1739 */ 1740 spin_lock_irqsave(&srq->lock, flags); 1741 1742 while (wr) { 1743 u32 idx = srq->rq_put % srq->num_rqe; 1744 struct siw_rqe *rqe = &srq->recvq[idx]; 1745 1746 if (rqe->flags) { 1747 siw_dbg_pd(base_srq->pd, "SRQ full\n"); 1748 rv = -ENOMEM; 1749 break; 1750 } 1751 if (unlikely(wr->num_sge > srq->max_sge)) { 1752 siw_dbg_pd(base_srq->pd, 1753 "[SRQ]: too many sge's: %d\n", wr->num_sge); 1754 rv = -EINVAL; 1755 break; 1756 } 1757 rqe->id = wr->wr_id; 1758 rqe->num_sge = wr->num_sge; 1759 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge); 1760 1761 /* Make sure S-RQE is completely written before valid */ 1762 smp_wmb(); 1763 1764 rqe->flags = SIW_WQE_VALID; 1765 1766 srq->rq_put++; 1767 wr = wr->next; 1768 } 1769 spin_unlock_irqrestore(&srq->lock, flags); 1770 out: 1771 if (unlikely(rv < 0)) { 1772 siw_dbg_pd(base_srq->pd, "[SRQ]: error %d\n", rv); 1773 *bad_wr = wr; 1774 } 1775 return rv; 1776 } 1777 1778 void siw_qp_event(struct siw_qp *qp, enum ib_event_type etype) 1779 { 1780 struct ib_event event; 1781 struct ib_qp *base_qp = &qp->base_qp; 1782 1783 /* 1784 * Do not report asynchronous errors on QP which gets 1785 * destroyed via verbs interface (siw_destroy_qp()) 1786 */ 1787 if (qp->attrs.flags & SIW_QP_IN_DESTROY) 1788 return; 1789 1790 event.event = etype; 1791 event.device = base_qp->device; 1792 event.element.qp = base_qp; 1793 1794 if (base_qp->event_handler) { 1795 siw_dbg_qp(qp, "reporting event %d\n", etype); 1796 base_qp->event_handler(&event, base_qp->qp_context); 1797 } 1798 } 1799 1800 void siw_cq_event(struct siw_cq *cq, enum ib_event_type etype) 1801 { 1802 struct ib_event event; 1803 struct ib_cq *base_cq = &cq->base_cq; 1804 1805 event.event = etype; 1806 event.device = base_cq->device; 1807 event.element.cq = base_cq; 1808 1809 if (base_cq->event_handler) { 1810 siw_dbg_cq(cq, "reporting CQ event %d\n", etype); 1811 base_cq->event_handler(&event, base_cq->cq_context); 1812 } 1813 } 1814 1815 void siw_srq_event(struct siw_srq *srq, enum ib_event_type etype) 1816 { 1817 struct ib_event event; 1818 struct ib_srq *base_srq = &srq->base_srq; 1819 1820 event.event = etype; 1821 event.device = base_srq->device; 1822 event.element.srq = base_srq; 1823 1824 if (base_srq->event_handler) { 1825 siw_dbg_pd(srq->base_srq.pd, 1826 "reporting SRQ event %d\n", etype); 1827 base_srq->event_handler(&event, base_srq->srq_context); 1828 } 1829 } 1830 1831 void siw_port_event(struct siw_device *sdev, u8 port, enum ib_event_type etype) 1832 { 1833 struct ib_event event; 1834 1835 event.event = etype; 1836 event.device = &sdev->base_dev; 1837 event.element.port_num = port; 1838 1839 siw_dbg(&sdev->base_dev, "reporting port event %d\n", etype); 1840 1841 ib_dispatch_event(&event); 1842 } 1843