1 /* 2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/pci.h> 34 #include <linux/io.h> 35 #include <linux/delay.h> 36 #include <linux/vmalloc.h> 37 #include <linux/aer.h> 38 39 #include "qib.h" 40 41 /* 42 * This file contains PCIe utility routines that are common to the 43 * various QLogic InfiniPath adapters 44 */ 45 46 /* 47 * Code to adjust PCIe capabilities. 48 * To minimize the change footprint, we call it 49 * from qib_pcie_params, which every chip-specific 50 * file calls, even though this violates some 51 * expectations of harmlessness. 52 */ 53 static int qib_tune_pcie_caps(struct qib_devdata *); 54 static int qib_tune_pcie_coalesce(struct qib_devdata *); 55 56 /* 57 * Do all the common PCIe setup and initialization. 58 * devdata is not yet allocated, and is not allocated until after this 59 * routine returns success. Therefore qib_dev_err() can't be used for error 60 * printing. 61 */ 62 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 63 { 64 int ret; 65 66 ret = pci_enable_device(pdev); 67 if (ret) { 68 /* 69 * This can happen (in theory) iff: 70 * We did a chip reset, and then failed to reprogram the 71 * BAR, or the chip reset due to an internal error. We then 72 * unloaded the driver and reloaded it. 73 * 74 * Both reset cases set the BAR back to initial state. For 75 * the latter case, the AER sticky error bit at offset 0x718 76 * should be set, but the Linux kernel doesn't yet know 77 * about that, it appears. If the original BAR was retained 78 * in the kernel data structures, this may be OK. 79 */ 80 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", 81 -ret); 82 goto done; 83 } 84 85 ret = pci_request_regions(pdev, QIB_DRV_NAME); 86 if (ret) { 87 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); 88 goto bail; 89 } 90 91 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 92 if (ret) { 93 /* 94 * If the 64 bit setup fails, try 32 bit. Some systems 95 * do not setup 64 bit maps on systems with 2GB or less 96 * memory installed. 97 */ 98 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 99 if (ret) { 100 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); 101 goto bail; 102 } 103 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 104 } else 105 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 106 if (ret) { 107 qib_early_err(&pdev->dev, 108 "Unable to set DMA consistent mask: %d\n", ret); 109 goto bail; 110 } 111 112 pci_set_master(pdev); 113 ret = pci_enable_pcie_error_reporting(pdev); 114 if (ret) { 115 qib_early_err(&pdev->dev, 116 "Unable to enable pcie error reporting: %d\n", 117 ret); 118 ret = 0; 119 } 120 goto done; 121 122 bail: 123 pci_disable_device(pdev); 124 pci_release_regions(pdev); 125 done: 126 return ret; 127 } 128 129 /* 130 * Do remaining PCIe setup, once dd is allocated, and save away 131 * fields required to re-initialize after a chip reset, or for 132 * various other purposes 133 */ 134 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, 135 const struct pci_device_id *ent) 136 { 137 unsigned long len; 138 resource_size_t addr; 139 140 dd->pcidev = pdev; 141 pci_set_drvdata(pdev, dd); 142 143 addr = pci_resource_start(pdev, 0); 144 len = pci_resource_len(pdev, 0); 145 146 #if defined(__powerpc__) 147 /* There isn't a generic way to specify writethrough mappings */ 148 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU); 149 #else 150 dd->kregbase = ioremap_nocache(addr, len); 151 #endif 152 153 if (!dd->kregbase) 154 return -ENOMEM; 155 156 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); 157 dd->physaddr = addr; /* used for io_remap, etc. */ 158 159 /* 160 * Save BARs to rewrite after device reset. Save all 64 bits of 161 * BAR, just in case. 162 */ 163 dd->pcibar0 = addr; 164 dd->pcibar1 = addr >> 32; 165 dd->deviceid = ent->device; /* save for later use */ 166 dd->vendorid = ent->vendor; 167 168 return 0; 169 } 170 171 /* 172 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior 173 * to releasing the dd memory. 174 * void because none of the core pcie cleanup returns are void 175 */ 176 void qib_pcie_ddcleanup(struct qib_devdata *dd) 177 { 178 u64 __iomem *base = (void __iomem *) dd->kregbase; 179 180 dd->kregbase = NULL; 181 iounmap(base); 182 if (dd->piobase) 183 iounmap(dd->piobase); 184 if (dd->userbase) 185 iounmap(dd->userbase); 186 if (dd->piovl15base) 187 iounmap(dd->piovl15base); 188 189 pci_disable_device(dd->pcidev); 190 pci_release_regions(dd->pcidev); 191 192 pci_set_drvdata(dd->pcidev, NULL); 193 } 194 195 static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt, 196 struct msix_entry *msix_entry) 197 { 198 int ret; 199 u32 tabsize = 0; 200 u16 msix_flags; 201 202 pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags); 203 tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE); 204 if (tabsize > *msixcnt) 205 tabsize = *msixcnt; 206 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize); 207 if (ret > 0) { 208 tabsize = ret; 209 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize); 210 } 211 if (ret) { 212 qib_dev_err(dd, "pci_enable_msix %d vectors failed: %d, " 213 "falling back to INTx\n", tabsize, ret); 214 tabsize = 0; 215 } 216 *msixcnt = tabsize; 217 218 if (ret) 219 qib_enable_intx(dd->pcidev); 220 221 } 222 223 /** 224 * We save the msi lo and hi values, so we can restore them after 225 * chip reset (the kernel PCI infrastructure doesn't yet handle that 226 * correctly. 227 */ 228 static int qib_msi_setup(struct qib_devdata *dd, int pos) 229 { 230 struct pci_dev *pdev = dd->pcidev; 231 u16 control; 232 int ret; 233 234 ret = pci_enable_msi(pdev); 235 if (ret) 236 qib_dev_err(dd, "pci_enable_msi failed: %d, " 237 "interrupts may not work\n", ret); 238 /* continue even if it fails, we may still be OK... */ 239 240 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, 241 &dd->msi_lo); 242 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, 243 &dd->msi_hi); 244 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 245 /* now save the data (vector) info */ 246 pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT) 247 ? 12 : 8), 248 &dd->msi_data); 249 return ret; 250 } 251 252 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent, 253 struct msix_entry *entry) 254 { 255 u16 linkstat, speed; 256 int pos = 0, pose, ret = 1; 257 258 pose = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP); 259 if (!pose) { 260 qib_dev_err(dd, "Can't find PCI Express capability!\n"); 261 /* set up something... */ 262 dd->lbus_width = 1; 263 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 264 goto bail; 265 } 266 267 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSIX); 268 if (nent && *nent && pos) { 269 qib_msix_setup(dd, pos, nent, entry); 270 ret = 0; /* did it, either MSIx or INTx */ 271 } else { 272 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI); 273 if (pos) 274 ret = qib_msi_setup(dd, pos); 275 else 276 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n"); 277 } 278 if (!pos) 279 qib_enable_intx(dd->pcidev); 280 281 pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat); 282 /* 283 * speed is bits 0-3, linkwidth is bits 4-8 284 * no defines for them in headers 285 */ 286 speed = linkstat & 0xf; 287 linkstat >>= 4; 288 linkstat &= 0x1f; 289 dd->lbus_width = linkstat; 290 291 switch (speed) { 292 case 1: 293 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 294 break; 295 case 2: 296 dd->lbus_speed = 5000; /* Gen1, 5GHz */ 297 break; 298 default: /* not defined, assume gen1 */ 299 dd->lbus_speed = 2500; 300 break; 301 } 302 303 /* 304 * Check against expected pcie width and complain if "wrong" 305 * on first initialization, not afterwards (i.e., reset). 306 */ 307 if (minw && linkstat < minw) 308 qib_dev_err(dd, 309 "PCIe width %u (x%u HCA), performance reduced\n", 310 linkstat, minw); 311 312 qib_tune_pcie_caps(dd); 313 314 qib_tune_pcie_coalesce(dd); 315 316 bail: 317 /* fill in string, even on errors */ 318 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 319 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); 320 return ret; 321 } 322 323 /* 324 * Setup pcie interrupt stuff again after a reset. I'd like to just call 325 * pci_enable_msi() again for msi, but when I do that, 326 * the MSI enable bit doesn't get set in the command word, and 327 * we switch to to a different interrupt vector, which is confusing, 328 * so I instead just do it all inline. Perhaps somehow can tie this 329 * into the PCIe hotplug support at some point 330 */ 331 int qib_reinit_intr(struct qib_devdata *dd) 332 { 333 int pos; 334 u16 control; 335 int ret = 0; 336 337 /* If we aren't using MSI, don't restore it */ 338 if (!dd->msi_lo) 339 goto bail; 340 341 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI); 342 if (!pos) { 343 qib_dev_err(dd, "Can't find MSI capability, " 344 "can't restore MSI settings\n"); 345 ret = 0; 346 /* nothing special for MSIx, just MSI */ 347 goto bail; 348 } 349 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, 350 dd->msi_lo); 351 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, 352 dd->msi_hi); 353 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); 354 if (!(control & PCI_MSI_FLAGS_ENABLE)) { 355 control |= PCI_MSI_FLAGS_ENABLE; 356 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, 357 control); 358 } 359 /* now rewrite the data (vector) info */ 360 pci_write_config_word(dd->pcidev, pos + 361 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), 362 dd->msi_data); 363 ret = 1; 364 bail: 365 if (!ret && (dd->flags & QIB_HAS_INTX)) { 366 qib_enable_intx(dd->pcidev); 367 ret = 1; 368 } 369 370 /* and now set the pci master bit again */ 371 pci_set_master(dd->pcidev); 372 373 return ret; 374 } 375 376 /* 377 * Disable msi interrupt if enabled, and clear msi_lo. 378 * This is used primarily for the fallback to INTx, but 379 * is also used in reinit after reset, and during cleanup. 380 */ 381 void qib_nomsi(struct qib_devdata *dd) 382 { 383 dd->msi_lo = 0; 384 pci_disable_msi(dd->pcidev); 385 } 386 387 /* 388 * Same as qib_nosmi, but for MSIx. 389 */ 390 void qib_nomsix(struct qib_devdata *dd) 391 { 392 pci_disable_msix(dd->pcidev); 393 } 394 395 /* 396 * Similar to pci_intx(pdev, 1), except that we make sure 397 * msi(x) is off. 398 */ 399 void qib_enable_intx(struct pci_dev *pdev) 400 { 401 u16 cw, new; 402 int pos; 403 404 /* first, turn on INTx */ 405 pci_read_config_word(pdev, PCI_COMMAND, &cw); 406 new = cw & ~PCI_COMMAND_INTX_DISABLE; 407 if (new != cw) 408 pci_write_config_word(pdev, PCI_COMMAND, new); 409 410 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 411 if (pos) { 412 /* then turn off MSI */ 413 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw); 414 new = cw & ~PCI_MSI_FLAGS_ENABLE; 415 if (new != cw) 416 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new); 417 } 418 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 419 if (pos) { 420 /* then turn off MSIx */ 421 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw); 422 new = cw & ~PCI_MSIX_FLAGS_ENABLE; 423 if (new != cw) 424 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new); 425 } 426 } 427 428 /* 429 * These two routines are helper routines for the device reset code 430 * to move all the pcie code out of the chip-specific driver code. 431 */ 432 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) 433 { 434 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); 435 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 436 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 437 } 438 439 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) 440 { 441 int r; 442 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 443 dd->pcibar0); 444 if (r) 445 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r); 446 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 447 dd->pcibar1); 448 if (r) 449 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r); 450 /* now re-enable memory access, and restore cosmetic settings */ 451 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); 452 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 453 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 454 r = pci_enable_device(dd->pcidev); 455 if (r) 456 qib_dev_err(dd, "pci_enable_device failed after " 457 "reset: %d\n", r); 458 } 459 460 /* code to adjust PCIe capabilities. */ 461 462 static int fld2val(int wd, int mask) 463 { 464 int lsbmask; 465 466 if (!mask) 467 return 0; 468 wd &= mask; 469 lsbmask = mask ^ (mask & (mask - 1)); 470 wd /= lsbmask; 471 return wd; 472 } 473 474 static int val2fld(int wd, int mask) 475 { 476 int lsbmask; 477 478 if (!mask) 479 return 0; 480 lsbmask = mask ^ (mask & (mask - 1)); 481 wd *= lsbmask; 482 return wd; 483 } 484 485 static int qib_pcie_coalesce; 486 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO); 487 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets"); 488 489 /* 490 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300 491 * chipsets. This is known to be unsafe for some revisions of some 492 * of these chipsets, with some BIOS settings, and enabling it on those 493 * systems may result in the system crashing, and/or data corruption. 494 */ 495 static int qib_tune_pcie_coalesce(struct qib_devdata *dd) 496 { 497 int r; 498 struct pci_dev *parent; 499 int ppos; 500 u16 devid; 501 u32 mask, bits, val; 502 503 if (!qib_pcie_coalesce) 504 return 0; 505 506 /* Find out supported and configured values for parent (root) */ 507 parent = dd->pcidev->bus->self; 508 if (parent->bus->parent) { 509 qib_devinfo(dd->pcidev, "Parent not root\n"); 510 return 1; 511 } 512 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); 513 if (!ppos) 514 return 1; 515 if (parent->vendor != 0x8086) 516 return 1; 517 518 /* 519 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1 520 * - bit 11: COALESCE_FORCE: need to set to 0 521 * - bit 10: COALESCE_EN: need to set to 1 522 * (but limitations on some on some chipsets) 523 * 524 * On the Intel 5000, 5100, and 7300 chipsets, there is 525 * also: - bit 25:24: COALESCE_MODE, need to set to 0 526 */ 527 devid = parent->device; 528 if (devid >= 0x25e2 && devid <= 0x25fa) { 529 /* 5000 P/V/X/Z */ 530 if (parent->revision <= 0xb2) 531 bits = 1U << 10; 532 else 533 bits = 7U << 10; 534 mask = (3U << 24) | (7U << 10); 535 } else if (devid >= 0x65e2 && devid <= 0x65fa) { 536 /* 5100 */ 537 bits = 1U << 10; 538 mask = (3U << 24) | (7U << 10); 539 } else if (devid >= 0x4021 && devid <= 0x402e) { 540 /* 5400 */ 541 bits = 7U << 10; 542 mask = 7U << 10; 543 } else if (devid >= 0x3604 && devid <= 0x360a) { 544 /* 7300 */ 545 bits = 7U << 10; 546 mask = (3U << 24) | (7U << 10); 547 } else { 548 /* not one of the chipsets that we know about */ 549 return 1; 550 } 551 pci_read_config_dword(parent, 0x48, &val); 552 val &= ~mask; 553 val |= bits; 554 r = pci_write_config_dword(parent, 0x48, val); 555 return 0; 556 } 557 558 /* 559 * BIOS may not set PCIe bus-utilization parameters for best performance. 560 * Check and optionally adjust them to maximize our throughput. 561 */ 562 static int qib_pcie_caps; 563 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO); 564 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (4lsb), ReadReq (D4..7)"); 565 566 static int qib_tune_pcie_caps(struct qib_devdata *dd) 567 { 568 int ret = 1; /* Assume the worst */ 569 struct pci_dev *parent; 570 int ppos, epos; 571 u16 pcaps, pctl, ecaps, ectl; 572 int rc_sup, ep_sup; 573 int rc_cur, ep_cur; 574 575 /* Find out supported and configured values for parent (root) */ 576 parent = dd->pcidev->bus->self; 577 if (parent->bus->parent) { 578 qib_devinfo(dd->pcidev, "Parent not root\n"); 579 goto bail; 580 } 581 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); 582 if (ppos) { 583 pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps); 584 pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl); 585 } else 586 goto bail; 587 /* Find out supported and configured values for endpoint (us) */ 588 epos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP); 589 if (epos) { 590 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps); 591 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl); 592 } else 593 goto bail; 594 ret = 0; 595 /* Find max payload supported by root, endpoint */ 596 rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD); 597 ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD); 598 if (rc_sup > ep_sup) 599 rc_sup = ep_sup; 600 601 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD); 602 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD); 603 604 /* If Supported greater than limit in module param, limit it */ 605 if (rc_sup > (qib_pcie_caps & 7)) 606 rc_sup = qib_pcie_caps & 7; 607 /* If less than (allowed, supported), bump root payload */ 608 if (rc_sup > rc_cur) { 609 rc_cur = rc_sup; 610 pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) | 611 val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD); 612 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl); 613 } 614 /* If less than (allowed, supported), bump endpoint payload */ 615 if (rc_sup > ep_cur) { 616 ep_cur = rc_sup; 617 ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) | 618 val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD); 619 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl); 620 } 621 622 /* 623 * Now the Read Request size. 624 * No field for max supported, but PCIe spec limits it to 4096, 625 * which is code '5' (log2(4096) - 7) 626 */ 627 rc_sup = 5; 628 if (rc_sup > ((qib_pcie_caps >> 4) & 7)) 629 rc_sup = (qib_pcie_caps >> 4) & 7; 630 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ); 631 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ); 632 633 if (rc_sup > rc_cur) { 634 rc_cur = rc_sup; 635 pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) | 636 val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ); 637 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl); 638 } 639 if (rc_sup > ep_cur) { 640 ep_cur = rc_sup; 641 ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) | 642 val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ); 643 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl); 644 } 645 bail: 646 return ret; 647 } 648 /* End of PCIe capability tuning */ 649 650 /* 651 * From here through qib_pci_err_handler definition is invoked via 652 * PCI error infrastructure, registered via pci 653 */ 654 static pci_ers_result_t 655 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 656 { 657 struct qib_devdata *dd = pci_get_drvdata(pdev); 658 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 659 660 switch (state) { 661 case pci_channel_io_normal: 662 qib_devinfo(pdev, "State Normal, ignoring\n"); 663 break; 664 665 case pci_channel_io_frozen: 666 qib_devinfo(pdev, "State Frozen, requesting reset\n"); 667 pci_disable_device(pdev); 668 ret = PCI_ERS_RESULT_NEED_RESET; 669 break; 670 671 case pci_channel_io_perm_failure: 672 qib_devinfo(pdev, "State Permanent Failure, disabling\n"); 673 if (dd) { 674 /* no more register accesses! */ 675 dd->flags &= ~QIB_PRESENT; 676 qib_disable_after_error(dd); 677 } 678 /* else early, or other problem */ 679 ret = PCI_ERS_RESULT_DISCONNECT; 680 break; 681 682 default: /* shouldn't happen */ 683 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n", 684 state); 685 break; 686 } 687 return ret; 688 } 689 690 static pci_ers_result_t 691 qib_pci_mmio_enabled(struct pci_dev *pdev) 692 { 693 u64 words = 0U; 694 struct qib_devdata *dd = pci_get_drvdata(pdev); 695 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 696 697 if (dd && dd->pport) { 698 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); 699 if (words == ~0ULL) 700 ret = PCI_ERS_RESULT_NEED_RESET; 701 } 702 qib_devinfo(pdev, "QIB mmio_enabled function called, " 703 "read wordscntr %Lx, returning %d\n", words, ret); 704 return ret; 705 } 706 707 static pci_ers_result_t 708 qib_pci_slot_reset(struct pci_dev *pdev) 709 { 710 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 711 return PCI_ERS_RESULT_CAN_RECOVER; 712 } 713 714 static pci_ers_result_t 715 qib_pci_link_reset(struct pci_dev *pdev) 716 { 717 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 718 return PCI_ERS_RESULT_CAN_RECOVER; 719 } 720 721 static void 722 qib_pci_resume(struct pci_dev *pdev) 723 { 724 struct qib_devdata *dd = pci_get_drvdata(pdev); 725 qib_devinfo(pdev, "QIB resume function called\n"); 726 pci_cleanup_aer_uncorrect_error_status(pdev); 727 /* 728 * Running jobs will fail, since it's asynchronous 729 * unlike sysfs-requested reset. Better than 730 * doing nothing. 731 */ 732 qib_init(dd, 1); /* same as re-init after reset */ 733 } 734 735 struct pci_error_handlers qib_pci_err_handler = { 736 .error_detected = qib_pci_error_detected, 737 .mmio_enabled = qib_pci_mmio_enabled, 738 .link_reset = qib_pci_link_reset, 739 .slot_reset = qib_pci_slot_reset, 740 .resume = qib_pci_resume, 741 }; 742