1 /* 2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/pci.h> 34 #include <linux/io.h> 35 #include <linux/delay.h> 36 #include <linux/vmalloc.h> 37 #include <linux/aer.h> 38 #include <linux/module.h> 39 40 #include "qib.h" 41 42 /* 43 * This file contains PCIe utility routines that are common to the 44 * various QLogic InfiniPath adapters 45 */ 46 47 /* 48 * Code to adjust PCIe capabilities. 49 * To minimize the change footprint, we call it 50 * from qib_pcie_params, which every chip-specific 51 * file calls, even though this violates some 52 * expectations of harmlessness. 53 */ 54 static void qib_tune_pcie_caps(struct qib_devdata *); 55 static void qib_tune_pcie_coalesce(struct qib_devdata *); 56 57 /* 58 * Do all the common PCIe setup and initialization. 59 * devdata is not yet allocated, and is not allocated until after this 60 * routine returns success. Therefore qib_dev_err() can't be used for error 61 * printing. 62 */ 63 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent) 64 { 65 int ret; 66 67 ret = pci_enable_device(pdev); 68 if (ret) { 69 /* 70 * This can happen (in theory) iff: 71 * We did a chip reset, and then failed to reprogram the 72 * BAR, or the chip reset due to an internal error. We then 73 * unloaded the driver and reloaded it. 74 * 75 * Both reset cases set the BAR back to initial state. For 76 * the latter case, the AER sticky error bit at offset 0x718 77 * should be set, but the Linux kernel doesn't yet know 78 * about that, it appears. If the original BAR was retained 79 * in the kernel data structures, this may be OK. 80 */ 81 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", 82 -ret); 83 goto done; 84 } 85 86 ret = pci_request_regions(pdev, QIB_DRV_NAME); 87 if (ret) { 88 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); 89 goto bail; 90 } 91 92 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 93 if (ret) { 94 /* 95 * If the 64 bit setup fails, try 32 bit. Some systems 96 * do not setup 64 bit maps on systems with 2GB or less 97 * memory installed. 98 */ 99 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 100 if (ret) { 101 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret); 102 goto bail; 103 } 104 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 105 } else 106 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 107 if (ret) { 108 qib_early_err(&pdev->dev, 109 "Unable to set DMA consistent mask: %d\n", ret); 110 goto bail; 111 } 112 113 pci_set_master(pdev); 114 ret = pci_enable_pcie_error_reporting(pdev); 115 if (ret) { 116 qib_early_err(&pdev->dev, 117 "Unable to enable pcie error reporting: %d\n", 118 ret); 119 ret = 0; 120 } 121 goto done; 122 123 bail: 124 pci_disable_device(pdev); 125 pci_release_regions(pdev); 126 done: 127 return ret; 128 } 129 130 /* 131 * Do remaining PCIe setup, once dd is allocated, and save away 132 * fields required to re-initialize after a chip reset, or for 133 * various other purposes 134 */ 135 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, 136 const struct pci_device_id *ent) 137 { 138 unsigned long len; 139 resource_size_t addr; 140 141 dd->pcidev = pdev; 142 pci_set_drvdata(pdev, dd); 143 144 addr = pci_resource_start(pdev, 0); 145 len = pci_resource_len(pdev, 0); 146 147 dd->kregbase = ioremap_nocache(addr, len); 148 if (!dd->kregbase) 149 return -ENOMEM; 150 151 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); 152 dd->physaddr = addr; /* used for io_remap, etc. */ 153 154 /* 155 * Save BARs to rewrite after device reset. Save all 64 bits of 156 * BAR, just in case. 157 */ 158 dd->pcibar0 = addr; 159 dd->pcibar1 = addr >> 32; 160 dd->deviceid = ent->device; /* save for later use */ 161 dd->vendorid = ent->vendor; 162 163 return 0; 164 } 165 166 /* 167 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior 168 * to releasing the dd memory. 169 * void because none of the core pcie cleanup returns are void 170 */ 171 void qib_pcie_ddcleanup(struct qib_devdata *dd) 172 { 173 u64 __iomem *base = (void __iomem *) dd->kregbase; 174 175 dd->kregbase = NULL; 176 iounmap(base); 177 if (dd->piobase) 178 iounmap(dd->piobase); 179 if (dd->userbase) 180 iounmap(dd->userbase); 181 if (dd->piovl15base) 182 iounmap(dd->piovl15base); 183 184 pci_disable_device(dd->pcidev); 185 pci_release_regions(dd->pcidev); 186 187 pci_set_drvdata(dd->pcidev, NULL); 188 } 189 190 static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt, 191 struct qib_msix_entry *qib_msix_entry) 192 { 193 int ret; 194 int nvec = *msixcnt; 195 struct msix_entry *msix_entry; 196 int i; 197 198 ret = pci_msix_vec_count(dd->pcidev); 199 if (ret < 0) 200 goto do_intx; 201 202 nvec = min(nvec, ret); 203 204 /* We can't pass qib_msix_entry array to qib_msix_setup 205 * so use a dummy msix_entry array and copy the allocated 206 * irq back to the qib_msix_entry array. */ 207 msix_entry = kcalloc(nvec, sizeof(*msix_entry), GFP_KERNEL); 208 if (!msix_entry) 209 goto do_intx; 210 211 for (i = 0; i < nvec; i++) 212 msix_entry[i] = qib_msix_entry[i].msix; 213 214 ret = pci_enable_msix_range(dd->pcidev, msix_entry, 1, nvec); 215 if (ret < 0) 216 goto free_msix_entry; 217 else 218 nvec = ret; 219 220 for (i = 0; i < nvec; i++) 221 qib_msix_entry[i].msix = msix_entry[i]; 222 223 kfree(msix_entry); 224 *msixcnt = nvec; 225 return; 226 227 free_msix_entry: 228 kfree(msix_entry); 229 230 do_intx: 231 qib_dev_err( 232 dd, 233 "pci_enable_msix_range %d vectors failed: %d, falling back to INTx\n", 234 nvec, ret); 235 *msixcnt = 0; 236 qib_enable_intx(dd->pcidev); 237 } 238 239 /** 240 * We save the msi lo and hi values, so we can restore them after 241 * chip reset (the kernel PCI infrastructure doesn't yet handle that 242 * correctly. 243 */ 244 static int qib_msi_setup(struct qib_devdata *dd, int pos) 245 { 246 struct pci_dev *pdev = dd->pcidev; 247 u16 control; 248 int ret; 249 250 ret = pci_enable_msi(pdev); 251 if (ret) 252 qib_dev_err(dd, 253 "pci_enable_msi failed: %d, interrupts may not work\n", 254 ret); 255 /* continue even if it fails, we may still be OK... */ 256 257 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, 258 &dd->msi_lo); 259 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, 260 &dd->msi_hi); 261 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); 262 /* now save the data (vector) info */ 263 pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT) 264 ? 12 : 8), 265 &dd->msi_data); 266 return ret; 267 } 268 269 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent, 270 struct qib_msix_entry *entry) 271 { 272 u16 linkstat, speed; 273 int pos = 0, ret = 1; 274 275 if (!pci_is_pcie(dd->pcidev)) { 276 qib_dev_err(dd, "Can't find PCI Express capability!\n"); 277 /* set up something... */ 278 dd->lbus_width = 1; 279 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 280 goto bail; 281 } 282 283 pos = dd->pcidev->msix_cap; 284 if (nent && *nent && pos) { 285 qib_msix_setup(dd, pos, nent, entry); 286 ret = 0; /* did it, either MSIx or INTx */ 287 } else { 288 pos = dd->pcidev->msi_cap; 289 if (pos) 290 ret = qib_msi_setup(dd, pos); 291 else 292 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n"); 293 } 294 if (!pos) 295 qib_enable_intx(dd->pcidev); 296 297 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 298 /* 299 * speed is bits 0-3, linkwidth is bits 4-8 300 * no defines for them in headers 301 */ 302 speed = linkstat & 0xf; 303 linkstat >>= 4; 304 linkstat &= 0x1f; 305 dd->lbus_width = linkstat; 306 307 switch (speed) { 308 case 1: 309 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ 310 break; 311 case 2: 312 dd->lbus_speed = 5000; /* Gen1, 5GHz */ 313 break; 314 default: /* not defined, assume gen1 */ 315 dd->lbus_speed = 2500; 316 break; 317 } 318 319 /* 320 * Check against expected pcie width and complain if "wrong" 321 * on first initialization, not afterwards (i.e., reset). 322 */ 323 if (minw && linkstat < minw) 324 qib_dev_err(dd, 325 "PCIe width %u (x%u HCA), performance reduced\n", 326 linkstat, minw); 327 328 qib_tune_pcie_caps(dd); 329 330 qib_tune_pcie_coalesce(dd); 331 332 bail: 333 /* fill in string, even on errors */ 334 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 335 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); 336 return ret; 337 } 338 339 /* 340 * Setup pcie interrupt stuff again after a reset. I'd like to just call 341 * pci_enable_msi() again for msi, but when I do that, 342 * the MSI enable bit doesn't get set in the command word, and 343 * we switch to to a different interrupt vector, which is confusing, 344 * so I instead just do it all inline. Perhaps somehow can tie this 345 * into the PCIe hotplug support at some point 346 */ 347 int qib_reinit_intr(struct qib_devdata *dd) 348 { 349 int pos; 350 u16 control; 351 int ret = 0; 352 353 /* If we aren't using MSI, don't restore it */ 354 if (!dd->msi_lo) 355 goto bail; 356 357 pos = dd->pcidev->msi_cap; 358 if (!pos) { 359 qib_dev_err(dd, 360 "Can't find MSI capability, can't restore MSI settings\n"); 361 ret = 0; 362 /* nothing special for MSIx, just MSI */ 363 goto bail; 364 } 365 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, 366 dd->msi_lo); 367 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, 368 dd->msi_hi); 369 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); 370 if (!(control & PCI_MSI_FLAGS_ENABLE)) { 371 control |= PCI_MSI_FLAGS_ENABLE; 372 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, 373 control); 374 } 375 /* now rewrite the data (vector) info */ 376 pci_write_config_word(dd->pcidev, pos + 377 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), 378 dd->msi_data); 379 ret = 1; 380 bail: 381 if (!ret && (dd->flags & QIB_HAS_INTX)) { 382 qib_enable_intx(dd->pcidev); 383 ret = 1; 384 } 385 386 /* and now set the pci master bit again */ 387 pci_set_master(dd->pcidev); 388 389 return ret; 390 } 391 392 /* 393 * Disable msi interrupt if enabled, and clear msi_lo. 394 * This is used primarily for the fallback to INTx, but 395 * is also used in reinit after reset, and during cleanup. 396 */ 397 void qib_nomsi(struct qib_devdata *dd) 398 { 399 dd->msi_lo = 0; 400 pci_disable_msi(dd->pcidev); 401 } 402 403 /* 404 * Same as qib_nosmi, but for MSIx. 405 */ 406 void qib_nomsix(struct qib_devdata *dd) 407 { 408 pci_disable_msix(dd->pcidev); 409 } 410 411 /* 412 * Similar to pci_intx(pdev, 1), except that we make sure 413 * msi(x) is off. 414 */ 415 void qib_enable_intx(struct pci_dev *pdev) 416 { 417 u16 cw, new; 418 int pos; 419 420 /* first, turn on INTx */ 421 pci_read_config_word(pdev, PCI_COMMAND, &cw); 422 new = cw & ~PCI_COMMAND_INTX_DISABLE; 423 if (new != cw) 424 pci_write_config_word(pdev, PCI_COMMAND, new); 425 426 pos = pdev->msi_cap; 427 if (pos) { 428 /* then turn off MSI */ 429 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw); 430 new = cw & ~PCI_MSI_FLAGS_ENABLE; 431 if (new != cw) 432 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new); 433 } 434 pos = pdev->msix_cap; 435 if (pos) { 436 /* then turn off MSIx */ 437 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw); 438 new = cw & ~PCI_MSIX_FLAGS_ENABLE; 439 if (new != cw) 440 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new); 441 } 442 } 443 444 /* 445 * These two routines are helper routines for the device reset code 446 * to move all the pcie code out of the chip-specific driver code. 447 */ 448 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) 449 { 450 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); 451 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 452 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 453 } 454 455 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) 456 { 457 int r; 458 459 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 460 dd->pcibar0); 461 if (r) 462 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r); 463 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 464 dd->pcibar1); 465 if (r) 466 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r); 467 /* now re-enable memory access, and restore cosmetic settings */ 468 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); 469 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); 470 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); 471 r = pci_enable_device(dd->pcidev); 472 if (r) 473 qib_dev_err(dd, 474 "pci_enable_device failed after reset: %d\n", r); 475 } 476 477 478 static int qib_pcie_coalesce; 479 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO); 480 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets"); 481 482 /* 483 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300 484 * chipsets. This is known to be unsafe for some revisions of some 485 * of these chipsets, with some BIOS settings, and enabling it on those 486 * systems may result in the system crashing, and/or data corruption. 487 */ 488 static void qib_tune_pcie_coalesce(struct qib_devdata *dd) 489 { 490 int r; 491 struct pci_dev *parent; 492 u16 devid; 493 u32 mask, bits, val; 494 495 if (!qib_pcie_coalesce) 496 return; 497 498 /* Find out supported and configured values for parent (root) */ 499 parent = dd->pcidev->bus->self; 500 if (parent->bus->parent) { 501 qib_devinfo(dd->pcidev, "Parent not root\n"); 502 return; 503 } 504 if (!pci_is_pcie(parent)) 505 return; 506 if (parent->vendor != 0x8086) 507 return; 508 509 /* 510 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1 511 * - bit 11: COALESCE_FORCE: need to set to 0 512 * - bit 10: COALESCE_EN: need to set to 1 513 * (but limitations on some on some chipsets) 514 * 515 * On the Intel 5000, 5100, and 7300 chipsets, there is 516 * also: - bit 25:24: COALESCE_MODE, need to set to 0 517 */ 518 devid = parent->device; 519 if (devid >= 0x25e2 && devid <= 0x25fa) { 520 /* 5000 P/V/X/Z */ 521 if (parent->revision <= 0xb2) 522 bits = 1U << 10; 523 else 524 bits = 7U << 10; 525 mask = (3U << 24) | (7U << 10); 526 } else if (devid >= 0x65e2 && devid <= 0x65fa) { 527 /* 5100 */ 528 bits = 1U << 10; 529 mask = (3U << 24) | (7U << 10); 530 } else if (devid >= 0x4021 && devid <= 0x402e) { 531 /* 5400 */ 532 bits = 7U << 10; 533 mask = 7U << 10; 534 } else if (devid >= 0x3604 && devid <= 0x360a) { 535 /* 7300 */ 536 bits = 7U << 10; 537 mask = (3U << 24) | (7U << 10); 538 } else { 539 /* not one of the chipsets that we know about */ 540 return; 541 } 542 pci_read_config_dword(parent, 0x48, &val); 543 val &= ~mask; 544 val |= bits; 545 r = pci_write_config_dword(parent, 0x48, val); 546 } 547 548 /* 549 * BIOS may not set PCIe bus-utilization parameters for best performance. 550 * Check and optionally adjust them to maximize our throughput. 551 */ 552 static int qib_pcie_caps; 553 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO); 554 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); 555 556 static void qib_tune_pcie_caps(struct qib_devdata *dd) 557 { 558 struct pci_dev *parent; 559 u16 rc_mpss, rc_mps, ep_mpss, ep_mps; 560 u16 rc_mrrs, ep_mrrs, max_mrrs; 561 562 /* Find out supported and configured values for parent (root) */ 563 parent = dd->pcidev->bus->self; 564 if (!pci_is_root_bus(parent->bus)) { 565 qib_devinfo(dd->pcidev, "Parent not root\n"); 566 return; 567 } 568 569 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) 570 return; 571 572 rc_mpss = parent->pcie_mpss; 573 rc_mps = ffs(pcie_get_mps(parent)) - 8; 574 /* Find out supported and configured values for endpoint (us) */ 575 ep_mpss = dd->pcidev->pcie_mpss; 576 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; 577 578 /* Find max payload supported by root, endpoint */ 579 if (rc_mpss > ep_mpss) 580 rc_mpss = ep_mpss; 581 582 /* If Supported greater than limit in module param, limit it */ 583 if (rc_mpss > (qib_pcie_caps & 7)) 584 rc_mpss = qib_pcie_caps & 7; 585 /* If less than (allowed, supported), bump root payload */ 586 if (rc_mpss > rc_mps) { 587 rc_mps = rc_mpss; 588 pcie_set_mps(parent, 128 << rc_mps); 589 } 590 /* If less than (allowed, supported), bump endpoint payload */ 591 if (rc_mpss > ep_mps) { 592 ep_mps = rc_mpss; 593 pcie_set_mps(dd->pcidev, 128 << ep_mps); 594 } 595 596 /* 597 * Now the Read Request size. 598 * No field for max supported, but PCIe spec limits it to 4096, 599 * which is code '5' (log2(4096) - 7) 600 */ 601 max_mrrs = 5; 602 if (max_mrrs > ((qib_pcie_caps >> 4) & 7)) 603 max_mrrs = (qib_pcie_caps >> 4) & 7; 604 605 max_mrrs = 128 << max_mrrs; 606 rc_mrrs = pcie_get_readrq(parent); 607 ep_mrrs = pcie_get_readrq(dd->pcidev); 608 609 if (max_mrrs > rc_mrrs) { 610 rc_mrrs = max_mrrs; 611 pcie_set_readrq(parent, rc_mrrs); 612 } 613 if (max_mrrs > ep_mrrs) { 614 ep_mrrs = max_mrrs; 615 pcie_set_readrq(dd->pcidev, ep_mrrs); 616 } 617 } 618 /* End of PCIe capability tuning */ 619 620 /* 621 * From here through qib_pci_err_handler definition is invoked via 622 * PCI error infrastructure, registered via pci 623 */ 624 static pci_ers_result_t 625 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 626 { 627 struct qib_devdata *dd = pci_get_drvdata(pdev); 628 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 629 630 switch (state) { 631 case pci_channel_io_normal: 632 qib_devinfo(pdev, "State Normal, ignoring\n"); 633 break; 634 635 case pci_channel_io_frozen: 636 qib_devinfo(pdev, "State Frozen, requesting reset\n"); 637 pci_disable_device(pdev); 638 ret = PCI_ERS_RESULT_NEED_RESET; 639 break; 640 641 case pci_channel_io_perm_failure: 642 qib_devinfo(pdev, "State Permanent Failure, disabling\n"); 643 if (dd) { 644 /* no more register accesses! */ 645 dd->flags &= ~QIB_PRESENT; 646 qib_disable_after_error(dd); 647 } 648 /* else early, or other problem */ 649 ret = PCI_ERS_RESULT_DISCONNECT; 650 break; 651 652 default: /* shouldn't happen */ 653 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n", 654 state); 655 break; 656 } 657 return ret; 658 } 659 660 static pci_ers_result_t 661 qib_pci_mmio_enabled(struct pci_dev *pdev) 662 { 663 u64 words = 0U; 664 struct qib_devdata *dd = pci_get_drvdata(pdev); 665 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; 666 667 if (dd && dd->pport) { 668 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); 669 if (words == ~0ULL) 670 ret = PCI_ERS_RESULT_NEED_RESET; 671 } 672 qib_devinfo(pdev, 673 "QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n", 674 words, ret); 675 return ret; 676 } 677 678 static pci_ers_result_t 679 qib_pci_slot_reset(struct pci_dev *pdev) 680 { 681 qib_devinfo(pdev, "QIB slot_reset function called, ignored\n"); 682 return PCI_ERS_RESULT_CAN_RECOVER; 683 } 684 685 static pci_ers_result_t 686 qib_pci_link_reset(struct pci_dev *pdev) 687 { 688 qib_devinfo(pdev, "QIB link_reset function called, ignored\n"); 689 return PCI_ERS_RESULT_CAN_RECOVER; 690 } 691 692 static void 693 qib_pci_resume(struct pci_dev *pdev) 694 { 695 struct qib_devdata *dd = pci_get_drvdata(pdev); 696 697 qib_devinfo(pdev, "QIB resume function called\n"); 698 pci_cleanup_aer_uncorrect_error_status(pdev); 699 /* 700 * Running jobs will fail, since it's asynchronous 701 * unlike sysfs-requested reset. Better than 702 * doing nothing. 703 */ 704 qib_init(dd, 1); /* same as re-init after reset */ 705 } 706 707 const struct pci_error_handlers qib_pci_err_handler = { 708 .error_detected = qib_pci_error_detected, 709 .mmio_enabled = qib_pci_mmio_enabled, 710 .link_reset = qib_pci_link_reset, 711 .slot_reset = qib_pci_slot_reset, 712 .resume = qib_pci_resume, 713 }; 714