1 /* 2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 /* 34 * This file contains all of the code that is specific to the 35 * InfiniPath 7322 chip 36 */ 37 38 #include <linux/interrupt.h> 39 #include <linux/pci.h> 40 #include <linux/delay.h> 41 #include <linux/io.h> 42 #include <linux/jiffies.h> 43 #include <linux/module.h> 44 #include <rdma/ib_verbs.h> 45 #include <rdma/ib_smi.h> 46 47 #include "qib.h" 48 #include "qib_7322_regs.h" 49 #include "qib_qsfp.h" 50 51 #include "qib_mad.h" 52 53 static void qib_setup_7322_setextled(struct qib_pportdata *, u32); 54 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t); 55 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op); 56 static irqreturn_t qib_7322intr(int irq, void *data); 57 static irqreturn_t qib_7322bufavail(int irq, void *data); 58 static irqreturn_t sdma_intr(int irq, void *data); 59 static irqreturn_t sdma_idle_intr(int irq, void *data); 60 static irqreturn_t sdma_progress_intr(int irq, void *data); 61 static irqreturn_t sdma_cleanup_intr(int irq, void *data); 62 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32, 63 struct qib_ctxtdata *rcd); 64 static u8 qib_7322_phys_portstate(u64); 65 static u32 qib_7322_iblink_state(u64); 66 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, 67 u16 linitcmd); 68 static void force_h1(struct qib_pportdata *); 69 static void adj_tx_serdes(struct qib_pportdata *); 70 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8); 71 static void qib_7322_mini_pcs_reset(struct qib_pportdata *); 72 73 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); 74 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); 75 static void serdes_7322_los_enable(struct qib_pportdata *, int); 76 static int serdes_7322_init_old(struct qib_pportdata *); 77 static int serdes_7322_init_new(struct qib_pportdata *); 78 79 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb)) 80 81 /* LE2 serdes values for different cases */ 82 #define LE2_DEFAULT 5 83 #define LE2_5m 4 84 #define LE2_QME 0 85 86 /* Below is special-purpose, so only really works for the IB SerDes blocks. */ 87 #define IBSD(hw_pidx) (hw_pidx + 2) 88 89 /* these are variables for documentation and experimentation purposes */ 90 static const unsigned rcv_int_timeout = 375; 91 static const unsigned rcv_int_count = 16; 92 static const unsigned sdma_idle_cnt = 64; 93 94 /* Time to stop altering Rx Equalization parameters, after link up. */ 95 #define RXEQ_DISABLE_MSECS 2500 96 97 /* 98 * Number of VLs we are configured to use (to allow for more 99 * credits per vl, etc.) 100 */ 101 ushort qib_num_cfg_vls = 2; 102 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO); 103 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)"); 104 105 static ushort qib_chase = 1; 106 module_param_named(chase, qib_chase, ushort, S_IRUGO); 107 MODULE_PARM_DESC(chase, "Enable state chase handling"); 108 109 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */ 110 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO); 111 MODULE_PARM_DESC(long_attenuation, \ 112 "attenuation cutoff (dB) for long copper cable setup"); 113 114 static ushort qib_singleport; 115 module_param_named(singleport, qib_singleport, ushort, S_IRUGO); 116 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space"); 117 118 static ushort qib_krcvq01_no_msi; 119 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO); 120 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2"); 121 122 /* 123 * Receive header queue sizes 124 */ 125 static unsigned qib_rcvhdrcnt; 126 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO); 127 MODULE_PARM_DESC(rcvhdrcnt, "receive header count"); 128 129 static unsigned qib_rcvhdrsize; 130 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO); 131 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words"); 132 133 static unsigned qib_rcvhdrentsize; 134 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO); 135 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words"); 136 137 #define MAX_ATTEN_LEN 64 /* plenty for any real system */ 138 /* for read back, default index is ~5m copper cable */ 139 static char txselect_list[MAX_ATTEN_LEN] = "10"; 140 static struct kparam_string kp_txselect = { 141 .string = txselect_list, 142 .maxlen = MAX_ATTEN_LEN 143 }; 144 static int setup_txselect(const char *, struct kernel_param *); 145 module_param_call(txselect, setup_txselect, param_get_string, 146 &kp_txselect, S_IWUSR | S_IRUGO); 147 MODULE_PARM_DESC(txselect, \ 148 "Tx serdes indices (for no QSFP or invalid QSFP data)"); 149 150 #define BOARD_QME7342 5 151 #define BOARD_QMH7342 6 152 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ 153 BOARD_QMH7342) 154 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ 155 BOARD_QME7342) 156 157 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64)) 158 159 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64))) 160 161 #define MASK_ACROSS(lsb, msb) \ 162 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb)) 163 164 #define SYM_RMASK(regname, fldname) ((u64) \ 165 QIB_7322_##regname##_##fldname##_RMASK) 166 167 #define SYM_MASK(regname, fldname) ((u64) \ 168 QIB_7322_##regname##_##fldname##_RMASK << \ 169 QIB_7322_##regname##_##fldname##_LSB) 170 171 #define SYM_FIELD(value, regname, fldname) ((u64) \ 172 (((value) >> SYM_LSB(regname, fldname)) & \ 173 SYM_RMASK(regname, fldname))) 174 175 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */ 176 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \ 177 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits)) 178 179 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask) 180 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask) 181 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask) 182 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask) 183 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port) 184 /* Below because most, but not all, fields of IntMask have that full suffix */ 185 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port) 186 187 188 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB) 189 190 /* 191 * the size bits give us 2^N, in KB units. 0 marks as invalid, 192 * and 7 is reserved. We currently use only 2KB and 4KB 193 */ 194 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB 195 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */ 196 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */ 197 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */ 198 199 #define SendIBSLIDAssignMask \ 200 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 201 #define SendIBSLMCMask \ 202 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 203 204 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn) 205 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn) 206 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn) 207 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn) 208 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN) 209 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN) 210 211 #define _QIB_GPIO_SDA_NUM 1 212 #define _QIB_GPIO_SCL_NUM 0 213 #define QIB_EEPROM_WEN_NUM 14 214 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */ 215 216 /* HW counter clock is at 4nsec */ 217 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000 218 219 /* full speed IB port 1 only */ 220 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR) 221 #define PORT_SPD_CAP_SHIFT 3 222 223 /* full speed featuremask, both ports */ 224 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT)) 225 226 /* 227 * This file contains almost all the chip-specific register information and 228 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip. 229 */ 230 231 /* Use defines to tie machine-generated names to lower-case names */ 232 #define kr_contextcnt KREG_IDX(ContextCnt) 233 #define kr_control KREG_IDX(Control) 234 #define kr_counterregbase KREG_IDX(CntrRegBase) 235 #define kr_errclear KREG_IDX(ErrClear) 236 #define kr_errmask KREG_IDX(ErrMask) 237 #define kr_errstatus KREG_IDX(ErrStatus) 238 #define kr_extctrl KREG_IDX(EXTCtrl) 239 #define kr_extstatus KREG_IDX(EXTStatus) 240 #define kr_gpio_clear KREG_IDX(GPIOClear) 241 #define kr_gpio_mask KREG_IDX(GPIOMask) 242 #define kr_gpio_out KREG_IDX(GPIOOut) 243 #define kr_gpio_status KREG_IDX(GPIOStatus) 244 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl) 245 #define kr_debugportval KREG_IDX(DebugPortValueReg) 246 #define kr_fmask KREG_IDX(feature_mask) 247 #define kr_act_fmask KREG_IDX(active_feature_mask) 248 #define kr_hwerrclear KREG_IDX(HwErrClear) 249 #define kr_hwerrmask KREG_IDX(HwErrMask) 250 #define kr_hwerrstatus KREG_IDX(HwErrStatus) 251 #define kr_intclear KREG_IDX(IntClear) 252 #define kr_intmask KREG_IDX(IntMask) 253 #define kr_intredirect KREG_IDX(IntRedirect0) 254 #define kr_intstatus KREG_IDX(IntStatus) 255 #define kr_pagealign KREG_IDX(PageAlign) 256 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0) 257 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */ 258 #define kr_rcvegrbase KREG_IDX(RcvEgrBase) 259 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt) 260 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt) 261 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize) 262 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize) 263 #define kr_rcvtidbase KREG_IDX(RcvTIDBase) 264 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt) 265 #define kr_revision KREG_IDX(Revision) 266 #define kr_scratch KREG_IDX(Scratch) 267 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */ 268 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */ 269 #define kr_sendctrl KREG_IDX(SendCtrl) 270 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */ 271 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */ 272 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr) 273 #define kr_sendpiobufbase KREG_IDX(SendBufBase) 274 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt) 275 #define kr_sendpiosize KREG_IDX(SendBufSize) 276 #define kr_sendregbase KREG_IDX(SendRegBase) 277 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0) 278 #define kr_userregbase KREG_IDX(UserRegBase) 279 #define kr_intgranted KREG_IDX(Int_Granted) 280 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int) 281 #define kr_intblocked KREG_IDX(IntBlocked) 282 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG) 283 284 /* 285 * per-port kernel registers. Access only with qib_read_kreg_port() 286 * or qib_write_kreg_port() 287 */ 288 #define krp_errclear KREG_IBPORT_IDX(ErrClear) 289 #define krp_errmask KREG_IBPORT_IDX(ErrMask) 290 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus) 291 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0) 292 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit) 293 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID) 294 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig) 295 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA) 296 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB) 297 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC) 298 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA) 299 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB) 300 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus) 301 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0) 302 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl) 303 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey) 304 #define krp_psinterval KREG_IBPORT_IDX(PSInterval) 305 #define krp_psstart KREG_IBPORT_IDX(PSStart) 306 #define krp_psstat KREG_IBPORT_IDX(PSStat) 307 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP) 308 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl) 309 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt) 310 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA) 311 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0) 312 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15) 313 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl) 314 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl) 315 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase) 316 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0) 317 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1) 318 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2) 319 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0) 320 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1) 321 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2) 322 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt) 323 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead) 324 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr) 325 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt) 326 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen) 327 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld) 328 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt) 329 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus) 330 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail) 331 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom) 332 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign) 333 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask) 334 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX) 335 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD) 336 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE) 337 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl) 338 339 /* 340 * Per-context kernel registers. Access only with qib_read_kreg_ctxt() 341 * or qib_write_kreg_ctxt() 342 */ 343 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0) 344 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0) 345 346 /* 347 * TID Flow table, per context. Reduces 348 * number of hdrq updates to one per flow (or on errors). 349 * context 0 and 1 share same memory, but have distinct 350 * addresses. Since for now, we never use expected sends 351 * on kernel contexts, we don't worry about that (we initialize 352 * those entries for ctxt 0/1 on driver load twice, for example). 353 */ 354 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */ 355 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0)) 356 357 /* these are the error bits in the tid flows, and are W1C */ 358 #define TIDFLOW_ERRBITS ( \ 359 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \ 360 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \ 361 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \ 362 SYM_LSB(RcvTIDFlowTable0, SeqMismatch))) 363 364 /* Most (not all) Counters are per-IBport. 365 * Requires LBIntCnt is at offset 0 in the group 366 */ 367 #define CREG_IDX(regname) \ 368 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) 369 370 #define crp_badformat CREG_IDX(RxVersionErrCnt) 371 #define crp_err_rlen CREG_IDX(RxLenErrCnt) 372 #define crp_erricrc CREG_IDX(RxICRCErrCnt) 373 #define crp_errlink CREG_IDX(RxLinkMalformCnt) 374 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt) 375 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt) 376 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt) 377 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt) 378 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt) 379 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt) 380 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt) 381 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt) 382 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt) 383 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt) 384 #define crp_pktrcv CREG_IDX(RxDataPktCnt) 385 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt) 386 #define crp_pktsend CREG_IDX(TxDataPktCnt) 387 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt) 388 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount) 389 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount) 390 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount) 391 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount) 392 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount) 393 #define crp_rcvebp CREG_IDX(RxEBPCnt) 394 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt) 395 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt) 396 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt) 397 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt) 398 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt) 399 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt) 400 #define crp_rxvlerr CREG_IDX(RxVlErrCnt) 401 #define crp_sendstall CREG_IDX(TxFlowStallCnt) 402 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt) 403 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt) 404 #define crp_txlenerr CREG_IDX(TxLenErrCnt) 405 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt) 406 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt) 407 #define crp_txunderrun CREG_IDX(TxUnderrunCnt) 408 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt) 409 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt) 410 #define crp_wordrcv CREG_IDX(RxDwordCnt) 411 #define crp_wordsend CREG_IDX(TxDwordCnt) 412 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut) 413 414 /* these are the (few) counters that are not port-specific */ 415 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \ 416 QIB_7322_LBIntCnt_OFFS) / sizeof(u64)) 417 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt) 418 #define cr_lbint CREG_DEVIDX(LBIntCnt) 419 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt) 420 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt) 421 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt) 422 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt) 423 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt) 424 425 /* no chip register for # of IB ports supported, so define */ 426 #define NUM_IB_PORTS 2 427 428 /* 1 VL15 buffer per hardware IB port, no register for this, so define */ 429 #define NUM_VL15_BUFS NUM_IB_PORTS 430 431 /* 432 * context 0 and 1 are special, and there is no chip register that 433 * defines this value, so we have to define it here. 434 * These are all allocated to either 0 or 1 for single port 435 * hardware configuration, otherwise each gets half 436 */ 437 #define KCTXT0_EGRCNT 2048 438 439 /* values for vl and port fields in PBC, 7322-specific */ 440 #define PBC_PORT_SEL_LSB 26 441 #define PBC_PORT_SEL_RMASK 1 442 #define PBC_VL_NUM_LSB 27 443 #define PBC_VL_NUM_RMASK 7 444 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */ 445 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */ 446 447 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = { 448 [IB_RATE_2_5_GBPS] = 16, 449 [IB_RATE_5_GBPS] = 8, 450 [IB_RATE_10_GBPS] = 4, 451 [IB_RATE_20_GBPS] = 2, 452 [IB_RATE_30_GBPS] = 2, 453 [IB_RATE_40_GBPS] = 1 454 }; 455 456 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive) 457 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive) 458 459 /* link training states, from IBC */ 460 #define IB_7322_LT_STATE_DISABLED 0x00 461 #define IB_7322_LT_STATE_LINKUP 0x01 462 #define IB_7322_LT_STATE_POLLACTIVE 0x02 463 #define IB_7322_LT_STATE_POLLQUIET 0x03 464 #define IB_7322_LT_STATE_SLEEPDELAY 0x04 465 #define IB_7322_LT_STATE_SLEEPQUIET 0x05 466 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08 467 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09 468 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a 469 #define IB_7322_LT_STATE_CFGIDLE 0x0b 470 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c 471 #define IB_7322_LT_STATE_TXREVLANES 0x0d 472 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e 473 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f 474 #define IB_7322_LT_STATE_CFGENH 0x10 475 #define IB_7322_LT_STATE_CFGTEST 0x11 476 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12 477 #define IB_7322_LT_STATE_CFGWAITENH 0x13 478 479 /* link state machine states from IBC */ 480 #define IB_7322_L_STATE_DOWN 0x0 481 #define IB_7322_L_STATE_INIT 0x1 482 #define IB_7322_L_STATE_ARM 0x2 483 #define IB_7322_L_STATE_ACTIVE 0x3 484 #define IB_7322_L_STATE_ACT_DEFER 0x4 485 486 static const u8 qib_7322_physportstate[0x20] = { 487 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED, 488 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP, 489 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL, 490 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL, 491 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP, 492 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP, 493 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN, 494 [IB_7322_LT_STATE_CFGRCVFCFG] = 495 IB_PHYSPORTSTATE_CFG_TRAIN, 496 [IB_7322_LT_STATE_CFGWAITRMT] = 497 IB_PHYSPORTSTATE_CFG_TRAIN, 498 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE, 499 [IB_7322_LT_STATE_RECOVERRETRAIN] = 500 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 501 [IB_7322_LT_STATE_RECOVERWAITRMT] = 502 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 503 [IB_7322_LT_STATE_RECOVERIDLE] = 504 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 505 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH, 506 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN, 507 [IB_7322_LT_STATE_CFGWAITRMTTEST] = 508 IB_PHYSPORTSTATE_CFG_TRAIN, 509 [IB_7322_LT_STATE_CFGWAITENH] = 510 IB_PHYSPORTSTATE_CFG_WAIT_ENH, 511 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN, 512 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN, 513 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN, 514 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN 515 }; 516 517 struct qib_chip_specific { 518 u64 __iomem *cregbase; 519 u64 *cntrs; 520 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */ 521 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */ 522 u64 main_int_mask; /* clear bits which have dedicated handlers */ 523 u64 int_enable_mask; /* for per port interrupts in single port mode */ 524 u64 errormask; 525 u64 hwerrmask; 526 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */ 527 u64 gpio_mask; /* shadow the gpio mask register */ 528 u64 extctrl; /* shadow the gpio output enable, etc... */ 529 u32 ncntrs; 530 u32 nportcntrs; 531 u32 cntrnamelen; 532 u32 portcntrnamelen; 533 u32 numctxts; 534 u32 rcvegrcnt; 535 u32 updthresh; /* current AvailUpdThld */ 536 u32 updthresh_dflt; /* default AvailUpdThld */ 537 u32 r1; 538 int irq; 539 u32 num_msix_entries; 540 u32 sdmabufcnt; 541 u32 lastbuf_for_pio; 542 u32 stay_in_freeze; 543 u32 recovery_ports_initted; 544 struct msix_entry *msix_entries; 545 void **msix_arg; 546 unsigned long *sendchkenable; 547 unsigned long *sendgrhchk; 548 unsigned long *sendibchk; 549 u32 rcvavail_timeout[18]; 550 char emsgbuf[128]; /* for device error interrupt msg buffer */ 551 }; 552 553 /* Table of entries in "human readable" form Tx Emphasis. */ 554 struct txdds_ent { 555 u8 amp; 556 u8 pre; 557 u8 main; 558 u8 post; 559 }; 560 561 struct vendor_txdds_ent { 562 u8 oui[QSFP_VOUI_LEN]; 563 u8 *partnum; 564 struct txdds_ent sdr; 565 struct txdds_ent ddr; 566 struct txdds_ent qdr; 567 }; 568 569 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *); 570 571 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ 572 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */ 573 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */ 574 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ 575 576 #define H1_FORCE_VAL 8 577 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */ 578 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */ 579 580 /* The static and dynamic registers are paired, and the pairs indexed by spd */ 581 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \ 582 + ((spd) * 2)) 583 584 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */ 585 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */ 586 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */ 587 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */ 588 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */ 589 590 struct qib_chippport_specific { 591 u64 __iomem *kpregbase; 592 u64 __iomem *cpregbase; 593 u64 *portcntrs; 594 struct qib_pportdata *ppd; 595 wait_queue_head_t autoneg_wait; 596 struct delayed_work autoneg_work; 597 struct delayed_work ipg_work; 598 struct timer_list chase_timer; 599 /* 600 * these 5 fields are used to establish deltas for IB symbol 601 * errors and linkrecovery errors. They can be reported on 602 * some chips during link negotiation prior to INIT, and with 603 * DDR when faking DDR negotiations with non-IBTA switches. 604 * The chip counters are adjusted at driver unload if there is 605 * a non-zero delta. 606 */ 607 u64 ibdeltainprog; 608 u64 ibsymdelta; 609 u64 ibsymsnap; 610 u64 iblnkerrdelta; 611 u64 iblnkerrsnap; 612 u64 iblnkdownsnap; 613 u64 iblnkdowndelta; 614 u64 ibmalfdelta; 615 u64 ibmalfsnap; 616 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */ 617 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */ 618 u64 qdr_dfe_time; 619 u64 chase_end; 620 u32 autoneg_tries; 621 u32 recovery_init; 622 u32 qdr_dfe_on; 623 u32 qdr_reforce; 624 /* 625 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR. 626 * entry zero is unused, to simplify indexing 627 */ 628 u8 h1_val; 629 u8 no_eep; /* txselect table index to use if no qsfp info */ 630 u8 ipg_tries; 631 u8 ibmalfusesnap; 632 struct qib_qsfp_data qsfp_data; 633 char epmsgbuf[192]; /* for port error interrupt msg buffer */ 634 }; 635 636 static struct { 637 const char *name; 638 irq_handler_t handler; 639 int lsb; 640 int port; /* 0 if not port-specific, else port # */ 641 } irq_table[] = { 642 { QIB_DRV_NAME, qib_7322intr, -1, 0 }, 643 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail, 644 SYM_LSB(IntStatus, SendBufAvail), 0 }, 645 { QIB_DRV_NAME " (sdma 0)", sdma_intr, 646 SYM_LSB(IntStatus, SDmaInt_0), 1 }, 647 { QIB_DRV_NAME " (sdma 1)", sdma_intr, 648 SYM_LSB(IntStatus, SDmaInt_1), 2 }, 649 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr, 650 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 }, 651 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr, 652 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 }, 653 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr, 654 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 }, 655 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr, 656 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 }, 657 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr, 658 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 }, 659 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr, 660 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 }, 661 }; 662 663 /* ibcctrl bits */ 664 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 665 /* cycle through TS1/TS2 till OK */ 666 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2 667 /* wait for TS1, then go on */ 668 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3 669 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16 670 671 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */ 672 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */ 673 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */ 674 675 #define BLOB_7322_IBCHG 0x101 676 677 static inline void qib_write_kreg(const struct qib_devdata *dd, 678 const u32 regno, u64 value); 679 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32); 680 static void write_7322_initregs(struct qib_devdata *); 681 static void write_7322_init_portregs(struct qib_pportdata *); 682 static void setup_7322_link_recovery(struct qib_pportdata *, u32); 683 static void check_7322_rxe_status(struct qib_pportdata *); 684 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *); 685 686 /** 687 * qib_read_ureg32 - read 32-bit virtualized per-context register 688 * @dd: device 689 * @regno: register number 690 * @ctxt: context number 691 * 692 * Return the contents of a register that is virtualized to be per context. 693 * Returns -1 on errors (not distinguishable from valid contents at 694 * runtime; we may add a separate error variable at some point). 695 */ 696 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, 697 enum qib_ureg regno, int ctxt) 698 { 699 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 700 return 0; 701 return readl(regno + (u64 __iomem *)( 702 (dd->ureg_align * ctxt) + (dd->userbase ? 703 (char __iomem *)dd->userbase : 704 (char __iomem *)dd->kregbase + dd->uregbase))); 705 } 706 707 /** 708 * qib_read_ureg - read virtualized per-context register 709 * @dd: device 710 * @regno: register number 711 * @ctxt: context number 712 * 713 * Return the contents of a register that is virtualized to be per context. 714 * Returns -1 on errors (not distinguishable from valid contents at 715 * runtime; we may add a separate error variable at some point). 716 */ 717 static inline u64 qib_read_ureg(const struct qib_devdata *dd, 718 enum qib_ureg regno, int ctxt) 719 { 720 721 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 722 return 0; 723 return readq(regno + (u64 __iomem *)( 724 (dd->ureg_align * ctxt) + (dd->userbase ? 725 (char __iomem *)dd->userbase : 726 (char __iomem *)dd->kregbase + dd->uregbase))); 727 } 728 729 /** 730 * qib_write_ureg - write virtualized per-context register 731 * @dd: device 732 * @regno: register number 733 * @value: value 734 * @ctxt: context 735 * 736 * Write the contents of a register that is virtualized to be per context. 737 */ 738 static inline void qib_write_ureg(const struct qib_devdata *dd, 739 enum qib_ureg regno, u64 value, int ctxt) 740 { 741 u64 __iomem *ubase; 742 if (dd->userbase) 743 ubase = (u64 __iomem *) 744 ((char __iomem *) dd->userbase + 745 dd->ureg_align * ctxt); 746 else 747 ubase = (u64 __iomem *) 748 (dd->uregbase + 749 (char __iomem *) dd->kregbase + 750 dd->ureg_align * ctxt); 751 752 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 753 writeq(value, &ubase[regno]); 754 } 755 756 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, 757 const u32 regno) 758 { 759 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 760 return -1; 761 return readl((u32 __iomem *) &dd->kregbase[regno]); 762 } 763 764 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, 765 const u32 regno) 766 { 767 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 768 return -1; 769 return readq(&dd->kregbase[regno]); 770 } 771 772 static inline void qib_write_kreg(const struct qib_devdata *dd, 773 const u32 regno, u64 value) 774 { 775 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 776 writeq(value, &dd->kregbase[regno]); 777 } 778 779 /* 780 * not many sanity checks for the port-specific kernel register routines, 781 * since they are only used when it's known to be safe. 782 */ 783 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd, 784 const u16 regno) 785 { 786 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) 787 return 0ULL; 788 return readq(&ppd->cpspec->kpregbase[regno]); 789 } 790 791 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd, 792 const u16 regno, u64 value) 793 { 794 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && 795 (ppd->dd->flags & QIB_PRESENT)) 796 writeq(value, &ppd->cpspec->kpregbase[regno]); 797 } 798 799 /** 800 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register 801 * @dd: the qlogic_ib device 802 * @regno: the register number to write 803 * @ctxt: the context containing the register 804 * @value: the value to write 805 */ 806 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, 807 const u16 regno, unsigned ctxt, 808 u64 value) 809 { 810 qib_write_kreg(dd, regno + ctxt, value); 811 } 812 813 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) 814 { 815 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 816 return 0; 817 return readq(&dd->cspec->cregbase[regno]); 818 819 820 } 821 822 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) 823 { 824 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 825 return 0; 826 return readl(&dd->cspec->cregbase[regno]); 827 828 829 } 830 831 static inline void write_7322_creg_port(const struct qib_pportdata *ppd, 832 u16 regno, u64 value) 833 { 834 if (ppd->cpspec && ppd->cpspec->cpregbase && 835 (ppd->dd->flags & QIB_PRESENT)) 836 writeq(value, &ppd->cpspec->cpregbase[regno]); 837 } 838 839 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd, 840 u16 regno) 841 { 842 if (!ppd->cpspec || !ppd->cpspec->cpregbase || 843 !(ppd->dd->flags & QIB_PRESENT)) 844 return 0; 845 return readq(&ppd->cpspec->cpregbase[regno]); 846 } 847 848 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd, 849 u16 regno) 850 { 851 if (!ppd->cpspec || !ppd->cpspec->cpregbase || 852 !(ppd->dd->flags & QIB_PRESENT)) 853 return 0; 854 return readl(&ppd->cpspec->cpregbase[regno]); 855 } 856 857 /* bits in Control register */ 858 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset) 859 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn) 860 861 /* bits in general interrupt regs */ 862 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask) 863 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17) 864 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB) 865 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask) 866 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17) 867 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB) 868 #define QIB_I_C_ERROR INT_MASK(Err) 869 870 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1)) 871 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail) 872 #define QIB_I_GPIO INT_MASK(AssertGPIO) 873 #define QIB_I_P_SDMAINT(pidx) \ 874 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ 875 INT_MASK_P(SDmaProgress, pidx) | \ 876 INT_MASK_PM(SDmaCleanupDone, pidx)) 877 878 /* Interrupt bits that are "per port" */ 879 #define QIB_I_P_BITSEXTANT(pidx) \ 880 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \ 881 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \ 882 INT_MASK_P(SDmaProgress, pidx) | \ 883 INT_MASK_PM(SDmaCleanupDone, pidx)) 884 885 /* Interrupt bits that are common to a device */ 886 /* currently unused: QIB_I_SPIOSENT */ 887 #define QIB_I_C_BITSEXTANT \ 888 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \ 889 QIB_I_SPIOSENT | \ 890 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO) 891 892 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \ 893 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1)) 894 895 /* 896 * Error bits that are "per port". 897 */ 898 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged) 899 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr) 900 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr) 901 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr) 902 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr) 903 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr) 904 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr) 905 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr) 906 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr) 907 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr) 908 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr) 909 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr) 910 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr) 911 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr) 912 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr) 913 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr) 914 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr) 915 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr) 916 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr) 917 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr) 918 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr) 919 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr) 920 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr) 921 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr) 922 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr) 923 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr) 924 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr) 925 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr) 926 927 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr) 928 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr) 929 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr) 930 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr) 931 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr) 932 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr) 933 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr) 934 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr) 935 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr) 936 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr) 937 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr) 938 939 /* Error bits that are common to a device */ 940 #define QIB_E_RESET ERR_MASK(ResetNegated) 941 #define QIB_E_HARDWARE ERR_MASK(HardwareErr) 942 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr) 943 944 945 /* 946 * Per chip (rather than per-port) errors. Most either do 947 * nothing but trigger a print (because they self-recover, or 948 * always occur in tandem with other errors that handle the 949 * issue), or because they indicate errors with no recovery, 950 * but we want to know that they happened. 951 */ 952 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr) 953 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd) 954 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr) 955 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr) 956 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr) 957 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr) 958 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr) 959 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr) 960 961 /* SDMA chip errors (not per port) 962 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get 963 * the SDMAHALT error immediately, so we just print the dup error via the 964 * E_AUTO mechanism. This is true of most of the per-port fatal errors 965 * as well, but since this is port-independent, by definition, it's 966 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per 967 * packet send errors, and so are handled in the same manner as other 968 * per-packet errors. 969 */ 970 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err) 971 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr) 972 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr) 973 974 /* 975 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS 976 * it is used to print "common" packet errors. 977 */ 978 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\ 979 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\ 980 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\ 981 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ 982 QIB_E_P_REBP) 983 984 /* Error Bits that Packet-related (Receive, per-port) */ 985 #define QIB_E_P_RPKTERRS (\ 986 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \ 987 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \ 988 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\ 989 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \ 990 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \ 991 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP) 992 993 /* 994 * Error bits that are Send-related (per port) 995 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling). 996 * All of these potentially need to have a buffer disarmed 997 */ 998 #define QIB_E_P_SPKTERRS (\ 999 QIB_E_P_SUNEXP_PKTNUM |\ 1000 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ 1001 QIB_E_P_SMAXPKTLEN |\ 1002 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \ 1003 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \ 1004 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL) 1005 1006 #define QIB_E_SPKTERRS ( \ 1007 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \ 1008 ERR_MASK_N(SendUnsupportedVLErr) | \ 1009 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT) 1010 1011 #define QIB_E_P_SDMAERRS ( \ 1012 QIB_E_P_SDMAHALT | \ 1013 QIB_E_P_SDMADESCADDRMISALIGN | \ 1014 QIB_E_P_SDMAUNEXPDATA | \ 1015 QIB_E_P_SDMAMISSINGDW | \ 1016 QIB_E_P_SDMADWEN | \ 1017 QIB_E_P_SDMARPYTAG | \ 1018 QIB_E_P_SDMA1STDESC | \ 1019 QIB_E_P_SDMABASE | \ 1020 QIB_E_P_SDMATAILOUTOFBOUND | \ 1021 QIB_E_P_SDMAOUTOFBOUND | \ 1022 QIB_E_P_SDMAGENMISMATCH) 1023 1024 /* 1025 * This sets some bits more than once, but makes it more obvious which 1026 * bits are not handled under other categories, and the repeat definition 1027 * is not a problem. 1028 */ 1029 #define QIB_E_P_BITSEXTANT ( \ 1030 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \ 1031 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \ 1032 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \ 1033 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \ 1034 ) 1035 1036 /* 1037 * These are errors that can occur when the link 1038 * changes state while a packet is being sent or received. This doesn't 1039 * cover things like EBP or VCRC that can be the result of a sending 1040 * having the link change state, so we receive a "known bad" packet. 1041 * All of these are "per port", so renamed: 1042 */ 1043 #define QIB_E_P_LINK_PKTERRS (\ 1044 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\ 1045 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\ 1046 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\ 1047 QIB_E_P_RUNEXPCHAR) 1048 1049 /* 1050 * This sets some bits more than once, but makes it more obvious which 1051 * bits are not handled under other categories (such as QIB_E_SPKTERRS), 1052 * and the repeat definition is not a problem. 1053 */ 1054 #define QIB_E_C_BITSEXTANT (\ 1055 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\ 1056 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\ 1057 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE) 1058 1059 /* Likewise Neuter E_SPKT_ERRS_IGNORE */ 1060 #define E_SPKT_ERRS_IGNORE 0 1061 1062 #define QIB_EXTS_MEMBIST_DISABLED \ 1063 SYM_MASK(EXTStatus, MemBISTDisabled) 1064 #define QIB_EXTS_MEMBIST_ENDTEST \ 1065 SYM_MASK(EXTStatus, MemBISTEndTest) 1066 1067 #define QIB_E_SPIOARMLAUNCH \ 1068 ERR_MASK(SendArmLaunchErr) 1069 1070 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd) 1071 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd) 1072 1073 /* 1074 * IBTA_1_2 is set when multiple speeds are enabled (normal), 1075 * and also if forced QDR (only QDR enabled). It's enabled for the 1076 * forced QDR case so that scrambling will be enabled by the TS3 1077 * exchange, when supported by both sides of the link. 1078 */ 1079 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE) 1080 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED) 1081 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR) 1082 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) 1083 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) 1084 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \ 1085 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)) 1086 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR) 1087 1088 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod) 1089 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod) 1090 1091 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS) 1092 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) 1093 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS)) 1094 1095 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP) 1096 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP) 1097 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \ 1098 SYM_MASK(IBCCtrlB_0, HRTBT_ENB)) 1099 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \ 1100 SYM_LSB(IBCCtrlB_0, HRTBT_ENB)) 1101 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB) 1102 1103 #define IBA7322_REDIRECT_VEC_PER_REG 12 1104 1105 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En) 1106 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En) 1107 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En) 1108 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En) 1109 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En) 1110 1111 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */ 1112 1113 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \ 1114 .msg = #fldname , .sz = sizeof(#fldname) } 1115 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \ 1116 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) } 1117 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = { 1118 HWE_AUTO_P(IBSerdesPClkNotDetect, 1), 1119 HWE_AUTO_P(IBSerdesPClkNotDetect, 0), 1120 HWE_AUTO(PCIESerdesPClkNotDetect), 1121 HWE_AUTO(PowerOnBISTFailed), 1122 HWE_AUTO(TempsenseTholdReached), 1123 HWE_AUTO(MemoryErr), 1124 HWE_AUTO(PCIeBusParityErr), 1125 HWE_AUTO(PcieCplTimeout), 1126 HWE_AUTO(PciePoisonedTLP), 1127 HWE_AUTO_P(SDmaMemReadErr, 1), 1128 HWE_AUTO_P(SDmaMemReadErr, 0), 1129 HWE_AUTO_P(IBCBusFromSPCParityErr, 1), 1130 HWE_AUTO_P(IBCBusToSPCParityErr, 1), 1131 HWE_AUTO_P(IBCBusFromSPCParityErr, 0), 1132 HWE_AUTO(statusValidNoEop), 1133 HWE_AUTO(LATriggered), 1134 { .mask = 0, .sz = 0 } 1135 }; 1136 1137 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \ 1138 .msg = #fldname, .sz = sizeof(#fldname) } 1139 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \ 1140 .msg = #fldname, .sz = sizeof(#fldname) } 1141 static const struct qib_hwerror_msgs qib_7322error_msgs[] = { 1142 E_AUTO(RcvEgrFullErr), 1143 E_AUTO(RcvHdrFullErr), 1144 E_AUTO(ResetNegated), 1145 E_AUTO(HardwareErr), 1146 E_AUTO(InvalidAddrErr), 1147 E_AUTO(SDmaVL15Err), 1148 E_AUTO(SBufVL15MisUseErr), 1149 E_AUTO(InvalidEEPCmd), 1150 E_AUTO(RcvContextShareErr), 1151 E_AUTO(SendVLMismatchErr), 1152 E_AUTO(SendArmLaunchErr), 1153 E_AUTO(SendSpecialTriggerErr), 1154 E_AUTO(SDmaWrongPortErr), 1155 E_AUTO(SDmaBufMaskDuplicateErr), 1156 { .mask = 0, .sz = 0 } 1157 }; 1158 1159 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = { 1160 E_P_AUTO(IBStatusChanged), 1161 E_P_AUTO(SHeadersErr), 1162 E_P_AUTO(VL15BufMisuseErr), 1163 /* 1164 * SDmaHaltErr is not really an error, make it clearer; 1165 */ 1166 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted", 1167 .sz = 11}, 1168 E_P_AUTO(SDmaDescAddrMisalignErr), 1169 E_P_AUTO(SDmaUnexpDataErr), 1170 E_P_AUTO(SDmaMissingDwErr), 1171 E_P_AUTO(SDmaDwEnErr), 1172 E_P_AUTO(SDmaRpyTagErr), 1173 E_P_AUTO(SDma1stDescErr), 1174 E_P_AUTO(SDmaBaseErr), 1175 E_P_AUTO(SDmaTailOutOfBoundErr), 1176 E_P_AUTO(SDmaOutOfBoundErr), 1177 E_P_AUTO(SDmaGenMismatchErr), 1178 E_P_AUTO(SendBufMisuseErr), 1179 E_P_AUTO(SendUnsupportedVLErr), 1180 E_P_AUTO(SendUnexpectedPktNumErr), 1181 E_P_AUTO(SendDroppedDataPktErr), 1182 E_P_AUTO(SendDroppedSmpPktErr), 1183 E_P_AUTO(SendPktLenErr), 1184 E_P_AUTO(SendUnderRunErr), 1185 E_P_AUTO(SendMaxPktLenErr), 1186 E_P_AUTO(SendMinPktLenErr), 1187 E_P_AUTO(RcvIBLostLinkErr), 1188 E_P_AUTO(RcvHdrErr), 1189 E_P_AUTO(RcvHdrLenErr), 1190 E_P_AUTO(RcvBadTidErr), 1191 E_P_AUTO(RcvBadVersionErr), 1192 E_P_AUTO(RcvIBFlowErr), 1193 E_P_AUTO(RcvEBPErr), 1194 E_P_AUTO(RcvUnsupportedVLErr), 1195 E_P_AUTO(RcvUnexpectedCharErr), 1196 E_P_AUTO(RcvShortPktLenErr), 1197 E_P_AUTO(RcvLongPktLenErr), 1198 E_P_AUTO(RcvMaxPktLenErr), 1199 E_P_AUTO(RcvMinPktLenErr), 1200 E_P_AUTO(RcvICRCErr), 1201 E_P_AUTO(RcvVCRCErr), 1202 E_P_AUTO(RcvFormatErr), 1203 { .mask = 0, .sz = 0 } 1204 }; 1205 1206 /* 1207 * Below generates "auto-message" for interrupts not specific to any port or 1208 * context 1209 */ 1210 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \ 1211 .msg = #fldname, .sz = sizeof(#fldname) } 1212 /* Below generates "auto-message" for interrupts specific to a port */ 1213 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\ 1214 SYM_LSB(IntMask, fldname##Mask##_0), \ 1215 SYM_LSB(IntMask, fldname##Mask##_1)), \ 1216 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } 1217 /* For some reason, the SerDesTrimDone bits are reversed */ 1218 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\ 1219 SYM_LSB(IntMask, fldname##Mask##_1), \ 1220 SYM_LSB(IntMask, fldname##Mask##_0)), \ 1221 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") } 1222 /* 1223 * Below generates "auto-message" for interrupts specific to a context, 1224 * with ctxt-number appended 1225 */ 1226 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\ 1227 SYM_LSB(IntMask, fldname##0IntMask), \ 1228 SYM_LSB(IntMask, fldname##17IntMask)), \ 1229 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") } 1230 1231 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = { 1232 INTR_AUTO_P(SDmaInt), 1233 INTR_AUTO_P(SDmaProgressInt), 1234 INTR_AUTO_P(SDmaIdleInt), 1235 INTR_AUTO_P(SDmaCleanupDone), 1236 INTR_AUTO_C(RcvUrg), 1237 INTR_AUTO_P(ErrInt), 1238 INTR_AUTO(ErrInt), /* non-port-specific errs */ 1239 INTR_AUTO(AssertGPIOInt), 1240 INTR_AUTO_P(SendDoneInt), 1241 INTR_AUTO(SendBufAvailInt), 1242 INTR_AUTO_C(RcvAvail), 1243 { .mask = 0, .sz = 0 } 1244 }; 1245 1246 #define TXSYMPTOM_AUTO_P(fldname) \ 1247 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \ 1248 .msg = #fldname, .sz = sizeof(#fldname) } 1249 static const struct qib_hwerror_msgs hdrchk_msgs[] = { 1250 TXSYMPTOM_AUTO_P(NonKeyPacket), 1251 TXSYMPTOM_AUTO_P(GRHFail), 1252 TXSYMPTOM_AUTO_P(PkeyFail), 1253 TXSYMPTOM_AUTO_P(QPFail), 1254 TXSYMPTOM_AUTO_P(SLIDFail), 1255 TXSYMPTOM_AUTO_P(RawIPV6), 1256 TXSYMPTOM_AUTO_P(PacketTooSmall), 1257 { .mask = 0, .sz = 0 } 1258 }; 1259 1260 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */ 1261 1262 /* 1263 * Called when we might have an error that is specific to a particular 1264 * PIO buffer, and may need to cancel that buffer, so it can be re-used, 1265 * because we don't need to force the update of pioavail 1266 */ 1267 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd) 1268 { 1269 struct qib_devdata *dd = ppd->dd; 1270 u32 i; 1271 int any; 1272 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 1273 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG; 1274 unsigned long sbuf[4]; 1275 1276 /* 1277 * It's possible that sendbuffererror could have bits set; might 1278 * have already done this as a result of hardware error handling. 1279 */ 1280 any = 0; 1281 for (i = 0; i < regcnt; ++i) { 1282 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i); 1283 if (sbuf[i]) { 1284 any = 1; 1285 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]); 1286 } 1287 } 1288 1289 if (any) 1290 qib_disarm_piobufs_set(dd, sbuf, piobcnt); 1291 } 1292 1293 /* No txe_recover yet, if ever */ 1294 1295 /* No decode__errors yet */ 1296 static void err_decode(char *msg, size_t len, u64 errs, 1297 const struct qib_hwerror_msgs *msp) 1298 { 1299 u64 these, lmask; 1300 int took, multi, n = 0; 1301 1302 while (errs && msp && msp->mask) { 1303 multi = (msp->mask & (msp->mask - 1)); 1304 while (errs & msp->mask) { 1305 these = (errs & msp->mask); 1306 lmask = (these & (these - 1)) ^ these; 1307 if (len) { 1308 if (n++) { 1309 /* separate the strings */ 1310 *msg++ = ','; 1311 len--; 1312 } 1313 BUG_ON(!msp->sz); 1314 /* msp->sz counts the nul */ 1315 took = min_t(size_t, msp->sz - (size_t)1, len); 1316 memcpy(msg, msp->msg, took); 1317 len -= took; 1318 msg += took; 1319 if (len) 1320 *msg = '\0'; 1321 } 1322 errs &= ~lmask; 1323 if (len && multi) { 1324 /* More than one bit this mask */ 1325 int idx = -1; 1326 1327 while (lmask & msp->mask) { 1328 ++idx; 1329 lmask >>= 1; 1330 } 1331 took = scnprintf(msg, len, "_%d", idx); 1332 len -= took; 1333 msg += took; 1334 } 1335 } 1336 ++msp; 1337 } 1338 /* If some bits are left, show in hex. */ 1339 if (len && errs) 1340 snprintf(msg, len, "%sMORE:%llX", n ? "," : "", 1341 (unsigned long long) errs); 1342 } 1343 1344 /* only called if r1 set */ 1345 static void flush_fifo(struct qib_pportdata *ppd) 1346 { 1347 struct qib_devdata *dd = ppd->dd; 1348 u32 __iomem *piobuf; 1349 u32 bufn; 1350 u32 *hdr; 1351 u64 pbc; 1352 const unsigned hdrwords = 7; 1353 static struct qib_ib_header ibhdr = { 1354 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH), 1355 .lrh[1] = IB_LID_PERMISSIVE, 1356 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC), 1357 .lrh[3] = IB_LID_PERMISSIVE, 1358 .u.oth.bth[0] = cpu_to_be32( 1359 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY), 1360 .u.oth.bth[1] = cpu_to_be32(0), 1361 .u.oth.bth[2] = cpu_to_be32(0), 1362 .u.oth.u.ud.deth[0] = cpu_to_be32(0), 1363 .u.oth.u.ud.deth[1] = cpu_to_be32(0), 1364 }; 1365 1366 /* 1367 * Send a dummy VL15 packet to flush the launch FIFO. 1368 * This will not actually be sent since the TxeBypassIbc bit is set. 1369 */ 1370 pbc = PBC_7322_VL15_SEND | 1371 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) | 1372 (hdrwords + SIZE_OF_CRC); 1373 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn); 1374 if (!piobuf) 1375 return; 1376 writeq(pbc, piobuf); 1377 hdr = (u32 *) &ibhdr; 1378 if (dd->flags & QIB_PIO_FLUSH_WC) { 1379 qib_flush_wc(); 1380 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1); 1381 qib_flush_wc(); 1382 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1); 1383 qib_flush_wc(); 1384 } else 1385 qib_pio_copy(piobuf + 2, hdr, hdrwords); 1386 qib_sendbuf_done(dd, bufn); 1387 } 1388 1389 /* 1390 * This is called with interrupts disabled and sdma_lock held. 1391 */ 1392 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) 1393 { 1394 struct qib_devdata *dd = ppd->dd; 1395 u64 set_sendctrl = 0; 1396 u64 clr_sendctrl = 0; 1397 1398 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE) 1399 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); 1400 else 1401 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable); 1402 1403 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE) 1404 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); 1405 else 1406 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable); 1407 1408 if (op & QIB_SDMA_SENDCTRL_OP_HALT) 1409 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); 1410 else 1411 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt); 1412 1413 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) 1414 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | 1415 SYM_MASK(SendCtrl_0, TxeAbortIbc) | 1416 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); 1417 else 1418 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) | 1419 SYM_MASK(SendCtrl_0, TxeAbortIbc) | 1420 SYM_MASK(SendCtrl_0, TxeDrainRmFifo); 1421 1422 spin_lock(&dd->sendctrl_lock); 1423 1424 /* If we are draining everything, block sends first */ 1425 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { 1426 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); 1427 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1428 qib_write_kreg(dd, kr_scratch, 0); 1429 } 1430 1431 ppd->p_sendctrl |= set_sendctrl; 1432 ppd->p_sendctrl &= ~clr_sendctrl; 1433 1434 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP) 1435 qib_write_kreg_port(ppd, krp_sendctrl, 1436 ppd->p_sendctrl | 1437 SYM_MASK(SendCtrl_0, SDmaCleanup)); 1438 else 1439 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1440 qib_write_kreg(dd, kr_scratch, 0); 1441 1442 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) { 1443 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); 1444 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 1445 qib_write_kreg(dd, kr_scratch, 0); 1446 } 1447 1448 spin_unlock(&dd->sendctrl_lock); 1449 1450 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) 1451 flush_fifo(ppd); 1452 } 1453 1454 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd) 1455 { 1456 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned); 1457 } 1458 1459 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd) 1460 { 1461 /* 1462 * Set SendDmaLenGen and clear and set 1463 * the MSB of the generation count to enable generation checking 1464 * and load the internal generation counter. 1465 */ 1466 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt); 1467 qib_write_kreg_port(ppd, krp_senddmalengen, 1468 ppd->sdma_descq_cnt | 1469 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB)); 1470 } 1471 1472 /* 1473 * Must be called with sdma_lock held, or before init finished. 1474 */ 1475 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail) 1476 { 1477 /* Commit writes to memory and advance the tail on the chip */ 1478 wmb(); 1479 ppd->sdma_descq_tail = tail; 1480 qib_write_kreg_port(ppd, krp_senddmatail, tail); 1481 } 1482 1483 /* 1484 * This is called with interrupts disabled and sdma_lock held. 1485 */ 1486 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd) 1487 { 1488 /* 1489 * Drain all FIFOs. 1490 * The hardware doesn't require this but we do it so that verbs 1491 * and user applications don't wait for link active to send stale 1492 * data. 1493 */ 1494 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH); 1495 1496 qib_sdma_7322_setlengen(ppd); 1497 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ 1498 ppd->sdma_head_dma[0] = 0; 1499 qib_7322_sdma_sendctrl(ppd, 1500 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP); 1501 } 1502 1503 #define DISABLES_SDMA ( \ 1504 QIB_E_P_SDMAHALT | \ 1505 QIB_E_P_SDMADESCADDRMISALIGN | \ 1506 QIB_E_P_SDMAMISSINGDW | \ 1507 QIB_E_P_SDMADWEN | \ 1508 QIB_E_P_SDMARPYTAG | \ 1509 QIB_E_P_SDMA1STDESC | \ 1510 QIB_E_P_SDMABASE | \ 1511 QIB_E_P_SDMATAILOUTOFBOUND | \ 1512 QIB_E_P_SDMAOUTOFBOUND | \ 1513 QIB_E_P_SDMAGENMISMATCH) 1514 1515 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs) 1516 { 1517 unsigned long flags; 1518 struct qib_devdata *dd = ppd->dd; 1519 1520 errs &= QIB_E_P_SDMAERRS; 1521 1522 if (errs & QIB_E_P_SDMAUNEXPDATA) 1523 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, 1524 ppd->port); 1525 1526 spin_lock_irqsave(&ppd->sdma_lock, flags); 1527 1528 switch (ppd->sdma_state.current_state) { 1529 case qib_sdma_state_s00_hw_down: 1530 break; 1531 1532 case qib_sdma_state_s10_hw_start_up_wait: 1533 if (errs & QIB_E_P_SDMAHALT) 1534 __qib_sdma_process_event(ppd, 1535 qib_sdma_event_e20_hw_started); 1536 break; 1537 1538 case qib_sdma_state_s20_idle: 1539 break; 1540 1541 case qib_sdma_state_s30_sw_clean_up_wait: 1542 break; 1543 1544 case qib_sdma_state_s40_hw_clean_up_wait: 1545 if (errs & QIB_E_P_SDMAHALT) 1546 __qib_sdma_process_event(ppd, 1547 qib_sdma_event_e50_hw_cleaned); 1548 break; 1549 1550 case qib_sdma_state_s50_hw_halt_wait: 1551 if (errs & QIB_E_P_SDMAHALT) 1552 __qib_sdma_process_event(ppd, 1553 qib_sdma_event_e60_hw_halted); 1554 break; 1555 1556 case qib_sdma_state_s99_running: 1557 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted); 1558 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted); 1559 break; 1560 } 1561 1562 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 1563 } 1564 1565 /* 1566 * handle per-device errors (not per-port errors) 1567 */ 1568 static noinline void handle_7322_errors(struct qib_devdata *dd) 1569 { 1570 char *msg; 1571 u64 iserr = 0; 1572 u64 errs; 1573 u64 mask; 1574 int log_idx; 1575 1576 qib_stats.sps_errints++; 1577 errs = qib_read_kreg64(dd, kr_errstatus); 1578 if (!errs) { 1579 qib_devinfo(dd->pcidev, "device error interrupt, " 1580 "but no error bits set!\n"); 1581 goto done; 1582 } 1583 1584 /* don't report errors that are masked */ 1585 errs &= dd->cspec->errormask; 1586 msg = dd->cspec->emsgbuf; 1587 1588 /* do these first, they are most important */ 1589 if (errs & QIB_E_HARDWARE) { 1590 *msg = '\0'; 1591 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf); 1592 } else 1593 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx) 1594 if (errs & dd->eep_st_masks[log_idx].errs_to_log) 1595 qib_inc_eeprom_err(dd, log_idx, 1); 1596 1597 if (errs & QIB_E_SPKTERRS) { 1598 qib_disarm_7322_senderrbufs(dd->pport); 1599 qib_stats.sps_txerrs++; 1600 } else if (errs & QIB_E_INVALIDADDR) 1601 qib_stats.sps_txerrs++; 1602 else if (errs & QIB_E_ARMLAUNCH) { 1603 qib_stats.sps_txerrs++; 1604 qib_disarm_7322_senderrbufs(dd->pport); 1605 } 1606 qib_write_kreg(dd, kr_errclear, errs); 1607 1608 /* 1609 * The ones we mask off are handled specially below 1610 * or above. Also mask SDMADISABLED by default as it 1611 * is too chatty. 1612 */ 1613 mask = QIB_E_HARDWARE; 1614 *msg = '\0'; 1615 1616 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask, 1617 qib_7322error_msgs); 1618 1619 /* 1620 * Getting reset is a tragedy for all ports. Mark the device 1621 * _and_ the ports as "offline" in way meaningful to each. 1622 */ 1623 if (errs & QIB_E_RESET) { 1624 int pidx; 1625 1626 qib_dev_err(dd, "Got reset, requires re-init " 1627 "(unload and reload driver)\n"); 1628 dd->flags &= ~QIB_INITTED; /* needs re-init */ 1629 /* mark as having had error */ 1630 *dd->devstatusp |= QIB_STATUS_HWERROR; 1631 for (pidx = 0; pidx < dd->num_pports; ++pidx) 1632 if (dd->pport[pidx].link_speed_supported) 1633 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; 1634 } 1635 1636 if (*msg && iserr) 1637 qib_dev_err(dd, "%s error\n", msg); 1638 1639 /* 1640 * If there were hdrq or egrfull errors, wake up any processes 1641 * waiting in poll. We used to try to check which contexts had 1642 * the overflow, but given the cost of that and the chip reads 1643 * to support it, it's better to just wake everybody up if we 1644 * get an overflow; waiters can poll again if it's not them. 1645 */ 1646 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) { 1647 qib_handle_urcv(dd, ~0U); 1648 if (errs & ERR_MASK(RcvEgrFullErr)) 1649 qib_stats.sps_buffull++; 1650 else 1651 qib_stats.sps_hdrfull++; 1652 } 1653 1654 done: 1655 return; 1656 } 1657 1658 static void qib_error_tasklet(unsigned long data) 1659 { 1660 struct qib_devdata *dd = (struct qib_devdata *)data; 1661 1662 handle_7322_errors(dd); 1663 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1664 } 1665 1666 static void reenable_chase(unsigned long opaque) 1667 { 1668 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque; 1669 1670 ppd->cpspec->chase_timer.expires = 0; 1671 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1672 QLOGIC_IB_IBCC_LINKINITCMD_POLL); 1673 } 1674 1675 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt) 1676 { 1677 ppd->cpspec->chase_end = 0; 1678 1679 if (!qib_chase) 1680 return; 1681 1682 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN, 1683 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1684 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME; 1685 add_timer(&ppd->cpspec->chase_timer); 1686 } 1687 1688 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst) 1689 { 1690 u8 ibclt; 1691 u64 tnow; 1692 1693 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState); 1694 1695 /* 1696 * Detect and handle the state chase issue, where we can 1697 * get stuck if we are unlucky on timing on both sides of 1698 * the link. If we are, we disable, set a timer, and 1699 * then re-enable. 1700 */ 1701 switch (ibclt) { 1702 case IB_7322_LT_STATE_CFGRCVFCFG: 1703 case IB_7322_LT_STATE_CFGWAITRMT: 1704 case IB_7322_LT_STATE_TXREVLANES: 1705 case IB_7322_LT_STATE_CFGENH: 1706 tnow = get_jiffies_64(); 1707 if (ppd->cpspec->chase_end && 1708 time_after64(tnow, ppd->cpspec->chase_end)) 1709 disable_chase(ppd, tnow, ibclt); 1710 else if (!ppd->cpspec->chase_end) 1711 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME; 1712 break; 1713 default: 1714 ppd->cpspec->chase_end = 0; 1715 break; 1716 } 1717 1718 if (((ibclt >= IB_7322_LT_STATE_CFGTEST && 1719 ibclt <= IB_7322_LT_STATE_CFGWAITENH) || 1720 ibclt == IB_7322_LT_STATE_LINKUP) && 1721 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { 1722 force_h1(ppd); 1723 ppd->cpspec->qdr_reforce = 1; 1724 if (!ppd->dd->cspec->r1) 1725 serdes_7322_los_enable(ppd, 0); 1726 } else if (ppd->cpspec->qdr_reforce && 1727 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && 1728 (ibclt == IB_7322_LT_STATE_CFGENH || 1729 ibclt == IB_7322_LT_STATE_CFGIDLE || 1730 ibclt == IB_7322_LT_STATE_LINKUP)) 1731 force_h1(ppd); 1732 1733 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && 1734 ppd->link_speed_enabled == QIB_IB_QDR && 1735 (ibclt == IB_7322_LT_STATE_CFGTEST || 1736 ibclt == IB_7322_LT_STATE_CFGENH || 1737 (ibclt >= IB_7322_LT_STATE_POLLACTIVE && 1738 ibclt <= IB_7322_LT_STATE_SLEEPQUIET))) 1739 adj_tx_serdes(ppd); 1740 1741 if (ibclt != IB_7322_LT_STATE_LINKUP) { 1742 u8 ltstate = qib_7322_phys_portstate(ibcst); 1743 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, 1744 LinkTrainingState); 1745 if (!ppd->dd->cspec->r1 && 1746 pibclt == IB_7322_LT_STATE_LINKUP && 1747 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1748 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1749 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1750 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1751 /* If the link went down (but no into recovery, 1752 * turn LOS back on */ 1753 serdes_7322_los_enable(ppd, 1); 1754 if (!ppd->cpspec->qdr_dfe_on && 1755 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) { 1756 ppd->cpspec->qdr_dfe_on = 1; 1757 ppd->cpspec->qdr_dfe_time = 0; 1758 /* On link down, reenable QDR adaptation */ 1759 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 1760 ppd->dd->cspec->r1 ? 1761 QDR_STATIC_ADAPT_DOWN_R1 : 1762 QDR_STATIC_ADAPT_DOWN); 1763 printk(KERN_INFO QIB_DRV_NAME 1764 " IB%u:%u re-enabled QDR adaptation " 1765 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt); 1766 } 1767 } 1768 } 1769 1770 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32); 1771 1772 /* 1773 * This is per-pport error handling. 1774 * will likely get it's own MSIx interrupt (one for each port, 1775 * although just a single handler). 1776 */ 1777 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd) 1778 { 1779 char *msg; 1780 u64 ignore_this_time = 0, iserr = 0, errs, fmask; 1781 struct qib_devdata *dd = ppd->dd; 1782 1783 /* do this as soon as possible */ 1784 fmask = qib_read_kreg64(dd, kr_act_fmask); 1785 if (!fmask) 1786 check_7322_rxe_status(ppd); 1787 1788 errs = qib_read_kreg_port(ppd, krp_errstatus); 1789 if (!errs) 1790 qib_devinfo(dd->pcidev, 1791 "Port%d error interrupt, but no error bits set!\n", 1792 ppd->port); 1793 if (!fmask) 1794 errs &= ~QIB_E_P_IBSTATUSCHANGED; 1795 if (!errs) 1796 goto done; 1797 1798 msg = ppd->cpspec->epmsgbuf; 1799 *msg = '\0'; 1800 1801 if (errs & ~QIB_E_P_BITSEXTANT) { 1802 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, 1803 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs); 1804 if (!*msg) 1805 snprintf(msg, sizeof ppd->cpspec->epmsgbuf, 1806 "no others"); 1807 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown" 1808 " errors 0x%016Lx set (and %s)\n", 1809 (errs & ~QIB_E_P_BITSEXTANT), msg); 1810 *msg = '\0'; 1811 } 1812 1813 if (errs & QIB_E_P_SHDR) { 1814 u64 symptom; 1815 1816 /* determine cause, then write to clear */ 1817 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom); 1818 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0); 1819 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom, 1820 hdrchk_msgs); 1821 *msg = '\0'; 1822 /* senderrbuf cleared in SPKTERRS below */ 1823 } 1824 1825 if (errs & QIB_E_P_SPKTERRS) { 1826 if ((errs & QIB_E_P_LINK_PKTERRS) && 1827 !(ppd->lflags & QIBL_LINKACTIVE)) { 1828 /* 1829 * This can happen when trying to bring the link 1830 * up, but the IB link changes state at the "wrong" 1831 * time. The IB logic then complains that the packet 1832 * isn't valid. We don't want to confuse people, so 1833 * we just don't print them, except at debug 1834 */ 1835 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, 1836 (errs & QIB_E_P_LINK_PKTERRS), 1837 qib_7322p_error_msgs); 1838 *msg = '\0'; 1839 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; 1840 } 1841 qib_disarm_7322_senderrbufs(ppd); 1842 } else if ((errs & QIB_E_P_LINK_PKTERRS) && 1843 !(ppd->lflags & QIBL_LINKACTIVE)) { 1844 /* 1845 * This can happen when SMA is trying to bring the link 1846 * up, but the IB link changes state at the "wrong" time. 1847 * The IB logic then complains that the packet isn't 1848 * valid. We don't want to confuse people, so we just 1849 * don't print them, except at debug 1850 */ 1851 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs, 1852 qib_7322p_error_msgs); 1853 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS; 1854 *msg = '\0'; 1855 } 1856 1857 qib_write_kreg_port(ppd, krp_errclear, errs); 1858 1859 errs &= ~ignore_this_time; 1860 if (!errs) 1861 goto done; 1862 1863 if (errs & QIB_E_P_RPKTERRS) 1864 qib_stats.sps_rcverrs++; 1865 if (errs & QIB_E_P_SPKTERRS) 1866 qib_stats.sps_txerrs++; 1867 1868 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS); 1869 1870 if (errs & QIB_E_P_SDMAERRS) 1871 sdma_7322_p_errors(ppd, errs); 1872 1873 if (errs & QIB_E_P_IBSTATUSCHANGED) { 1874 u64 ibcs; 1875 u8 ltstate; 1876 1877 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a); 1878 ltstate = qib_7322_phys_portstate(ibcs); 1879 1880 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 1881 handle_serdes_issues(ppd, ibcs); 1882 if (!(ppd->cpspec->ibcctrl_a & 1883 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) { 1884 /* 1885 * We got our interrupt, so init code should be 1886 * happy and not try alternatives. Now squelch 1887 * other "chatter" from link-negotiation (pre Init) 1888 */ 1889 ppd->cpspec->ibcctrl_a |= 1890 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 1891 qib_write_kreg_port(ppd, krp_ibcctrl_a, 1892 ppd->cpspec->ibcctrl_a); 1893 } 1894 1895 /* Update our picture of width and speed from chip */ 1896 ppd->link_width_active = 1897 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ? 1898 IB_WIDTH_4X : IB_WIDTH_1X; 1899 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, 1900 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs & 1901 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ? 1902 QIB_IB_DDR : QIB_IB_SDR; 1903 1904 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate != 1905 IB_PHYSPORTSTATE_DISABLED) 1906 qib_set_ib_7322_lstate(ppd, 0, 1907 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1908 else 1909 /* 1910 * Since going into a recovery state causes the link 1911 * state to go down and since recovery is transitory, 1912 * it is better if we "miss" ever seeing the link 1913 * training state go into recovery (i.e., ignore this 1914 * transition for link state special handling purposes) 1915 * without updating lastibcstat. 1916 */ 1917 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1918 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1919 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1920 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1921 qib_handle_e_ibstatuschanged(ppd, ibcs); 1922 } 1923 if (*msg && iserr) 1924 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); 1925 1926 if (ppd->state_wanted & ppd->lflags) 1927 wake_up_interruptible(&ppd->state_wait); 1928 done: 1929 return; 1930 } 1931 1932 /* enable/disable chip from delivering interrupts */ 1933 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) 1934 { 1935 if (enable) { 1936 if (dd->flags & QIB_BADINTR) 1937 return; 1938 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); 1939 /* cause any pending enabled interrupts to be re-delivered */ 1940 qib_write_kreg(dd, kr_intclear, 0ULL); 1941 if (dd->cspec->num_msix_entries) { 1942 /* and same for MSIx */ 1943 u64 val = qib_read_kreg64(dd, kr_intgranted); 1944 if (val) 1945 qib_write_kreg(dd, kr_intgranted, val); 1946 } 1947 } else 1948 qib_write_kreg(dd, kr_intmask, 0ULL); 1949 } 1950 1951 /* 1952 * Try to cleanup as much as possible for anything that might have gone 1953 * wrong while in freeze mode, such as pio buffers being written by user 1954 * processes (causing armlaunch), send errors due to going into freeze mode, 1955 * etc., and try to avoid causing extra interrupts while doing so. 1956 * Forcibly update the in-memory pioavail register copies after cleanup 1957 * because the chip won't do it while in freeze mode (the register values 1958 * themselves are kept correct). 1959 * Make sure that we don't lose any important interrupts by using the chip 1960 * feature that says that writing 0 to a bit in *clear that is set in 1961 * *status will cause an interrupt to be generated again (if allowed by 1962 * the *mask value). 1963 * This is in chip-specific code because of all of the register accesses, 1964 * even though the details are similar on most chips. 1965 */ 1966 static void qib_7322_clear_freeze(struct qib_devdata *dd) 1967 { 1968 int pidx; 1969 1970 /* disable error interrupts, to avoid confusion */ 1971 qib_write_kreg(dd, kr_errmask, 0ULL); 1972 1973 for (pidx = 0; pidx < dd->num_pports; ++pidx) 1974 if (dd->pport[pidx].link_speed_supported) 1975 qib_write_kreg_port(dd->pport + pidx, krp_errmask, 1976 0ULL); 1977 1978 /* also disable interrupts; errormask is sometimes overwriten */ 1979 qib_7322_set_intr_state(dd, 0); 1980 1981 /* clear the freeze, and be sure chip saw it */ 1982 qib_write_kreg(dd, kr_control, dd->control); 1983 qib_read_kreg32(dd, kr_scratch); 1984 1985 /* 1986 * Force new interrupt if any hwerr, error or interrupt bits are 1987 * still set, and clear "safe" send packet errors related to freeze 1988 * and cancelling sends. Re-enable error interrupts before possible 1989 * force of re-interrupt on pending interrupts. 1990 */ 1991 qib_write_kreg(dd, kr_hwerrclear, 0ULL); 1992 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); 1993 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1994 /* We need to purge per-port errs and reset mask, too */ 1995 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 1996 if (!dd->pport[pidx].link_speed_supported) 1997 continue; 1998 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); 1999 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); 2000 } 2001 qib_7322_set_intr_state(dd, 1); 2002 } 2003 2004 /* no error handling to speak of */ 2005 /** 2006 * qib_7322_handle_hwerrors - display hardware errors. 2007 * @dd: the qlogic_ib device 2008 * @msg: the output buffer 2009 * @msgl: the size of the output buffer 2010 * 2011 * Use same msg buffer as regular errors to avoid excessive stack 2012 * use. Most hardware errors are catastrophic, but for right now, 2013 * we'll print them and continue. We reuse the same message buffer as 2014 * qib_handle_errors() to avoid excessive stack usage. 2015 */ 2016 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, 2017 size_t msgl) 2018 { 2019 u64 hwerrs; 2020 u32 ctrl; 2021 int isfatal = 0; 2022 2023 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 2024 if (!hwerrs) 2025 goto bail; 2026 if (hwerrs == ~0ULL) { 2027 qib_dev_err(dd, "Read of hardware error status failed " 2028 "(all bits set); ignoring\n"); 2029 goto bail; 2030 } 2031 qib_stats.sps_hwerrs++; 2032 2033 /* Always clear the error status register, except BIST fail */ 2034 qib_write_kreg(dd, kr_hwerrclear, hwerrs & 2035 ~HWE_MASK(PowerOnBISTFailed)); 2036 2037 hwerrs &= dd->cspec->hwerrmask; 2038 2039 /* no EEPROM logging, yet */ 2040 2041 if (hwerrs) 2042 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx " 2043 "(cleared)\n", (unsigned long long) hwerrs); 2044 2045 ctrl = qib_read_kreg32(dd, kr_control); 2046 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { 2047 /* 2048 * No recovery yet... 2049 */ 2050 if ((hwerrs & ~HWE_MASK(LATriggered)) || 2051 dd->cspec->stay_in_freeze) { 2052 /* 2053 * If any set that we aren't ignoring only make the 2054 * complaint once, in case it's stuck or recurring, 2055 * and we get here multiple times 2056 * Force link down, so switch knows, and 2057 * LEDs are turned off. 2058 */ 2059 if (dd->flags & QIB_INITTED) 2060 isfatal = 1; 2061 } else 2062 qib_7322_clear_freeze(dd); 2063 } 2064 2065 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) { 2066 isfatal = 1; 2067 strlcpy(msg, "[Memory BIST test failed, " 2068 "InfiniPath hardware unusable]", msgl); 2069 /* ignore from now on, so disable until driver reloaded */ 2070 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); 2071 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 2072 } 2073 2074 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs); 2075 2076 /* Ignore esoteric PLL failures et al. */ 2077 2078 qib_dev_err(dd, "%s hardware error\n", msg); 2079 2080 if (isfatal && !dd->diag_client) { 2081 qib_dev_err(dd, "Fatal Hardware Error, no longer" 2082 " usable, SN %.16s\n", dd->serial); 2083 /* 2084 * for /sys status file and user programs to print; if no 2085 * trailing brace is copied, we'll know it was truncated. 2086 */ 2087 if (dd->freezemsg) 2088 snprintf(dd->freezemsg, dd->freezelen, 2089 "{%s}", msg); 2090 qib_disable_after_error(dd); 2091 } 2092 bail:; 2093 } 2094 2095 /** 2096 * qib_7322_init_hwerrors - enable hardware errors 2097 * @dd: the qlogic_ib device 2098 * 2099 * now that we have finished initializing everything that might reasonably 2100 * cause a hardware error, and cleared those errors bits as they occur, 2101 * we can enable hardware errors in the mask (potentially enabling 2102 * freeze mode), and enable hardware errors as errors (along with 2103 * everything else) in errormask 2104 */ 2105 static void qib_7322_init_hwerrors(struct qib_devdata *dd) 2106 { 2107 int pidx; 2108 u64 extsval; 2109 2110 extsval = qib_read_kreg64(dd, kr_extstatus); 2111 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED | 2112 QIB_EXTS_MEMBIST_ENDTEST))) 2113 qib_dev_err(dd, "MemBIST did not complete!\n"); 2114 2115 /* never clear BIST failure, so reported on each driver load */ 2116 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); 2117 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 2118 2119 /* clear all */ 2120 qib_write_kreg(dd, kr_errclear, ~0ULL); 2121 /* enable errors that are masked, at least this first time. */ 2122 qib_write_kreg(dd, kr_errmask, ~0ULL); 2123 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); 2124 for (pidx = 0; pidx < dd->num_pports; ++pidx) 2125 if (dd->pport[pidx].link_speed_supported) 2126 qib_write_kreg_port(dd->pport + pidx, krp_errmask, 2127 ~0ULL); 2128 } 2129 2130 /* 2131 * Disable and enable the armlaunch error. Used for PIO bandwidth testing 2132 * on chips that are count-based, rather than trigger-based. There is no 2133 * reference counting, but that's also fine, given the intended use. 2134 * Only chip-specific because it's all register accesses 2135 */ 2136 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) 2137 { 2138 if (enable) { 2139 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH); 2140 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; 2141 } else 2142 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; 2143 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 2144 } 2145 2146 /* 2147 * Formerly took parameter <which> in pre-shifted, 2148 * pre-merged form with LinkCmd and LinkInitCmd 2149 * together, and assuming the zero was NOP. 2150 */ 2151 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, 2152 u16 linitcmd) 2153 { 2154 u64 mod_wd; 2155 struct qib_devdata *dd = ppd->dd; 2156 unsigned long flags; 2157 2158 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) { 2159 /* 2160 * If we are told to disable, note that so link-recovery 2161 * code does not attempt to bring us back up. 2162 * Also reset everything that we can, so we start 2163 * completely clean when re-enabled (before we 2164 * actually issue the disable to the IBC) 2165 */ 2166 qib_7322_mini_pcs_reset(ppd); 2167 spin_lock_irqsave(&ppd->lflags_lock, flags); 2168 ppd->lflags |= QIBL_IB_LINK_DISABLED; 2169 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2170 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) { 2171 /* 2172 * Any other linkinitcmd will lead to LINKDOWN and then 2173 * to INIT (if all is well), so clear flag to let 2174 * link-recovery code attempt to bring us back up. 2175 */ 2176 spin_lock_irqsave(&ppd->lflags_lock, flags); 2177 ppd->lflags &= ~QIBL_IB_LINK_DISABLED; 2178 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2179 /* 2180 * Clear status change interrupt reduction so the 2181 * new state is seen. 2182 */ 2183 ppd->cpspec->ibcctrl_a &= 2184 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 2185 } 2186 2187 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) | 2188 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 2189 2190 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a | 2191 mod_wd); 2192 /* write to chip to prevent back-to-back writes of ibc reg */ 2193 qib_write_kreg(dd, kr_scratch, 0); 2194 2195 } 2196 2197 /* 2198 * The total RCV buffer memory is 64KB, used for both ports, and is 2199 * in units of 64 bytes (same as IB flow control credit unit). 2200 * The consumedVL unit in the same registers are in 32 byte units! 2201 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks, 2202 * and we can therefore allocate just 9 IB credits for 2 VL15 packets 2203 * in krp_rxcreditvl15, rather than 10. 2204 */ 2205 #define RCV_BUF_UNITSZ 64 2206 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports)) 2207 2208 static void set_vls(struct qib_pportdata *ppd) 2209 { 2210 int i, numvls, totcred, cred_vl, vl0extra; 2211 struct qib_devdata *dd = ppd->dd; 2212 u64 val; 2213 2214 numvls = qib_num_vls(ppd->vls_operational); 2215 2216 /* 2217 * Set up per-VL credits. Below is kluge based on these assumptions: 2218 * 1) port is disabled at the time early_init is called. 2219 * 2) give VL15 17 credits, for two max-plausible packets. 2220 * 3) Give VL0-N the rest, with any rounding excess used for VL0 2221 */ 2222 /* 2 VL15 packets @ 288 bytes each (including IB headers) */ 2223 totcred = NUM_RCV_BUF_UNITS(dd); 2224 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ; 2225 totcred -= cred_vl; 2226 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl); 2227 cred_vl = totcred / numvls; 2228 vl0extra = totcred - cred_vl * numvls; 2229 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra); 2230 for (i = 1; i < numvls; i++) 2231 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl); 2232 for (; i < 8; i++) /* no buffer space for other VLs */ 2233 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); 2234 2235 /* Notify IBC that credits need to be recalculated */ 2236 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); 2237 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); 2238 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 2239 qib_write_kreg(dd, kr_scratch, 0ULL); 2240 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE); 2241 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 2242 2243 for (i = 0; i < numvls; i++) 2244 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i); 2245 val = qib_read_kreg_port(ppd, krp_rxcreditvl15); 2246 2247 /* Change the number of operational VLs */ 2248 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a & 2249 ~SYM_MASK(IBCCtrlA_0, NumVLane)) | 2250 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); 2251 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 2252 qib_write_kreg(dd, kr_scratch, 0ULL); 2253 } 2254 2255 /* 2256 * The code that deals with actual SerDes is in serdes_7322_init(). 2257 * Compared to the code for iba7220, it is minimal. 2258 */ 2259 static int serdes_7322_init(struct qib_pportdata *ppd); 2260 2261 /** 2262 * qib_7322_bringup_serdes - bring up the serdes 2263 * @ppd: physical port on the qlogic_ib device 2264 */ 2265 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd) 2266 { 2267 struct qib_devdata *dd = ppd->dd; 2268 u64 val, guid, ibc; 2269 unsigned long flags; 2270 int ret = 0; 2271 2272 /* 2273 * SerDes model not in Pd, but still need to 2274 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere 2275 * eventually. 2276 */ 2277 /* Put IBC in reset, sends disabled (should be in reset already) */ 2278 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); 2279 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 2280 qib_write_kreg(dd, kr_scratch, 0ULL); 2281 2282 if (qib_compat_ddr_negotiate) { 2283 ppd->cpspec->ibdeltainprog = 1; 2284 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, 2285 crp_ibsymbolerr); 2286 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, 2287 crp_iblinkerrrecov); 2288 } 2289 2290 /* flowcontrolwatermark is in units of KBytes */ 2291 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark); 2292 /* 2293 * Flow control is sent this often, even if no changes in 2294 * buffer space occur. Units are 128ns for this chip. 2295 * Set to 3usec. 2296 */ 2297 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod); 2298 /* max error tolerance */ 2299 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold); 2300 /* IB credit flow control. */ 2301 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold); 2302 /* 2303 * set initial max size pkt IBC will send, including ICRC; it's the 2304 * PIO buffer size in dwords, less 1; also see qib_set_mtu() 2305 */ 2306 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << 2307 SYM_LSB(IBCCtrlA_0, MaxPktLen); 2308 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */ 2309 2310 /* initially come up waiting for TS1, without sending anything. */ 2311 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << 2312 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 2313 2314 ppd->cpspec->ibcctrl_a = val; 2315 /* 2316 * Reset the PCS interface to the serdes (and also ibc, which is still 2317 * in reset from above). Writes new value of ibcctrl_a as last step. 2318 */ 2319 qib_7322_mini_pcs_reset(ppd); 2320 qib_write_kreg(dd, kr_scratch, 0ULL); 2321 /* clear the linkinit cmds */ 2322 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); 2323 2324 if (!ppd->cpspec->ibcctrl_b) { 2325 unsigned lse = ppd->link_speed_enabled; 2326 2327 /* 2328 * Not on re-init after reset, establish shadow 2329 * and force initial config. 2330 */ 2331 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd, 2332 krp_ibcctrl_b); 2333 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR | 2334 IBA7322_IBC_SPEED_DDR | 2335 IBA7322_IBC_SPEED_SDR | 2336 IBA7322_IBC_WIDTH_AUTONEG | 2337 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED)); 2338 if (lse & (lse - 1)) /* Muliple speeds enabled */ 2339 ppd->cpspec->ibcctrl_b |= 2340 (lse << IBA7322_IBC_SPEED_LSB) | 2341 IBA7322_IBC_IBTA_1_2_MASK | 2342 IBA7322_IBC_MAX_SPEED_MASK; 2343 else 2344 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ? 2345 IBA7322_IBC_SPEED_QDR | 2346 IBA7322_IBC_IBTA_1_2_MASK : 2347 (lse == QIB_IB_DDR) ? 2348 IBA7322_IBC_SPEED_DDR : 2349 IBA7322_IBC_SPEED_SDR; 2350 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) == 2351 (IB_WIDTH_1X | IB_WIDTH_4X)) 2352 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG; 2353 else 2354 ppd->cpspec->ibcctrl_b |= 2355 ppd->link_width_enabled == IB_WIDTH_4X ? 2356 IBA7322_IBC_WIDTH_4X_ONLY : 2357 IBA7322_IBC_WIDTH_1X_ONLY; 2358 2359 /* always enable these on driver reload, not sticky */ 2360 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK | 2361 IBA7322_IBC_HRTBT_MASK); 2362 } 2363 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 2364 2365 /* setup so we have more time at CFGTEST to change H1 */ 2366 val = qib_read_kreg_port(ppd, krp_ibcctrl_c); 2367 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH); 2368 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); 2369 qib_write_kreg_port(ppd, krp_ibcctrl_c, val); 2370 2371 serdes_7322_init(ppd); 2372 2373 guid = be64_to_cpu(ppd->guid); 2374 if (!guid) { 2375 if (dd->base_guid) 2376 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; 2377 ppd->guid = cpu_to_be64(guid); 2378 } 2379 2380 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid); 2381 /* write to chip to prevent back-to-back writes of ibc reg */ 2382 qib_write_kreg(dd, kr_scratch, 0); 2383 2384 /* Enable port */ 2385 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); 2386 set_vls(ppd); 2387 2388 /* be paranoid against later code motion, etc. */ 2389 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 2390 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); 2391 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); 2392 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 2393 2394 /* Also enable IBSTATUSCHG interrupt. */ 2395 val = qib_read_kreg_port(ppd, krp_errmask); 2396 qib_write_kreg_port(ppd, krp_errmask, 2397 val | ERR_MASK_N(IBStatusChanged)); 2398 2399 /* Always zero until we start messing with SerDes for real */ 2400 return ret; 2401 } 2402 2403 /** 2404 * qib_7322_quiet_serdes - set serdes to txidle 2405 * @dd: the qlogic_ib device 2406 * Called when driver is being unloaded 2407 */ 2408 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd) 2409 { 2410 u64 val; 2411 unsigned long flags; 2412 2413 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 2414 2415 spin_lock_irqsave(&ppd->lflags_lock, flags); 2416 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; 2417 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 2418 wake_up(&ppd->cpspec->autoneg_wait); 2419 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work); 2420 if (ppd->dd->cspec->r1) 2421 cancel_delayed_work_sync(&ppd->cpspec->ipg_work); 2422 2423 ppd->cpspec->chase_end = 0; 2424 if (ppd->cpspec->chase_timer.data) /* if initted */ 2425 del_timer_sync(&ppd->cpspec->chase_timer); 2426 2427 /* 2428 * Despite the name, actually disables IBC as well. Do it when 2429 * we are as sure as possible that no more packets can be 2430 * received, following the down and the PCS reset. 2431 * The actual disabling happens in qib_7322_mini_pci_reset(), 2432 * along with the PCS being reset. 2433 */ 2434 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); 2435 qib_7322_mini_pcs_reset(ppd); 2436 2437 /* 2438 * Update the adjusted counters so the adjustment persists 2439 * across driver reload. 2440 */ 2441 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta || 2442 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) { 2443 struct qib_devdata *dd = ppd->dd; 2444 u64 diagc; 2445 2446 /* enable counter writes */ 2447 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); 2448 qib_write_kreg(dd, kr_hwdiagctrl, 2449 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); 2450 2451 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) { 2452 val = read_7322_creg32_port(ppd, crp_ibsymbolerr); 2453 if (ppd->cpspec->ibdeltainprog) 2454 val -= val - ppd->cpspec->ibsymsnap; 2455 val -= ppd->cpspec->ibsymdelta; 2456 write_7322_creg_port(ppd, crp_ibsymbolerr, val); 2457 } 2458 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) { 2459 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov); 2460 if (ppd->cpspec->ibdeltainprog) 2461 val -= val - ppd->cpspec->iblnkerrsnap; 2462 val -= ppd->cpspec->iblnkerrdelta; 2463 write_7322_creg_port(ppd, crp_iblinkerrrecov, val); 2464 } 2465 if (ppd->cpspec->iblnkdowndelta) { 2466 val = read_7322_creg32_port(ppd, crp_iblinkdown); 2467 val += ppd->cpspec->iblnkdowndelta; 2468 write_7322_creg_port(ppd, crp_iblinkdown, val); 2469 } 2470 /* 2471 * No need to save ibmalfdelta since IB perfcounters 2472 * are cleared on driver reload. 2473 */ 2474 2475 /* and disable counter writes */ 2476 qib_write_kreg(dd, kr_hwdiagctrl, diagc); 2477 } 2478 } 2479 2480 /** 2481 * qib_setup_7322_setextled - set the state of the two external LEDs 2482 * @ppd: physical port on the qlogic_ib device 2483 * @on: whether the link is up or not 2484 * 2485 * The exact combo of LEDs if on is true is determined by looking 2486 * at the ibcstatus. 2487 * 2488 * These LEDs indicate the physical and logical state of IB link. 2489 * For this chip (at least with recommended board pinouts), LED1 2490 * is Yellow (logical state) and LED2 is Green (physical state), 2491 * 2492 * Note: We try to match the Mellanox HCA LED behavior as best 2493 * we can. Green indicates physical link state is OK (something is 2494 * plugged in, and we can train). 2495 * Amber indicates the link is logically up (ACTIVE). 2496 * Mellanox further blinks the amber LED to indicate data packet 2497 * activity, but we have no hardware support for that, so it would 2498 * require waking up every 10-20 msecs and checking the counters 2499 * on the chip, and then turning the LED off if appropriate. That's 2500 * visible overhead, so not something we will do. 2501 */ 2502 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on) 2503 { 2504 struct qib_devdata *dd = ppd->dd; 2505 u64 extctl, ledblink = 0, val; 2506 unsigned long flags; 2507 int yel, grn; 2508 2509 /* 2510 * The diags use the LED to indicate diag info, so we leave 2511 * the external LED alone when the diags are running. 2512 */ 2513 if (dd->diag_client) 2514 return; 2515 2516 /* Allow override of LED display for, e.g. Locating system in rack */ 2517 if (ppd->led_override) { 2518 grn = (ppd->led_override & QIB_LED_PHYS); 2519 yel = (ppd->led_override & QIB_LED_LOG); 2520 } else if (on) { 2521 val = qib_read_kreg_port(ppd, krp_ibcstatus_a); 2522 grn = qib_7322_phys_portstate(val) == 2523 IB_PHYSPORTSTATE_LINKUP; 2524 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE; 2525 } else { 2526 grn = 0; 2527 yel = 0; 2528 } 2529 2530 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 2531 extctl = dd->cspec->extctrl & (ppd->port == 1 ? 2532 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK); 2533 if (grn) { 2534 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN; 2535 /* 2536 * Counts are in chip clock (4ns) periods. 2537 * This is 1/16 sec (66.6ms) on, 2538 * 3/16 sec (187.5 ms) off, with packets rcvd. 2539 */ 2540 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) | 2541 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT); 2542 } 2543 if (yel) 2544 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL; 2545 dd->cspec->extctrl = extctl; 2546 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 2547 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 2548 2549 if (ledblink) /* blink the LED on packet receive */ 2550 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink); 2551 } 2552 2553 /* 2554 * Disable MSIx interrupt if enabled, call generic MSIx code 2555 * to cleanup, and clear pending MSIx interrupts. 2556 * Used for fallback to INTx, after reset, and when MSIx setup fails. 2557 */ 2558 static void qib_7322_nomsix(struct qib_devdata *dd) 2559 { 2560 u64 intgranted; 2561 int n; 2562 2563 dd->cspec->main_int_mask = ~0ULL; 2564 n = dd->cspec->num_msix_entries; 2565 if (n) { 2566 int i; 2567 2568 dd->cspec->num_msix_entries = 0; 2569 for (i = 0; i < n; i++) 2570 free_irq(dd->cspec->msix_entries[i].vector, 2571 dd->cspec->msix_arg[i]); 2572 qib_nomsix(dd); 2573 } 2574 /* make sure no MSIx interrupts are left pending */ 2575 intgranted = qib_read_kreg64(dd, kr_intgranted); 2576 if (intgranted) 2577 qib_write_kreg(dd, kr_intgranted, intgranted); 2578 } 2579 2580 static void qib_7322_free_irq(struct qib_devdata *dd) 2581 { 2582 if (dd->cspec->irq) { 2583 free_irq(dd->cspec->irq, dd); 2584 dd->cspec->irq = 0; 2585 } 2586 qib_7322_nomsix(dd); 2587 } 2588 2589 static void qib_setup_7322_cleanup(struct qib_devdata *dd) 2590 { 2591 int i; 2592 2593 qib_7322_free_irq(dd); 2594 kfree(dd->cspec->cntrs); 2595 kfree(dd->cspec->sendchkenable); 2596 kfree(dd->cspec->sendgrhchk); 2597 kfree(dd->cspec->sendibchk); 2598 kfree(dd->cspec->msix_entries); 2599 kfree(dd->cspec->msix_arg); 2600 for (i = 0; i < dd->num_pports; i++) { 2601 unsigned long flags; 2602 u32 mask = QSFP_GPIO_MOD_PRS_N | 2603 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT); 2604 2605 kfree(dd->pport[i].cpspec->portcntrs); 2606 if (dd->flags & QIB_HAS_QSFP) { 2607 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 2608 dd->cspec->gpio_mask &= ~mask; 2609 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 2610 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 2611 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data); 2612 } 2613 if (dd->pport[i].ibport_data.smi_ah) 2614 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah); 2615 } 2616 } 2617 2618 /* handle SDMA interrupts */ 2619 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) 2620 { 2621 struct qib_pportdata *ppd0 = &dd->pport[0]; 2622 struct qib_pportdata *ppd1 = &dd->pport[1]; 2623 u64 intr0 = istat & (INT_MASK_P(SDma, 0) | 2624 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0)); 2625 u64 intr1 = istat & (INT_MASK_P(SDma, 1) | 2626 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1)); 2627 2628 if (intr0) 2629 qib_sdma_intr(ppd0); 2630 if (intr1) 2631 qib_sdma_intr(ppd1); 2632 2633 if (istat & INT_MASK_PM(SDmaCleanupDone, 0)) 2634 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started); 2635 if (istat & INT_MASK_PM(SDmaCleanupDone, 1)) 2636 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started); 2637 } 2638 2639 /* 2640 * Set or clear the Send buffer available interrupt enable bit. 2641 */ 2642 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) 2643 { 2644 unsigned long flags; 2645 2646 spin_lock_irqsave(&dd->sendctrl_lock, flags); 2647 if (needint) 2648 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); 2649 else 2650 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); 2651 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 2652 qib_write_kreg(dd, kr_scratch, 0ULL); 2653 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 2654 } 2655 2656 /* 2657 * Somehow got an interrupt with reserved bits set in interrupt status. 2658 * Print a message so we know it happened, then clear them. 2659 * keep mainline interrupt handler cache-friendly 2660 */ 2661 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) 2662 { 2663 u64 kills; 2664 char msg[128]; 2665 2666 kills = istat & ~QIB_I_BITSEXTANT; 2667 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:" 2668 " %s\n", (unsigned long long) kills, msg); 2669 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); 2670 } 2671 2672 /* keep mainline interrupt handler cache-friendly */ 2673 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) 2674 { 2675 u32 gpiostatus; 2676 int handled = 0; 2677 int pidx; 2678 2679 /* 2680 * Boards for this chip currently don't use GPIO interrupts, 2681 * so clear by writing GPIOstatus to GPIOclear, and complain 2682 * to developer. To avoid endless repeats, clear 2683 * the bits in the mask, since there is some kind of 2684 * programming error or chip problem. 2685 */ 2686 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); 2687 /* 2688 * In theory, writing GPIOstatus to GPIOclear could 2689 * have a bad side-effect on some diagnostic that wanted 2690 * to poll for a status-change, but the various shadows 2691 * make that problematic at best. Diags will just suppress 2692 * all GPIO interrupts during such tests. 2693 */ 2694 qib_write_kreg(dd, kr_gpio_clear, gpiostatus); 2695 /* 2696 * Check for QSFP MOD_PRS changes 2697 * only works for single port if IB1 != pidx1 2698 */ 2699 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); 2700 ++pidx) { 2701 struct qib_pportdata *ppd; 2702 struct qib_qsfp_data *qd; 2703 u32 mask; 2704 if (!dd->pport[pidx].link_speed_supported) 2705 continue; 2706 mask = QSFP_GPIO_MOD_PRS_N; 2707 ppd = dd->pport + pidx; 2708 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); 2709 if (gpiostatus & dd->cspec->gpio_mask & mask) { 2710 u64 pins; 2711 qd = &ppd->cpspec->qsfp_data; 2712 gpiostatus &= ~mask; 2713 pins = qib_read_kreg64(dd, kr_extstatus); 2714 pins >>= SYM_LSB(EXTStatus, GPIOIn); 2715 if (!(pins & mask)) { 2716 ++handled; 2717 qd->t_insert = get_jiffies_64(); 2718 queue_work(ib_wq, &qd->work); 2719 } 2720 } 2721 } 2722 2723 if (gpiostatus && !handled) { 2724 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); 2725 u32 gpio_irq = mask & gpiostatus; 2726 2727 /* 2728 * Clear any troublemakers, and update chip from shadow 2729 */ 2730 dd->cspec->gpio_mask &= ~gpio_irq; 2731 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 2732 } 2733 } 2734 2735 /* 2736 * Handle errors and unusual events first, separate function 2737 * to improve cache hits for fast path interrupt handling. 2738 */ 2739 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) 2740 { 2741 if (istat & ~QIB_I_BITSEXTANT) 2742 unknown_7322_ibits(dd, istat); 2743 if (istat & QIB_I_GPIO) 2744 unknown_7322_gpio_intr(dd); 2745 if (istat & QIB_I_C_ERROR) { 2746 qib_write_kreg(dd, kr_errmask, 0ULL); 2747 tasklet_schedule(&dd->error_tasklet); 2748 } 2749 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) 2750 handle_7322_p_errors(dd->rcd[0]->ppd); 2751 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) 2752 handle_7322_p_errors(dd->rcd[1]->ppd); 2753 } 2754 2755 /* 2756 * Dynamically adjust the rcv int timeout for a context based on incoming 2757 * packet rate. 2758 */ 2759 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts) 2760 { 2761 struct qib_devdata *dd = rcd->dd; 2762 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; 2763 2764 /* 2765 * Dynamically adjust idle timeout on chip 2766 * based on number of packets processed. 2767 */ 2768 if (npkts < rcv_int_count && timeout > 2) 2769 timeout >>= 1; 2770 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout) 2771 timeout = min(timeout << 1, rcv_int_timeout); 2772 else 2773 return; 2774 2775 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; 2776 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); 2777 } 2778 2779 /* 2780 * This is the main interrupt handler. 2781 * It will normally only be used for low frequency interrupts but may 2782 * have to handle all interrupts if INTx is enabled or fewer than normal 2783 * MSIx interrupts were allocated. 2784 * This routine should ignore the interrupt bits for any of the 2785 * dedicated MSIx handlers. 2786 */ 2787 static irqreturn_t qib_7322intr(int irq, void *data) 2788 { 2789 struct qib_devdata *dd = data; 2790 irqreturn_t ret; 2791 u64 istat; 2792 u64 ctxtrbits; 2793 u64 rmask; 2794 unsigned i; 2795 u32 npkts; 2796 2797 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { 2798 /* 2799 * This return value is not great, but we do not want the 2800 * interrupt core code to remove our interrupt handler 2801 * because we don't appear to be handling an interrupt 2802 * during a chip reset. 2803 */ 2804 ret = IRQ_HANDLED; 2805 goto bail; 2806 } 2807 2808 istat = qib_read_kreg64(dd, kr_intstatus); 2809 2810 if (unlikely(istat == ~0ULL)) { 2811 qib_bad_intrstatus(dd); 2812 qib_dev_err(dd, "Interrupt status all f's, skipping\n"); 2813 /* don't know if it was our interrupt or not */ 2814 ret = IRQ_NONE; 2815 goto bail; 2816 } 2817 2818 istat &= dd->cspec->main_int_mask; 2819 if (unlikely(!istat)) { 2820 /* already handled, or shared and not us */ 2821 ret = IRQ_NONE; 2822 goto bail; 2823 } 2824 2825 qib_stats.sps_ints++; 2826 if (dd->int_counter != (u32) -1) 2827 dd->int_counter++; 2828 2829 /* handle "errors" of various kinds first, device ahead of port */ 2830 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO | 2831 QIB_I_C_ERROR | INT_MASK_P(Err, 0) | 2832 INT_MASK_P(Err, 1)))) 2833 unlikely_7322_intr(dd, istat); 2834 2835 /* 2836 * Clear the interrupt bits we found set, relatively early, so we 2837 * "know" know the chip will have seen this by the time we process 2838 * the queue, and will re-interrupt if necessary. The processor 2839 * itself won't take the interrupt again until we return. 2840 */ 2841 qib_write_kreg(dd, kr_intclear, istat); 2842 2843 /* 2844 * Handle kernel receive queues before checking for pio buffers 2845 * available since receives can overflow; piobuf waiters can afford 2846 * a few extra cycles, since they were waiting anyway. 2847 */ 2848 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK); 2849 if (ctxtrbits) { 2850 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) | 2851 (1ULL << QIB_I_RCVURG_LSB); 2852 for (i = 0; i < dd->first_user_ctxt; i++) { 2853 if (ctxtrbits & rmask) { 2854 ctxtrbits &= ~rmask; 2855 if (dd->rcd[i]) 2856 qib_kreceive(dd->rcd[i], NULL, &npkts); 2857 } 2858 rmask <<= 1; 2859 } 2860 if (ctxtrbits) { 2861 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) | 2862 (ctxtrbits >> QIB_I_RCVURG_LSB); 2863 qib_handle_urcv(dd, ctxtrbits); 2864 } 2865 } 2866 2867 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1))) 2868 sdma_7322_intr(dd, istat); 2869 2870 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) 2871 qib_ib_piobufavail(dd); 2872 2873 ret = IRQ_HANDLED; 2874 bail: 2875 return ret; 2876 } 2877 2878 /* 2879 * Dedicated receive packet available interrupt handler. 2880 */ 2881 static irqreturn_t qib_7322pintr(int irq, void *data) 2882 { 2883 struct qib_ctxtdata *rcd = data; 2884 struct qib_devdata *dd = rcd->dd; 2885 u32 npkts; 2886 2887 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2888 /* 2889 * This return value is not great, but we do not want the 2890 * interrupt core code to remove our interrupt handler 2891 * because we don't appear to be handling an interrupt 2892 * during a chip reset. 2893 */ 2894 return IRQ_HANDLED; 2895 2896 qib_stats.sps_ints++; 2897 if (dd->int_counter != (u32) -1) 2898 dd->int_counter++; 2899 2900 /* Clear the interrupt bit we expect to be set. */ 2901 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | 2902 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); 2903 2904 qib_kreceive(rcd, NULL, &npkts); 2905 2906 return IRQ_HANDLED; 2907 } 2908 2909 /* 2910 * Dedicated Send buffer available interrupt handler. 2911 */ 2912 static irqreturn_t qib_7322bufavail(int irq, void *data) 2913 { 2914 struct qib_devdata *dd = data; 2915 2916 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2917 /* 2918 * This return value is not great, but we do not want the 2919 * interrupt core code to remove our interrupt handler 2920 * because we don't appear to be handling an interrupt 2921 * during a chip reset. 2922 */ 2923 return IRQ_HANDLED; 2924 2925 qib_stats.sps_ints++; 2926 if (dd->int_counter != (u32) -1) 2927 dd->int_counter++; 2928 2929 /* Clear the interrupt bit we expect to be set. */ 2930 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL); 2931 2932 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */ 2933 if (dd->flags & QIB_INITTED) 2934 qib_ib_piobufavail(dd); 2935 else 2936 qib_wantpiobuf_7322_intr(dd, 0); 2937 2938 return IRQ_HANDLED; 2939 } 2940 2941 /* 2942 * Dedicated Send DMA interrupt handler. 2943 */ 2944 static irqreturn_t sdma_intr(int irq, void *data) 2945 { 2946 struct qib_pportdata *ppd = data; 2947 struct qib_devdata *dd = ppd->dd; 2948 2949 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2950 /* 2951 * This return value is not great, but we do not want the 2952 * interrupt core code to remove our interrupt handler 2953 * because we don't appear to be handling an interrupt 2954 * during a chip reset. 2955 */ 2956 return IRQ_HANDLED; 2957 2958 qib_stats.sps_ints++; 2959 if (dd->int_counter != (u32) -1) 2960 dd->int_counter++; 2961 2962 /* Clear the interrupt bit we expect to be set. */ 2963 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 2964 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0)); 2965 qib_sdma_intr(ppd); 2966 2967 return IRQ_HANDLED; 2968 } 2969 2970 /* 2971 * Dedicated Send DMA idle interrupt handler. 2972 */ 2973 static irqreturn_t sdma_idle_intr(int irq, void *data) 2974 { 2975 struct qib_pportdata *ppd = data; 2976 struct qib_devdata *dd = ppd->dd; 2977 2978 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 2979 /* 2980 * This return value is not great, but we do not want the 2981 * interrupt core code to remove our interrupt handler 2982 * because we don't appear to be handling an interrupt 2983 * during a chip reset. 2984 */ 2985 return IRQ_HANDLED; 2986 2987 qib_stats.sps_ints++; 2988 if (dd->int_counter != (u32) -1) 2989 dd->int_counter++; 2990 2991 /* Clear the interrupt bit we expect to be set. */ 2992 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 2993 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0)); 2994 qib_sdma_intr(ppd); 2995 2996 return IRQ_HANDLED; 2997 } 2998 2999 /* 3000 * Dedicated Send DMA progress interrupt handler. 3001 */ 3002 static irqreturn_t sdma_progress_intr(int irq, void *data) 3003 { 3004 struct qib_pportdata *ppd = data; 3005 struct qib_devdata *dd = ppd->dd; 3006 3007 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3008 /* 3009 * This return value is not great, but we do not want the 3010 * interrupt core code to remove our interrupt handler 3011 * because we don't appear to be handling an interrupt 3012 * during a chip reset. 3013 */ 3014 return IRQ_HANDLED; 3015 3016 qib_stats.sps_ints++; 3017 if (dd->int_counter != (u32) -1) 3018 dd->int_counter++; 3019 3020 /* Clear the interrupt bit we expect to be set. */ 3021 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3022 INT_MASK_P(SDmaProgress, 1) : 3023 INT_MASK_P(SDmaProgress, 0)); 3024 qib_sdma_intr(ppd); 3025 3026 return IRQ_HANDLED; 3027 } 3028 3029 /* 3030 * Dedicated Send DMA cleanup interrupt handler. 3031 */ 3032 static irqreturn_t sdma_cleanup_intr(int irq, void *data) 3033 { 3034 struct qib_pportdata *ppd = data; 3035 struct qib_devdata *dd = ppd->dd; 3036 3037 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) 3038 /* 3039 * This return value is not great, but we do not want the 3040 * interrupt core code to remove our interrupt handler 3041 * because we don't appear to be handling an interrupt 3042 * during a chip reset. 3043 */ 3044 return IRQ_HANDLED; 3045 3046 qib_stats.sps_ints++; 3047 if (dd->int_counter != (u32) -1) 3048 dd->int_counter++; 3049 3050 /* Clear the interrupt bit we expect to be set. */ 3051 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? 3052 INT_MASK_PM(SDmaCleanupDone, 1) : 3053 INT_MASK_PM(SDmaCleanupDone, 0)); 3054 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started); 3055 3056 return IRQ_HANDLED; 3057 } 3058 3059 /* 3060 * Set up our chip-specific interrupt handler. 3061 * The interrupt type has already been setup, so 3062 * we just need to do the registration and error checking. 3063 * If we are using MSIx interrupts, we may fall back to 3064 * INTx later, if the interrupt handler doesn't get called 3065 * within 1/2 second (see verify_interrupt()). 3066 */ 3067 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) 3068 { 3069 int ret, i, msixnum; 3070 u64 redirect[6]; 3071 u64 mask; 3072 3073 if (!dd->num_pports) 3074 return; 3075 3076 if (clearpend) { 3077 /* 3078 * if not switching interrupt types, be sure interrupts are 3079 * disabled, and then clear anything pending at this point, 3080 * because we are starting clean. 3081 */ 3082 qib_7322_set_intr_state(dd, 0); 3083 3084 /* clear the reset error, init error/hwerror mask */ 3085 qib_7322_init_hwerrors(dd); 3086 3087 /* clear any interrupt bits that might be set */ 3088 qib_write_kreg(dd, kr_intclear, ~0ULL); 3089 3090 /* make sure no pending MSIx intr, and clear diag reg */ 3091 qib_write_kreg(dd, kr_intgranted, ~0ULL); 3092 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL); 3093 } 3094 3095 if (!dd->cspec->num_msix_entries) { 3096 /* Try to get INTx interrupt */ 3097 try_intx: 3098 if (!dd->pcidev->irq) { 3099 qib_dev_err(dd, "irq is 0, BIOS error? " 3100 "Interrupts won't work\n"); 3101 goto bail; 3102 } 3103 ret = request_irq(dd->pcidev->irq, qib_7322intr, 3104 IRQF_SHARED, QIB_DRV_NAME, dd); 3105 if (ret) { 3106 qib_dev_err(dd, "Couldn't setup INTx " 3107 "interrupt (irq=%d): %d\n", 3108 dd->pcidev->irq, ret); 3109 goto bail; 3110 } 3111 dd->cspec->irq = dd->pcidev->irq; 3112 dd->cspec->main_int_mask = ~0ULL; 3113 goto bail; 3114 } 3115 3116 /* Try to get MSIx interrupts */ 3117 memset(redirect, 0, sizeof redirect); 3118 mask = ~0ULL; 3119 msixnum = 0; 3120 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { 3121 irq_handler_t handler; 3122 const char *name; 3123 void *arg; 3124 u64 val; 3125 int lsb, reg, sh; 3126 3127 if (i < ARRAY_SIZE(irq_table)) { 3128 if (irq_table[i].port) { 3129 /* skip if for a non-configured port */ 3130 if (irq_table[i].port > dd->num_pports) 3131 continue; 3132 arg = dd->pport + irq_table[i].port - 1; 3133 } else 3134 arg = dd; 3135 lsb = irq_table[i].lsb; 3136 handler = irq_table[i].handler; 3137 name = irq_table[i].name; 3138 } else { 3139 unsigned ctxt; 3140 3141 ctxt = i - ARRAY_SIZE(irq_table); 3142 /* per krcvq context receive interrupt */ 3143 arg = dd->rcd[ctxt]; 3144 if (!arg) 3145 continue; 3146 if (qib_krcvq01_no_msi && ctxt < 2) 3147 continue; 3148 lsb = QIB_I_RCVAVAIL_LSB + ctxt; 3149 handler = qib_7322pintr; 3150 name = QIB_DRV_NAME " (kctx)"; 3151 } 3152 ret = request_irq(dd->cspec->msix_entries[msixnum].vector, 3153 handler, 0, name, arg); 3154 if (ret) { 3155 /* 3156 * Shouldn't happen since the enable said we could 3157 * have as many as we are trying to setup here. 3158 */ 3159 qib_dev_err(dd, "Couldn't setup MSIx " 3160 "interrupt (vec=%d, irq=%d): %d\n", msixnum, 3161 dd->cspec->msix_entries[msixnum].vector, 3162 ret); 3163 qib_7322_nomsix(dd); 3164 goto try_intx; 3165 } 3166 dd->cspec->msix_arg[msixnum] = arg; 3167 if (lsb >= 0) { 3168 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG; 3169 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) * 3170 SYM_LSB(IntRedirect0, vec1); 3171 mask &= ~(1ULL << lsb); 3172 redirect[reg] |= ((u64) msixnum) << sh; 3173 } 3174 val = qib_read_kreg64(dd, 2 * msixnum + 1 + 3175 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3176 msixnum++; 3177 } 3178 /* Initialize the vector mapping */ 3179 for (i = 0; i < ARRAY_SIZE(redirect); i++) 3180 qib_write_kreg(dd, kr_intredirect + i, redirect[i]); 3181 dd->cspec->main_int_mask = mask; 3182 tasklet_init(&dd->error_tasklet, qib_error_tasklet, 3183 (unsigned long)dd); 3184 bail:; 3185 } 3186 3187 /** 3188 * qib_7322_boardname - fill in the board name and note features 3189 * @dd: the qlogic_ib device 3190 * 3191 * info will be based on the board revision register 3192 */ 3193 static unsigned qib_7322_boardname(struct qib_devdata *dd) 3194 { 3195 /* Will need enumeration of board-types here */ 3196 char *n; 3197 u32 boardid, namelen; 3198 unsigned features = DUAL_PORT_CAP; 3199 3200 boardid = SYM_FIELD(dd->revision, Revision, BoardID); 3201 3202 switch (boardid) { 3203 case 0: 3204 n = "InfiniPath_QLE7342_Emulation"; 3205 break; 3206 case 1: 3207 n = "InfiniPath_QLE7340"; 3208 dd->flags |= QIB_HAS_QSFP; 3209 features = PORT_SPD_CAP; 3210 break; 3211 case 2: 3212 n = "InfiniPath_QLE7342"; 3213 dd->flags |= QIB_HAS_QSFP; 3214 break; 3215 case 3: 3216 n = "InfiniPath_QMI7342"; 3217 break; 3218 case 4: 3219 n = "InfiniPath_Unsupported7342"; 3220 qib_dev_err(dd, "Unsupported version of QMH7342\n"); 3221 features = 0; 3222 break; 3223 case BOARD_QMH7342: 3224 n = "InfiniPath_QMH7342"; 3225 features = 0x24; 3226 break; 3227 case BOARD_QME7342: 3228 n = "InfiniPath_QME7342"; 3229 break; 3230 case 8: 3231 n = "InfiniPath_QME7362"; 3232 dd->flags |= QIB_HAS_QSFP; 3233 break; 3234 case 15: 3235 n = "InfiniPath_QLE7342_TEST"; 3236 dd->flags |= QIB_HAS_QSFP; 3237 break; 3238 default: 3239 n = "InfiniPath_QLE73xy_UNKNOWN"; 3240 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid); 3241 break; 3242 } 3243 dd->board_atten = 1; /* index into txdds_Xdr */ 3244 3245 namelen = strlen(n) + 1; 3246 dd->boardname = kmalloc(namelen, GFP_KERNEL); 3247 if (!dd->boardname) 3248 qib_dev_err(dd, "Failed allocation for board name: %s\n", n); 3249 else 3250 snprintf(dd->boardname, namelen, "%s", n); 3251 3252 snprintf(dd->boardversion, sizeof(dd->boardversion), 3253 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n", 3254 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, 3255 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch), 3256 dd->majrev, dd->minrev, 3257 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW)); 3258 3259 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) { 3260 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode" 3261 " by module parameter\n", dd->unit); 3262 features &= PORT_SPD_CAP; 3263 } 3264 3265 return features; 3266 } 3267 3268 /* 3269 * This routine sleeps, so it can only be called from user context, not 3270 * from interrupt context. 3271 */ 3272 static int qib_do_7322_reset(struct qib_devdata *dd) 3273 { 3274 u64 val; 3275 u64 *msix_vecsave; 3276 int i, msix_entries, ret = 1; 3277 u16 cmdval; 3278 u8 int_line, clinesz; 3279 unsigned long flags; 3280 3281 /* Use dev_err so it shows up in logs, etc. */ 3282 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); 3283 3284 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); 3285 3286 msix_entries = dd->cspec->num_msix_entries; 3287 3288 /* no interrupts till re-initted */ 3289 qib_7322_set_intr_state(dd, 0); 3290 3291 if (msix_entries) { 3292 qib_7322_nomsix(dd); 3293 /* can be up to 512 bytes, too big for stack */ 3294 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * 3295 sizeof(u64), GFP_KERNEL); 3296 if (!msix_vecsave) 3297 qib_dev_err(dd, "No mem to save MSIx data\n"); 3298 } else 3299 msix_vecsave = NULL; 3300 3301 /* 3302 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector 3303 * info that is set up by the BIOS, so we have to save and restore 3304 * it ourselves. There is some risk something could change it, 3305 * after we save it, but since we have disabled the MSIx, it 3306 * shouldn't be touched... 3307 */ 3308 for (i = 0; i < msix_entries; i++) { 3309 u64 vecaddr, vecdata; 3310 vecaddr = qib_read_kreg64(dd, 2 * i + 3311 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3312 vecdata = qib_read_kreg64(dd, 1 + 2 * i + 3313 (QIB_7322_MsixTable_OFFS / sizeof(u64))); 3314 if (msix_vecsave) { 3315 msix_vecsave[2 * i] = vecaddr; 3316 /* save it without the masked bit set */ 3317 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL; 3318 } 3319 } 3320 3321 dd->pport->cpspec->ibdeltainprog = 0; 3322 dd->pport->cpspec->ibsymdelta = 0; 3323 dd->pport->cpspec->iblnkerrdelta = 0; 3324 dd->pport->cpspec->ibmalfdelta = 0; 3325 dd->int_counter = 0; /* so we check interrupts work again */ 3326 3327 /* 3328 * Keep chip from being accessed until we are ready. Use 3329 * writeq() directly, to allow the write even though QIB_PRESENT 3330 * isn't set. 3331 */ 3332 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); 3333 dd->flags |= QIB_DOING_RESET; 3334 val = dd->control | QLOGIC_IB_C_RESET; 3335 writeq(val, &dd->kregbase[kr_control]); 3336 3337 for (i = 1; i <= 5; i++) { 3338 /* 3339 * Allow MBIST, etc. to complete; longer on each retry. 3340 * We sometimes get machine checks from bus timeout if no 3341 * response, so for now, make it *really* long. 3342 */ 3343 msleep(1000 + (1 + i) * 3000); 3344 3345 qib_pcie_reenable(dd, cmdval, int_line, clinesz); 3346 3347 /* 3348 * Use readq directly, so we don't need to mark it as PRESENT 3349 * until we get a successful indication that all is well. 3350 */ 3351 val = readq(&dd->kregbase[kr_revision]); 3352 if (val == dd->revision) 3353 break; 3354 if (i == 5) { 3355 qib_dev_err(dd, "Failed to initialize after reset, " 3356 "unusable\n"); 3357 ret = 0; 3358 goto bail; 3359 } 3360 } 3361 3362 dd->flags |= QIB_PRESENT; /* it's back */ 3363 3364 if (msix_entries) { 3365 /* restore the MSIx vector address and data if saved above */ 3366 for (i = 0; i < msix_entries; i++) { 3367 dd->cspec->msix_entries[i].entry = i; 3368 if (!msix_vecsave || !msix_vecsave[2 * i]) 3369 continue; 3370 qib_write_kreg(dd, 2 * i + 3371 (QIB_7322_MsixTable_OFFS / sizeof(u64)), 3372 msix_vecsave[2 * i]); 3373 qib_write_kreg(dd, 1 + 2 * i + 3374 (QIB_7322_MsixTable_OFFS / sizeof(u64)), 3375 msix_vecsave[1 + 2 * i]); 3376 } 3377 } 3378 3379 /* initialize the remaining registers. */ 3380 for (i = 0; i < dd->num_pports; ++i) 3381 write_7322_init_portregs(&dd->pport[i]); 3382 write_7322_initregs(dd); 3383 3384 if (qib_pcie_params(dd, dd->lbus_width, 3385 &dd->cspec->num_msix_entries, 3386 dd->cspec->msix_entries)) 3387 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; " 3388 "continuing anyway\n"); 3389 3390 qib_setup_7322_interrupt(dd, 1); 3391 3392 for (i = 0; i < dd->num_pports; ++i) { 3393 struct qib_pportdata *ppd = &dd->pport[i]; 3394 3395 spin_lock_irqsave(&ppd->lflags_lock, flags); 3396 ppd->lflags |= QIBL_IB_FORCE_NOTIFY; 3397 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 3398 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 3399 } 3400 3401 bail: 3402 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ 3403 kfree(msix_vecsave); 3404 return ret; 3405 } 3406 3407 /** 3408 * qib_7322_put_tid - write a TID to the chip 3409 * @dd: the qlogic_ib device 3410 * @tidptr: pointer to the expected TID (in chip) to update 3411 * @tidtype: 0 for eager, 1 for expected 3412 * @pa: physical address of in memory buffer; tidinvalid if freeing 3413 */ 3414 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, 3415 u32 type, unsigned long pa) 3416 { 3417 if (!(dd->flags & QIB_PRESENT)) 3418 return; 3419 if (pa != dd->tidinvalid) { 3420 u64 chippa = pa >> IBA7322_TID_PA_SHIFT; 3421 3422 /* paranoia checks */ 3423 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) { 3424 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", 3425 pa); 3426 return; 3427 } 3428 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) { 3429 qib_dev_err(dd, "Physical page address 0x%lx " 3430 "larger than supported\n", pa); 3431 return; 3432 } 3433 3434 if (type == RCVHQ_RCV_TYPE_EAGER) 3435 chippa |= dd->tidtemplate; 3436 else /* for now, always full 4KB page */ 3437 chippa |= IBA7322_TID_SZ_4K; 3438 pa = chippa; 3439 } 3440 writeq(pa, tidptr); 3441 mmiowb(); 3442 } 3443 3444 /** 3445 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager 3446 * @dd: the qlogic_ib device 3447 * @ctxt: the ctxt 3448 * 3449 * clear all TID entries for a ctxt, expected and eager. 3450 * Used from qib_close(). 3451 */ 3452 static void qib_7322_clear_tids(struct qib_devdata *dd, 3453 struct qib_ctxtdata *rcd) 3454 { 3455 u64 __iomem *tidbase; 3456 unsigned long tidinv; 3457 u32 ctxt; 3458 int i; 3459 3460 if (!dd->kregbase || !rcd) 3461 return; 3462 3463 ctxt = rcd->ctxt; 3464 3465 tidinv = dd->tidinvalid; 3466 tidbase = (u64 __iomem *) 3467 ((char __iomem *) dd->kregbase + 3468 dd->rcvtidbase + 3469 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); 3470 3471 for (i = 0; i < dd->rcvtidcnt; i++) 3472 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, 3473 tidinv); 3474 3475 tidbase = (u64 __iomem *) 3476 ((char __iomem *) dd->kregbase + 3477 dd->rcvegrbase + 3478 rcd->rcvegr_tid_base * sizeof(*tidbase)); 3479 3480 for (i = 0; i < rcd->rcvegrcnt; i++) 3481 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, 3482 tidinv); 3483 } 3484 3485 /** 3486 * qib_7322_tidtemplate - setup constants for TID updates 3487 * @dd: the qlogic_ib device 3488 * 3489 * We setup stuff that we use a lot, to avoid calculating each time 3490 */ 3491 static void qib_7322_tidtemplate(struct qib_devdata *dd) 3492 { 3493 /* 3494 * For now, we always allocate 4KB buffers (at init) so we can 3495 * receive max size packets. We may want a module parameter to 3496 * specify 2KB or 4KB and/or make it per port instead of per device 3497 * for those who want to reduce memory footprint. Note that the 3498 * rcvhdrentsize size must be large enough to hold the largest 3499 * IB header (currently 96 bytes) that we expect to handle (plus of 3500 * course the 2 dwords of RHF). 3501 */ 3502 if (dd->rcvegrbufsize == 2048) 3503 dd->tidtemplate = IBA7322_TID_SZ_2K; 3504 else if (dd->rcvegrbufsize == 4096) 3505 dd->tidtemplate = IBA7322_TID_SZ_4K; 3506 dd->tidinvalid = 0; 3507 } 3508 3509 /** 3510 * qib_init_7322_get_base_info - set chip-specific flags for user code 3511 * @rcd: the qlogic_ib ctxt 3512 * @kbase: qib_base_info pointer 3513 * 3514 * We set the PCIE flag because the lower bandwidth on PCIe vs 3515 * HyperTransport can affect some user packet algorithims. 3516 */ 3517 3518 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd, 3519 struct qib_base_info *kinfo) 3520 { 3521 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP | 3522 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL | 3523 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA; 3524 if (rcd->dd->cspec->r1) 3525 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK; 3526 if (rcd->dd->flags & QIB_USE_SPCL_TRIG) 3527 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER; 3528 3529 return 0; 3530 } 3531 3532 static struct qib_message_header * 3533 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) 3534 { 3535 u32 offset = qib_hdrget_offset(rhf_addr); 3536 3537 return (struct qib_message_header *) 3538 (rhf_addr - dd->rhf_offset + offset); 3539 } 3540 3541 /* 3542 * Configure number of contexts. 3543 */ 3544 static void qib_7322_config_ctxts(struct qib_devdata *dd) 3545 { 3546 unsigned long flags; 3547 u32 nchipctxts; 3548 3549 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); 3550 dd->cspec->numctxts = nchipctxts; 3551 if (qib_n_krcv_queues > 1 && dd->num_pports) { 3552 dd->first_user_ctxt = NUM_IB_PORTS + 3553 (qib_n_krcv_queues - 1) * dd->num_pports; 3554 if (dd->first_user_ctxt > nchipctxts) 3555 dd->first_user_ctxt = nchipctxts; 3556 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; 3557 } else { 3558 dd->first_user_ctxt = NUM_IB_PORTS; 3559 dd->n_krcv_queues = 1; 3560 } 3561 3562 if (!qib_cfgctxts) { 3563 int nctxts = dd->first_user_ctxt + num_online_cpus(); 3564 3565 if (nctxts <= 6) 3566 dd->ctxtcnt = 6; 3567 else if (nctxts <= 10) 3568 dd->ctxtcnt = 10; 3569 else if (nctxts <= nchipctxts) 3570 dd->ctxtcnt = nchipctxts; 3571 } else if (qib_cfgctxts < dd->num_pports) 3572 dd->ctxtcnt = dd->num_pports; 3573 else if (qib_cfgctxts <= nchipctxts) 3574 dd->ctxtcnt = qib_cfgctxts; 3575 if (!dd->ctxtcnt) /* none of the above, set to max */ 3576 dd->ctxtcnt = nchipctxts; 3577 3578 /* 3579 * Chip can be configured for 6, 10, or 18 ctxts, and choice 3580 * affects number of eager TIDs per ctxt (1K, 2K, 4K). 3581 * Lock to be paranoid about later motion, etc. 3582 */ 3583 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 3584 if (dd->ctxtcnt > 10) 3585 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); 3586 else if (dd->ctxtcnt > 6) 3587 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); 3588 /* else configure for default 6 receive ctxts */ 3589 3590 /* The XRC opcode is 5. */ 3591 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); 3592 3593 /* 3594 * RcvCtrl *must* be written here so that the 3595 * chip understands how to change rcvegrcnt below. 3596 */ 3597 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 3598 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 3599 3600 /* kr_rcvegrcnt changes based on the number of contexts enabled */ 3601 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); 3602 if (qib_rcvhdrcnt) 3603 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); 3604 else 3605 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, 3606 dd->num_pports > 1 ? 1024U : 2048U); 3607 } 3608 3609 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) 3610 { 3611 3612 int lsb, ret = 0; 3613 u64 maskr; /* right-justified mask */ 3614 3615 switch (which) { 3616 3617 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */ 3618 ret = ppd->link_width_enabled; 3619 goto done; 3620 3621 case QIB_IB_CFG_LWID: /* Get currently active Link-width */ 3622 ret = ppd->link_width_active; 3623 goto done; 3624 3625 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */ 3626 ret = ppd->link_speed_enabled; 3627 goto done; 3628 3629 case QIB_IB_CFG_SPD: /* Get current Link spd */ 3630 ret = ppd->link_speed_active; 3631 goto done; 3632 3633 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */ 3634 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3635 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3636 break; 3637 3638 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */ 3639 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3640 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3641 break; 3642 3643 case QIB_IB_CFG_LINKLATENCY: 3644 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) & 3645 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency); 3646 goto done; 3647 3648 case QIB_IB_CFG_OP_VLS: 3649 ret = ppd->vls_operational; 3650 goto done; 3651 3652 case QIB_IB_CFG_VL_HIGH_CAP: 3653 ret = 16; 3654 goto done; 3655 3656 case QIB_IB_CFG_VL_LOW_CAP: 3657 ret = 16; 3658 goto done; 3659 3660 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 3661 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3662 OverrunThreshold); 3663 goto done; 3664 3665 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 3666 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3667 PhyerrThreshold); 3668 goto done; 3669 3670 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 3671 /* will only take effect when the link state changes */ 3672 ret = (ppd->cpspec->ibcctrl_a & 3673 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ? 3674 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL; 3675 goto done; 3676 3677 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */ 3678 lsb = IBA7322_IBC_HRTBT_LSB; 3679 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ 3680 break; 3681 3682 case QIB_IB_CFG_PMA_TICKS: 3683 /* 3684 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs 3685 * Since the clock is always 250MHz, the value is 3, 1 or 0. 3686 */ 3687 if (ppd->link_speed_active == QIB_IB_QDR) 3688 ret = 3; 3689 else if (ppd->link_speed_active == QIB_IB_DDR) 3690 ret = 1; 3691 else 3692 ret = 0; 3693 goto done; 3694 3695 default: 3696 ret = -EINVAL; 3697 goto done; 3698 } 3699 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr); 3700 done: 3701 return ret; 3702 } 3703 3704 /* 3705 * Below again cribbed liberally from older version. Do not lean 3706 * heavily on it. 3707 */ 3708 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB 3709 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \ 3710 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16)) 3711 3712 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) 3713 { 3714 struct qib_devdata *dd = ppd->dd; 3715 u64 maskr; /* right-justified mask */ 3716 int lsb, ret = 0; 3717 u16 lcmd, licmd; 3718 unsigned long flags; 3719 3720 switch (which) { 3721 case QIB_IB_CFG_LIDLMC: 3722 /* 3723 * Set LID and LMC. Combined to avoid possible hazard 3724 * caller puts LMC in 16MSbits, DLID in 16LSbits of val 3725 */ 3726 lsb = IBA7322_IBC_DLIDLMC_SHIFT; 3727 maskr = IBA7322_IBC_DLIDLMC_MASK; 3728 /* 3729 * For header-checking, the SLID in the packet will 3730 * be masked with SendIBSLMCMask, and compared 3731 * with SendIBSLIDAssignMask. Make sure we do not 3732 * set any bits not covered by the mask, or we get 3733 * false-positives. 3734 */ 3735 qib_write_kreg_port(ppd, krp_sendslid, 3736 val & (val >> 16) & SendIBSLIDAssignMask); 3737 qib_write_kreg_port(ppd, krp_sendslidmask, 3738 (val >> 16) & SendIBSLMCMask); 3739 break; 3740 3741 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */ 3742 ppd->link_width_enabled = val; 3743 /* convert IB value to chip register value */ 3744 if (val == IB_WIDTH_1X) 3745 val = 0; 3746 else if (val == IB_WIDTH_4X) 3747 val = 1; 3748 else 3749 val = 3; 3750 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS); 3751 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS); 3752 break; 3753 3754 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */ 3755 /* 3756 * As with width, only write the actual register if the 3757 * link is currently down, otherwise takes effect on next 3758 * link change. Since setting is being explicitly requested 3759 * (via MAD or sysfs), clear autoneg failure status if speed 3760 * autoneg is enabled. 3761 */ 3762 ppd->link_speed_enabled = val; 3763 val <<= IBA7322_IBC_SPEED_LSB; 3764 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK | 3765 IBA7322_IBC_MAX_SPEED_MASK; 3766 if (val & (val - 1)) { 3767 /* Muliple speeds enabled */ 3768 val |= IBA7322_IBC_IBTA_1_2_MASK | 3769 IBA7322_IBC_MAX_SPEED_MASK; 3770 spin_lock_irqsave(&ppd->lflags_lock, flags); 3771 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 3772 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 3773 } else if (val & IBA7322_IBC_SPEED_QDR) 3774 val |= IBA7322_IBC_IBTA_1_2_MASK; 3775 /* IBTA 1.2 mode + min/max + speed bits are contiguous */ 3776 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE); 3777 break; 3778 3779 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */ 3780 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3781 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP); 3782 break; 3783 3784 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */ 3785 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3786 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); 3787 break; 3788 3789 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 3790 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3791 OverrunThreshold); 3792 if (maskr != val) { 3793 ppd->cpspec->ibcctrl_a &= 3794 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold); 3795 ppd->cpspec->ibcctrl_a |= (u64) val << 3796 SYM_LSB(IBCCtrlA_0, OverrunThreshold); 3797 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3798 ppd->cpspec->ibcctrl_a); 3799 qib_write_kreg(dd, kr_scratch, 0ULL); 3800 } 3801 goto bail; 3802 3803 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 3804 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, 3805 PhyerrThreshold); 3806 if (maskr != val) { 3807 ppd->cpspec->ibcctrl_a &= 3808 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold); 3809 ppd->cpspec->ibcctrl_a |= (u64) val << 3810 SYM_LSB(IBCCtrlA_0, PhyerrThreshold); 3811 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3812 ppd->cpspec->ibcctrl_a); 3813 qib_write_kreg(dd, kr_scratch, 0ULL); 3814 } 3815 goto bail; 3816 3817 case QIB_IB_CFG_PKEYS: /* update pkeys */ 3818 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | 3819 ((u64) ppd->pkeys[2] << 32) | 3820 ((u64) ppd->pkeys[3] << 48); 3821 qib_write_kreg_port(ppd, krp_partitionkey, maskr); 3822 goto bail; 3823 3824 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 3825 /* will only take effect when the link state changes */ 3826 if (val == IB_LINKINITCMD_POLL) 3827 ppd->cpspec->ibcctrl_a &= 3828 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); 3829 else /* SLEEP */ 3830 ppd->cpspec->ibcctrl_a |= 3831 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState); 3832 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 3833 qib_write_kreg(dd, kr_scratch, 0ULL); 3834 goto bail; 3835 3836 case QIB_IB_CFG_MTU: /* update the MTU in IBC */ 3837 /* 3838 * Update our housekeeping variables, and set IBC max 3839 * size, same as init code; max IBC is max we allow in 3840 * buffer, less the qword pbc, plus 1 for ICRC, in dwords 3841 * Set even if it's unchanged, print debug message only 3842 * on changes. 3843 */ 3844 val = (ppd->ibmaxlen >> 2) + 1; 3845 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); 3846 ppd->cpspec->ibcctrl_a |= (u64)val << 3847 SYM_LSB(IBCCtrlA_0, MaxPktLen); 3848 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3849 ppd->cpspec->ibcctrl_a); 3850 qib_write_kreg(dd, kr_scratch, 0ULL); 3851 goto bail; 3852 3853 case QIB_IB_CFG_LSTATE: /* set the IB link state */ 3854 switch (val & 0xffff0000) { 3855 case IB_LINKCMD_DOWN: 3856 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN; 3857 ppd->cpspec->ibmalfusesnap = 1; 3858 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, 3859 crp_errlink); 3860 if (!ppd->cpspec->ibdeltainprog && 3861 qib_compat_ddr_negotiate) { 3862 ppd->cpspec->ibdeltainprog = 1; 3863 ppd->cpspec->ibsymsnap = 3864 read_7322_creg32_port(ppd, 3865 crp_ibsymbolerr); 3866 ppd->cpspec->iblnkerrsnap = 3867 read_7322_creg32_port(ppd, 3868 crp_iblinkerrrecov); 3869 } 3870 break; 3871 3872 case IB_LINKCMD_ARMED: 3873 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED; 3874 if (ppd->cpspec->ibmalfusesnap) { 3875 ppd->cpspec->ibmalfusesnap = 0; 3876 ppd->cpspec->ibmalfdelta += 3877 read_7322_creg32_port(ppd, 3878 crp_errlink) - 3879 ppd->cpspec->ibmalfsnap; 3880 } 3881 break; 3882 3883 case IB_LINKCMD_ACTIVE: 3884 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE; 3885 break; 3886 3887 default: 3888 ret = -EINVAL; 3889 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); 3890 goto bail; 3891 } 3892 switch (val & 0xffff) { 3893 case IB_LINKINITCMD_NOP: 3894 licmd = 0; 3895 break; 3896 3897 case IB_LINKINITCMD_POLL: 3898 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL; 3899 break; 3900 3901 case IB_LINKINITCMD_SLEEP: 3902 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP; 3903 break; 3904 3905 case IB_LINKINITCMD_DISABLE: 3906 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE; 3907 ppd->cpspec->chase_end = 0; 3908 /* 3909 * stop state chase counter and timer, if running. 3910 * wait forpending timer, but don't clear .data (ppd)! 3911 */ 3912 if (ppd->cpspec->chase_timer.expires) { 3913 del_timer_sync(&ppd->cpspec->chase_timer); 3914 ppd->cpspec->chase_timer.expires = 0; 3915 } 3916 break; 3917 3918 default: 3919 ret = -EINVAL; 3920 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", 3921 val & 0xffff); 3922 goto bail; 3923 } 3924 qib_set_ib_7322_lstate(ppd, lcmd, licmd); 3925 goto bail; 3926 3927 case QIB_IB_CFG_OP_VLS: 3928 if (ppd->vls_operational != val) { 3929 ppd->vls_operational = val; 3930 set_vls(ppd); 3931 } 3932 goto bail; 3933 3934 case QIB_IB_CFG_VL_HIGH_LIMIT: 3935 qib_write_kreg_port(ppd, krp_highprio_limit, val); 3936 goto bail; 3937 3938 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */ 3939 if (val > 3) { 3940 ret = -EINVAL; 3941 goto bail; 3942 } 3943 lsb = IBA7322_IBC_HRTBT_LSB; 3944 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */ 3945 break; 3946 3947 case QIB_IB_CFG_PORT: 3948 /* val is the port number of the switch we are connected to. */ 3949 if (ppd->dd->cspec->r1) { 3950 cancel_delayed_work(&ppd->cpspec->ipg_work); 3951 ppd->cpspec->ipg_tries = 0; 3952 } 3953 goto bail; 3954 3955 default: 3956 ret = -EINVAL; 3957 goto bail; 3958 } 3959 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb); 3960 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb); 3961 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 3962 qib_write_kreg(dd, kr_scratch, 0); 3963 bail: 3964 return ret; 3965 } 3966 3967 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what) 3968 { 3969 int ret = 0; 3970 u64 val, ctrlb; 3971 3972 /* only IBC loopback, may add serdes and xgxs loopbacks later */ 3973 if (!strncmp(what, "ibc", 3)) { 3974 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, 3975 Loopback); 3976 val = 0; /* disable heart beat, so link will come up */ 3977 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", 3978 ppd->dd->unit, ppd->port); 3979 } else if (!strncmp(what, "off", 3)) { 3980 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, 3981 Loopback); 3982 /* enable heart beat again */ 3983 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB; 3984 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback " 3985 "(normal)\n", ppd->dd->unit, ppd->port); 3986 } else 3987 ret = -EINVAL; 3988 if (!ret) { 3989 qib_write_kreg_port(ppd, krp_ibcctrl_a, 3990 ppd->cpspec->ibcctrl_a); 3991 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK 3992 << IBA7322_IBC_HRTBT_LSB); 3993 ppd->cpspec->ibcctrl_b = ctrlb | val; 3994 qib_write_kreg_port(ppd, krp_ibcctrl_b, 3995 ppd->cpspec->ibcctrl_b); 3996 qib_write_kreg(ppd->dd, kr_scratch, 0); 3997 } 3998 return ret; 3999 } 4000 4001 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno, 4002 struct ib_vl_weight_elem *vl) 4003 { 4004 unsigned i; 4005 4006 for (i = 0; i < 16; i++, regno++, vl++) { 4007 u32 val = qib_read_kreg_port(ppd, regno); 4008 4009 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & 4010 SYM_RMASK(LowPriority0_0, VirtualLane); 4011 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & 4012 SYM_RMASK(LowPriority0_0, Weight); 4013 } 4014 } 4015 4016 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno, 4017 struct ib_vl_weight_elem *vl) 4018 { 4019 unsigned i; 4020 4021 for (i = 0; i < 16; i++, regno++, vl++) { 4022 u64 val; 4023 4024 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) << 4025 SYM_LSB(LowPriority0_0, VirtualLane)) | 4026 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) << 4027 SYM_LSB(LowPriority0_0, Weight)); 4028 qib_write_kreg_port(ppd, regno, val); 4029 } 4030 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { 4031 struct qib_devdata *dd = ppd->dd; 4032 unsigned long flags; 4033 4034 spin_lock_irqsave(&dd->sendctrl_lock, flags); 4035 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); 4036 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 4037 qib_write_kreg(dd, kr_scratch, 0); 4038 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 4039 } 4040 } 4041 4042 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t) 4043 { 4044 switch (which) { 4045 case QIB_IB_TBL_VL_HIGH_ARB: 4046 get_vl_weights(ppd, krp_highprio_0, t); 4047 break; 4048 4049 case QIB_IB_TBL_VL_LOW_ARB: 4050 get_vl_weights(ppd, krp_lowprio_0, t); 4051 break; 4052 4053 default: 4054 return -EINVAL; 4055 } 4056 return 0; 4057 } 4058 4059 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t) 4060 { 4061 switch (which) { 4062 case QIB_IB_TBL_VL_HIGH_ARB: 4063 set_vl_weights(ppd, krp_highprio_0, t); 4064 break; 4065 4066 case QIB_IB_TBL_VL_LOW_ARB: 4067 set_vl_weights(ppd, krp_lowprio_0, t); 4068 break; 4069 4070 default: 4071 return -EINVAL; 4072 } 4073 return 0; 4074 } 4075 4076 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, 4077 u32 updegr, u32 egrhd, u32 npkts) 4078 { 4079 /* 4080 * Need to write timeout register before updating rcvhdrhead to ensure 4081 * that the timer is enabled on reception of a packet. 4082 */ 4083 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT) 4084 adjust_rcv_timeout(rcd, npkts); 4085 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4086 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4087 if (updegr) 4088 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); 4089 } 4090 4091 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd) 4092 { 4093 u32 head, tail; 4094 4095 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); 4096 if (rcd->rcvhdrtail_kvaddr) 4097 tail = qib_get_rcvhdrtail(rcd); 4098 else 4099 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); 4100 return head == tail; 4101 } 4102 4103 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \ 4104 QIB_RCVCTRL_CTXT_DIS | \ 4105 QIB_RCVCTRL_TIDFLOW_ENB | \ 4106 QIB_RCVCTRL_TIDFLOW_DIS | \ 4107 QIB_RCVCTRL_TAILUPD_ENB | \ 4108 QIB_RCVCTRL_TAILUPD_DIS | \ 4109 QIB_RCVCTRL_INTRAVAIL_ENB | \ 4110 QIB_RCVCTRL_INTRAVAIL_DIS | \ 4111 QIB_RCVCTRL_BP_ENB | \ 4112 QIB_RCVCTRL_BP_DIS) 4113 4114 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \ 4115 QIB_RCVCTRL_CTXT_DIS | \ 4116 QIB_RCVCTRL_PKEY_DIS | \ 4117 QIB_RCVCTRL_PKEY_ENB) 4118 4119 /* 4120 * Modify the RCVCTRL register in chip-specific way. This 4121 * is a function because bit positions and (future) register 4122 * location is chip-specifc, but the needed operations are 4123 * generic. <op> is a bit-mask because we often want to 4124 * do multiple modifications. 4125 */ 4126 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op, 4127 int ctxt) 4128 { 4129 struct qib_devdata *dd = ppd->dd; 4130 struct qib_ctxtdata *rcd; 4131 u64 mask, val; 4132 unsigned long flags; 4133 4134 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 4135 4136 if (op & QIB_RCVCTRL_TIDFLOW_ENB) 4137 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); 4138 if (op & QIB_RCVCTRL_TIDFLOW_DIS) 4139 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); 4140 if (op & QIB_RCVCTRL_TAILUPD_ENB) 4141 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); 4142 if (op & QIB_RCVCTRL_TAILUPD_DIS) 4143 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); 4144 if (op & QIB_RCVCTRL_PKEY_ENB) 4145 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); 4146 if (op & QIB_RCVCTRL_PKEY_DIS) 4147 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); 4148 if (ctxt < 0) { 4149 mask = (1ULL << dd->ctxtcnt) - 1; 4150 rcd = NULL; 4151 } else { 4152 mask = (1ULL << ctxt); 4153 rcd = dd->rcd[ctxt]; 4154 } 4155 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) { 4156 ppd->p_rcvctrl |= 4157 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); 4158 if (!(dd->flags & QIB_NODMA_RTAIL)) { 4159 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */ 4160 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); 4161 } 4162 /* Write these registers before the context is enabled. */ 4163 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 4164 rcd->rcvhdrqtailaddr_phys); 4165 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 4166 rcd->rcvhdrq_phys); 4167 rcd->seq_cnt = 1; 4168 } 4169 if (op & QIB_RCVCTRL_CTXT_DIS) 4170 ppd->p_rcvctrl &= 4171 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); 4172 if (op & QIB_RCVCTRL_BP_ENB) 4173 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); 4174 if (op & QIB_RCVCTRL_BP_DIS) 4175 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); 4176 if (op & QIB_RCVCTRL_INTRAVAIL_ENB) 4177 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); 4178 if (op & QIB_RCVCTRL_INTRAVAIL_DIS) 4179 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); 4180 /* 4181 * Decide which registers to write depending on the ops enabled. 4182 * Special case is "flush" (no bits set at all) 4183 * which needs to write both. 4184 */ 4185 if (op == 0 || (op & RCVCTRL_COMMON_MODS)) 4186 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 4187 if (op == 0 || (op & RCVCTRL_PORT_MODS)) 4188 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); 4189 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { 4190 /* 4191 * Init the context registers also; if we were 4192 * disabled, tail and head should both be zero 4193 * already from the enable, but since we don't 4194 * know, we have to do it explicitly. 4195 */ 4196 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); 4197 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); 4198 4199 /* be sure enabling write seen; hd/tl should be 0 */ 4200 (void) qib_read_kreg32(dd, kr_scratch); 4201 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); 4202 dd->rcd[ctxt]->head = val; 4203 /* If kctxt, interrupt on next receive. */ 4204 if (ctxt < dd->first_user_ctxt) 4205 val |= dd->rhdrhead_intr_off; 4206 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 4207 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && 4208 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { 4209 /* arm rcv interrupt */ 4210 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; 4211 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 4212 } 4213 if (op & QIB_RCVCTRL_CTXT_DIS) { 4214 unsigned f; 4215 4216 /* Now that the context is disabled, clear these registers. */ 4217 if (ctxt >= 0) { 4218 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); 4219 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); 4220 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) 4221 qib_write_ureg(dd, ur_rcvflowtable + f, 4222 TIDFLOW_ERRBITS, ctxt); 4223 } else { 4224 unsigned i; 4225 4226 for (i = 0; i < dd->cfgctxts; i++) { 4227 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, 4228 i, 0); 4229 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0); 4230 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++) 4231 qib_write_ureg(dd, ur_rcvflowtable + f, 4232 TIDFLOW_ERRBITS, i); 4233 } 4234 } 4235 } 4236 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 4237 } 4238 4239 /* 4240 * Modify the SENDCTRL register in chip-specific way. This 4241 * is a function where there are multiple such registers with 4242 * slightly different layouts. 4243 * The chip doesn't allow back-to-back sendctrl writes, so write 4244 * the scratch register after writing sendctrl. 4245 * 4246 * Which register is written depends on the operation. 4247 * Most operate on the common register, while 4248 * SEND_ENB and SEND_DIS operate on the per-port ones. 4249 * SEND_ENB is included in common because it can change SPCL_TRIG 4250 */ 4251 #define SENDCTRL_COMMON_MODS (\ 4252 QIB_SENDCTRL_CLEAR | \ 4253 QIB_SENDCTRL_AVAIL_DIS | \ 4254 QIB_SENDCTRL_AVAIL_ENB | \ 4255 QIB_SENDCTRL_AVAIL_BLIP | \ 4256 QIB_SENDCTRL_DISARM | \ 4257 QIB_SENDCTRL_DISARM_ALL | \ 4258 QIB_SENDCTRL_SEND_ENB) 4259 4260 #define SENDCTRL_PORT_MODS (\ 4261 QIB_SENDCTRL_CLEAR | \ 4262 QIB_SENDCTRL_SEND_ENB | \ 4263 QIB_SENDCTRL_SEND_DIS | \ 4264 QIB_SENDCTRL_FLUSH) 4265 4266 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op) 4267 { 4268 struct qib_devdata *dd = ppd->dd; 4269 u64 tmp_dd_sendctrl; 4270 unsigned long flags; 4271 4272 spin_lock_irqsave(&dd->sendctrl_lock, flags); 4273 4274 /* First the dd ones that are "sticky", saved in shadow */ 4275 if (op & QIB_SENDCTRL_CLEAR) 4276 dd->sendctrl = 0; 4277 if (op & QIB_SENDCTRL_AVAIL_DIS) 4278 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4279 else if (op & QIB_SENDCTRL_AVAIL_ENB) { 4280 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); 4281 if (dd->flags & QIB_USE_SPCL_TRIG) 4282 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); 4283 } 4284 4285 /* Then the ppd ones that are "sticky", saved in shadow */ 4286 if (op & QIB_SENDCTRL_SEND_DIS) 4287 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); 4288 else if (op & QIB_SENDCTRL_SEND_ENB) 4289 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); 4290 4291 if (op & QIB_SENDCTRL_DISARM_ALL) { 4292 u32 i, last; 4293 4294 tmp_dd_sendctrl = dd->sendctrl; 4295 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 4296 /* 4297 * Disarm any buffers that are not yet launched, 4298 * disabling updates until done. 4299 */ 4300 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4301 for (i = 0; i < last; i++) { 4302 qib_write_kreg(dd, kr_sendctrl, 4303 tmp_dd_sendctrl | 4304 SYM_MASK(SendCtrl, Disarm) | i); 4305 qib_write_kreg(dd, kr_scratch, 0); 4306 } 4307 } 4308 4309 if (op & QIB_SENDCTRL_FLUSH) { 4310 u64 tmp_ppd_sendctrl = ppd->p_sendctrl; 4311 4312 /* 4313 * Now drain all the fifos. The Abort bit should never be 4314 * needed, so for now, at least, we don't use it. 4315 */ 4316 tmp_ppd_sendctrl |= 4317 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) | 4318 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) | 4319 SYM_MASK(SendCtrl_0, TxeBypassIbc); 4320 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl); 4321 qib_write_kreg(dd, kr_scratch, 0); 4322 } 4323 4324 tmp_dd_sendctrl = dd->sendctrl; 4325 4326 if (op & QIB_SENDCTRL_DISARM) 4327 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | 4328 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) << 4329 SYM_LSB(SendCtrl, DisarmSendBuf)); 4330 if ((op & QIB_SENDCTRL_AVAIL_BLIP) && 4331 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) 4332 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); 4333 4334 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) { 4335 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); 4336 qib_write_kreg(dd, kr_scratch, 0); 4337 } 4338 4339 if (op == 0 || (op & SENDCTRL_PORT_MODS)) { 4340 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); 4341 qib_write_kreg(dd, kr_scratch, 0); 4342 } 4343 4344 if (op & QIB_SENDCTRL_AVAIL_BLIP) { 4345 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 4346 qib_write_kreg(dd, kr_scratch, 0); 4347 } 4348 4349 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 4350 4351 if (op & QIB_SENDCTRL_FLUSH) { 4352 u32 v; 4353 /* 4354 * ensure writes have hit chip, then do a few 4355 * more reads, to allow DMA of pioavail registers 4356 * to occur, so in-memory copy is in sync with 4357 * the chip. Not always safe to sleep. 4358 */ 4359 v = qib_read_kreg32(dd, kr_scratch); 4360 qib_write_kreg(dd, kr_scratch, v); 4361 v = qib_read_kreg32(dd, kr_scratch); 4362 qib_write_kreg(dd, kr_scratch, v); 4363 qib_read_kreg32(dd, kr_scratch); 4364 } 4365 } 4366 4367 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */ 4368 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */ 4369 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */ 4370 4371 /** 4372 * qib_portcntr_7322 - read a per-port chip counter 4373 * @ppd: the qlogic_ib pport 4374 * @creg: the counter to read (not a chip offset) 4375 */ 4376 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg) 4377 { 4378 struct qib_devdata *dd = ppd->dd; 4379 u64 ret = 0ULL; 4380 u16 creg; 4381 /* 0xffff for unimplemented or synthesized counters */ 4382 static const u32 xlator[] = { 4383 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG, 4384 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG, 4385 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount, 4386 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount, 4387 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount, 4388 [QIBPORTCNTR_SENDSTALL] = crp_sendstall, 4389 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG, 4390 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount, 4391 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount, 4392 [QIBPORTCNTR_RCVEBP] = crp_rcvebp, 4393 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl, 4394 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG, 4395 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */ 4396 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr, 4397 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr, 4398 [QIBPORTCNTR_ERRICRC] = crp_erricrc, 4399 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc, 4400 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc, 4401 [QIBPORTCNTR_BADFORMAT] = crp_badformat, 4402 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen, 4403 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr, 4404 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen, 4405 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl, 4406 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl, 4407 [QIBPORTCNTR_ERRLINK] = crp_errlink, 4408 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown, 4409 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov, 4410 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr, 4411 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt, 4412 [QIBPORTCNTR_ERRPKEY] = crp_errpkey, 4413 /* 4414 * the next 3 aren't really counters, but were implemented 4415 * as counters in older chips, so still get accessed as 4416 * though they were counters from this code. 4417 */ 4418 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval, 4419 [QIBPORTCNTR_PSSTART] = krp_psstart, 4420 [QIBPORTCNTR_PSSTAT] = krp_psstat, 4421 /* pseudo-counter, summed for all ports */ 4422 [QIBPORTCNTR_KHDROVFL] = 0xffff, 4423 }; 4424 4425 if (reg >= ARRAY_SIZE(xlator)) { 4426 qib_devinfo(ppd->dd->pcidev, 4427 "Unimplemented portcounter %u\n", reg); 4428 goto done; 4429 } 4430 creg = xlator[reg] & _PORT_CNTR_IDXMASK; 4431 4432 /* handle non-counters and special cases first */ 4433 if (reg == QIBPORTCNTR_KHDROVFL) { 4434 int i; 4435 4436 /* sum over all kernel contexts (skip if mini_init) */ 4437 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { 4438 struct qib_ctxtdata *rcd = dd->rcd[i]; 4439 4440 if (!rcd || rcd->ppd != ppd) 4441 continue; 4442 ret += read_7322_creg32(dd, cr_base_egrovfl + i); 4443 } 4444 goto done; 4445 } else if (reg == QIBPORTCNTR_RXDROPPKT) { 4446 /* 4447 * Used as part of the synthesis of port_rcv_errors 4448 * in the verbs code for IBTA counters. Not needed for 7322, 4449 * because all the errors are already counted by other cntrs. 4450 */ 4451 goto done; 4452 } else if (reg == QIBPORTCNTR_PSINTERVAL || 4453 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) { 4454 /* were counters in older chips, now per-port kernel regs */ 4455 ret = qib_read_kreg_port(ppd, creg); 4456 goto done; 4457 } 4458 4459 /* 4460 * Only fast increment counters are 64 bits; use 32 bit reads to 4461 * avoid two independent reads when on Opteron. 4462 */ 4463 if (xlator[reg] & _PORT_64BIT_FLAG) 4464 ret = read_7322_creg_port(ppd, creg); 4465 else 4466 ret = read_7322_creg32_port(ppd, creg); 4467 if (creg == crp_ibsymbolerr) { 4468 if (ppd->cpspec->ibdeltainprog) 4469 ret -= ret - ppd->cpspec->ibsymsnap; 4470 ret -= ppd->cpspec->ibsymdelta; 4471 } else if (creg == crp_iblinkerrrecov) { 4472 if (ppd->cpspec->ibdeltainprog) 4473 ret -= ret - ppd->cpspec->iblnkerrsnap; 4474 ret -= ppd->cpspec->iblnkerrdelta; 4475 } else if (creg == crp_errlink) 4476 ret -= ppd->cpspec->ibmalfdelta; 4477 else if (creg == crp_iblinkdown) 4478 ret += ppd->cpspec->iblnkdowndelta; 4479 done: 4480 return ret; 4481 } 4482 4483 /* 4484 * Device counter names (not port-specific), one line per stat, 4485 * single string. Used by utilities like ipathstats to print the stats 4486 * in a way which works for different versions of drivers, without changing 4487 * the utility. Names need to be 12 chars or less (w/o newline), for proper 4488 * display by utility. 4489 * Non-error counters are first. 4490 * Start of "error" conters is indicated by a leading "E " on the first 4491 * "error" counter, and doesn't count in label length. 4492 * The EgrOvfl list needs to be last so we truncate them at the configured 4493 * context count for the device. 4494 * cntr7322indices contains the corresponding register indices. 4495 */ 4496 static const char cntr7322names[] = 4497 "Interrupts\n" 4498 "HostBusStall\n" 4499 "E RxTIDFull\n" 4500 "RxTIDInvalid\n" 4501 "RxTIDFloDrop\n" /* 7322 only */ 4502 "Ctxt0EgrOvfl\n" 4503 "Ctxt1EgrOvfl\n" 4504 "Ctxt2EgrOvfl\n" 4505 "Ctxt3EgrOvfl\n" 4506 "Ctxt4EgrOvfl\n" 4507 "Ctxt5EgrOvfl\n" 4508 "Ctxt6EgrOvfl\n" 4509 "Ctxt7EgrOvfl\n" 4510 "Ctxt8EgrOvfl\n" 4511 "Ctxt9EgrOvfl\n" 4512 "Ctx10EgrOvfl\n" 4513 "Ctx11EgrOvfl\n" 4514 "Ctx12EgrOvfl\n" 4515 "Ctx13EgrOvfl\n" 4516 "Ctx14EgrOvfl\n" 4517 "Ctx15EgrOvfl\n" 4518 "Ctx16EgrOvfl\n" 4519 "Ctx17EgrOvfl\n" 4520 ; 4521 4522 static const u32 cntr7322indices[] = { 4523 cr_lbint | _PORT_64BIT_FLAG, 4524 cr_lbstall | _PORT_64BIT_FLAG, 4525 cr_tidfull, 4526 cr_tidinvalid, 4527 cr_rxtidflowdrop, 4528 cr_base_egrovfl + 0, 4529 cr_base_egrovfl + 1, 4530 cr_base_egrovfl + 2, 4531 cr_base_egrovfl + 3, 4532 cr_base_egrovfl + 4, 4533 cr_base_egrovfl + 5, 4534 cr_base_egrovfl + 6, 4535 cr_base_egrovfl + 7, 4536 cr_base_egrovfl + 8, 4537 cr_base_egrovfl + 9, 4538 cr_base_egrovfl + 10, 4539 cr_base_egrovfl + 11, 4540 cr_base_egrovfl + 12, 4541 cr_base_egrovfl + 13, 4542 cr_base_egrovfl + 14, 4543 cr_base_egrovfl + 15, 4544 cr_base_egrovfl + 16, 4545 cr_base_egrovfl + 17, 4546 }; 4547 4548 /* 4549 * same as cntr7322names and cntr7322indices, but for port-specific counters. 4550 * portcntr7322indices is somewhat complicated by some registers needing 4551 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG 4552 */ 4553 static const char portcntr7322names[] = 4554 "TxPkt\n" 4555 "TxFlowPkt\n" 4556 "TxWords\n" 4557 "RxPkt\n" 4558 "RxFlowPkt\n" 4559 "RxWords\n" 4560 "TxFlowStall\n" 4561 "TxDmaDesc\n" /* 7220 and 7322-only */ 4562 "E RxDlidFltr\n" /* 7220 and 7322-only */ 4563 "IBStatusChng\n" 4564 "IBLinkDown\n" 4565 "IBLnkRecov\n" 4566 "IBRxLinkErr\n" 4567 "IBSymbolErr\n" 4568 "RxLLIErr\n" 4569 "RxBadFormat\n" 4570 "RxBadLen\n" 4571 "RxBufOvrfl\n" 4572 "RxEBP\n" 4573 "RxFlowCtlErr\n" 4574 "RxICRCerr\n" 4575 "RxLPCRCerr\n" 4576 "RxVCRCerr\n" 4577 "RxInvalLen\n" 4578 "RxInvalPKey\n" 4579 "RxPktDropped\n" 4580 "TxBadLength\n" 4581 "TxDropped\n" 4582 "TxInvalLen\n" 4583 "TxUnderrun\n" 4584 "TxUnsupVL\n" 4585 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */ 4586 "RxVL15Drop\n" 4587 "RxVlErr\n" 4588 "XcessBufOvfl\n" 4589 "RxQPBadCtxt\n" /* 7322-only from here down */ 4590 "TXBadHeader\n" 4591 ; 4592 4593 static const u32 portcntr7322indices[] = { 4594 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG, 4595 crp_pktsendflow, 4596 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG, 4597 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG, 4598 crp_pktrcvflowctrl, 4599 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG, 4600 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG, 4601 crp_txsdmadesc | _PORT_64BIT_FLAG, 4602 crp_rxdlidfltr, 4603 crp_ibstatuschange, 4604 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG, 4605 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG, 4606 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG, 4607 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG, 4608 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG, 4609 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG, 4610 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG, 4611 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG, 4612 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG, 4613 crp_rcvflowctrlviol, 4614 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG, 4615 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG, 4616 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG, 4617 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG, 4618 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG, 4619 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG, 4620 crp_txminmaxlenerr, 4621 crp_txdroppedpkt, 4622 crp_txlenerr, 4623 crp_txunderrun, 4624 crp_txunsupvl, 4625 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG, 4626 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG, 4627 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG, 4628 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG, 4629 crp_rxqpinvalidctxt, 4630 crp_txhdrerr, 4631 }; 4632 4633 /* do all the setup to make the counter reads efficient later */ 4634 static void init_7322_cntrnames(struct qib_devdata *dd) 4635 { 4636 int i, j = 0; 4637 char *s; 4638 4639 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; 4640 i++) { 4641 /* we always have at least one counter before the egrovfl */ 4642 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12)) 4643 j = 1; 4644 s = strchr(s + 1, '\n'); 4645 if (s && j) 4646 j++; 4647 } 4648 dd->cspec->ncntrs = i; 4649 if (!s) 4650 /* full list; size is without terminating null */ 4651 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; 4652 else 4653 dd->cspec->cntrnamelen = 1 + s - cntr7322names; 4654 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs 4655 * sizeof(u64), GFP_KERNEL); 4656 if (!dd->cspec->cntrs) 4657 qib_dev_err(dd, "Failed allocation for counters\n"); 4658 4659 for (i = 0, s = (char *)portcntr7322names; s; i++) 4660 s = strchr(s + 1, '\n'); 4661 dd->cspec->nportcntrs = i - 1; 4662 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; 4663 for (i = 0; i < dd->num_pports; ++i) { 4664 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs 4665 * sizeof(u64), GFP_KERNEL); 4666 if (!dd->pport[i].cpspec->portcntrs) 4667 qib_dev_err(dd, "Failed allocation for" 4668 " portcounters\n"); 4669 } 4670 } 4671 4672 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, 4673 u64 **cntrp) 4674 { 4675 u32 ret; 4676 4677 if (namep) { 4678 ret = dd->cspec->cntrnamelen; 4679 if (pos >= ret) 4680 ret = 0; /* final read after getting everything */ 4681 else 4682 *namep = (char *) cntr7322names; 4683 } else { 4684 u64 *cntr = dd->cspec->cntrs; 4685 int i; 4686 4687 ret = dd->cspec->ncntrs * sizeof(u64); 4688 if (!cntr || pos >= ret) { 4689 /* everything read, or couldn't get memory */ 4690 ret = 0; 4691 goto done; 4692 } 4693 *cntrp = cntr; 4694 for (i = 0; i < dd->cspec->ncntrs; i++) 4695 if (cntr7322indices[i] & _PORT_64BIT_FLAG) 4696 *cntr++ = read_7322_creg(dd, 4697 cntr7322indices[i] & 4698 _PORT_CNTR_IDXMASK); 4699 else 4700 *cntr++ = read_7322_creg32(dd, 4701 cntr7322indices[i]); 4702 } 4703 done: 4704 return ret; 4705 } 4706 4707 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, 4708 char **namep, u64 **cntrp) 4709 { 4710 u32 ret; 4711 4712 if (namep) { 4713 ret = dd->cspec->portcntrnamelen; 4714 if (pos >= ret) 4715 ret = 0; /* final read after getting everything */ 4716 else 4717 *namep = (char *)portcntr7322names; 4718 } else { 4719 struct qib_pportdata *ppd = &dd->pport[port]; 4720 u64 *cntr = ppd->cpspec->portcntrs; 4721 int i; 4722 4723 ret = dd->cspec->nportcntrs * sizeof(u64); 4724 if (!cntr || pos >= ret) { 4725 /* everything read, or couldn't get memory */ 4726 ret = 0; 4727 goto done; 4728 } 4729 *cntrp = cntr; 4730 for (i = 0; i < dd->cspec->nportcntrs; i++) { 4731 if (portcntr7322indices[i] & _PORT_VIRT_FLAG) 4732 *cntr++ = qib_portcntr_7322(ppd, 4733 portcntr7322indices[i] & 4734 _PORT_CNTR_IDXMASK); 4735 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG) 4736 *cntr++ = read_7322_creg_port(ppd, 4737 portcntr7322indices[i] & 4738 _PORT_CNTR_IDXMASK); 4739 else 4740 *cntr++ = read_7322_creg32_port(ppd, 4741 portcntr7322indices[i]); 4742 } 4743 } 4744 done: 4745 return ret; 4746 } 4747 4748 /** 4749 * qib_get_7322_faststats - get word counters from chip before they overflow 4750 * @opaque - contains a pointer to the qlogic_ib device qib_devdata 4751 * 4752 * VESTIGIAL IBA7322 has no "small fast counters", so the only 4753 * real purpose of this function is to maintain the notion of 4754 * "active time", which in turn is only logged into the eeprom, 4755 * which we don;t have, yet, for 7322-based boards. 4756 * 4757 * called from add_timer 4758 */ 4759 static void qib_get_7322_faststats(unsigned long opaque) 4760 { 4761 struct qib_devdata *dd = (struct qib_devdata *) opaque; 4762 struct qib_pportdata *ppd; 4763 unsigned long flags; 4764 u64 traffic_wds; 4765 int pidx; 4766 4767 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 4768 ppd = dd->pport + pidx; 4769 4770 /* 4771 * If port isn't enabled or not operational ports, or 4772 * diags is running (can cause memory diags to fail) 4773 * skip this port this time. 4774 */ 4775 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) 4776 || dd->diag_client) 4777 continue; 4778 4779 /* 4780 * Maintain an activity timer, based on traffic 4781 * exceeding a threshold, so we need to check the word-counts 4782 * even if they are 64-bit. 4783 */ 4784 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) + 4785 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND); 4786 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); 4787 traffic_wds -= ppd->dd->traffic_wds; 4788 ppd->dd->traffic_wds += traffic_wds; 4789 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD) 4790 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time); 4791 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); 4792 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active & 4793 QIB_IB_QDR) && 4794 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | 4795 QIBL_LINKACTIVE)) && 4796 ppd->cpspec->qdr_dfe_time && 4797 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) { 4798 ppd->cpspec->qdr_dfe_on = 0; 4799 4800 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 4801 ppd->dd->cspec->r1 ? 4802 QDR_STATIC_ADAPT_INIT_R1 : 4803 QDR_STATIC_ADAPT_INIT); 4804 force_h1(ppd); 4805 } 4806 } 4807 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); 4808 } 4809 4810 /* 4811 * If we were using MSIx, try to fallback to INTx. 4812 */ 4813 static int qib_7322_intr_fallback(struct qib_devdata *dd) 4814 { 4815 if (!dd->cspec->num_msix_entries) 4816 return 0; /* already using INTx */ 4817 4818 qib_devinfo(dd->pcidev, "MSIx interrupt not detected," 4819 " trying INTx interrupts\n"); 4820 qib_7322_nomsix(dd); 4821 qib_enable_intx(dd->pcidev); 4822 qib_setup_7322_interrupt(dd, 0); 4823 return 1; 4824 } 4825 4826 /* 4827 * Reset the XGXS (between serdes and IBC). Slightly less intrusive 4828 * than resetting the IBC or external link state, and useful in some 4829 * cases to cause some retraining. To do this right, we reset IBC 4830 * as well, then return to previous state (which may be still in reset) 4831 * NOTE: some callers of this "know" this writes the current value 4832 * of cpspec->ibcctrl_a as part of it's operation, so if that changes, 4833 * check all callers. 4834 */ 4835 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd) 4836 { 4837 u64 val; 4838 struct qib_devdata *dd = ppd->dd; 4839 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) | 4840 SYM_MASK(IBPCSConfig_0, xcv_treset) | 4841 SYM_MASK(IBPCSConfig_0, tx_rx_reset); 4842 4843 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig); 4844 qib_write_kreg(dd, kr_hwerrmask, 4845 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); 4846 qib_write_kreg_port(ppd, krp_ibcctrl_a, 4847 ppd->cpspec->ibcctrl_a & 4848 ~SYM_MASK(IBCCtrlA_0, IBLinkEn)); 4849 4850 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits); 4851 qib_read_kreg32(dd, kr_scratch); 4852 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits); 4853 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); 4854 qib_write_kreg(dd, kr_scratch, 0ULL); 4855 qib_write_kreg(dd, kr_hwerrclear, 4856 SYM_MASK(HwErrClear, statusValidNoEopClear)); 4857 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 4858 } 4859 4860 /* 4861 * This code for non-IBTA-compliant IB speed negotiation is only known to 4862 * work for the SDR to DDR transition, and only between an HCA and a switch 4863 * with recent firmware. It is based on observed heuristics, rather than 4864 * actual knowledge of the non-compliant speed negotiation. 4865 * It has a number of hard-coded fields, since the hope is to rewrite this 4866 * when a spec is available on how the negoation is intended to work. 4867 */ 4868 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr, 4869 u32 dcnt, u32 *data) 4870 { 4871 int i; 4872 u64 pbc; 4873 u32 __iomem *piobuf; 4874 u32 pnum, control, len; 4875 struct qib_devdata *dd = ppd->dd; 4876 4877 i = 0; 4878 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */ 4879 control = qib_7322_setpbc_control(ppd, len, 0, 15); 4880 pbc = ((u64) control << 32) | len; 4881 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) { 4882 if (i++ > 15) 4883 return; 4884 udelay(2); 4885 } 4886 /* disable header check on this packet, since it can't be valid */ 4887 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); 4888 writeq(pbc, piobuf); 4889 qib_flush_wc(); 4890 qib_pio_copy(piobuf + 2, hdr, 7); 4891 qib_pio_copy(piobuf + 9, data, dcnt); 4892 if (dd->flags & QIB_USE_SPCL_TRIG) { 4893 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; 4894 4895 qib_flush_wc(); 4896 __raw_writel(0xaebecede, piobuf + spcl_off); 4897 } 4898 qib_flush_wc(); 4899 qib_sendbuf_done(dd, pnum); 4900 /* and re-enable hdr check */ 4901 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); 4902 } 4903 4904 /* 4905 * _start packet gets sent twice at start, _done gets sent twice at end 4906 */ 4907 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which) 4908 { 4909 struct qib_devdata *dd = ppd->dd; 4910 static u32 swapped; 4911 u32 dw, i, hcnt, dcnt, *data; 4912 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba }; 4913 static u32 madpayload_start[0x40] = { 4914 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, 4915 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 4916 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */ 4917 }; 4918 static u32 madpayload_done[0x40] = { 4919 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0, 4920 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 4921 0x40000001, 0x1388, 0x15e, /* rest 0's */ 4922 }; 4923 4924 dcnt = ARRAY_SIZE(madpayload_start); 4925 hcnt = ARRAY_SIZE(hdr); 4926 if (!swapped) { 4927 /* for maintainability, do it at runtime */ 4928 for (i = 0; i < hcnt; i++) { 4929 dw = (__force u32) cpu_to_be32(hdr[i]); 4930 hdr[i] = dw; 4931 } 4932 for (i = 0; i < dcnt; i++) { 4933 dw = (__force u32) cpu_to_be32(madpayload_start[i]); 4934 madpayload_start[i] = dw; 4935 dw = (__force u32) cpu_to_be32(madpayload_done[i]); 4936 madpayload_done[i] = dw; 4937 } 4938 swapped = 1; 4939 } 4940 4941 data = which ? madpayload_done : madpayload_start; 4942 4943 autoneg_7322_sendpkt(ppd, hdr, dcnt, data); 4944 qib_read_kreg64(dd, kr_scratch); 4945 udelay(2); 4946 autoneg_7322_sendpkt(ppd, hdr, dcnt, data); 4947 qib_read_kreg64(dd, kr_scratch); 4948 udelay(2); 4949 } 4950 4951 /* 4952 * Do the absolute minimum to cause an IB speed change, and make it 4953 * ready, but don't actually trigger the change. The caller will 4954 * do that when ready (if link is in Polling training state, it will 4955 * happen immediately, otherwise when link next goes down) 4956 * 4957 * This routine should only be used as part of the DDR autonegotation 4958 * code for devices that are not compliant with IB 1.2 (or code that 4959 * fixes things up for same). 4960 * 4961 * When link has gone down, and autoneg enabled, or autoneg has 4962 * failed and we give up until next time we set both speeds, and 4963 * then we want IBTA enabled as well as "use max enabled speed. 4964 */ 4965 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed) 4966 { 4967 u64 newctrlb; 4968 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK | 4969 IBA7322_IBC_IBTA_1_2_MASK | 4970 IBA7322_IBC_MAX_SPEED_MASK); 4971 4972 if (speed & (speed - 1)) /* multiple speeds */ 4973 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) | 4974 IBA7322_IBC_IBTA_1_2_MASK | 4975 IBA7322_IBC_MAX_SPEED_MASK; 4976 else 4977 newctrlb |= speed == QIB_IB_QDR ? 4978 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK : 4979 ((speed == QIB_IB_DDR ? 4980 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR)); 4981 4982 if (newctrlb == ppd->cpspec->ibcctrl_b) 4983 return; 4984 4985 ppd->cpspec->ibcctrl_b = newctrlb; 4986 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); 4987 qib_write_kreg(ppd->dd, kr_scratch, 0); 4988 } 4989 4990 /* 4991 * This routine is only used when we are not talking to another 4992 * IB 1.2-compliant device that we think can do DDR. 4993 * (This includes all existing switch chips as of Oct 2007.) 4994 * 1.2-compliant devices go directly to DDR prior to reaching INIT 4995 */ 4996 static void try_7322_autoneg(struct qib_pportdata *ppd) 4997 { 4998 unsigned long flags; 4999 5000 spin_lock_irqsave(&ppd->lflags_lock, flags); 5001 ppd->lflags |= QIBL_IB_AUTONEG_INPROG; 5002 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5003 qib_autoneg_7322_send(ppd, 0); 5004 set_7322_ibspeed_fast(ppd, QIB_IB_DDR); 5005 qib_7322_mini_pcs_reset(ppd); 5006 /* 2 msec is minimum length of a poll cycle */ 5007 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work, 5008 msecs_to_jiffies(2)); 5009 } 5010 5011 /* 5012 * Handle the empirically determined mechanism for auto-negotiation 5013 * of DDR speed with switches. 5014 */ 5015 static void autoneg_7322_work(struct work_struct *work) 5016 { 5017 struct qib_pportdata *ppd; 5018 struct qib_devdata *dd; 5019 u64 startms; 5020 u32 i; 5021 unsigned long flags; 5022 5023 ppd = container_of(work, struct qib_chippport_specific, 5024 autoneg_work.work)->ppd; 5025 dd = ppd->dd; 5026 5027 startms = jiffies_to_msecs(jiffies); 5028 5029 /* 5030 * Busy wait for this first part, it should be at most a 5031 * few hundred usec, since we scheduled ourselves for 2msec. 5032 */ 5033 for (i = 0; i < 25; i++) { 5034 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState) 5035 == IB_7322_LT_STATE_POLLQUIET) { 5036 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE); 5037 break; 5038 } 5039 udelay(100); 5040 } 5041 5042 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) 5043 goto done; /* we got there early or told to stop */ 5044 5045 /* we expect this to timeout */ 5046 if (wait_event_timeout(ppd->cpspec->autoneg_wait, 5047 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5048 msecs_to_jiffies(90))) 5049 goto done; 5050 qib_7322_mini_pcs_reset(ppd); 5051 5052 /* we expect this to timeout */ 5053 if (wait_event_timeout(ppd->cpspec->autoneg_wait, 5054 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5055 msecs_to_jiffies(1700))) 5056 goto done; 5057 qib_7322_mini_pcs_reset(ppd); 5058 5059 set_7322_ibspeed_fast(ppd, QIB_IB_SDR); 5060 5061 /* 5062 * Wait up to 250 msec for link to train and get to INIT at DDR; 5063 * this should terminate early. 5064 */ 5065 wait_event_timeout(ppd->cpspec->autoneg_wait, 5066 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), 5067 msecs_to_jiffies(250)); 5068 done: 5069 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) { 5070 spin_lock_irqsave(&ppd->lflags_lock, flags); 5071 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; 5072 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) { 5073 ppd->lflags |= QIBL_IB_AUTONEG_FAILED; 5074 ppd->cpspec->autoneg_tries = 0; 5075 } 5076 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5077 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5078 } 5079 } 5080 5081 /* 5082 * This routine is used to request IPG set in the QLogic switch. 5083 * Only called if r1. 5084 */ 5085 static void try_7322_ipg(struct qib_pportdata *ppd) 5086 { 5087 struct qib_ibport *ibp = &ppd->ibport_data; 5088 struct ib_mad_send_buf *send_buf; 5089 struct ib_mad_agent *agent; 5090 struct ib_smp *smp; 5091 unsigned delay; 5092 int ret; 5093 5094 agent = ibp->send_agent; 5095 if (!agent) 5096 goto retry; 5097 5098 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR, 5099 IB_MGMT_MAD_DATA, GFP_ATOMIC); 5100 if (IS_ERR(send_buf)) 5101 goto retry; 5102 5103 if (!ibp->smi_ah) { 5104 struct ib_ah_attr attr; 5105 struct ib_ah *ah; 5106 5107 memset(&attr, 0, sizeof attr); 5108 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE); 5109 attr.port_num = ppd->port; 5110 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr); 5111 if (IS_ERR(ah)) 5112 ret = -EINVAL; 5113 else { 5114 send_buf->ah = ah; 5115 ibp->smi_ah = to_iah(ah); 5116 ret = 0; 5117 } 5118 } else { 5119 send_buf->ah = &ibp->smi_ah->ibah; 5120 ret = 0; 5121 } 5122 5123 smp = send_buf->mad; 5124 smp->base_version = IB_MGMT_BASE_VERSION; 5125 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE; 5126 smp->class_version = 1; 5127 smp->method = IB_MGMT_METHOD_SEND; 5128 smp->hop_cnt = 1; 5129 smp->attr_id = QIB_VENDOR_IPG; 5130 smp->attr_mod = 0; 5131 5132 if (!ret) 5133 ret = ib_post_send_mad(send_buf, NULL); 5134 if (ret) 5135 ib_free_send_mad(send_buf); 5136 retry: 5137 delay = 2 << ppd->cpspec->ipg_tries; 5138 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work, 5139 msecs_to_jiffies(delay)); 5140 } 5141 5142 /* 5143 * Timeout handler for setting IPG. 5144 * Only called if r1. 5145 */ 5146 static void ipg_7322_work(struct work_struct *work) 5147 { 5148 struct qib_pportdata *ppd; 5149 5150 ppd = container_of(work, struct qib_chippport_specific, 5151 ipg_work.work)->ppd; 5152 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE)) 5153 && ++ppd->cpspec->ipg_tries <= 10) 5154 try_7322_ipg(ppd); 5155 } 5156 5157 static u32 qib_7322_iblink_state(u64 ibcs) 5158 { 5159 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState); 5160 5161 switch (state) { 5162 case IB_7322_L_STATE_INIT: 5163 state = IB_PORT_INIT; 5164 break; 5165 case IB_7322_L_STATE_ARM: 5166 state = IB_PORT_ARMED; 5167 break; 5168 case IB_7322_L_STATE_ACTIVE: 5169 /* fall through */ 5170 case IB_7322_L_STATE_ACT_DEFER: 5171 state = IB_PORT_ACTIVE; 5172 break; 5173 default: /* fall through */ 5174 case IB_7322_L_STATE_DOWN: 5175 state = IB_PORT_DOWN; 5176 break; 5177 } 5178 return state; 5179 } 5180 5181 /* returns the IBTA port state, rather than the IBC link training state */ 5182 static u8 qib_7322_phys_portstate(u64 ibcs) 5183 { 5184 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState); 5185 return qib_7322_physportstate[state]; 5186 } 5187 5188 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) 5189 { 5190 int ret = 0, symadj = 0; 5191 unsigned long flags; 5192 int mult; 5193 5194 spin_lock_irqsave(&ppd->lflags_lock, flags); 5195 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; 5196 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5197 5198 /* Update our picture of width and speed from chip */ 5199 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) { 5200 ppd->link_speed_active = QIB_IB_QDR; 5201 mult = 4; 5202 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) { 5203 ppd->link_speed_active = QIB_IB_DDR; 5204 mult = 2; 5205 } else { 5206 ppd->link_speed_active = QIB_IB_SDR; 5207 mult = 1; 5208 } 5209 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) { 5210 ppd->link_width_active = IB_WIDTH_4X; 5211 mult *= 4; 5212 } else 5213 ppd->link_width_active = IB_WIDTH_1X; 5214 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)]; 5215 5216 if (!ibup) { 5217 u64 clr; 5218 5219 /* Link went down. */ 5220 /* do IPG MAD again after linkdown, even if last time failed */ 5221 ppd->cpspec->ipg_tries = 0; 5222 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) & 5223 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) | 5224 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk)); 5225 if (clr) 5226 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr); 5227 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | 5228 QIBL_IB_AUTONEG_INPROG))) 5229 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5230 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5231 struct qib_qsfp_data *qd = 5232 &ppd->cpspec->qsfp_data; 5233 /* unlock the Tx settings, speed may change */ 5234 qib_write_kreg_port(ppd, krp_tx_deemph_override, 5235 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 5236 reset_tx_deemphasis_override)); 5237 qib_cancel_sends(ppd); 5238 /* on link down, ensure sane pcs state */ 5239 qib_7322_mini_pcs_reset(ppd); 5240 /* schedule the qsfp refresh which should turn the link 5241 off */ 5242 if (ppd->dd->flags & QIB_HAS_QSFP) { 5243 qd->t_insert = get_jiffies_64(); 5244 schedule_work(&qd->work); 5245 } 5246 spin_lock_irqsave(&ppd->sdma_lock, flags); 5247 if (__qib_sdma_running(ppd)) 5248 __qib_sdma_process_event(ppd, 5249 qib_sdma_event_e70_go_idle); 5250 spin_unlock_irqrestore(&ppd->sdma_lock, flags); 5251 } 5252 clr = read_7322_creg32_port(ppd, crp_iblinkdown); 5253 if (clr == ppd->cpspec->iblnkdownsnap) 5254 ppd->cpspec->iblnkdowndelta++; 5255 } else { 5256 if (qib_compat_ddr_negotiate && 5257 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | 5258 QIBL_IB_AUTONEG_INPROG)) && 5259 ppd->link_speed_active == QIB_IB_SDR && 5260 (ppd->link_speed_enabled & QIB_IB_DDR) 5261 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) { 5262 /* we are SDR, and auto-negotiation enabled */ 5263 ++ppd->cpspec->autoneg_tries; 5264 if (!ppd->cpspec->ibdeltainprog) { 5265 ppd->cpspec->ibdeltainprog = 1; 5266 ppd->cpspec->ibsymdelta += 5267 read_7322_creg32_port(ppd, 5268 crp_ibsymbolerr) - 5269 ppd->cpspec->ibsymsnap; 5270 ppd->cpspec->iblnkerrdelta += 5271 read_7322_creg32_port(ppd, 5272 crp_iblinkerrrecov) - 5273 ppd->cpspec->iblnkerrsnap; 5274 } 5275 try_7322_autoneg(ppd); 5276 ret = 1; /* no other IB status change processing */ 5277 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && 5278 ppd->link_speed_active == QIB_IB_SDR) { 5279 qib_autoneg_7322_send(ppd, 1); 5280 set_7322_ibspeed_fast(ppd, QIB_IB_DDR); 5281 qib_7322_mini_pcs_reset(ppd); 5282 udelay(2); 5283 ret = 1; /* no other IB status change processing */ 5284 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && 5285 (ppd->link_speed_active & QIB_IB_DDR)) { 5286 spin_lock_irqsave(&ppd->lflags_lock, flags); 5287 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG | 5288 QIBL_IB_AUTONEG_FAILED); 5289 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5290 ppd->cpspec->autoneg_tries = 0; 5291 /* re-enable SDR, for next link down */ 5292 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); 5293 wake_up(&ppd->cpspec->autoneg_wait); 5294 symadj = 1; 5295 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) { 5296 /* 5297 * Clear autoneg failure flag, and do setup 5298 * so we'll try next time link goes down and 5299 * back to INIT (possibly connected to a 5300 * different device). 5301 */ 5302 spin_lock_irqsave(&ppd->lflags_lock, flags); 5303 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; 5304 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5305 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK; 5306 symadj = 1; 5307 } 5308 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5309 symadj = 1; 5310 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) 5311 try_7322_ipg(ppd); 5312 if (!ppd->cpspec->recovery_init) 5313 setup_7322_link_recovery(ppd, 0); 5314 ppd->cpspec->qdr_dfe_time = jiffies + 5315 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY); 5316 } 5317 ppd->cpspec->ibmalfusesnap = 0; 5318 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, 5319 crp_errlink); 5320 } 5321 if (symadj) { 5322 ppd->cpspec->iblnkdownsnap = 5323 read_7322_creg32_port(ppd, crp_iblinkdown); 5324 if (ppd->cpspec->ibdeltainprog) { 5325 ppd->cpspec->ibdeltainprog = 0; 5326 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd, 5327 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap; 5328 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd, 5329 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap; 5330 } 5331 } else if (!ibup && qib_compat_ddr_negotiate && 5332 !ppd->cpspec->ibdeltainprog && 5333 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { 5334 ppd->cpspec->ibdeltainprog = 1; 5335 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, 5336 crp_ibsymbolerr); 5337 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, 5338 crp_iblinkerrrecov); 5339 } 5340 5341 if (!ret) 5342 qib_setup_7322_setextled(ppd, ibup); 5343 return ret; 5344 } 5345 5346 /* 5347 * Does read/modify/write to appropriate registers to 5348 * set output and direction bits selected by mask. 5349 * these are in their canonical postions (e.g. lsb of 5350 * dir will end up in D48 of extctrl on existing chips). 5351 * returns contents of GP Inputs. 5352 */ 5353 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) 5354 { 5355 u64 read_val, new_out; 5356 unsigned long flags; 5357 5358 if (mask) { 5359 /* some bits being written, lock access to GPIO */ 5360 dir &= mask; 5361 out &= mask; 5362 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 5363 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); 5364 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); 5365 new_out = (dd->cspec->gpio_out & ~mask) | out; 5366 5367 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 5368 qib_write_kreg(dd, kr_gpio_out, new_out); 5369 dd->cspec->gpio_out = new_out; 5370 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 5371 } 5372 /* 5373 * It is unlikely that a read at this time would get valid 5374 * data on a pin whose direction line was set in the same 5375 * call to this function. We include the read here because 5376 * that allows us to potentially combine a change on one pin with 5377 * a read on another, and because the old code did something like 5378 * this. 5379 */ 5380 read_val = qib_read_kreg64(dd, kr_extstatus); 5381 return SYM_FIELD(read_val, EXTStatus, GPIOIn); 5382 } 5383 5384 /* Enable writes to config EEPROM, if possible. Returns previous state */ 5385 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) 5386 { 5387 int prev_wen; 5388 u32 mask; 5389 5390 mask = 1 << QIB_EEPROM_WEN_NUM; 5391 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM; 5392 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); 5393 5394 return prev_wen & 1; 5395 } 5396 5397 /* 5398 * Read fundamental info we need to use the chip. These are 5399 * the registers that describe chip capabilities, and are 5400 * saved in shadow registers. 5401 */ 5402 static void get_7322_chip_params(struct qib_devdata *dd) 5403 { 5404 u64 val; 5405 u32 piobufs; 5406 int mtu; 5407 5408 dd->palign = qib_read_kreg32(dd, kr_pagealign); 5409 5410 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); 5411 5412 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); 5413 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); 5414 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); 5415 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); 5416 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; 5417 5418 val = qib_read_kreg64(dd, kr_sendpiobufcnt); 5419 dd->piobcnt2k = val & ~0U; 5420 dd->piobcnt4k = val >> 32; 5421 val = qib_read_kreg64(dd, kr_sendpiosize); 5422 dd->piosize2k = val & ~0U; 5423 dd->piosize4k = val >> 32; 5424 5425 mtu = ib_mtu_enum_to_int(qib_ibmtu); 5426 if (mtu == -1) 5427 mtu = QIB_DEFAULT_MTU; 5428 dd->pport[0].ibmtu = (u32)mtu; 5429 dd->pport[1].ibmtu = (u32)mtu; 5430 5431 /* these may be adjusted in init_chip_wc_pat() */ 5432 dd->pio2kbase = (u32 __iomem *) 5433 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); 5434 dd->pio4kbase = (u32 __iomem *) 5435 ((char __iomem *) dd->kregbase + 5436 (dd->piobufbase >> 32)); 5437 /* 5438 * 4K buffers take 2 pages; we use roundup just to be 5439 * paranoid; we calculate it once here, rather than on 5440 * ever buf allocate 5441 */ 5442 dd->align4k = ALIGN(dd->piosize4k, dd->palign); 5443 5444 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; 5445 5446 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / 5447 (sizeof(u64) * BITS_PER_BYTE / 2); 5448 } 5449 5450 /* 5451 * The chip base addresses in cspec and cpspec have to be set 5452 * after possible init_chip_wc_pat(), rather than in 5453 * get_7322_chip_params(), so split out as separate function 5454 */ 5455 static void qib_7322_set_baseaddrs(struct qib_devdata *dd) 5456 { 5457 u32 cregbase; 5458 cregbase = qib_read_kreg32(dd, kr_counterregbase); 5459 5460 dd->cspec->cregbase = (u64 __iomem *)(cregbase + 5461 (char __iomem *)dd->kregbase); 5462 5463 dd->egrtidbase = (u64 __iomem *) 5464 ((char __iomem *) dd->kregbase + dd->rcvegrbase); 5465 5466 /* port registers are defined as relative to base of chip */ 5467 dd->pport[0].cpspec->kpregbase = 5468 (u64 __iomem *)((char __iomem *)dd->kregbase); 5469 dd->pport[1].cpspec->kpregbase = 5470 (u64 __iomem *)(dd->palign + 5471 (char __iomem *)dd->kregbase); 5472 dd->pport[0].cpspec->cpregbase = 5473 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], 5474 kr_counterregbase) + (char __iomem *)dd->kregbase); 5475 dd->pport[1].cpspec->cpregbase = 5476 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], 5477 kr_counterregbase) + (char __iomem *)dd->kregbase); 5478 } 5479 5480 /* 5481 * This is a fairly special-purpose observer, so we only support 5482 * the port-specific parts of SendCtrl 5483 */ 5484 5485 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \ 5486 SYM_MASK(SendCtrl_0, SDmaEnable) | \ 5487 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \ 5488 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \ 5489 SYM_MASK(SendCtrl_0, SDmaHalt) | \ 5490 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \ 5491 SYM_MASK(SendCtrl_0, ForceCreditUpToDate)) 5492 5493 static int sendctrl_hook(struct qib_devdata *dd, 5494 const struct diag_observer *op, u32 offs, 5495 u64 *data, u64 mask, int only_32) 5496 { 5497 unsigned long flags; 5498 unsigned idx; 5499 unsigned pidx; 5500 struct qib_pportdata *ppd = NULL; 5501 u64 local_data, all_bits; 5502 5503 /* 5504 * The fixed correspondence between Physical ports and pports is 5505 * severed. We need to hunt for the ppd that corresponds 5506 * to the offset we got. And we have to do that without admitting 5507 * we know the stride, apparently. 5508 */ 5509 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 5510 u64 __iomem *psptr; 5511 u32 psoffs; 5512 5513 ppd = dd->pport + pidx; 5514 if (!ppd->cpspec->kpregbase) 5515 continue; 5516 5517 psptr = ppd->cpspec->kpregbase + krp_sendctrl; 5518 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); 5519 if (psoffs == offs) 5520 break; 5521 } 5522 5523 /* If pport is not being managed by driver, just avoid shadows. */ 5524 if (pidx >= dd->num_pports) 5525 ppd = NULL; 5526 5527 /* In any case, "idx" is flat index in kreg space */ 5528 idx = offs / sizeof(u64); 5529 5530 all_bits = ~0ULL; 5531 if (only_32) 5532 all_bits >>= 32; 5533 5534 spin_lock_irqsave(&dd->sendctrl_lock, flags); 5535 if (!ppd || (mask & all_bits) != all_bits) { 5536 /* 5537 * At least some mask bits are zero, so we need 5538 * to read. The judgement call is whether from 5539 * reg or shadow. First-cut: read reg, and complain 5540 * if any bits which should be shadowed are different 5541 * from their shadowed value. 5542 */ 5543 if (only_32) 5544 local_data = (u64)qib_read_kreg32(dd, idx); 5545 else 5546 local_data = qib_read_kreg64(dd, idx); 5547 *data = (local_data & ~mask) | (*data & mask); 5548 } 5549 if (mask) { 5550 /* 5551 * At least some mask bits are one, so we need 5552 * to write, but only shadow some bits. 5553 */ 5554 u64 sval, tval; /* Shadowed, transient */ 5555 5556 /* 5557 * New shadow val is bits we don't want to touch, 5558 * ORed with bits we do, that are intended for shadow. 5559 */ 5560 if (ppd) { 5561 sval = ppd->p_sendctrl & ~mask; 5562 sval |= *data & SENDCTRL_SHADOWED & mask; 5563 ppd->p_sendctrl = sval; 5564 } else 5565 sval = *data & SENDCTRL_SHADOWED & mask; 5566 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask); 5567 qib_write_kreg(dd, idx, tval); 5568 qib_write_kreg(dd, kr_scratch, 0Ull); 5569 } 5570 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 5571 return only_32 ? 4 : 8; 5572 } 5573 5574 static const struct diag_observer sendctrl_0_observer = { 5575 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64), 5576 KREG_IDX(SendCtrl_0) * sizeof(u64) 5577 }; 5578 5579 static const struct diag_observer sendctrl_1_observer = { 5580 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64), 5581 KREG_IDX(SendCtrl_1) * sizeof(u64) 5582 }; 5583 5584 static ushort sdma_fetch_prio = 8; 5585 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO); 5586 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority"); 5587 5588 /* Besides logging QSFP events, we set appropriate TxDDS values */ 5589 static void init_txdds_table(struct qib_pportdata *ppd, int override); 5590 5591 static void qsfp_7322_event(struct work_struct *work) 5592 { 5593 struct qib_qsfp_data *qd; 5594 struct qib_pportdata *ppd; 5595 u64 pwrup; 5596 unsigned long flags; 5597 int ret; 5598 u32 le2; 5599 5600 qd = container_of(work, struct qib_qsfp_data, work); 5601 ppd = qd->ppd; 5602 pwrup = qd->t_insert + 5603 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC); 5604 5605 /* Delay for 20 msecs to allow ModPrs resistor to setup */ 5606 mdelay(QSFP_MODPRS_LAG_MSEC); 5607 5608 if (!qib_qsfp_mod_present(ppd)) { 5609 ppd->cpspec->qsfp_data.modpresent = 0; 5610 /* Set the physical link to disabled */ 5611 qib_set_ib_7322_lstate(ppd, 0, 5612 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 5613 spin_lock_irqsave(&ppd->lflags_lock, flags); 5614 ppd->lflags &= ~QIBL_LINKV; 5615 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5616 } else { 5617 /* 5618 * Some QSFP's not only do not respond until the full power-up 5619 * time, but may behave badly if we try. So hold off responding 5620 * to insertion. 5621 */ 5622 while (1) { 5623 u64 now = get_jiffies_64(); 5624 if (time_after64(now, pwrup)) 5625 break; 5626 msleep(20); 5627 } 5628 5629 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); 5630 5631 /* 5632 * Need to change LE2 back to defaults if we couldn't 5633 * read the cable type (to handle cable swaps), so do this 5634 * even on failure to read cable information. We don't 5635 * get here for QME, so IS_QME check not needed here. 5636 */ 5637 if (!ret && !ppd->dd->cspec->r1) { 5638 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech)) 5639 le2 = LE2_QME; 5640 else if (qd->cache.atten[1] >= qib_long_atten && 5641 QSFP_IS_CU(qd->cache.tech)) 5642 le2 = LE2_5m; 5643 else 5644 le2 = LE2_DEFAULT; 5645 } else 5646 le2 = LE2_DEFAULT; 5647 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7)); 5648 /* 5649 * We always change parameteters, since we can choose 5650 * values for cables without eeproms, and the cable may have 5651 * changed from a cable with full or partial eeprom content 5652 * to one with partial or no content. 5653 */ 5654 init_txdds_table(ppd, 0); 5655 /* The physical link is being re-enabled only when the 5656 * previous state was DISABLED and the VALID bit is not 5657 * set. This should only happen when the cable has been 5658 * physically pulled. */ 5659 if (!ppd->cpspec->qsfp_data.modpresent && 5660 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) { 5661 ppd->cpspec->qsfp_data.modpresent = 1; 5662 qib_set_ib_7322_lstate(ppd, 0, 5663 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); 5664 spin_lock_irqsave(&ppd->lflags_lock, flags); 5665 ppd->lflags |= QIBL_LINKV; 5666 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 5667 } 5668 } 5669 } 5670 5671 /* 5672 * There is little we can do but complain to the user if QSFP 5673 * initialization fails. 5674 */ 5675 static void qib_init_7322_qsfp(struct qib_pportdata *ppd) 5676 { 5677 unsigned long flags; 5678 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data; 5679 struct qib_devdata *dd = ppd->dd; 5680 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N; 5681 5682 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); 5683 qd->ppd = ppd; 5684 qib_qsfp_init(qd, qsfp_7322_event); 5685 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 5686 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); 5687 dd->cspec->gpio_mask |= mod_prs_bit; 5688 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 5689 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 5690 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 5691 } 5692 5693 /* 5694 * called at device initialization time, and also if the txselect 5695 * module parameter is changed. This is used for cables that don't 5696 * have valid QSFP EEPROMs (not present, or attenuation is zero). 5697 * We initialize to the default, then if there is a specific 5698 * unit,port match, we use that (and set it immediately, for the 5699 * current speed, if the link is at INIT or better). 5700 * String format is "default# unit#,port#=# ... u,p=#", separators must 5701 * be a SPACE character. A newline terminates. The u,p=# tuples may 5702 * optionally have "u,p=#,#", where the final # is the H1 value 5703 * The last specific match is used (actually, all are used, but last 5704 * one is the one that winds up set); if none at all, fall back on default. 5705 */ 5706 static void set_no_qsfp_atten(struct qib_devdata *dd, int change) 5707 { 5708 char *nxt, *str; 5709 u32 pidx, unit, port, deflt, h1; 5710 unsigned long val; 5711 int any = 0, seth1; 5712 int txdds_size; 5713 5714 str = txselect_list; 5715 5716 /* default number is validated in setup_txselect() */ 5717 deflt = simple_strtoul(str, &nxt, 0); 5718 for (pidx = 0; pidx < dd->num_pports; ++pidx) 5719 dd->pport[pidx].cpspec->no_eep = deflt; 5720 5721 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ; 5722 if (IS_QME(dd) || IS_QMH(dd)) 5723 txdds_size += TXDDS_MFG_SZ; 5724 5725 while (*nxt && nxt[1]) { 5726 str = ++nxt; 5727 unit = simple_strtoul(str, &nxt, 0); 5728 if (nxt == str || !*nxt || *nxt != ',') { 5729 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 5730 ; 5731 continue; 5732 } 5733 str = ++nxt; 5734 port = simple_strtoul(str, &nxt, 0); 5735 if (nxt == str || *nxt != '=') { 5736 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 5737 ; 5738 continue; 5739 } 5740 str = ++nxt; 5741 val = simple_strtoul(str, &nxt, 0); 5742 if (nxt == str) { 5743 while (*nxt && *nxt++ != ' ') /* skip to next, if any */ 5744 ; 5745 continue; 5746 } 5747 if (val >= txdds_size) 5748 continue; 5749 seth1 = 0; 5750 h1 = 0; /* gcc thinks it might be used uninitted */ 5751 if (*nxt == ',' && nxt[1]) { 5752 str = ++nxt; 5753 h1 = (u32)simple_strtoul(str, &nxt, 0); 5754 if (nxt == str) 5755 while (*nxt && *nxt++ != ' ') /* skip */ 5756 ; 5757 else 5758 seth1 = 1; 5759 } 5760 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; 5761 ++pidx) { 5762 struct qib_pportdata *ppd = &dd->pport[pidx]; 5763 5764 if (ppd->port != port || !ppd->link_speed_supported) 5765 continue; 5766 ppd->cpspec->no_eep = val; 5767 if (seth1) 5768 ppd->cpspec->h1_val = h1; 5769 /* now change the IBC and serdes, overriding generic */ 5770 init_txdds_table(ppd, 1); 5771 /* Re-enable the physical state machine on mezz boards 5772 * now that the correct settings have been set. 5773 * QSFP boards are handles by the QSFP event handler */ 5774 if (IS_QMH(dd) || IS_QME(dd)) 5775 qib_set_ib_7322_lstate(ppd, 0, 5776 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP); 5777 any++; 5778 } 5779 if (*nxt == '\n') 5780 break; /* done */ 5781 } 5782 if (change && !any) { 5783 /* no specific setting, use the default. 5784 * Change the IBC and serdes, but since it's 5785 * general, don't override specific settings. 5786 */ 5787 for (pidx = 0; pidx < dd->num_pports; ++pidx) 5788 if (dd->pport[pidx].link_speed_supported) 5789 init_txdds_table(&dd->pport[pidx], 0); 5790 } 5791 } 5792 5793 /* handle the txselect parameter changing */ 5794 static int setup_txselect(const char *str, struct kernel_param *kp) 5795 { 5796 struct qib_devdata *dd; 5797 unsigned long val; 5798 char *n; 5799 if (strlen(str) >= MAX_ATTEN_LEN) { 5800 printk(KERN_INFO QIB_DRV_NAME " txselect_values string " 5801 "too long\n"); 5802 return -ENOSPC; 5803 } 5804 val = simple_strtoul(str, &n, 0); 5805 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 5806 TXDDS_MFG_SZ)) { 5807 printk(KERN_INFO QIB_DRV_NAME 5808 "txselect_values must start with a number < %d\n", 5809 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ); 5810 return -EINVAL; 5811 } 5812 strcpy(txselect_list, str); 5813 5814 list_for_each_entry(dd, &qib_dev_list, list) 5815 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) 5816 set_no_qsfp_atten(dd, 1); 5817 return 0; 5818 } 5819 5820 /* 5821 * Write the final few registers that depend on some of the 5822 * init setup. Done late in init, just before bringing up 5823 * the serdes. 5824 */ 5825 static int qib_late_7322_initreg(struct qib_devdata *dd) 5826 { 5827 int ret = 0, n; 5828 u64 val; 5829 5830 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); 5831 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); 5832 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); 5833 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); 5834 val = qib_read_kreg64(dd, kr_sendpioavailaddr); 5835 if (val != dd->pioavailregs_phys) { 5836 qib_dev_err(dd, "Catastrophic software error, " 5837 "SendPIOAvailAddr written as %lx, " 5838 "read back as %llx\n", 5839 (unsigned long) dd->pioavailregs_phys, 5840 (unsigned long long) val); 5841 ret = -EINVAL; 5842 } 5843 5844 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; 5845 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL); 5846 /* driver sends get pkey, lid, etc. checking also, to catch bugs */ 5847 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL); 5848 5849 qib_register_observer(dd, &sendctrl_0_observer); 5850 qib_register_observer(dd, &sendctrl_1_observer); 5851 5852 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; 5853 qib_write_kreg(dd, kr_control, dd->control); 5854 /* 5855 * Set SendDmaFetchPriority and init Tx params, including 5856 * QSFP handler on boards that have QSFP. 5857 * First set our default attenuation entry for cables that 5858 * don't have valid attenuation. 5859 */ 5860 set_no_qsfp_atten(dd, 0); 5861 for (n = 0; n < dd->num_pports; ++n) { 5862 struct qib_pportdata *ppd = dd->pport + n; 5863 5864 qib_write_kreg_port(ppd, krp_senddmaprioritythld, 5865 sdma_fetch_prio & 0xf); 5866 /* Initialize qsfp if present on board. */ 5867 if (dd->flags & QIB_HAS_QSFP) 5868 qib_init_7322_qsfp(ppd); 5869 } 5870 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; 5871 qib_write_kreg(dd, kr_control, dd->control); 5872 5873 return ret; 5874 } 5875 5876 /* per IB port errors. */ 5877 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \ 5878 MASK_ACROSS(8, 15)) 5879 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41)) 5880 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \ 5881 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \ 5882 MASK_ACROSS(0, 11)) 5883 5884 /* 5885 * Write the initialization per-port registers that need to be done at 5886 * driver load and after reset completes (i.e., that aren't done as part 5887 * of other init procedures called from qib_init.c). 5888 * Some of these should be redundant on reset, but play safe. 5889 */ 5890 static void write_7322_init_portregs(struct qib_pportdata *ppd) 5891 { 5892 u64 val; 5893 int i; 5894 5895 if (!ppd->link_speed_supported) { 5896 /* no buffer credits for this port */ 5897 for (i = 1; i < 8; i++) 5898 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0); 5899 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0); 5900 qib_write_kreg(ppd->dd, kr_scratch, 0); 5901 return; 5902 } 5903 5904 /* 5905 * Set the number of supported virtual lanes in IBC, 5906 * for flow control packet handling on unsupported VLs 5907 */ 5908 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx); 5909 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP); 5910 val |= (u64)(ppd->vls_supported - 1) << 5911 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP); 5912 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val); 5913 5914 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP); 5915 5916 /* enable tx header checking */ 5917 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY | 5918 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID | 5919 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ); 5920 5921 qib_write_kreg_port(ppd, krp_ncmodectrl, 5922 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal)); 5923 5924 /* 5925 * Unconditionally clear the bufmask bits. If SDMA is 5926 * enabled, we'll set them appropriately later. 5927 */ 5928 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0); 5929 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0); 5930 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0); 5931 if (ppd->dd->cspec->r1) 5932 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); 5933 } 5934 5935 /* 5936 * Write the initialization per-device registers that need to be done at 5937 * driver load and after reset completes (i.e., that aren't done as part 5938 * of other init procedures called from qib_init.c). Also write per-port 5939 * registers that are affected by overall device config, such as QP mapping 5940 * Some of these should be redundant on reset, but play safe. 5941 */ 5942 static void write_7322_initregs(struct qib_devdata *dd) 5943 { 5944 struct qib_pportdata *ppd; 5945 int i, pidx; 5946 u64 val; 5947 5948 /* Set Multicast QPs received by port 2 to map to context one. */ 5949 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1); 5950 5951 for (pidx = 0; pidx < dd->num_pports; ++pidx) { 5952 unsigned n, regno; 5953 unsigned long flags; 5954 5955 if (dd->n_krcv_queues < 2 || 5956 !dd->pport[pidx].link_speed_supported) 5957 continue; 5958 5959 ppd = &dd->pport[pidx]; 5960 5961 /* be paranoid against later code motion, etc. */ 5962 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 5963 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); 5964 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 5965 5966 /* Initialize QP to context mapping */ 5967 regno = krp_rcvqpmaptable; 5968 val = 0; 5969 if (dd->num_pports > 1) 5970 n = dd->first_user_ctxt / dd->num_pports; 5971 else 5972 n = dd->first_user_ctxt - 1; 5973 for (i = 0; i < 32; ) { 5974 unsigned ctxt; 5975 5976 if (dd->num_pports > 1) 5977 ctxt = (i % n) * dd->num_pports + pidx; 5978 else if (i % n) 5979 ctxt = (i % n) + 1; 5980 else 5981 ctxt = ppd->hw_pidx; 5982 val |= ctxt << (5 * (i % 6)); 5983 i++; 5984 if (i % 6 == 0) { 5985 qib_write_kreg_port(ppd, regno, val); 5986 val = 0; 5987 regno++; 5988 } 5989 } 5990 qib_write_kreg_port(ppd, regno, val); 5991 } 5992 5993 /* 5994 * Setup up interrupt mitigation for kernel contexts, but 5995 * not user contexts (user contexts use interrupts when 5996 * stalled waiting for any packet, so want those interrupts 5997 * right away). 5998 */ 5999 for (i = 0; i < dd->first_user_ctxt; i++) { 6000 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; 6001 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout); 6002 } 6003 6004 /* 6005 * Initialize as (disabled) rcvflow tables. Application code 6006 * will setup each flow as it uses the flow. 6007 * Doesn't clear any of the error bits that might be set. 6008 */ 6009 val = TIDFLOW_ERRBITS; /* these are W1C */ 6010 for (i = 0; i < dd->cfgctxts; i++) { 6011 int flow; 6012 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++) 6013 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); 6014 } 6015 6016 /* 6017 * dual cards init to dual port recovery, single port cards to 6018 * the one port. Dual port cards may later adjust to 1 port, 6019 * and then back to dual port if both ports are connected 6020 * */ 6021 if (dd->num_pports) 6022 setup_7322_link_recovery(dd->pport, dd->num_pports > 1); 6023 } 6024 6025 static int qib_init_7322_variables(struct qib_devdata *dd) 6026 { 6027 struct qib_pportdata *ppd; 6028 unsigned features, pidx, sbufcnt; 6029 int ret, mtu; 6030 u32 sbufs, updthresh; 6031 6032 /* pport structs are contiguous, allocated after devdata */ 6033 ppd = (struct qib_pportdata *)(dd + 1); 6034 dd->pport = ppd; 6035 ppd[0].dd = dd; 6036 ppd[1].dd = dd; 6037 6038 dd->cspec = (struct qib_chip_specific *)(ppd + 2); 6039 6040 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); 6041 ppd[1].cpspec = &ppd[0].cpspec[1]; 6042 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */ 6043 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */ 6044 6045 spin_lock_init(&dd->cspec->rcvmod_lock); 6046 spin_lock_init(&dd->cspec->gpio_lock); 6047 6048 /* we haven't yet set QIB_PRESENT, so use read directly */ 6049 dd->revision = readq(&dd->kregbase[kr_revision]); 6050 6051 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { 6052 qib_dev_err(dd, "Revision register read failure, " 6053 "giving up initialization\n"); 6054 ret = -ENODEV; 6055 goto bail; 6056 } 6057 dd->flags |= QIB_PRESENT; /* now register routines work */ 6058 6059 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); 6060 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); 6061 dd->cspec->r1 = dd->minrev == 1; 6062 6063 get_7322_chip_params(dd); 6064 features = qib_7322_boardname(dd); 6065 6066 /* now that piobcnt2k and 4k set, we can allocate these */ 6067 sbufcnt = dd->piobcnt2k + dd->piobcnt4k + 6068 NUM_VL15_BUFS + BITS_PER_LONG - 1; 6069 sbufcnt /= BITS_PER_LONG; 6070 dd->cspec->sendchkenable = kmalloc(sbufcnt * 6071 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL); 6072 dd->cspec->sendgrhchk = kmalloc(sbufcnt * 6073 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL); 6074 dd->cspec->sendibchk = kmalloc(sbufcnt * 6075 sizeof(*dd->cspec->sendibchk), GFP_KERNEL); 6076 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || 6077 !dd->cspec->sendibchk) { 6078 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n"); 6079 ret = -ENOMEM; 6080 goto bail; 6081 } 6082 6083 ppd = dd->pport; 6084 6085 /* 6086 * GPIO bits for TWSI data and clock, 6087 * used for serial EEPROM. 6088 */ 6089 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; 6090 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; 6091 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; 6092 6093 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | 6094 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP | 6095 QIB_HAS_THRESH_UPDATE | 6096 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0); 6097 dd->flags |= qib_special_trigger ? 6098 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA; 6099 6100 /* 6101 * Setup initial values. These may change when PAT is enabled, but 6102 * we need these to do initial chip register accesses. 6103 */ 6104 qib_7322_set_baseaddrs(dd); 6105 6106 mtu = ib_mtu_enum_to_int(qib_ibmtu); 6107 if (mtu == -1) 6108 mtu = QIB_DEFAULT_MTU; 6109 6110 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; 6111 /* all hwerrors become interrupts, unless special purposed */ 6112 dd->cspec->hwerrmask = ~0ULL; 6113 /* link_recovery setup causes these errors, so ignore them, 6114 * other than clearing them when they occur */ 6115 dd->cspec->hwerrmask &= 6116 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) | 6117 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) | 6118 HWE_MASK(LATriggered)); 6119 6120 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) { 6121 struct qib_chippport_specific *cp = ppd->cpspec; 6122 ppd->link_speed_supported = features & PORT_SPD_CAP; 6123 features >>= PORT_SPD_CAP_SHIFT; 6124 if (!ppd->link_speed_supported) { 6125 /* single port mode (7340, or configured) */ 6126 dd->skip_kctxt_mask |= 1 << pidx; 6127 if (pidx == 0) { 6128 /* Make sure port is disabled. */ 6129 qib_write_kreg_port(ppd, krp_rcvctrl, 0); 6130 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); 6131 ppd[0] = ppd[1]; 6132 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, 6133 IBSerdesPClkNotDetectMask_0) 6134 | SYM_MASK(HwErrMask, 6135 SDmaMemReadErrMask_0)); 6136 dd->cspec->int_enable_mask &= ~( 6137 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) | 6138 SYM_MASK(IntMask, SDmaIdleIntMask_0) | 6139 SYM_MASK(IntMask, SDmaProgressIntMask_0) | 6140 SYM_MASK(IntMask, SDmaIntMask_0) | 6141 SYM_MASK(IntMask, ErrIntMask_0) | 6142 SYM_MASK(IntMask, SendDoneIntMask_0)); 6143 } else { 6144 /* Make sure port is disabled. */ 6145 qib_write_kreg_port(ppd, krp_rcvctrl, 0); 6146 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0); 6147 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, 6148 IBSerdesPClkNotDetectMask_1) 6149 | SYM_MASK(HwErrMask, 6150 SDmaMemReadErrMask_1)); 6151 dd->cspec->int_enable_mask &= ~( 6152 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) | 6153 SYM_MASK(IntMask, SDmaIdleIntMask_1) | 6154 SYM_MASK(IntMask, SDmaProgressIntMask_1) | 6155 SYM_MASK(IntMask, SDmaIntMask_1) | 6156 SYM_MASK(IntMask, ErrIntMask_1) | 6157 SYM_MASK(IntMask, SendDoneIntMask_1)); 6158 } 6159 continue; 6160 } 6161 6162 dd->num_pports++; 6163 qib_init_pportdata(ppd, dd, pidx, dd->num_pports); 6164 6165 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; 6166 ppd->link_width_enabled = IB_WIDTH_4X; 6167 ppd->link_speed_enabled = ppd->link_speed_supported; 6168 /* 6169 * Set the initial values to reasonable default, will be set 6170 * for real when link is up. 6171 */ 6172 ppd->link_width_active = IB_WIDTH_4X; 6173 ppd->link_speed_active = QIB_IB_SDR; 6174 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS]; 6175 switch (qib_num_cfg_vls) { 6176 case 1: 6177 ppd->vls_supported = IB_VL_VL0; 6178 break; 6179 case 2: 6180 ppd->vls_supported = IB_VL_VL0_1; 6181 break; 6182 default: 6183 qib_devinfo(dd->pcidev, 6184 "Invalid num_vls %u, using 4 VLs\n", 6185 qib_num_cfg_vls); 6186 qib_num_cfg_vls = 4; 6187 /* fall through */ 6188 case 4: 6189 ppd->vls_supported = IB_VL_VL0_3; 6190 break; 6191 case 8: 6192 if (mtu <= 2048) 6193 ppd->vls_supported = IB_VL_VL0_7; 6194 else { 6195 qib_devinfo(dd->pcidev, 6196 "Invalid num_vls %u for MTU %d " 6197 ", using 4 VLs\n", 6198 qib_num_cfg_vls, mtu); 6199 ppd->vls_supported = IB_VL_VL0_3; 6200 qib_num_cfg_vls = 4; 6201 } 6202 break; 6203 } 6204 ppd->vls_operational = ppd->vls_supported; 6205 6206 init_waitqueue_head(&cp->autoneg_wait); 6207 INIT_DELAYED_WORK(&cp->autoneg_work, 6208 autoneg_7322_work); 6209 if (ppd->dd->cspec->r1) 6210 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work); 6211 6212 /* 6213 * For Mez and similar cards, no qsfp info, so do 6214 * the "cable info" setup here. Can be overridden 6215 * in adapter-specific routines. 6216 */ 6217 if (!(dd->flags & QIB_HAS_QSFP)) { 6218 if (!IS_QMH(dd) && !IS_QME(dd)) 6219 qib_devinfo(dd->pcidev, "IB%u:%u: " 6220 "Unknown mezzanine card type\n", 6221 dd->unit, ppd->port); 6222 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; 6223 /* 6224 * Choose center value as default tx serdes setting 6225 * until changed through module parameter. 6226 */ 6227 ppd->cpspec->no_eep = IS_QMH(dd) ? 6228 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4; 6229 } else 6230 cp->h1_val = H1_FORCE_VAL; 6231 6232 /* Avoid writes to chip for mini_init */ 6233 if (!qib_mini_init) 6234 write_7322_init_portregs(ppd); 6235 6236 init_timer(&cp->chase_timer); 6237 cp->chase_timer.function = reenable_chase; 6238 cp->chase_timer.data = (unsigned long)ppd; 6239 6240 ppd++; 6241 } 6242 6243 dd->rcvhdrentsize = qib_rcvhdrentsize ? 6244 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE; 6245 dd->rcvhdrsize = qib_rcvhdrsize ? 6246 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE; 6247 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); 6248 6249 /* we always allocate at least 2048 bytes for eager buffers */ 6250 dd->rcvegrbufsize = max(mtu, 2048); 6251 BUG_ON(!is_power_of_2(dd->rcvegrbufsize)); 6252 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); 6253 6254 qib_7322_tidtemplate(dd); 6255 6256 /* 6257 * We can request a receive interrupt for 1 or 6258 * more packets from current offset. 6259 */ 6260 dd->rhdrhead_intr_off = 6261 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT; 6262 6263 /* setup the stats timer; the add_timer is done at end of init */ 6264 init_timer(&dd->stats_timer); 6265 dd->stats_timer.function = qib_get_7322_faststats; 6266 dd->stats_timer.data = (unsigned long) dd; 6267 6268 dd->ureg_align = 0x10000; /* 64KB alignment */ 6269 6270 dd->piosize2kmax_dwords = dd->piosize2k >> 2; 6271 6272 qib_7322_config_ctxts(dd); 6273 qib_set_ctxtcnt(dd); 6274 6275 if (qib_wc_pat) { 6276 resource_size_t vl15off; 6277 /* 6278 * We do not set WC on the VL15 buffers to avoid 6279 * a rare problem with unaligned writes from 6280 * interrupt-flushed store buffers, so we need 6281 * to map those separately here. We can't solve 6282 * this for the rarely used mtrr case. 6283 */ 6284 ret = init_chip_wc_pat(dd, 0); 6285 if (ret) 6286 goto bail; 6287 6288 /* vl15 buffers start just after the 4k buffers */ 6289 vl15off = dd->physaddr + (dd->piobufbase >> 32) + 6290 dd->piobcnt4k * dd->align4k; 6291 dd->piovl15base = ioremap_nocache(vl15off, 6292 NUM_VL15_BUFS * dd->align4k); 6293 if (!dd->piovl15base) 6294 goto bail; 6295 } 6296 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ 6297 6298 ret = 0; 6299 if (qib_mini_init) 6300 goto bail; 6301 if (!dd->num_pports) { 6302 qib_dev_err(dd, "No ports enabled, giving up initialization\n"); 6303 goto bail; /* no error, so can still figure out why err */ 6304 } 6305 6306 write_7322_initregs(dd); 6307 ret = qib_create_ctxts(dd); 6308 init_7322_cntrnames(dd); 6309 6310 updthresh = 8U; /* update threshold */ 6311 6312 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA. 6313 * reserve the update threshold amount for other kernel use, such 6314 * as sending SMI, MAD, and ACKs, or 3, whichever is greater, 6315 * unless we aren't enabling SDMA, in which case we want to use 6316 * all the 4k bufs for the kernel. 6317 * if this was less than the update threshold, we could wait 6318 * a long time for an update. Coded this way because we 6319 * sometimes change the update threshold for various reasons, 6320 * and we want this to remain robust. 6321 */ 6322 if (dd->flags & QIB_HAS_SEND_DMA) { 6323 dd->cspec->sdmabufcnt = dd->piobcnt4k; 6324 sbufs = updthresh > 3 ? updthresh : 3; 6325 } else { 6326 dd->cspec->sdmabufcnt = 0; 6327 sbufs = dd->piobcnt4k; 6328 } 6329 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - 6330 dd->cspec->sdmabufcnt; 6331 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; 6332 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ 6333 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? 6334 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; 6335 6336 /* 6337 * If we have 16 user contexts, we will have 7 sbufs 6338 * per context, so reduce the update threshold to match. We 6339 * want to update before we actually run out, at low pbufs/ctxt 6340 * so give ourselves some margin. 6341 */ 6342 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) 6343 updthresh = dd->pbufsctxt - 2; 6344 dd->cspec->updthresh_dflt = updthresh; 6345 dd->cspec->updthresh = updthresh; 6346 6347 /* before full enable, no interrupts, no locking needed */ 6348 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) 6349 << SYM_LSB(SendCtrl, AvailUpdThld)) | 6350 SYM_MASK(SendCtrl, SendBufAvailPad64Byte); 6351 6352 dd->psxmitwait_supported = 1; 6353 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; 6354 bail: 6355 if (!dd->ctxtcnt) 6356 dd->ctxtcnt = 1; /* for other initialization code */ 6357 6358 return ret; 6359 } 6360 6361 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc, 6362 u32 *pbufnum) 6363 { 6364 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK; 6365 struct qib_devdata *dd = ppd->dd; 6366 6367 /* last is same for 2k and 4k, because we use 4k if all 2k busy */ 6368 if (pbc & PBC_7322_VL15_SEND) { 6369 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; 6370 last = first; 6371 } else { 6372 if ((plen + 1) > dd->piosize2kmax_dwords) 6373 first = dd->piobcnt2k; 6374 else 6375 first = 0; 6376 last = dd->cspec->lastbuf_for_pio; 6377 } 6378 return qib_getsendbuf_range(dd, pbufnum, first, last); 6379 } 6380 6381 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv, 6382 u32 start) 6383 { 6384 qib_write_kreg_port(ppd, krp_psinterval, intv); 6385 qib_write_kreg_port(ppd, krp_psstart, start); 6386 } 6387 6388 /* 6389 * Must be called with sdma_lock held, or before init finished. 6390 */ 6391 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) 6392 { 6393 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt); 6394 } 6395 6396 static struct sdma_set_state_action sdma_7322_action_table[] = { 6397 [qib_sdma_state_s00_hw_down] = { 6398 .go_s99_running_tofalse = 1, 6399 .op_enable = 0, 6400 .op_intenable = 0, 6401 .op_halt = 0, 6402 .op_drain = 0, 6403 }, 6404 [qib_sdma_state_s10_hw_start_up_wait] = { 6405 .op_enable = 0, 6406 .op_intenable = 1, 6407 .op_halt = 1, 6408 .op_drain = 0, 6409 }, 6410 [qib_sdma_state_s20_idle] = { 6411 .op_enable = 1, 6412 .op_intenable = 1, 6413 .op_halt = 1, 6414 .op_drain = 0, 6415 }, 6416 [qib_sdma_state_s30_sw_clean_up_wait] = { 6417 .op_enable = 0, 6418 .op_intenable = 1, 6419 .op_halt = 1, 6420 .op_drain = 0, 6421 }, 6422 [qib_sdma_state_s40_hw_clean_up_wait] = { 6423 .op_enable = 1, 6424 .op_intenable = 1, 6425 .op_halt = 1, 6426 .op_drain = 0, 6427 }, 6428 [qib_sdma_state_s50_hw_halt_wait] = { 6429 .op_enable = 1, 6430 .op_intenable = 1, 6431 .op_halt = 1, 6432 .op_drain = 1, 6433 }, 6434 [qib_sdma_state_s99_running] = { 6435 .op_enable = 1, 6436 .op_intenable = 1, 6437 .op_halt = 0, 6438 .op_drain = 0, 6439 .go_s99_running_totrue = 1, 6440 }, 6441 }; 6442 6443 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd) 6444 { 6445 ppd->sdma_state.set_state_action = sdma_7322_action_table; 6446 } 6447 6448 static int init_sdma_7322_regs(struct qib_pportdata *ppd) 6449 { 6450 struct qib_devdata *dd = ppd->dd; 6451 unsigned lastbuf, erstbuf; 6452 u64 senddmabufmask[3] = { 0 }; 6453 int n, ret = 0; 6454 6455 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys); 6456 qib_sdma_7322_setlengen(ppd); 6457 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */ 6458 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt); 6459 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0); 6460 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys); 6461 6462 if (dd->num_pports) 6463 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ 6464 else 6465 n = dd->cspec->sdmabufcnt; /* failsafe for init */ 6466 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - 6467 ((dd->num_pports == 1 || ppd->port == 2) ? n : 6468 dd->cspec->sdmabufcnt); 6469 lastbuf = erstbuf + n; 6470 6471 ppd->sdma_state.first_sendbuf = erstbuf; 6472 ppd->sdma_state.last_sendbuf = lastbuf; 6473 for (; erstbuf < lastbuf; ++erstbuf) { 6474 unsigned word = erstbuf / BITS_PER_LONG; 6475 unsigned bit = erstbuf & (BITS_PER_LONG - 1); 6476 6477 BUG_ON(word >= 3); 6478 senddmabufmask[word] |= 1ULL << bit; 6479 } 6480 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]); 6481 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]); 6482 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]); 6483 return ret; 6484 } 6485 6486 /* sdma_lock must be held */ 6487 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd) 6488 { 6489 struct qib_devdata *dd = ppd->dd; 6490 int sane; 6491 int use_dmahead; 6492 u16 swhead; 6493 u16 swtail; 6494 u16 cnt; 6495 u16 hwhead; 6496 6497 use_dmahead = __qib_sdma_running(ppd) && 6498 (dd->flags & QIB_HAS_SDMA_TIMEOUT); 6499 retry: 6500 hwhead = use_dmahead ? 6501 (u16) le64_to_cpu(*ppd->sdma_head_dma) : 6502 (u16) qib_read_kreg_port(ppd, krp_senddmahead); 6503 6504 swhead = ppd->sdma_descq_head; 6505 swtail = ppd->sdma_descq_tail; 6506 cnt = ppd->sdma_descq_cnt; 6507 6508 if (swhead < swtail) 6509 /* not wrapped */ 6510 sane = (hwhead >= swhead) & (hwhead <= swtail); 6511 else if (swhead > swtail) 6512 /* wrapped around */ 6513 sane = ((hwhead >= swhead) && (hwhead < cnt)) || 6514 (hwhead <= swtail); 6515 else 6516 /* empty */ 6517 sane = (hwhead == swhead); 6518 6519 if (unlikely(!sane)) { 6520 if (use_dmahead) { 6521 /* try one more time, directly from the register */ 6522 use_dmahead = 0; 6523 goto retry; 6524 } 6525 /* proceed as if no progress */ 6526 hwhead = swhead; 6527 } 6528 6529 return hwhead; 6530 } 6531 6532 static int qib_sdma_7322_busy(struct qib_pportdata *ppd) 6533 { 6534 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus); 6535 6536 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) || 6537 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) || 6538 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) || 6539 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty)); 6540 } 6541 6542 /* 6543 * Compute the amount of delay before sending the next packet if the 6544 * port's send rate differs from the static rate set for the QP. 6545 * The delay affects the next packet and the amount of the delay is 6546 * based on the length of the this packet. 6547 */ 6548 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen, 6549 u8 srate, u8 vl) 6550 { 6551 u8 snd_mult = ppd->delay_mult; 6552 u8 rcv_mult = ib_rate_to_delay[srate]; 6553 u32 ret; 6554 6555 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0; 6556 6557 /* Indicate VL15, else set the VL in the control word */ 6558 if (vl == 15) 6559 ret |= PBC_7322_VL15_SEND_CTRL; 6560 else 6561 ret |= vl << PBC_VL_NUM_LSB; 6562 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB; 6563 6564 return ret; 6565 } 6566 6567 /* 6568 * Enable the per-port VL15 send buffers for use. 6569 * They follow the rest of the buffers, without a config parameter. 6570 * This was in initregs, but that is done before the shadow 6571 * is set up, and this has to be done after the shadow is 6572 * set up. 6573 */ 6574 static void qib_7322_initvl15_bufs(struct qib_devdata *dd) 6575 { 6576 unsigned vl15bufs; 6577 6578 vl15bufs = dd->piobcnt2k + dd->piobcnt4k; 6579 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS, 6580 TXCHK_CHG_TYPE_KERN, NULL); 6581 } 6582 6583 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd) 6584 { 6585 if (rcd->ctxt < NUM_IB_PORTS) { 6586 if (rcd->dd->num_pports > 1) { 6587 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2; 6588 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0; 6589 } else { 6590 rcd->rcvegrcnt = KCTXT0_EGRCNT; 6591 rcd->rcvegr_tid_base = 0; 6592 } 6593 } else { 6594 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; 6595 rcd->rcvegr_tid_base = KCTXT0_EGRCNT + 6596 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt; 6597 } 6598 } 6599 6600 #define QTXSLEEPS 5000 6601 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, 6602 u32 len, u32 which, struct qib_ctxtdata *rcd) 6603 { 6604 int i; 6605 const int last = start + len - 1; 6606 const int lastr = last / BITS_PER_LONG; 6607 u32 sleeps = 0; 6608 int wait = rcd != NULL; 6609 unsigned long flags; 6610 6611 while (wait) { 6612 unsigned long shadow; 6613 int cstart, previ = -1; 6614 6615 /* 6616 * when flipping from kernel to user, we can't change 6617 * the checking type if the buffer is allocated to the 6618 * driver. It's OK the other direction, because it's 6619 * from close, and we have just disarm'ed all the 6620 * buffers. All the kernel to kernel changes are also 6621 * OK. 6622 */ 6623 for (cstart = start; cstart <= last; cstart++) { 6624 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) 6625 / BITS_PER_LONG; 6626 if (i != previ) { 6627 shadow = (unsigned long) 6628 le64_to_cpu(dd->pioavailregs_dma[i]); 6629 previ = i; 6630 } 6631 if (test_bit(((2 * cstart) + 6632 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT) 6633 % BITS_PER_LONG, &shadow)) 6634 break; 6635 } 6636 6637 if (cstart > last) 6638 break; 6639 6640 if (sleeps == QTXSLEEPS) 6641 break; 6642 /* make sure we see an updated copy next time around */ 6643 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6644 sleeps++; 6645 msleep(20); 6646 } 6647 6648 switch (which) { 6649 case TXCHK_CHG_TYPE_DIS1: 6650 /* 6651 * disable checking on a range; used by diags; just 6652 * one buffer, but still written generically 6653 */ 6654 for (i = start; i <= last; i++) 6655 clear_bit(i, dd->cspec->sendchkenable); 6656 break; 6657 6658 case TXCHK_CHG_TYPE_ENAB1: 6659 /* 6660 * (re)enable checking on a range; used by diags; just 6661 * one buffer, but still written generically; read 6662 * scratch to be sure buffer actually triggered, not 6663 * just flushed from processor. 6664 */ 6665 qib_read_kreg32(dd, kr_scratch); 6666 for (i = start; i <= last; i++) 6667 set_bit(i, dd->cspec->sendchkenable); 6668 break; 6669 6670 case TXCHK_CHG_TYPE_KERN: 6671 /* usable by kernel */ 6672 for (i = start; i <= last; i++) { 6673 set_bit(i, dd->cspec->sendibchk); 6674 clear_bit(i, dd->cspec->sendgrhchk); 6675 } 6676 spin_lock_irqsave(&dd->uctxt_lock, flags); 6677 /* see if we need to raise avail update threshold */ 6678 for (i = dd->first_user_ctxt; 6679 dd->cspec->updthresh != dd->cspec->updthresh_dflt 6680 && i < dd->cfgctxts; i++) 6681 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && 6682 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) 6683 < dd->cspec->updthresh_dflt) 6684 break; 6685 spin_unlock_irqrestore(&dd->uctxt_lock, flags); 6686 if (i == dd->cfgctxts) { 6687 spin_lock_irqsave(&dd->sendctrl_lock, flags); 6688 dd->cspec->updthresh = dd->cspec->updthresh_dflt; 6689 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); 6690 dd->sendctrl |= (dd->cspec->updthresh & 6691 SYM_RMASK(SendCtrl, AvailUpdThld)) << 6692 SYM_LSB(SendCtrl, AvailUpdThld); 6693 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 6694 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6695 } 6696 break; 6697 6698 case TXCHK_CHG_TYPE_USER: 6699 /* for user process */ 6700 for (i = start; i <= last; i++) { 6701 clear_bit(i, dd->cspec->sendibchk); 6702 set_bit(i, dd->cspec->sendgrhchk); 6703 } 6704 spin_lock_irqsave(&dd->sendctrl_lock, flags); 6705 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt 6706 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { 6707 dd->cspec->updthresh = (rcd->piocnt / 6708 rcd->subctxt_cnt) - 1; 6709 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); 6710 dd->sendctrl |= (dd->cspec->updthresh & 6711 SYM_RMASK(SendCtrl, AvailUpdThld)) 6712 << SYM_LSB(SendCtrl, AvailUpdThld); 6713 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 6714 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6715 } else 6716 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 6717 break; 6718 6719 default: 6720 break; 6721 } 6722 6723 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i) 6724 qib_write_kreg(dd, kr_sendcheckmask + i, 6725 dd->cspec->sendchkenable[i]); 6726 6727 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) { 6728 qib_write_kreg(dd, kr_sendgrhcheckmask + i, 6729 dd->cspec->sendgrhchk[i]); 6730 qib_write_kreg(dd, kr_sendibpktmask + i, 6731 dd->cspec->sendibchk[i]); 6732 } 6733 6734 /* 6735 * Be sure whatever we did was seen by the chip and acted upon, 6736 * before we return. Mostly important for which >= 2. 6737 */ 6738 qib_read_kreg32(dd, kr_scratch); 6739 } 6740 6741 6742 /* useful for trigger analyzers, etc. */ 6743 static void writescratch(struct qib_devdata *dd, u32 val) 6744 { 6745 qib_write_kreg(dd, kr_scratch, val); 6746 } 6747 6748 /* Dummy for now, use chip regs soon */ 6749 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) 6750 { 6751 return -ENXIO; 6752 } 6753 6754 /** 6755 * qib_init_iba7322_funcs - set up the chip-specific function pointers 6756 * @dev: the pci_dev for qlogic_ib device 6757 * @ent: pci_device_id struct for this dev 6758 * 6759 * Also allocates, inits, and returns the devdata struct for this 6760 * device instance 6761 * 6762 * This is global, and is called directly at init to set up the 6763 * chip-specific function pointers for later use. 6764 */ 6765 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev, 6766 const struct pci_device_id *ent) 6767 { 6768 struct qib_devdata *dd; 6769 int ret, i; 6770 u32 tabsize, actual_cnt = 0; 6771 6772 dd = qib_alloc_devdata(pdev, 6773 NUM_IB_PORTS * sizeof(struct qib_pportdata) + 6774 sizeof(struct qib_chip_specific) + 6775 NUM_IB_PORTS * sizeof(struct qib_chippport_specific)); 6776 if (IS_ERR(dd)) 6777 goto bail; 6778 6779 dd->f_bringup_serdes = qib_7322_bringup_serdes; 6780 dd->f_cleanup = qib_setup_7322_cleanup; 6781 dd->f_clear_tids = qib_7322_clear_tids; 6782 dd->f_free_irq = qib_7322_free_irq; 6783 dd->f_get_base_info = qib_7322_get_base_info; 6784 dd->f_get_msgheader = qib_7322_get_msgheader; 6785 dd->f_getsendbuf = qib_7322_getsendbuf; 6786 dd->f_gpio_mod = gpio_7322_mod; 6787 dd->f_eeprom_wen = qib_7322_eeprom_wen; 6788 dd->f_hdrqempty = qib_7322_hdrqempty; 6789 dd->f_ib_updown = qib_7322_ib_updown; 6790 dd->f_init_ctxt = qib_7322_init_ctxt; 6791 dd->f_initvl15_bufs = qib_7322_initvl15_bufs; 6792 dd->f_intr_fallback = qib_7322_intr_fallback; 6793 dd->f_late_initreg = qib_late_7322_initreg; 6794 dd->f_setpbc_control = qib_7322_setpbc_control; 6795 dd->f_portcntr = qib_portcntr_7322; 6796 dd->f_put_tid = qib_7322_put_tid; 6797 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; 6798 dd->f_rcvctrl = rcvctrl_7322_mod; 6799 dd->f_read_cntrs = qib_read_7322cntrs; 6800 dd->f_read_portcntrs = qib_read_7322portcntrs; 6801 dd->f_reset = qib_do_7322_reset; 6802 dd->f_init_sdma_regs = init_sdma_7322_regs; 6803 dd->f_sdma_busy = qib_sdma_7322_busy; 6804 dd->f_sdma_gethead = qib_sdma_7322_gethead; 6805 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; 6806 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; 6807 dd->f_sdma_update_tail = qib_sdma_update_7322_tail; 6808 dd->f_sendctrl = sendctrl_7322_mod; 6809 dd->f_set_armlaunch = qib_set_7322_armlaunch; 6810 dd->f_set_cntr_sample = qib_set_cntr_7322_sample; 6811 dd->f_iblink_state = qib_7322_iblink_state; 6812 dd->f_ibphys_portstate = qib_7322_phys_portstate; 6813 dd->f_get_ib_cfg = qib_7322_get_ib_cfg; 6814 dd->f_set_ib_cfg = qib_7322_set_ib_cfg; 6815 dd->f_set_ib_loopback = qib_7322_set_loopback; 6816 dd->f_get_ib_table = qib_7322_get_ib_table; 6817 dd->f_set_ib_table = qib_7322_set_ib_table; 6818 dd->f_set_intr_state = qib_7322_set_intr_state; 6819 dd->f_setextled = qib_setup_7322_setextled; 6820 dd->f_txchk_change = qib_7322_txchk_change; 6821 dd->f_update_usrhead = qib_update_7322_usrhead; 6822 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; 6823 dd->f_xgxs_reset = qib_7322_mini_pcs_reset; 6824 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; 6825 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; 6826 dd->f_sdma_init_early = qib_7322_sdma_init_early; 6827 dd->f_writescratch = writescratch; 6828 dd->f_tempsense_rd = qib_7322_tempsense_rd; 6829 /* 6830 * Do remaining PCIe setup and save PCIe values in dd. 6831 * Any error printing is already done by the init code. 6832 * On return, we have the chip mapped, but chip registers 6833 * are not set up until start of qib_init_7322_variables. 6834 */ 6835 ret = qib_pcie_ddinit(dd, pdev, ent); 6836 if (ret < 0) 6837 goto bail_free; 6838 6839 /* initialize chip-specific variables */ 6840 ret = qib_init_7322_variables(dd); 6841 if (ret) 6842 goto bail_cleanup; 6843 6844 if (qib_mini_init || !dd->num_pports) 6845 goto bail; 6846 6847 /* 6848 * Determine number of vectors we want; depends on port count 6849 * and number of configured kernel receive queues actually used. 6850 * Should also depend on whether sdma is enabled or not, but 6851 * that's such a rare testing case it's not worth worrying about. 6852 */ 6853 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); 6854 for (i = 0; i < tabsize; i++) 6855 if ((i < ARRAY_SIZE(irq_table) && 6856 irq_table[i].port <= dd->num_pports) || 6857 (i >= ARRAY_SIZE(irq_table) && 6858 dd->rcd[i - ARRAY_SIZE(irq_table)])) 6859 actual_cnt++; 6860 /* reduce by ctxt's < 2 */ 6861 if (qib_krcvq01_no_msi) 6862 actual_cnt -= dd->num_pports; 6863 6864 tabsize = actual_cnt; 6865 dd->cspec->msix_entries = kmalloc(tabsize * 6866 sizeof(struct msix_entry), GFP_KERNEL); 6867 dd->cspec->msix_arg = kmalloc(tabsize * 6868 sizeof(void *), GFP_KERNEL); 6869 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) { 6870 qib_dev_err(dd, "No memory for MSIx table\n"); 6871 tabsize = 0; 6872 } 6873 for (i = 0; i < tabsize; i++) 6874 dd->cspec->msix_entries[i].entry = i; 6875 6876 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries)) 6877 qib_dev_err(dd, "Failed to setup PCIe or interrupts; " 6878 "continuing anyway\n"); 6879 /* may be less than we wanted, if not enough available */ 6880 dd->cspec->num_msix_entries = tabsize; 6881 6882 /* setup interrupt handler */ 6883 qib_setup_7322_interrupt(dd, 1); 6884 6885 /* clear diagctrl register, in case diags were running and crashed */ 6886 qib_write_kreg(dd, kr_hwdiagctrl, 0); 6887 6888 goto bail; 6889 6890 bail_cleanup: 6891 qib_pcie_ddcleanup(dd); 6892 bail_free: 6893 qib_free_devdata(dd); 6894 dd = ERR_PTR(ret); 6895 bail: 6896 return dd; 6897 } 6898 6899 /* 6900 * Set the table entry at the specified index from the table specifed. 6901 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first 6902 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR. 6903 * 'idx' below addresses the correct entry, while its 4 LSBs select the 6904 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table. 6905 */ 6906 #define DDS_ENT_AMP_LSB 14 6907 #define DDS_ENT_MAIN_LSB 9 6908 #define DDS_ENT_POST_LSB 5 6909 #define DDS_ENT_PRE_XTRA_LSB 3 6910 #define DDS_ENT_PRE_LSB 0 6911 6912 /* 6913 * Set one entry in the TxDDS table for spec'd port 6914 * ridx picks one of the entries, while tp points 6915 * to the appropriate table entry. 6916 */ 6917 static void set_txdds(struct qib_pportdata *ppd, int ridx, 6918 const struct txdds_ent *tp) 6919 { 6920 struct qib_devdata *dd = ppd->dd; 6921 u32 pack_ent; 6922 int regidx; 6923 6924 /* Get correct offset in chip-space, and in source table */ 6925 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx; 6926 /* 6927 * We do not use qib_write_kreg_port() because it was intended 6928 * only for registers in the lower "port specific" pages. 6929 * So do index calculation by hand. 6930 */ 6931 if (ppd->hw_pidx) 6932 regidx += (dd->palign / sizeof(u64)); 6933 6934 pack_ent = tp->amp << DDS_ENT_AMP_LSB; 6935 pack_ent |= tp->main << DDS_ENT_MAIN_LSB; 6936 pack_ent |= tp->pre << DDS_ENT_PRE_LSB; 6937 pack_ent |= tp->post << DDS_ENT_POST_LSB; 6938 qib_write_kreg(dd, regidx, pack_ent); 6939 /* Prevent back-to-back writes by hitting scratch */ 6940 qib_write_kreg(ppd->dd, kr_scratch, 0); 6941 } 6942 6943 static const struct vendor_txdds_ent vendor_txdds[] = { 6944 { /* Amphenol 1m 30awg NoEq */ 6945 { 0x41, 0x50, 0x48 }, "584470002 ", 6946 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 }, 6947 }, 6948 { /* Amphenol 3m 28awg NoEq */ 6949 { 0x41, 0x50, 0x48 }, "584470004 ", 6950 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 }, 6951 }, 6952 { /* Finisar 3m OM2 Optical */ 6953 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL", 6954 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 }, 6955 }, 6956 { /* Finisar 30m OM2 Optical */ 6957 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL", 6958 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 }, 6959 }, 6960 { /* Finisar Default OM2 Optical */ 6961 { 0x00, 0x90, 0x65 }, NULL, 6962 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 }, 6963 }, 6964 { /* Gore 1m 30awg NoEq */ 6965 { 0x00, 0x21, 0x77 }, "QSN3300-1 ", 6966 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 }, 6967 }, 6968 { /* Gore 2m 30awg NoEq */ 6969 { 0x00, 0x21, 0x77 }, "QSN3300-2 ", 6970 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 }, 6971 }, 6972 { /* Gore 1m 28awg NoEq */ 6973 { 0x00, 0x21, 0x77 }, "QSN3800-1 ", 6974 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 }, 6975 }, 6976 { /* Gore 3m 28awg NoEq */ 6977 { 0x00, 0x21, 0x77 }, "QSN3800-3 ", 6978 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 }, 6979 }, 6980 { /* Gore 5m 24awg Eq */ 6981 { 0x00, 0x21, 0x77 }, "QSN7000-5 ", 6982 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 }, 6983 }, 6984 { /* Gore 7m 24awg Eq */ 6985 { 0x00, 0x21, 0x77 }, "QSN7000-7 ", 6986 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 }, 6987 }, 6988 { /* Gore 5m 26awg Eq */ 6989 { 0x00, 0x21, 0x77 }, "QSN7600-5 ", 6990 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 }, 6991 }, 6992 { /* Gore 7m 26awg Eq */ 6993 { 0x00, 0x21, 0x77 }, "QSN7600-7 ", 6994 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 }, 6995 }, 6996 { /* Intersil 12m 24awg Active */ 6997 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224", 6998 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 }, 6999 }, 7000 { /* Intersil 10m 28awg Active */ 7001 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028", 7002 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 }, 7003 }, 7004 { /* Intersil 7m 30awg Active */ 7005 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730", 7006 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 }, 7007 }, 7008 { /* Intersil 5m 32awg Active */ 7009 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532", 7010 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 }, 7011 }, 7012 { /* Intersil Default Active */ 7013 { 0x00, 0x30, 0xB4 }, NULL, 7014 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 }, 7015 }, 7016 { /* Luxtera 20m Active Optical */ 7017 { 0x00, 0x25, 0x63 }, NULL, 7018 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 }, 7019 }, 7020 { /* Molex 1M Cu loopback */ 7021 { 0x00, 0x09, 0x3A }, "74763-0025 ", 7022 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, 7023 }, 7024 { /* Molex 2m 28awg NoEq */ 7025 { 0x00, 0x09, 0x3A }, "74757-2201 ", 7026 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 }, 7027 }, 7028 }; 7029 7030 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = { 7031 /* amp, pre, main, post */ 7032 { 2, 2, 15, 6 }, /* Loopback */ 7033 { 0, 0, 0, 1 }, /* 2 dB */ 7034 { 0, 0, 0, 2 }, /* 3 dB */ 7035 { 0, 0, 0, 3 }, /* 4 dB */ 7036 { 0, 0, 0, 4 }, /* 5 dB */ 7037 { 0, 0, 0, 5 }, /* 6 dB */ 7038 { 0, 0, 0, 6 }, /* 7 dB */ 7039 { 0, 0, 0, 7 }, /* 8 dB */ 7040 { 0, 0, 0, 8 }, /* 9 dB */ 7041 { 0, 0, 0, 9 }, /* 10 dB */ 7042 { 0, 0, 0, 10 }, /* 11 dB */ 7043 { 0, 0, 0, 11 }, /* 12 dB */ 7044 { 0, 0, 0, 12 }, /* 13 dB */ 7045 { 0, 0, 0, 13 }, /* 14 dB */ 7046 { 0, 0, 0, 14 }, /* 15 dB */ 7047 { 0, 0, 0, 15 }, /* 16 dB */ 7048 }; 7049 7050 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = { 7051 /* amp, pre, main, post */ 7052 { 2, 2, 15, 6 }, /* Loopback */ 7053 { 0, 0, 0, 8 }, /* 2 dB */ 7054 { 0, 0, 0, 8 }, /* 3 dB */ 7055 { 0, 0, 0, 9 }, /* 4 dB */ 7056 { 0, 0, 0, 9 }, /* 5 dB */ 7057 { 0, 0, 0, 10 }, /* 6 dB */ 7058 { 0, 0, 0, 10 }, /* 7 dB */ 7059 { 0, 0, 0, 11 }, /* 8 dB */ 7060 { 0, 0, 0, 11 }, /* 9 dB */ 7061 { 0, 0, 0, 12 }, /* 10 dB */ 7062 { 0, 0, 0, 12 }, /* 11 dB */ 7063 { 0, 0, 0, 13 }, /* 12 dB */ 7064 { 0, 0, 0, 13 }, /* 13 dB */ 7065 { 0, 0, 0, 14 }, /* 14 dB */ 7066 { 0, 0, 0, 14 }, /* 15 dB */ 7067 { 0, 0, 0, 15 }, /* 16 dB */ 7068 }; 7069 7070 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = { 7071 /* amp, pre, main, post */ 7072 { 2, 2, 15, 6 }, /* Loopback */ 7073 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */ 7074 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */ 7075 { 0, 1, 0, 11 }, /* 4 dB */ 7076 { 0, 1, 0, 13 }, /* 5 dB */ 7077 { 0, 1, 0, 15 }, /* 6 dB */ 7078 { 0, 1, 3, 15 }, /* 7 dB */ 7079 { 0, 1, 7, 15 }, /* 8 dB */ 7080 { 0, 1, 7, 15 }, /* 9 dB */ 7081 { 0, 1, 8, 15 }, /* 10 dB */ 7082 { 0, 1, 9, 15 }, /* 11 dB */ 7083 { 0, 1, 10, 15 }, /* 12 dB */ 7084 { 0, 2, 6, 15 }, /* 13 dB */ 7085 { 0, 2, 7, 15 }, /* 14 dB */ 7086 { 0, 2, 8, 15 }, /* 15 dB */ 7087 { 0, 2, 9, 15 }, /* 16 dB */ 7088 }; 7089 7090 /* 7091 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ. 7092 * These are mostly used for mez cards going through connectors 7093 * and backplane traces, but can be used to add other "unusual" 7094 * table values as well. 7095 */ 7096 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = { 7097 /* amp, pre, main, post */ 7098 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ 7099 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */ 7100 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ 7101 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */ 7102 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7103 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7104 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7105 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7106 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7107 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7108 { 0, 0, 0, 11 }, /* QME7342 backplane settings */ 7109 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */ 7110 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */ 7111 }; 7112 7113 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = { 7114 /* amp, pre, main, post */ 7115 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ 7116 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */ 7117 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ 7118 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */ 7119 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7120 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7121 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7122 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7123 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7124 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7125 { 0, 0, 0, 13 }, /* QME7342 backplane settings */ 7126 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */ 7127 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */ 7128 }; 7129 7130 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = { 7131 /* amp, pre, main, post */ 7132 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */ 7133 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */ 7134 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */ 7135 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */ 7136 { 0, 1, 12, 10 }, /* QME7342 backplane setting */ 7137 { 0, 1, 12, 11 }, /* QME7342 backplane setting */ 7138 { 0, 1, 12, 12 }, /* QME7342 backplane setting */ 7139 { 0, 1, 12, 14 }, /* QME7342 backplane setting */ 7140 { 0, 1, 12, 6 }, /* QME7342 backplane setting */ 7141 { 0, 1, 12, 7 }, /* QME7342 backplane setting */ 7142 { 0, 1, 12, 8 }, /* QME7342 backplane setting */ 7143 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */ 7144 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */ 7145 }; 7146 7147 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = { 7148 /* amp, pre, main, post */ 7149 { 0, 0, 0, 0 }, /* QME7342 mfg settings */ 7150 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */ 7151 }; 7152 7153 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, 7154 unsigned atten) 7155 { 7156 /* 7157 * The attenuation table starts at 2dB for entry 1, 7158 * with entry 0 being the loopback entry. 7159 */ 7160 if (atten <= 2) 7161 atten = 1; 7162 else if (atten > TXDDS_TABLE_SZ) 7163 atten = TXDDS_TABLE_SZ - 1; 7164 else 7165 atten--; 7166 return txdds + atten; 7167 } 7168 7169 /* 7170 * if override is set, the module parameter txselect has a value 7171 * for this specific port, so use it, rather than our normal mechanism. 7172 */ 7173 static void find_best_ent(struct qib_pportdata *ppd, 7174 const struct txdds_ent **sdr_dds, 7175 const struct txdds_ent **ddr_dds, 7176 const struct txdds_ent **qdr_dds, int override) 7177 { 7178 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache; 7179 int idx; 7180 7181 /* Search table of known cables */ 7182 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) { 7183 const struct vendor_txdds_ent *v = vendor_txdds + idx; 7184 7185 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) && 7186 (!v->partnum || 7187 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) { 7188 *sdr_dds = &v->sdr; 7189 *ddr_dds = &v->ddr; 7190 *qdr_dds = &v->qdr; 7191 return; 7192 } 7193 } 7194 7195 /* Active cables don't have attenuation so we only set SERDES 7196 * settings to account for the attenuation of the board traces. */ 7197 if (!override && QSFP_IS_ACTIVE(qd->tech)) { 7198 *sdr_dds = txdds_sdr + ppd->dd->board_atten; 7199 *ddr_dds = txdds_ddr + ppd->dd->board_atten; 7200 *qdr_dds = txdds_qdr + ppd->dd->board_atten; 7201 return; 7202 } 7203 7204 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] || 7205 qd->atten[1])) { 7206 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]); 7207 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]); 7208 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]); 7209 return; 7210 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) { 7211 /* 7212 * If we have no (or incomplete) data from the cable 7213 * EEPROM, or no QSFP, or override is set, use the 7214 * module parameter value to index into the attentuation 7215 * table. 7216 */ 7217 idx = ppd->cpspec->no_eep; 7218 *sdr_dds = &txdds_sdr[idx]; 7219 *ddr_dds = &txdds_ddr[idx]; 7220 *qdr_dds = &txdds_qdr[idx]; 7221 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) { 7222 /* similar to above, but index into the "extra" table. */ 7223 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ; 7224 *sdr_dds = &txdds_extra_sdr[idx]; 7225 *ddr_dds = &txdds_extra_ddr[idx]; 7226 *qdr_dds = &txdds_extra_qdr[idx]; 7227 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && 7228 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 7229 TXDDS_MFG_SZ)) { 7230 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); 7231 printk(KERN_INFO QIB_DRV_NAME 7232 " IB%u:%u use idx %u into txdds_mfg\n", 7233 ppd->dd->unit, ppd->port, idx); 7234 *sdr_dds = &txdds_extra_mfg[idx]; 7235 *ddr_dds = &txdds_extra_mfg[idx]; 7236 *qdr_dds = &txdds_extra_mfg[idx]; 7237 } else { 7238 /* this shouldn't happen, it's range checked */ 7239 *sdr_dds = txdds_sdr + qib_long_atten; 7240 *ddr_dds = txdds_ddr + qib_long_atten; 7241 *qdr_dds = txdds_qdr + qib_long_atten; 7242 } 7243 } 7244 7245 static void init_txdds_table(struct qib_pportdata *ppd, int override) 7246 { 7247 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; 7248 struct txdds_ent *dds; 7249 int idx; 7250 int single_ent = 0; 7251 7252 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override); 7253 7254 /* for mez cards or override, use the selected value for all entries */ 7255 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) 7256 single_ent = 1; 7257 7258 /* Fill in the first entry with the best entry found. */ 7259 set_txdds(ppd, 0, sdr_dds); 7260 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds); 7261 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds); 7262 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | 7263 QIBL_LINKACTIVE)) { 7264 dds = (struct txdds_ent *)(ppd->link_speed_active == 7265 QIB_IB_QDR ? qdr_dds : 7266 (ppd->link_speed_active == 7267 QIB_IB_DDR ? ddr_dds : sdr_dds)); 7268 write_tx_serdes_param(ppd, dds); 7269 } 7270 7271 /* Fill in the remaining entries with the default table values. */ 7272 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) { 7273 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx); 7274 set_txdds(ppd, idx + TXDDS_TABLE_SZ, 7275 single_ent ? ddr_dds : txdds_ddr + idx); 7276 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ, 7277 single_ent ? qdr_dds : txdds_qdr + idx); 7278 } 7279 } 7280 7281 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl) 7282 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg) 7283 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy) 7284 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address) 7285 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data) 7286 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read) 7287 #define AHB_TRANS_TRIES 10 7288 7289 /* 7290 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4, 7291 * 5=subsystem which is why most calls have "chan + chan >> 1" 7292 * for the channel argument. 7293 */ 7294 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, 7295 u32 data, u32 mask) 7296 { 7297 u32 rd_data, wr_data, sz_mask; 7298 u64 trans, acc, prev_acc; 7299 u32 ret = 0xBAD0BAD; 7300 int tries; 7301 7302 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC); 7303 /* From this point on, make sure we return access */ 7304 acc = (quad << 1) | 1; 7305 qib_write_kreg(dd, KR_AHB_ACC, acc); 7306 7307 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7308 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7309 if (trans & AHB_TRANS_RDY) 7310 break; 7311 } 7312 if (tries >= AHB_TRANS_TRIES) { 7313 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES); 7314 goto bail; 7315 } 7316 7317 /* If mask is not all 1s, we need to read, but different SerDes 7318 * entities have different sizes 7319 */ 7320 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1; 7321 wr_data = data & mask & sz_mask; 7322 if ((~mask & sz_mask) != 0) { 7323 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); 7324 qib_write_kreg(dd, KR_AHB_TRANS, trans); 7325 7326 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7327 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7328 if (trans & AHB_TRANS_RDY) 7329 break; 7330 } 7331 if (tries >= AHB_TRANS_TRIES) { 7332 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n", 7333 AHB_TRANS_TRIES); 7334 goto bail; 7335 } 7336 /* Re-read in case host split reads and read data first */ 7337 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7338 rd_data = (uint32_t)(trans >> AHB_DATA_LSB); 7339 wr_data |= (rd_data & ~mask & sz_mask); 7340 } 7341 7342 /* If mask is not zero, we need to write. */ 7343 if (mask & sz_mask) { 7344 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1); 7345 trans |= ((uint64_t)wr_data << AHB_DATA_LSB); 7346 trans |= AHB_WR; 7347 qib_write_kreg(dd, KR_AHB_TRANS, trans); 7348 7349 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) { 7350 trans = qib_read_kreg64(dd, KR_AHB_TRANS); 7351 if (trans & AHB_TRANS_RDY) 7352 break; 7353 } 7354 if (tries >= AHB_TRANS_TRIES) { 7355 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n", 7356 AHB_TRANS_TRIES); 7357 goto bail; 7358 } 7359 } 7360 ret = wr_data; 7361 bail: 7362 qib_write_kreg(dd, KR_AHB_ACC, prev_acc); 7363 return ret; 7364 } 7365 7366 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data, 7367 unsigned mask) 7368 { 7369 struct qib_devdata *dd = ppd->dd; 7370 int chan; 7371 u32 rbc; 7372 7373 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7374 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, 7375 data, mask); 7376 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7377 addr, 0, 0); 7378 } 7379 } 7380 7381 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable) 7382 { 7383 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl); 7384 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN); 7385 7386 if (enable && !state) { 7387 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS on\n", 7388 ppd->dd->unit, ppd->port); 7389 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7390 } else if (!enable && state) { 7391 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS off\n", 7392 ppd->dd->unit, ppd->port); 7393 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7394 } 7395 qib_write_kreg_port(ppd, krp_serdesctrl, data); 7396 } 7397 7398 static int serdes_7322_init(struct qib_pportdata *ppd) 7399 { 7400 int ret = 0; 7401 if (ppd->dd->cspec->r1) 7402 ret = serdes_7322_init_old(ppd); 7403 else 7404 ret = serdes_7322_init_new(ppd); 7405 return ret; 7406 } 7407 7408 static int serdes_7322_init_old(struct qib_pportdata *ppd) 7409 { 7410 u32 le_val; 7411 7412 /* 7413 * Initialize the Tx DDS tables. Also done every QSFP event, 7414 * for adapters with QSFP 7415 */ 7416 init_txdds_table(ppd, 0); 7417 7418 /* ensure no tx overrides from earlier driver loads */ 7419 qib_write_kreg_port(ppd, krp_tx_deemph_override, 7420 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7421 reset_tx_deemphasis_override)); 7422 7423 /* Patch some SerDes defaults to "Better for IB" */ 7424 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */ 7425 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 7426 7427 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 7428 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 7429 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */ 7430 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6)); 7431 7432 /* May be overridden in qsfp_7322_event */ 7433 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 7434 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 7435 7436 /* enable LE1 adaptation for all but QME, which is disabled */ 7437 le_val = IS_QME(ppd->dd) ? 0 : 1; 7438 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5)); 7439 7440 /* Clear cmode-override, may be set from older driver */ 7441 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7442 7443 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */ 7444 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8)); 7445 7446 /* setup LoS params; these are subsystem, so chan == 5 */ 7447 /* LoS filter threshold_count on, ch 0-3, set to 8 */ 7448 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 7449 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 7450 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 7451 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 7452 7453 /* LoS filter threshold_count off, ch 0-3, set to 4 */ 7454 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 7455 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 7456 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 7457 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 7458 7459 /* LoS filter select enabled */ 7460 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 7461 7462 /* LoS target data: SDR=4, DDR=2, QDR=1 */ 7463 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 7464 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7465 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7466 7467 serdes_7322_los_enable(ppd, 1); 7468 7469 /* rxbistena; set 0 to avoid effects of it switch later */ 7470 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15); 7471 7472 /* Configure 4 DFE taps, and only they adapt */ 7473 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0)); 7474 7475 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 7476 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 7477 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 7478 7479 /* 7480 * Set receive adaptation mode. SDR and DDR adaptation are 7481 * always on, and QDR is initially enabled; later disabled. 7482 */ 7483 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 7484 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 7485 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 7486 ppd->dd->cspec->r1 ? 7487 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 7488 ppd->cpspec->qdr_dfe_on = 1; 7489 7490 /* FLoop LOS gate: PPM filter enabled */ 7491 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 7492 7493 /* rx offset center enabled */ 7494 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4); 7495 7496 if (!ppd->dd->cspec->r1) { 7497 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12); 7498 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8); 7499 } 7500 7501 /* Set the frequency loop bandwidth to 15 */ 7502 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5)); 7503 7504 return 0; 7505 } 7506 7507 static int serdes_7322_init_new(struct qib_pportdata *ppd) 7508 { 7509 u64 tstart; 7510 u32 le_val, rxcaldone; 7511 int chan, chan_done = (1 << SERDES_CHANS) - 1; 7512 7513 /* Clear cmode-override, may be set from older driver */ 7514 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7515 7516 /* ensure no tx overrides from earlier driver loads */ 7517 qib_write_kreg_port(ppd, krp_tx_deemph_override, 7518 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7519 reset_tx_deemphasis_override)); 7520 7521 /* START OF LSI SUGGESTED SERDES BRINGUP */ 7522 /* Reset - Calibration Setup */ 7523 /* Stop DFE adaptaion */ 7524 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1)); 7525 /* Disable LE1 */ 7526 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5)); 7527 /* Disable autoadapt for LE1 */ 7528 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15)); 7529 /* Disable LE2 */ 7530 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6)); 7531 /* Disable VGA */ 7532 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7533 /* Disable AFE Offset Cancel */ 7534 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12)); 7535 /* Disable Timing Loop */ 7536 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3)); 7537 /* Disable Frequency Loop */ 7538 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4)); 7539 /* Disable Baseline Wander Correction */ 7540 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13)); 7541 /* Disable RX Calibration */ 7542 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7543 /* Disable RX Offset Calibration */ 7544 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4)); 7545 /* Select BB CDR */ 7546 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15)); 7547 /* CDR Step Size */ 7548 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8)); 7549 /* Enable phase Calibration */ 7550 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5)); 7551 /* DFE Bandwidth [2:14-12] */ 7552 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12)); 7553 /* DFE Config (4 taps only) */ 7554 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0)); 7555 /* Gain Loop Bandwidth */ 7556 if (!ppd->dd->cspec->r1) { 7557 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12)); 7558 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8)); 7559 } else { 7560 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11)); 7561 } 7562 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */ 7563 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */ 7564 /* Data Rate Select [5:7-6] (leave as default) */ 7565 /* RX Parallel Word Width [3:10-8] (leave as default) */ 7566 7567 /* RX REST */ 7568 /* Single- or Multi-channel reset */ 7569 /* RX Analog reset */ 7570 /* RX Digital reset */ 7571 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13)); 7572 msleep(20); 7573 /* RX Analog reset */ 7574 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14)); 7575 msleep(20); 7576 /* RX Digital reset */ 7577 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13)); 7578 msleep(20); 7579 7580 /* setup LoS params; these are subsystem, so chan == 5 */ 7581 /* LoS filter threshold_count on, ch 0-3, set to 8 */ 7582 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 7583 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 7584 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 7585 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 7586 7587 /* LoS filter threshold_count off, ch 0-3, set to 4 */ 7588 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 7589 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 7590 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 7591 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 7592 7593 /* LoS filter select enabled */ 7594 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 7595 7596 /* LoS target data: SDR=4, DDR=2, QDR=1 */ 7597 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 7598 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7599 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7600 7601 /* Turn on LOS on initial SERDES init */ 7602 serdes_7322_los_enable(ppd, 1); 7603 /* FLoop LOS gate: PPM filter enabled */ 7604 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 7605 7606 /* RX LATCH CALIBRATION */ 7607 /* Enable Eyefinder Phase Calibration latch */ 7608 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0)); 7609 /* Enable RX Offset Calibration latch */ 7610 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4)); 7611 msleep(20); 7612 /* Start Calibration */ 7613 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10)); 7614 tstart = get_jiffies_64(); 7615 while (chan_done && 7616 !time_after64(get_jiffies_64(), 7617 tstart + msecs_to_jiffies(500))) { 7618 msleep(20); 7619 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7620 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 7621 (chan + (chan >> 1)), 7622 25, 0, 0); 7623 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 && 7624 (~chan_done & (1 << chan)) == 0) 7625 chan_done &= ~(1 << chan); 7626 } 7627 } 7628 if (chan_done) { 7629 printk(KERN_INFO QIB_DRV_NAME 7630 " Serdes %d calibration not done after .5 sec: 0x%x\n", 7631 IBSD(ppd->hw_pidx), chan_done); 7632 } else { 7633 for (chan = 0; chan < SERDES_CHANS; ++chan) { 7634 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 7635 (chan + (chan >> 1)), 7636 25, 0, 0); 7637 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0) 7638 printk(KERN_INFO QIB_DRV_NAME 7639 " Serdes %d chan %d calibration " 7640 "failed\n", IBSD(ppd->hw_pidx), chan); 7641 } 7642 } 7643 7644 /* Turn off Calibration */ 7645 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7646 msleep(20); 7647 7648 /* BRING RX UP */ 7649 /* Set LE2 value (May be overridden in qsfp_7322_event) */ 7650 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 7651 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 7652 /* Set LE2 Loop bandwidth */ 7653 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5)); 7654 /* Enable LE2 */ 7655 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6)); 7656 msleep(20); 7657 /* Enable H0 only */ 7658 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1)); 7659 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 7660 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 7661 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 7662 /* Enable VGA */ 7663 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7664 msleep(20); 7665 /* Set Frequency Loop Bandwidth */ 7666 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5)); 7667 /* Enable Frequency Loop */ 7668 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4)); 7669 /* Set Timing Loop Bandwidth */ 7670 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 7671 /* Enable Timing Loop */ 7672 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3)); 7673 msleep(50); 7674 /* Enable DFE 7675 * Set receive adaptation mode. SDR and DDR adaptation are 7676 * always on, and QDR is initially enabled; later disabled. 7677 */ 7678 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 7679 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 7680 qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 7681 ppd->dd->cspec->r1 ? 7682 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 7683 ppd->cpspec->qdr_dfe_on = 1; 7684 /* Disable LE1 */ 7685 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5)); 7686 /* Disable auto adapt for LE1 */ 7687 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15)); 7688 msleep(20); 7689 /* Enable AFE Offset Cancel */ 7690 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12)); 7691 /* Enable Baseline Wander Correction */ 7692 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13)); 7693 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 7694 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 7695 /* VGA output common mode */ 7696 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2)); 7697 7698 /* 7699 * Initialize the Tx DDS tables. Also done every QSFP event, 7700 * for adapters with QSFP 7701 */ 7702 init_txdds_table(ppd, 0); 7703 7704 return 0; 7705 } 7706 7707 /* start adjust QMH serdes parameters */ 7708 7709 static void set_man_code(struct qib_pportdata *ppd, int chan, int code) 7710 { 7711 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7712 9, code << 9, 0x3f << 9); 7713 } 7714 7715 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan, 7716 int enable, u32 tapenable) 7717 { 7718 if (enable) 7719 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7720 1, 3 << 10, 0x1f << 10); 7721 else 7722 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7723 1, 0, 0x1f << 10); 7724 } 7725 7726 /* Set clock to 1, 0, 1, 0 */ 7727 static void clock_man(struct qib_pportdata *ppd, int chan) 7728 { 7729 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7730 4, 0x4000, 0x4000); 7731 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7732 4, 0, 0x4000); 7733 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7734 4, 0x4000, 0x4000); 7735 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), 7736 4, 0, 0x4000); 7737 } 7738 7739 /* 7740 * write the current Tx serdes pre,post,main,amp settings into the serdes. 7741 * The caller must pass the settings appropriate for the current speed, 7742 * or not care if they are correct for the current speed. 7743 */ 7744 static void write_tx_serdes_param(struct qib_pportdata *ppd, 7745 struct txdds_ent *txdds) 7746 { 7747 u64 deemph; 7748 7749 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override); 7750 /* field names for amp, main, post, pre, respectively */ 7751 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) | 7752 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) | 7753 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) | 7754 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena)); 7755 7756 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7757 tx_override_deemphasis_select); 7758 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7759 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7760 txampcntl_d2a); 7761 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7762 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7763 txc0_ena); 7764 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7765 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7766 txcp1_ena); 7767 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7768 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7769 txcn1_ena); 7770 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph); 7771 } 7772 7773 /* 7774 * Set the parameters for mez cards on link bounce, so they are 7775 * always exactly what was requested. Similar logic to init_txdds 7776 * but does just the serdes. 7777 */ 7778 static void adj_tx_serdes(struct qib_pportdata *ppd) 7779 { 7780 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds; 7781 struct txdds_ent *dds; 7782 7783 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1); 7784 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ? 7785 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ? 7786 ddr_dds : sdr_dds)); 7787 write_tx_serdes_param(ppd, dds); 7788 } 7789 7790 /* set QDR forced value for H1, if needed */ 7791 static void force_h1(struct qib_pportdata *ppd) 7792 { 7793 int chan; 7794 7795 ppd->cpspec->qdr_reforce = 0; 7796 if (!ppd->dd->cspec->r1) 7797 return; 7798 7799 for (chan = 0; chan < SERDES_CHANS; chan++) { 7800 set_man_mode_h1(ppd, chan, 1, 0); 7801 set_man_code(ppd, chan, ppd->cpspec->h1_val); 7802 clock_man(ppd, chan); 7803 set_man_mode_h1(ppd, chan, 0, 0); 7804 } 7805 } 7806 7807 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN) 7808 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en) 7809 7810 #define R_OPCODE_LSB 3 7811 #define R_OP_NOP 0 7812 #define R_OP_SHIFT 2 7813 #define R_OP_UPDATE 3 7814 #define R_TDI_LSB 2 7815 #define R_TDO_LSB 1 7816 #define R_RDY 1 7817 7818 static int qib_r_grab(struct qib_devdata *dd) 7819 { 7820 u64 val; 7821 val = SJA_EN; 7822 qib_write_kreg(dd, kr_r_access, val); 7823 qib_read_kreg32(dd, kr_scratch); 7824 return 0; 7825 } 7826 7827 /* qib_r_wait_for_rdy() not only waits for the ready bit, it 7828 * returns the current state of R_TDO 7829 */ 7830 static int qib_r_wait_for_rdy(struct qib_devdata *dd) 7831 { 7832 u64 val; 7833 int timeout; 7834 for (timeout = 0; timeout < 100 ; ++timeout) { 7835 val = qib_read_kreg32(dd, kr_r_access); 7836 if (val & R_RDY) 7837 return (val >> R_TDO_LSB) & 1; 7838 } 7839 return -1; 7840 } 7841 7842 static int qib_r_shift(struct qib_devdata *dd, int bisten, 7843 int len, u8 *inp, u8 *outp) 7844 { 7845 u64 valbase, val; 7846 int ret, pos; 7847 7848 valbase = SJA_EN | (bisten << BISTEN_LSB) | 7849 (R_OP_SHIFT << R_OPCODE_LSB); 7850 ret = qib_r_wait_for_rdy(dd); 7851 if (ret < 0) 7852 goto bail; 7853 for (pos = 0; pos < len; ++pos) { 7854 val = valbase; 7855 if (outp) { 7856 outp[pos >> 3] &= ~(1 << (pos & 7)); 7857 outp[pos >> 3] |= (ret << (pos & 7)); 7858 } 7859 if (inp) { 7860 int tdi = inp[pos >> 3] >> (pos & 7); 7861 val |= ((tdi & 1) << R_TDI_LSB); 7862 } 7863 qib_write_kreg(dd, kr_r_access, val); 7864 qib_read_kreg32(dd, kr_scratch); 7865 ret = qib_r_wait_for_rdy(dd); 7866 if (ret < 0) 7867 break; 7868 } 7869 /* Restore to NOP between operations. */ 7870 val = SJA_EN | (bisten << BISTEN_LSB); 7871 qib_write_kreg(dd, kr_r_access, val); 7872 qib_read_kreg32(dd, kr_scratch); 7873 ret = qib_r_wait_for_rdy(dd); 7874 7875 if (ret >= 0) 7876 ret = pos; 7877 bail: 7878 return ret; 7879 } 7880 7881 static int qib_r_update(struct qib_devdata *dd, int bisten) 7882 { 7883 u64 val; 7884 int ret; 7885 7886 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB); 7887 ret = qib_r_wait_for_rdy(dd); 7888 if (ret >= 0) { 7889 qib_write_kreg(dd, kr_r_access, val); 7890 qib_read_kreg32(dd, kr_scratch); 7891 } 7892 return ret; 7893 } 7894 7895 #define BISTEN_PORT_SEL 15 7896 #define LEN_PORT_SEL 625 7897 #define BISTEN_AT 17 7898 #define LEN_AT 156 7899 #define BISTEN_ETM 16 7900 #define LEN_ETM 632 7901 7902 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE) 7903 7904 /* these are common for all IB port use cases. */ 7905 static u8 reset_at[BIT2BYTE(LEN_AT)] = { 7906 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7907 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 7908 }; 7909 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = { 7910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7912 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e, 7913 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7, 7914 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70, 7915 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00, 7916 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7917 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 7918 }; 7919 static u8 at[BIT2BYTE(LEN_AT)] = { 7920 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 7921 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 7922 }; 7923 7924 /* used for IB1 or IB2, only one in use */ 7925 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = { 7926 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7927 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7928 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7929 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00, 7930 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7931 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03, 7932 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00, 7933 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, 7934 }; 7935 7936 /* used when both IB1 and IB2 are in use */ 7937 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = { 7938 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 7940 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 7941 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05, 7942 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 7943 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07, 7944 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00, 7945 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 7946 }; 7947 7948 /* used when only IB1 is in use */ 7949 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = { 7950 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, 7951 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, 7952 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7953 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7954 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, 7955 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 7956 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 7957 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 7958 }; 7959 7960 /* used when only IB2 is in use */ 7961 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = { 7962 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39, 7963 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32, 7964 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 7965 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 7966 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32, 7967 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 7968 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 7969 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 7970 }; 7971 7972 /* used when both IB1 and IB2 are in use */ 7973 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = { 7974 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13, 7975 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c, 7976 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7977 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 7978 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32, 7979 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a, 7980 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 7981 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 7982 }; 7983 7984 /* 7985 * Do setup to properly handle IB link recovery; if port is zero, we 7986 * are initializing to cover both ports; otherwise we are initializing 7987 * to cover a single port card, or the port has reached INIT and we may 7988 * need to switch coverage types. 7989 */ 7990 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both) 7991 { 7992 u8 *portsel, *etm; 7993 struct qib_devdata *dd = ppd->dd; 7994 7995 if (!ppd->dd->cspec->r1) 7996 return; 7997 if (!both) { 7998 dd->cspec->recovery_ports_initted++; 7999 ppd->cpspec->recovery_init = 1; 8000 } 8001 if (!both && dd->cspec->recovery_ports_initted == 1) { 8002 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2; 8003 etm = atetm_1port; 8004 } else { 8005 portsel = portsel_2port; 8006 etm = atetm_2port; 8007 } 8008 8009 if (qib_r_grab(dd) < 0 || 8010 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 || 8011 qib_r_update(dd, BISTEN_ETM) < 0 || 8012 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 || 8013 qib_r_update(dd, BISTEN_AT) < 0 || 8014 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL, 8015 portsel, NULL) < 0 || 8016 qib_r_update(dd, BISTEN_PORT_SEL) < 0 || 8017 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 || 8018 qib_r_update(dd, BISTEN_AT) < 0 || 8019 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 || 8020 qib_r_update(dd, BISTEN_ETM) < 0) 8021 qib_dev_err(dd, "Failed IB link recovery setup\n"); 8022 } 8023 8024 static void check_7322_rxe_status(struct qib_pportdata *ppd) 8025 { 8026 struct qib_devdata *dd = ppd->dd; 8027 u64 fmask; 8028 8029 if (dd->cspec->recovery_ports_initted != 1) 8030 return; /* rest doesn't apply to dualport */ 8031 qib_write_kreg(dd, kr_control, dd->control | 8032 SYM_MASK(Control, FreezeMode)); 8033 (void)qib_read_kreg64(dd, kr_scratch); 8034 udelay(3); /* ibcreset asserted 400ns, be sure that's over */ 8035 fmask = qib_read_kreg64(dd, kr_act_fmask); 8036 if (!fmask) { 8037 /* 8038 * require a powercycle before we'll work again, and make 8039 * sure we get no more interrupts, and don't turn off 8040 * freeze. 8041 */ 8042 ppd->dd->cspec->stay_in_freeze = 1; 8043 qib_7322_set_intr_state(ppd->dd, 0); 8044 qib_write_kreg(dd, kr_fmask, 0ULL); 8045 qib_dev_err(dd, "HCA unusable until powercycled\n"); 8046 return; /* eventually reset */ 8047 } 8048 8049 qib_write_kreg(ppd->dd, kr_hwerrclear, 8050 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1)); 8051 8052 /* don't do the full clear_freeze(), not needed for this */ 8053 qib_write_kreg(dd, kr_control, dd->control); 8054 qib_read_kreg32(dd, kr_scratch); 8055 /* take IBC out of reset */ 8056 if (ppd->link_speed_supported) { 8057 ppd->cpspec->ibcctrl_a &= 8058 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn); 8059 qib_write_kreg_port(ppd, krp_ibcctrl_a, 8060 ppd->cpspec->ibcctrl_a); 8061 qib_read_kreg32(dd, kr_scratch); 8062 if (ppd->lflags & QIBL_IB_LINK_DISABLED) 8063 qib_set_ib_7322_lstate(ppd, 0, 8064 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 8065 } 8066 } 8067