1 /*
2  * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
3  * All rights reserved.
4  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 /*
35  * This file contains all of the code that is specific to the
36  * QLogic_IB 7220 chip (except that specific to the SerDes)
37  */
38 
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/module.h>
43 #include <linux/io.h>
44 #include <rdma/ib_verbs.h>
45 
46 #include "qib.h"
47 #include "qib_7220.h"
48 
49 static void qib_setup_7220_setextled(struct qib_pportdata *, u32);
50 static void qib_7220_handle_hwerrors(struct qib_devdata *, char *, size_t);
51 static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op);
52 static u32 qib_7220_iblink_state(u64);
53 static u8 qib_7220_phys_portstate(u64);
54 static void qib_sdma_update_7220_tail(struct qib_pportdata *, u16);
55 static void qib_set_ib_7220_lstate(struct qib_pportdata *, u16, u16);
56 
57 /*
58  * This file contains almost all the chip-specific register information and
59  * access functions for the QLogic QLogic_IB 7220 PCI-Express chip, with the
60  * exception of SerDes support, which in in qib_sd7220.c.
61  */
62 
63 /* Below uses machine-generated qib_chipnum_regs.h file */
64 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
65 
66 /* Use defines to tie machine-generated names to lower-case names */
67 #define kr_control KREG_IDX(Control)
68 #define kr_counterregbase KREG_IDX(CntrRegBase)
69 #define kr_errclear KREG_IDX(ErrClear)
70 #define kr_errmask KREG_IDX(ErrMask)
71 #define kr_errstatus KREG_IDX(ErrStatus)
72 #define kr_extctrl KREG_IDX(EXTCtrl)
73 #define kr_extstatus KREG_IDX(EXTStatus)
74 #define kr_gpio_clear KREG_IDX(GPIOClear)
75 #define kr_gpio_mask KREG_IDX(GPIOMask)
76 #define kr_gpio_out KREG_IDX(GPIOOut)
77 #define kr_gpio_status KREG_IDX(GPIOStatus)
78 #define kr_hrtbt_guid KREG_IDX(HRTBT_GUID)
79 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
80 #define kr_hwerrclear KREG_IDX(HwErrClear)
81 #define kr_hwerrmask KREG_IDX(HwErrMask)
82 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
83 #define kr_ibcctrl KREG_IDX(IBCCtrl)
84 #define kr_ibcddrctrl KREG_IDX(IBCDDRCtrl)
85 #define kr_ibcddrstatus KREG_IDX(IBCDDRStatus)
86 #define kr_ibcstatus KREG_IDX(IBCStatus)
87 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
88 #define kr_intclear KREG_IDX(IntClear)
89 #define kr_intmask KREG_IDX(IntMask)
90 #define kr_intstatus KREG_IDX(IntStatus)
91 #define kr_ncmodectrl KREG_IDX(IBNCModeCtrl)
92 #define kr_palign KREG_IDX(PageAlign)
93 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
94 #define kr_portcnt KREG_IDX(PortCnt)
95 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
96 #define kr_rcvctrl KREG_IDX(RcvCtrl)
97 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
98 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
99 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
100 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
101 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
102 #define kr_rcvpktledcnt KREG_IDX(RcvPktLEDCnt)
103 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
104 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
105 #define kr_revision KREG_IDX(Revision)
106 #define kr_scratch KREG_IDX(Scratch)
107 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
108 #define kr_sendctrl KREG_IDX(SendCtrl)
109 #define kr_senddmabase KREG_IDX(SendDmaBase)
110 #define kr_senddmabufmask0 KREG_IDX(SendDmaBufMask0)
111 #define kr_senddmabufmask1 (KREG_IDX(SendDmaBufMask0) + 1)
112 #define kr_senddmabufmask2 (KREG_IDX(SendDmaBufMask0) + 2)
113 #define kr_senddmahead KREG_IDX(SendDmaHead)
114 #define kr_senddmaheadaddr KREG_IDX(SendDmaHeadAddr)
115 #define kr_senddmalengen KREG_IDX(SendDmaLenGen)
116 #define kr_senddmastatus KREG_IDX(SendDmaStatus)
117 #define kr_senddmatail KREG_IDX(SendDmaTail)
118 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
119 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
120 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
121 #define kr_sendpiosize KREG_IDX(SendBufSize)
122 #define kr_sendregbase KREG_IDX(SendRegBase)
123 #define kr_userregbase KREG_IDX(UserRegBase)
124 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
125 
126 /* These must only be written via qib_write_kreg_ctxt() */
127 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
128 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
129 
130 
131 #define CREG_IDX(regname) ((QIB_7220_##regname##_OFFS - \
132 			QIB_7220_LBIntCnt_OFFS) / sizeof(u64))
133 
134 #define cr_badformat CREG_IDX(RxVersionErrCnt)
135 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
136 #define cr_errlink CREG_IDX(RxLinkMalformCnt)
137 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
138 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
139 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlViolCnt)
140 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
141 #define cr_errslen CREG_IDX(TxLenErrCnt)
142 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
143 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
144 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
145 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
146 #define cr_lbint CREG_IDX(LBIntCnt)
147 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
148 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
149 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
150 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
151 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
152 #define cr_pktsend CREG_IDX(TxDataPktCnt)
153 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
154 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
155 #define cr_rcvebp CREG_IDX(RxEBPCnt)
156 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
157 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
158 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
159 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
160 #define cr_wordrcv CREG_IDX(RxDwordCnt)
161 #define cr_wordsend CREG_IDX(TxDwordCnt)
162 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
163 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
164 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
165 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
166 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
167 #define cr_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
168 #define cr_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
169 #define cr_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
170 #define cr_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
171 #define cr_rxvlerr CREG_IDX(RxVlErrCnt)
172 #define cr_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
173 #define cr_psstat CREG_IDX(PSStat)
174 #define cr_psstart CREG_IDX(PSStart)
175 #define cr_psinterval CREG_IDX(PSInterval)
176 #define cr_psrcvdatacount CREG_IDX(PSRcvDataCount)
177 #define cr_psrcvpktscount CREG_IDX(PSRcvPktsCount)
178 #define cr_psxmitdatacount CREG_IDX(PSXmitDataCount)
179 #define cr_psxmitpktscount CREG_IDX(PSXmitPktsCount)
180 #define cr_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
181 #define cr_txsdmadesc CREG_IDX(TxSDmaDescCnt)
182 #define cr_pcieretrydiag CREG_IDX(PcieRetryBufDiagQwordCnt)
183 
184 #define SYM_RMASK(regname, fldname) ((u64)              \
185 	QIB_7220_##regname##_##fldname##_RMASK)
186 #define SYM_MASK(regname, fldname) ((u64)               \
187 	QIB_7220_##regname##_##fldname##_RMASK <<       \
188 	 QIB_7220_##regname##_##fldname##_LSB)
189 #define SYM_LSB(regname, fldname) (QIB_7220_##regname##_##fldname##_LSB)
190 #define SYM_FIELD(value, regname, fldname) ((u64) \
191 	(((value) >> SYM_LSB(regname, fldname)) & \
192 	 SYM_RMASK(regname, fldname)))
193 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
194 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
195 
196 /* ibcctrl bits */
197 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
198 /* cycle through TS1/TS2 till OK */
199 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
200 /* wait for TS1, then go on */
201 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
202 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
203 
204 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1           /* move to 0x11 */
205 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2          /* move to 0x21 */
206 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
207 
208 #define BLOB_7220_IBCHG 0x81
209 
210 /*
211  * We could have a single register get/put routine, that takes a group type,
212  * but this is somewhat clearer and cleaner.  It also gives us some error
213  * checking.  64 bit register reads should always work, but are inefficient
214  * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
215  * so we use kreg32 wherever possible.  User register and counter register
216  * reads are always 32 bit reads, so only one form of those routines.
217  */
218 
219 /**
220  * qib_read_ureg32 - read 32-bit virtualized per-context register
221  * @dd: device
222  * @regno: register number
223  * @ctxt: context number
224  *
225  * Return the contents of a register that is virtualized to be per context.
226  * Returns -1 on errors (not distinguishable from valid contents at
227  * runtime; we may add a separate error variable at some point).
228  */
229 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
230 				  enum qib_ureg regno, int ctxt)
231 {
232 	if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
233 		return 0;
234 
235 	if (dd->userbase)
236 		return readl(regno + (u64 __iomem *)
237 			     ((char __iomem *)dd->userbase +
238 			      dd->ureg_align * ctxt));
239 	else
240 		return readl(regno + (u64 __iomem *)
241 			     (dd->uregbase +
242 			      (char __iomem *)dd->kregbase +
243 			      dd->ureg_align * ctxt));
244 }
245 
246 /**
247  * qib_write_ureg - write 32-bit virtualized per-context register
248  * @dd: device
249  * @regno: register number
250  * @value: value
251  * @ctxt: context
252  *
253  * Write the contents of a register that is virtualized to be per context.
254  */
255 static inline void qib_write_ureg(const struct qib_devdata *dd,
256 				  enum qib_ureg regno, u64 value, int ctxt)
257 {
258 	u64 __iomem *ubase;
259 
260 	if (dd->userbase)
261 		ubase = (u64 __iomem *)
262 			((char __iomem *) dd->userbase +
263 			 dd->ureg_align * ctxt);
264 	else
265 		ubase = (u64 __iomem *)
266 			(dd->uregbase +
267 			 (char __iomem *) dd->kregbase +
268 			 dd->ureg_align * ctxt);
269 
270 	if (dd->kregbase && (dd->flags & QIB_PRESENT))
271 		writeq(value, &ubase[regno]);
272 }
273 
274 /**
275  * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
276  * @dd: the qlogic_ib device
277  * @regno: the register number to write
278  * @ctxt: the context containing the register
279  * @value: the value to write
280  */
281 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
282 				       const u16 regno, unsigned ctxt,
283 				       u64 value)
284 {
285 	qib_write_kreg(dd, regno + ctxt, value);
286 }
287 
288 static inline void write_7220_creg(const struct qib_devdata *dd,
289 				   u16 regno, u64 value)
290 {
291 	if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
292 		writeq(value, &dd->cspec->cregbase[regno]);
293 }
294 
295 static inline u64 read_7220_creg(const struct qib_devdata *dd, u16 regno)
296 {
297 	if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
298 		return 0;
299 	return readq(&dd->cspec->cregbase[regno]);
300 }
301 
302 static inline u32 read_7220_creg32(const struct qib_devdata *dd, u16 regno)
303 {
304 	if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
305 		return 0;
306 	return readl(&dd->cspec->cregbase[regno]);
307 }
308 
309 /* kr_revision bits */
310 #define QLOGIC_IB_R_EMULATORREV_MASK ((1ULL << 22) - 1)
311 #define QLOGIC_IB_R_EMULATORREV_SHIFT 40
312 
313 /* kr_control bits */
314 #define QLOGIC_IB_C_RESET (1U << 7)
315 
316 /* kr_intstatus, kr_intclear, kr_intmask bits */
317 #define QLOGIC_IB_I_RCVURG_MASK ((1ULL << 17) - 1)
318 #define QLOGIC_IB_I_RCVURG_SHIFT 32
319 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1ULL << 17) - 1)
320 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 0
321 #define QLOGIC_IB_I_SERDESTRIMDONE (1ULL << 27)
322 
323 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
324 #define QLOGIC_IB_C_LINKENABLE 0x00000004
325 
326 #define QLOGIC_IB_I_SDMAINT             0x8000000000000000ULL
327 #define QLOGIC_IB_I_SDMADISABLED        0x4000000000000000ULL
328 #define QLOGIC_IB_I_ERROR               0x0000000080000000ULL
329 #define QLOGIC_IB_I_SPIOSENT            0x0000000040000000ULL
330 #define QLOGIC_IB_I_SPIOBUFAVAIL        0x0000000020000000ULL
331 #define QLOGIC_IB_I_GPIO                0x0000000010000000ULL
332 
333 /* variables for sanity checking interrupt and errors */
334 #define QLOGIC_IB_I_BITSEXTANT \
335 		(QLOGIC_IB_I_SDMAINT | QLOGIC_IB_I_SDMADISABLED | \
336 		(QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
337 		(QLOGIC_IB_I_RCVAVAIL_MASK << \
338 		 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
339 		QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
340 		QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO | \
341 		QLOGIC_IB_I_SERDESTRIMDONE)
342 
343 #define IB_HWE_BITSEXTANT \
344 	       (HWE_MASK(RXEMemParityErr) | \
345 		HWE_MASK(TXEMemParityErr) | \
346 		(QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<	 \
347 		 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
348 		QLOGIC_IB_HWE_PCIE1PLLFAILED | \
349 		QLOGIC_IB_HWE_PCIE0PLLFAILED | \
350 		QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
351 		QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
352 		QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
353 		QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
354 		QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
355 		HWE_MASK(PowerOnBISTFailed) |	  \
356 		QLOGIC_IB_HWE_COREPLL_FBSLIP | \
357 		QLOGIC_IB_HWE_COREPLL_RFSLIP | \
358 		QLOGIC_IB_HWE_SERDESPLLFAILED | \
359 		HWE_MASK(IBCBusToSPCParityErr) | \
360 		HWE_MASK(IBCBusFromSPCParityErr) | \
361 		QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR | \
362 		QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR | \
363 		QLOGIC_IB_HWE_SDMAMEMREADERR | \
364 		QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED | \
365 		QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT | \
366 		QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT | \
367 		QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT | \
368 		QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT | \
369 		QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR | \
370 		QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR | \
371 		QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR | \
372 		QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR)
373 
374 #define IB_E_BITSEXTANT							\
375 	(ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) |		\
376 	 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) |		\
377 	 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) |	\
378 	 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
379 	 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) |		\
380 	 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) |		\
381 	 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) |		\
382 	 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) |		\
383 	 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) |		\
384 	 ERR_MASK(SendSpecialTriggerErr) |				\
385 	 ERR_MASK(SDmaDisabledErr) | ERR_MASK(SendMinPktLenErr) |	\
386 	 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnderRunErr) |	\
387 	 ERR_MASK(SendPktLenErr) | ERR_MASK(SendDroppedSmpPktErr) |	\
388 	 ERR_MASK(SendDroppedDataPktErr) |				\
389 	 ERR_MASK(SendPioArmLaunchErr) |				\
390 	 ERR_MASK(SendUnexpectedPktNumErr) |				\
391 	 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(SendBufMisuseErr) |	\
392 	 ERR_MASK(SDmaGenMismatchErr) | ERR_MASK(SDmaOutOfBoundErr) |	\
393 	 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) |	\
394 	 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) |		\
395 	 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) |		\
396 	 ERR_MASK(SDmaUnexpDataErr) |					\
397 	 ERR_MASK(IBStatusChanged) | ERR_MASK(InvalidAddrErr) |		\
398 	 ERR_MASK(ResetNegated) | ERR_MASK(HardwareErr) |		\
399 	 ERR_MASK(SDmaDescAddrMisalignErr) |				\
400 	 ERR_MASK(InvalidEEPCmd))
401 
402 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
403 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK  0x00000000000000ffULL
404 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
405 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
406 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
407 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
408 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
409 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
410 #define QLOGIC_IB_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
411 #define QLOGIC_IB_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
412 #define QLOGIC_IB_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
413 #define QLOGIC_IB_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
414 #define QLOGIC_IB_HWE_SERDESPLLFAILED      0x1000000000000000ULL
415 /* specific to this chip */
416 #define QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR         0x0000000000000040ULL
417 #define QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR          0x0000000000000080ULL
418 #define QLOGIC_IB_HWE_SDMAMEMREADERR              0x0000000010000000ULL
419 #define QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED          0x2000000000000000ULL
420 #define QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT   0x0100000000000000ULL
421 #define QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT   0x0200000000000000ULL
422 #define QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT   0x0400000000000000ULL
423 #define QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT   0x0800000000000000ULL
424 #define QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR       0x0000008000000000ULL
425 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR        0x0000004000000000ULL
426 #define QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
427 #define QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
428 
429 #define IBA7220_IBCC_LINKCMD_SHIFT 19
430 
431 /* kr_ibcddrctrl bits */
432 #define IBA7220_IBC_DLIDLMC_MASK        0xFFFFFFFFUL
433 #define IBA7220_IBC_DLIDLMC_SHIFT       32
434 
435 #define IBA7220_IBC_HRTBT_MASK  (SYM_RMASK(IBCDDRCtrl, HRTBT_AUTO) | \
436 				 SYM_RMASK(IBCDDRCtrl, HRTBT_ENB))
437 #define IBA7220_IBC_HRTBT_SHIFT SYM_LSB(IBCDDRCtrl, HRTBT_ENB)
438 
439 #define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
440 #define IBA7220_IBC_LREV_MASK   1
441 #define IBA7220_IBC_LREV_SHIFT  8
442 #define IBA7220_IBC_RXPOL_MASK  1
443 #define IBA7220_IBC_RXPOL_SHIFT 7
444 #define IBA7220_IBC_WIDTH_SHIFT 5
445 #define IBA7220_IBC_WIDTH_MASK  0x3
446 #define IBA7220_IBC_WIDTH_1X_ONLY       (0 << IBA7220_IBC_WIDTH_SHIFT)
447 #define IBA7220_IBC_WIDTH_4X_ONLY       (1 << IBA7220_IBC_WIDTH_SHIFT)
448 #define IBA7220_IBC_WIDTH_AUTONEG       (2 << IBA7220_IBC_WIDTH_SHIFT)
449 #define IBA7220_IBC_SPEED_AUTONEG       (1 << 1)
450 #define IBA7220_IBC_SPEED_SDR           (1 << 2)
451 #define IBA7220_IBC_SPEED_DDR           (1 << 3)
452 #define IBA7220_IBC_SPEED_AUTONEG_MASK  (0x7 << 1)
453 #define IBA7220_IBC_IBTA_1_2_MASK       (1)
454 
455 /* kr_ibcddrstatus */
456 /* link latency shift is 0, don't bother defining */
457 #define IBA7220_DDRSTAT_LINKLAT_MASK    0x3ffffff
458 
459 /* kr_extstatus bits */
460 #define QLOGIC_IB_EXTS_FREQSEL 0x2
461 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
462 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST     0x0000000000004000
463 #define QLOGIC_IB_EXTS_MEMBIST_DISABLED    0x0000000000008000
464 
465 /* kr_xgxsconfig bits */
466 #define QLOGIC_IB_XGXS_RESET          0x5ULL
467 #define QLOGIC_IB_XGXS_FC_SAFE        (1ULL << 63)
468 
469 /* kr_rcvpktledcnt */
470 #define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
471 #define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
472 
473 #define _QIB_GPIO_SDA_NUM 1
474 #define _QIB_GPIO_SCL_NUM 0
475 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7220 cards. */
476 #define QIB_TWSI_TEMP_DEV 0x98
477 
478 /* HW counter clock is at 4nsec */
479 #define QIB_7220_PSXMITWAIT_CHECK_RATE 4000
480 
481 #define IBA7220_R_INTRAVAIL_SHIFT 17
482 #define IBA7220_R_PKEY_DIS_SHIFT 34
483 #define IBA7220_R_TAILUPD_SHIFT 35
484 #define IBA7220_R_CTXTCFG_SHIFT 36
485 
486 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
487 
488 /*
489  * the size bits give us 2^N, in KB units.  0 marks as invalid,
490  * and 7 is reserved.  We currently use only 2KB and 4KB
491  */
492 #define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
493 #define IBA7220_TID_SZ_2K (1UL << IBA7220_TID_SZ_SHIFT) /* 2KB */
494 #define IBA7220_TID_SZ_4K (2UL << IBA7220_TID_SZ_SHIFT) /* 4KB */
495 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
496 #define PBC_7220_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
497 #define PBC_7220_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
498 
499 #define AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
500 
501 /* packet rate matching delay multiplier */
502 static u8 rate_to_delay[2][2] = {
503 	/* 1x, 4x */
504 	{   8, 2 }, /* SDR */
505 	{   4, 1 }  /* DDR */
506 };
507 
508 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
509 	[IB_RATE_2_5_GBPS] = 8,
510 	[IB_RATE_5_GBPS] = 4,
511 	[IB_RATE_10_GBPS] = 2,
512 	[IB_RATE_20_GBPS] = 1
513 };
514 
515 #define IBA7220_LINKSPEED_SHIFT SYM_LSB(IBCStatus, LinkSpeedActive)
516 #define IBA7220_LINKWIDTH_SHIFT SYM_LSB(IBCStatus, LinkWidthActive)
517 
518 /* link training states, from IBC */
519 #define IB_7220_LT_STATE_DISABLED        0x00
520 #define IB_7220_LT_STATE_LINKUP          0x01
521 #define IB_7220_LT_STATE_POLLACTIVE      0x02
522 #define IB_7220_LT_STATE_POLLQUIET       0x03
523 #define IB_7220_LT_STATE_SLEEPDELAY      0x04
524 #define IB_7220_LT_STATE_SLEEPQUIET      0x05
525 #define IB_7220_LT_STATE_CFGDEBOUNCE     0x08
526 #define IB_7220_LT_STATE_CFGRCVFCFG      0x09
527 #define IB_7220_LT_STATE_CFGWAITRMT      0x0a
528 #define IB_7220_LT_STATE_CFGIDLE 0x0b
529 #define IB_7220_LT_STATE_RECOVERRETRAIN  0x0c
530 #define IB_7220_LT_STATE_RECOVERWAITRMT  0x0e
531 #define IB_7220_LT_STATE_RECOVERIDLE     0x0f
532 
533 /* link state machine states from IBC */
534 #define IB_7220_L_STATE_DOWN             0x0
535 #define IB_7220_L_STATE_INIT             0x1
536 #define IB_7220_L_STATE_ARM              0x2
537 #define IB_7220_L_STATE_ACTIVE           0x3
538 #define IB_7220_L_STATE_ACT_DEFER        0x4
539 
540 static const u8 qib_7220_physportstate[0x20] = {
541 	[IB_7220_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
542 	[IB_7220_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
543 	[IB_7220_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
544 	[IB_7220_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
545 	[IB_7220_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
546 	[IB_7220_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
547 	[IB_7220_LT_STATE_CFGDEBOUNCE] =
548 		IB_PHYSPORTSTATE_CFG_TRAIN,
549 	[IB_7220_LT_STATE_CFGRCVFCFG] =
550 		IB_PHYSPORTSTATE_CFG_TRAIN,
551 	[IB_7220_LT_STATE_CFGWAITRMT] =
552 		IB_PHYSPORTSTATE_CFG_TRAIN,
553 	[IB_7220_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN,
554 	[IB_7220_LT_STATE_RECOVERRETRAIN] =
555 		IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
556 	[IB_7220_LT_STATE_RECOVERWAITRMT] =
557 		IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
558 	[IB_7220_LT_STATE_RECOVERIDLE] =
559 		IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
560 	[0x10] = IB_PHYSPORTSTATE_CFG_TRAIN,
561 	[0x11] = IB_PHYSPORTSTATE_CFG_TRAIN,
562 	[0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
563 	[0x13] = IB_PHYSPORTSTATE_CFG_TRAIN,
564 	[0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
565 	[0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
566 	[0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
567 	[0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
568 };
569 
570 int qib_special_trigger;
571 module_param_named(special_trigger, qib_special_trigger, int, S_IRUGO);
572 MODULE_PARM_DESC(special_trigger, "Enable SpecialTrigger arm/launch");
573 
574 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
575 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
576 
577 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
578 	(1ULL << (SYM_LSB(regname, fldname) + (bit))))
579 
580 #define TXEMEMPARITYERR_PIOBUF \
581 	SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
582 #define TXEMEMPARITYERR_PIOPBC \
583 	SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
584 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
585 	SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
586 
587 #define RXEMEMPARITYERR_RCVBUF \
588 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
589 #define RXEMEMPARITYERR_LOOKUPQ \
590 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
591 #define RXEMEMPARITYERR_EXPTID \
592 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
593 #define RXEMEMPARITYERR_EAGERTID \
594 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
595 #define RXEMEMPARITYERR_FLAGBUF \
596 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
597 #define RXEMEMPARITYERR_DATAINFO \
598 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
599 #define RXEMEMPARITYERR_HDRINFO \
600 	SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
601 
602 /* 7220 specific hardware errors... */
603 static const struct qib_hwerror_msgs qib_7220_hwerror_msgs[] = {
604 	/* generic hardware errors */
605 	QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"),
606 	QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"),
607 
608 	QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF,
609 			  "TXE PIOBUF Memory Parity"),
610 	QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC,
611 			  "TXE PIOPBC Memory Parity"),
612 	QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO,
613 			  "TXE PIOLAUNCHFIFO Memory Parity"),
614 
615 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF,
616 			  "RXE RCVBUF Memory Parity"),
617 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ,
618 			  "RXE LOOKUPQ Memory Parity"),
619 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID,
620 			  "RXE EAGERTID Memory Parity"),
621 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID,
622 			  "RXE EXPTID Memory Parity"),
623 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF,
624 			  "RXE FLAGBUF Memory Parity"),
625 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO,
626 			  "RXE DATAINFO Memory Parity"),
627 	QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO,
628 			  "RXE HDRINFO Memory Parity"),
629 
630 	/* chip-specific hardware errors */
631 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP,
632 			  "PCIe Poisoned TLP"),
633 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT,
634 			  "PCIe completion timeout"),
635 	/*
636 	 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
637 	 * parity or memory parity error failures, because most likely we
638 	 * won't be able to talk to the core of the chip.  Nonetheless, we
639 	 * might see them, if they are in parts of the PCIe core that aren't
640 	 * essential.
641 	 */
642 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED,
643 			  "PCIePLL1"),
644 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED,
645 			  "PCIePLL0"),
646 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH,
647 			  "PCIe XTLH core parity"),
648 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM,
649 			  "PCIe ADM TX core parity"),
650 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM,
651 			  "PCIe ADM RX core parity"),
652 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED,
653 			  "SerDes PLL"),
654 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR,
655 			  "PCIe cpl header queue"),
656 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR,
657 			  "PCIe cpl data queue"),
658 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SDMAMEMREADERR,
659 			  "Send DMA memory read"),
660 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED,
661 			  "uC PLL clock not locked"),
662 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT,
663 			  "PCIe serdes Q0 no clock"),
664 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT,
665 			  "PCIe serdes Q1 no clock"),
666 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT,
667 			  "PCIe serdes Q2 no clock"),
668 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT,
669 			  "PCIe serdes Q3 no clock"),
670 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR,
671 			  "DDS RXEQ memory parity"),
672 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR,
673 			  "IB uC memory parity"),
674 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR,
675 			  "PCIe uC oct0 memory parity"),
676 	QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR,
677 			  "PCIe uC oct1 memory parity"),
678 };
679 
680 #define RXE_PARITY (RXEMEMPARITYERR_EAGERTID|RXEMEMPARITYERR_EXPTID)
681 
682 #define QLOGIC_IB_E_PKTERRS (\
683 		ERR_MASK(SendPktLenErr) |				\
684 		ERR_MASK(SendDroppedDataPktErr) |			\
685 		ERR_MASK(RcvVCRCErr) |					\
686 		ERR_MASK(RcvICRCErr) |					\
687 		ERR_MASK(RcvShortPktLenErr) |				\
688 		ERR_MASK(RcvEBPErr))
689 
690 /* Convenience for decoding Send DMA errors */
691 #define QLOGIC_IB_E_SDMAERRS ( \
692 		ERR_MASK(SDmaGenMismatchErr) |				\
693 		ERR_MASK(SDmaOutOfBoundErr) |				\
694 		ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
695 		ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) |	\
696 		ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) |	\
697 		ERR_MASK(SDmaUnexpDataErr) |				\
698 		ERR_MASK(SDmaDescAddrMisalignErr) |			\
699 		ERR_MASK(SDmaDisabledErr) |				\
700 		ERR_MASK(SendBufMisuseErr))
701 
702 /* These are all rcv-related errors which we want to count for stats */
703 #define E_SUM_PKTERRS \
704 	(ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) |		\
705 	 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) |		\
706 	 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) |	\
707 	 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) |	\
708 	 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) |	\
709 	 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
710 
711 /* These are all send-related errors which we want to count for stats */
712 #define E_SUM_ERRS \
713 	(ERR_MASK(SendPioArmLaunchErr) | ERR_MASK(SendUnexpectedPktNumErr) | \
714 	 ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
715 	 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) |	\
716 	 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) |		\
717 	 ERR_MASK(InvalidAddrErr))
718 
719 /*
720  * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
721  * errors not related to freeze and cancelling buffers.  Can't ignore
722  * armlaunch because could get more while still cleaning up, and need
723  * to cancel those as they happen.
724  */
725 #define E_SPKT_ERRS_IGNORE \
726 	(ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
727 	 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) |	\
728 	 ERR_MASK(SendPktLenErr))
729 
730 /*
731  * these are errors that can occur when the link changes state while
732  * a packet is being sent or received.  This doesn't cover things
733  * like EBP or VCRC that can be the result of a sending having the
734  * link change state, so we receive a "known bad" packet.
735  */
736 #define E_SUM_LINK_PKTERRS \
737 	(ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
738 	 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) |		\
739 	 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) |	\
740 	 ERR_MASK(RcvUnexpectedCharErr))
741 
742 static void autoneg_7220_work(struct work_struct *);
743 static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *, u64, u32 *);
744 
745 /*
746  * Called when we might have an error that is specific to a particular
747  * PIO buffer, and may need to cancel that buffer, so it can be re-used.
748  * because we don't need to force the update of pioavail.
749  */
750 static void qib_disarm_7220_senderrbufs(struct qib_pportdata *ppd)
751 {
752 	unsigned long sbuf[3];
753 	struct qib_devdata *dd = ppd->dd;
754 
755 	/*
756 	 * It's possible that sendbuffererror could have bits set; might
757 	 * have already done this as a result of hardware error handling.
758 	 */
759 	/* read these before writing errorclear */
760 	sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
761 	sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
762 	sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
763 
764 	if (sbuf[0] || sbuf[1] || sbuf[2])
765 		qib_disarm_piobufs_set(dd, sbuf,
766 				       dd->piobcnt2k + dd->piobcnt4k);
767 }
768 
769 static void qib_7220_txe_recover(struct qib_devdata *dd)
770 {
771 	qib_devinfo(dd->pcidev, "Recovering from TXE PIO parity error\n");
772 	qib_disarm_7220_senderrbufs(dd->pport);
773 }
774 
775 /*
776  * This is called with interrupts disabled and sdma_lock held.
777  */
778 static void qib_7220_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
779 {
780 	struct qib_devdata *dd = ppd->dd;
781 	u64 set_sendctrl = 0;
782 	u64 clr_sendctrl = 0;
783 
784 	if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
785 		set_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
786 	else
787 		clr_sendctrl |= SYM_MASK(SendCtrl, SDmaEnable);
788 
789 	if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
790 		set_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
791 	else
792 		clr_sendctrl |= SYM_MASK(SendCtrl, SDmaIntEnable);
793 
794 	if (op & QIB_SDMA_SENDCTRL_OP_HALT)
795 		set_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
796 	else
797 		clr_sendctrl |= SYM_MASK(SendCtrl, SDmaHalt);
798 
799 	spin_lock(&dd->sendctrl_lock);
800 
801 	dd->sendctrl |= set_sendctrl;
802 	dd->sendctrl &= ~clr_sendctrl;
803 
804 	qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
805 	qib_write_kreg(dd, kr_scratch, 0);
806 
807 	spin_unlock(&dd->sendctrl_lock);
808 }
809 
810 static void qib_decode_7220_sdma_errs(struct qib_pportdata *ppd,
811 				      u64 err, char *buf, size_t blen)
812 {
813 	static const struct {
814 		u64 err;
815 		const char *msg;
816 	} errs[] = {
817 		{ ERR_MASK(SDmaGenMismatchErr),
818 		  "SDmaGenMismatch" },
819 		{ ERR_MASK(SDmaOutOfBoundErr),
820 		  "SDmaOutOfBound" },
821 		{ ERR_MASK(SDmaTailOutOfBoundErr),
822 		  "SDmaTailOutOfBound" },
823 		{ ERR_MASK(SDmaBaseErr),
824 		  "SDmaBase" },
825 		{ ERR_MASK(SDma1stDescErr),
826 		  "SDma1stDesc" },
827 		{ ERR_MASK(SDmaRpyTagErr),
828 		  "SDmaRpyTag" },
829 		{ ERR_MASK(SDmaDwEnErr),
830 		  "SDmaDwEn" },
831 		{ ERR_MASK(SDmaMissingDwErr),
832 		  "SDmaMissingDw" },
833 		{ ERR_MASK(SDmaUnexpDataErr),
834 		  "SDmaUnexpData" },
835 		{ ERR_MASK(SDmaDescAddrMisalignErr),
836 		  "SDmaDescAddrMisalign" },
837 		{ ERR_MASK(SendBufMisuseErr),
838 		  "SendBufMisuse" },
839 		{ ERR_MASK(SDmaDisabledErr),
840 		  "SDmaDisabled" },
841 	};
842 	int i;
843 	size_t bidx = 0;
844 
845 	for (i = 0; i < ARRAY_SIZE(errs); i++) {
846 		if (err & errs[i].err)
847 			bidx += scnprintf(buf + bidx, blen - bidx,
848 					 "%s ", errs[i].msg);
849 	}
850 }
851 
852 /*
853  * This is called as part of link down clean up so disarm and flush
854  * all send buffers so that SMP packets can be sent.
855  */
856 static void qib_7220_sdma_hw_clean_up(struct qib_pportdata *ppd)
857 {
858 	/* This will trigger the Abort interrupt */
859 	sendctrl_7220_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH |
860 			  QIB_SENDCTRL_AVAIL_BLIP);
861 	ppd->dd->upd_pio_shadow  = 1; /* update our idea of what's busy */
862 }
863 
864 static void qib_sdma_7220_setlengen(struct qib_pportdata *ppd)
865 {
866 	/*
867 	 * Set SendDmaLenGen and clear and set
868 	 * the MSB of the generation count to enable generation checking
869 	 * and load the internal generation counter.
870 	 */
871 	qib_write_kreg(ppd->dd, kr_senddmalengen, ppd->sdma_descq_cnt);
872 	qib_write_kreg(ppd->dd, kr_senddmalengen,
873 		       ppd->sdma_descq_cnt |
874 		       (1ULL << QIB_7220_SendDmaLenGen_Generation_MSB));
875 }
876 
877 static void qib_7220_sdma_hw_start_up(struct qib_pportdata *ppd)
878 {
879 	qib_sdma_7220_setlengen(ppd);
880 	qib_sdma_update_7220_tail(ppd, 0); /* Set SendDmaTail */
881 	ppd->sdma_head_dma[0] = 0;
882 }
883 
884 #define DISABLES_SDMA (							\
885 		ERR_MASK(SDmaDisabledErr) |				\
886 		ERR_MASK(SDmaBaseErr) |					\
887 		ERR_MASK(SDmaTailOutOfBoundErr) |			\
888 		ERR_MASK(SDmaOutOfBoundErr) |				\
889 		ERR_MASK(SDma1stDescErr) |				\
890 		ERR_MASK(SDmaRpyTagErr) |				\
891 		ERR_MASK(SDmaGenMismatchErr) |				\
892 		ERR_MASK(SDmaDescAddrMisalignErr) |			\
893 		ERR_MASK(SDmaMissingDwErr) |				\
894 		ERR_MASK(SDmaDwEnErr))
895 
896 static void sdma_7220_errors(struct qib_pportdata *ppd, u64 errs)
897 {
898 	unsigned long flags;
899 	struct qib_devdata *dd = ppd->dd;
900 	char *msg;
901 
902 	errs &= QLOGIC_IB_E_SDMAERRS;
903 
904 	msg = dd->cspec->sdmamsgbuf;
905 	qib_decode_7220_sdma_errs(ppd, errs, msg,
906 		sizeof(dd->cspec->sdmamsgbuf));
907 	spin_lock_irqsave(&ppd->sdma_lock, flags);
908 
909 	if (errs & ERR_MASK(SendBufMisuseErr)) {
910 		unsigned long sbuf[3];
911 
912 		sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
913 		sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
914 		sbuf[2] = qib_read_kreg64(dd, kr_sendbuffererror + 2);
915 
916 		qib_dev_err(ppd->dd,
917 			    "IB%u:%u SendBufMisuse: %04lx %016lx %016lx\n",
918 			    ppd->dd->unit, ppd->port, sbuf[2], sbuf[1],
919 			    sbuf[0]);
920 	}
921 
922 	if (errs & ERR_MASK(SDmaUnexpDataErr))
923 		qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", ppd->dd->unit,
924 			    ppd->port);
925 
926 	switch (ppd->sdma_state.current_state) {
927 	case qib_sdma_state_s00_hw_down:
928 		/* not expecting any interrupts */
929 		break;
930 
931 	case qib_sdma_state_s10_hw_start_up_wait:
932 		/* handled in intr path */
933 		break;
934 
935 	case qib_sdma_state_s20_idle:
936 		/* not expecting any interrupts */
937 		break;
938 
939 	case qib_sdma_state_s30_sw_clean_up_wait:
940 		/* not expecting any interrupts */
941 		break;
942 
943 	case qib_sdma_state_s40_hw_clean_up_wait:
944 		if (errs & ERR_MASK(SDmaDisabledErr))
945 			__qib_sdma_process_event(ppd,
946 				qib_sdma_event_e50_hw_cleaned);
947 		break;
948 
949 	case qib_sdma_state_s50_hw_halt_wait:
950 		/* handled in intr path */
951 		break;
952 
953 	case qib_sdma_state_s99_running:
954 		if (errs & DISABLES_SDMA)
955 			__qib_sdma_process_event(ppd,
956 				qib_sdma_event_e7220_err_halted);
957 		break;
958 	}
959 
960 	spin_unlock_irqrestore(&ppd->sdma_lock, flags);
961 }
962 
963 /*
964  * Decode the error status into strings, deciding whether to always
965  * print * it or not depending on "normal packet errors" vs everything
966  * else.   Return 1 if "real" errors, otherwise 0 if only packet
967  * errors, so caller can decide what to print with the string.
968  */
969 static int qib_decode_7220_err(struct qib_devdata *dd, char *buf, size_t blen,
970 			       u64 err)
971 {
972 	int iserr = 1;
973 
974 	*buf = '\0';
975 	if (err & QLOGIC_IB_E_PKTERRS) {
976 		if (!(err & ~QLOGIC_IB_E_PKTERRS))
977 			iserr = 0;
978 		if ((err & ERR_MASK(RcvICRCErr)) &&
979 		    !(err & (ERR_MASK(RcvVCRCErr) | ERR_MASK(RcvEBPErr))))
980 			strlcat(buf, "CRC ", blen);
981 		if (!iserr)
982 			goto done;
983 	}
984 	if (err & ERR_MASK(RcvHdrLenErr))
985 		strlcat(buf, "rhdrlen ", blen);
986 	if (err & ERR_MASK(RcvBadTidErr))
987 		strlcat(buf, "rbadtid ", blen);
988 	if (err & ERR_MASK(RcvBadVersionErr))
989 		strlcat(buf, "rbadversion ", blen);
990 	if (err & ERR_MASK(RcvHdrErr))
991 		strlcat(buf, "rhdr ", blen);
992 	if (err & ERR_MASK(SendSpecialTriggerErr))
993 		strlcat(buf, "sendspecialtrigger ", blen);
994 	if (err & ERR_MASK(RcvLongPktLenErr))
995 		strlcat(buf, "rlongpktlen ", blen);
996 	if (err & ERR_MASK(RcvMaxPktLenErr))
997 		strlcat(buf, "rmaxpktlen ", blen);
998 	if (err & ERR_MASK(RcvMinPktLenErr))
999 		strlcat(buf, "rminpktlen ", blen);
1000 	if (err & ERR_MASK(SendMinPktLenErr))
1001 		strlcat(buf, "sminpktlen ", blen);
1002 	if (err & ERR_MASK(RcvFormatErr))
1003 		strlcat(buf, "rformaterr ", blen);
1004 	if (err & ERR_MASK(RcvUnsupportedVLErr))
1005 		strlcat(buf, "runsupvl ", blen);
1006 	if (err & ERR_MASK(RcvUnexpectedCharErr))
1007 		strlcat(buf, "runexpchar ", blen);
1008 	if (err & ERR_MASK(RcvIBFlowErr))
1009 		strlcat(buf, "ribflow ", blen);
1010 	if (err & ERR_MASK(SendUnderRunErr))
1011 		strlcat(buf, "sunderrun ", blen);
1012 	if (err & ERR_MASK(SendPioArmLaunchErr))
1013 		strlcat(buf, "spioarmlaunch ", blen);
1014 	if (err & ERR_MASK(SendUnexpectedPktNumErr))
1015 		strlcat(buf, "sunexperrpktnum ", blen);
1016 	if (err & ERR_MASK(SendDroppedSmpPktErr))
1017 		strlcat(buf, "sdroppedsmppkt ", blen);
1018 	if (err & ERR_MASK(SendMaxPktLenErr))
1019 		strlcat(buf, "smaxpktlen ", blen);
1020 	if (err & ERR_MASK(SendUnsupportedVLErr))
1021 		strlcat(buf, "sunsupVL ", blen);
1022 	if (err & ERR_MASK(InvalidAddrErr))
1023 		strlcat(buf, "invalidaddr ", blen);
1024 	if (err & ERR_MASK(RcvEgrFullErr))
1025 		strlcat(buf, "rcvegrfull ", blen);
1026 	if (err & ERR_MASK(RcvHdrFullErr))
1027 		strlcat(buf, "rcvhdrfull ", blen);
1028 	if (err & ERR_MASK(IBStatusChanged))
1029 		strlcat(buf, "ibcstatuschg ", blen);
1030 	if (err & ERR_MASK(RcvIBLostLinkErr))
1031 		strlcat(buf, "riblostlink ", blen);
1032 	if (err & ERR_MASK(HardwareErr))
1033 		strlcat(buf, "hardware ", blen);
1034 	if (err & ERR_MASK(ResetNegated))
1035 		strlcat(buf, "reset ", blen);
1036 	if (err & QLOGIC_IB_E_SDMAERRS)
1037 		qib_decode_7220_sdma_errs(dd->pport, err, buf, blen);
1038 	if (err & ERR_MASK(InvalidEEPCmd))
1039 		strlcat(buf, "invalideepromcmd ", blen);
1040 done:
1041 	return iserr;
1042 }
1043 
1044 static void reenable_7220_chase(unsigned long opaque)
1045 {
1046 	struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1047 
1048 	ppd->cpspec->chase_timer.expires = 0;
1049 	qib_set_ib_7220_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1050 		QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1051 }
1052 
1053 static void handle_7220_chase(struct qib_pportdata *ppd, u64 ibcst)
1054 {
1055 	u8 ibclt;
1056 	unsigned long tnow;
1057 
1058 	ibclt = (u8)SYM_FIELD(ibcst, IBCStatus, LinkTrainingState);
1059 
1060 	/*
1061 	 * Detect and handle the state chase issue, where we can
1062 	 * get stuck if we are unlucky on timing on both sides of
1063 	 * the link.   If we are, we disable, set a timer, and
1064 	 * then re-enable.
1065 	 */
1066 	switch (ibclt) {
1067 	case IB_7220_LT_STATE_CFGRCVFCFG:
1068 	case IB_7220_LT_STATE_CFGWAITRMT:
1069 	case IB_7220_LT_STATE_TXREVLANES:
1070 	case IB_7220_LT_STATE_CFGENH:
1071 		tnow = jiffies;
1072 		if (ppd->cpspec->chase_end &&
1073 		    time_after(tnow, ppd->cpspec->chase_end)) {
1074 			ppd->cpspec->chase_end = 0;
1075 			qib_set_ib_7220_lstate(ppd,
1076 				QLOGIC_IB_IBCC_LINKCMD_DOWN,
1077 				QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1078 			ppd->cpspec->chase_timer.expires = jiffies +
1079 				QIB_CHASE_DIS_TIME;
1080 			add_timer(&ppd->cpspec->chase_timer);
1081 		} else if (!ppd->cpspec->chase_end)
1082 			ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1083 		break;
1084 
1085 	default:
1086 		ppd->cpspec->chase_end = 0;
1087 		break;
1088 	}
1089 }
1090 
1091 static void handle_7220_errors(struct qib_devdata *dd, u64 errs)
1092 {
1093 	char *msg;
1094 	u64 ignore_this_time = 0;
1095 	u64 iserr = 0;
1096 	int log_idx;
1097 	struct qib_pportdata *ppd = dd->pport;
1098 	u64 mask;
1099 
1100 	/* don't report errors that are masked */
1101 	errs &= dd->cspec->errormask;
1102 	msg = dd->cspec->emsgbuf;
1103 
1104 	/* do these first, they are most important */
1105 	if (errs & ERR_MASK(HardwareErr))
1106 		qib_7220_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1107 	else
1108 		for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1109 			if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1110 				qib_inc_eeprom_err(dd, log_idx, 1);
1111 
1112 	if (errs & QLOGIC_IB_E_SDMAERRS)
1113 		sdma_7220_errors(ppd, errs);
1114 
1115 	if (errs & ~IB_E_BITSEXTANT)
1116 		qib_dev_err(dd,
1117 			"error interrupt with unknown errors %llx set\n",
1118 			(unsigned long long) (errs & ~IB_E_BITSEXTANT));
1119 
1120 	if (errs & E_SUM_ERRS) {
1121 		qib_disarm_7220_senderrbufs(ppd);
1122 		if ((errs & E_SUM_LINK_PKTERRS) &&
1123 		    !(ppd->lflags & QIBL_LINKACTIVE)) {
1124 			/*
1125 			 * This can happen when trying to bring the link
1126 			 * up, but the IB link changes state at the "wrong"
1127 			 * time. The IB logic then complains that the packet
1128 			 * isn't valid.  We don't want to confuse people, so
1129 			 * we just don't print them, except at debug
1130 			 */
1131 			ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1132 		}
1133 	} else if ((errs & E_SUM_LINK_PKTERRS) &&
1134 		   !(ppd->lflags & QIBL_LINKACTIVE)) {
1135 		/*
1136 		 * This can happen when SMA is trying to bring the link
1137 		 * up, but the IB link changes state at the "wrong" time.
1138 		 * The IB logic then complains that the packet isn't
1139 		 * valid.  We don't want to confuse people, so we just
1140 		 * don't print them, except at debug
1141 		 */
1142 		ignore_this_time = errs & E_SUM_LINK_PKTERRS;
1143 	}
1144 
1145 	qib_write_kreg(dd, kr_errclear, errs);
1146 
1147 	errs &= ~ignore_this_time;
1148 	if (!errs)
1149 		goto done;
1150 
1151 	/*
1152 	 * The ones we mask off are handled specially below
1153 	 * or above.  Also mask SDMADISABLED by default as it
1154 	 * is too chatty.
1155 	 */
1156 	mask = ERR_MASK(IBStatusChanged) |
1157 		ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) |
1158 		ERR_MASK(HardwareErr) | ERR_MASK(SDmaDisabledErr);
1159 
1160 	qib_decode_7220_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask);
1161 
1162 	if (errs & E_SUM_PKTERRS)
1163 		qib_stats.sps_rcverrs++;
1164 	if (errs & E_SUM_ERRS)
1165 		qib_stats.sps_txerrs++;
1166 	iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS |
1167 			 ERR_MASK(SDmaDisabledErr));
1168 
1169 	if (errs & ERR_MASK(IBStatusChanged)) {
1170 		u64 ibcs;
1171 
1172 		ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1173 		if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1174 			handle_7220_chase(ppd, ibcs);
1175 
1176 		/* Update our picture of width and speed from chip */
1177 		ppd->link_width_active =
1178 			((ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1) ?
1179 			    IB_WIDTH_4X : IB_WIDTH_1X;
1180 		ppd->link_speed_active =
1181 			((ibcs >> IBA7220_LINKSPEED_SHIFT) & 1) ?
1182 			    QIB_IB_DDR : QIB_IB_SDR;
1183 
1184 		/*
1185 		 * Since going into a recovery state causes the link state
1186 		 * to go down and since recovery is transitory, it is better
1187 		 * if we "miss" ever seeing the link training state go into
1188 		 * recovery (i.e., ignore this transition for link state
1189 		 * special handling purposes) without updating lastibcstat.
1190 		 */
1191 		if (qib_7220_phys_portstate(ibcs) !=
1192 					    IB_PHYSPORTSTATE_LINK_ERR_RECOVER)
1193 			qib_handle_e_ibstatuschanged(ppd, ibcs);
1194 	}
1195 
1196 	if (errs & ERR_MASK(ResetNegated)) {
1197 		qib_dev_err(dd,
1198 			"Got reset, requires re-init (unload and reload driver)\n");
1199 		dd->flags &= ~QIB_INITTED;  /* needs re-init */
1200 		/* mark as having had error */
1201 		*dd->devstatusp |= QIB_STATUS_HWERROR;
1202 		*dd->pport->statusp &= ~QIB_STATUS_IB_CONF;
1203 	}
1204 
1205 	if (*msg && iserr)
1206 		qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1207 
1208 	if (ppd->state_wanted & ppd->lflags)
1209 		wake_up_interruptible(&ppd->state_wait);
1210 
1211 	/*
1212 	 * If there were hdrq or egrfull errors, wake up any processes
1213 	 * waiting in poll.  We used to try to check which contexts had
1214 	 * the overflow, but given the cost of that and the chip reads
1215 	 * to support it, it's better to just wake everybody up if we
1216 	 * get an overflow; waiters can poll again if it's not them.
1217 	 */
1218 	if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1219 		qib_handle_urcv(dd, ~0U);
1220 		if (errs & ERR_MASK(RcvEgrFullErr))
1221 			qib_stats.sps_buffull++;
1222 		else
1223 			qib_stats.sps_hdrfull++;
1224 	}
1225 done:
1226 	return;
1227 }
1228 
1229 /* enable/disable chip from delivering interrupts */
1230 static void qib_7220_set_intr_state(struct qib_devdata *dd, u32 enable)
1231 {
1232 	if (enable) {
1233 		if (dd->flags & QIB_BADINTR)
1234 			return;
1235 		qib_write_kreg(dd, kr_intmask, ~0ULL);
1236 		/* force re-interrupt of any pending interrupts. */
1237 		qib_write_kreg(dd, kr_intclear, 0ULL);
1238 	} else
1239 		qib_write_kreg(dd, kr_intmask, 0ULL);
1240 }
1241 
1242 /*
1243  * Try to cleanup as much as possible for anything that might have gone
1244  * wrong while in freeze mode, such as pio buffers being written by user
1245  * processes (causing armlaunch), send errors due to going into freeze mode,
1246  * etc., and try to avoid causing extra interrupts while doing so.
1247  * Forcibly update the in-memory pioavail register copies after cleanup
1248  * because the chip won't do it while in freeze mode (the register values
1249  * themselves are kept correct).
1250  * Make sure that we don't lose any important interrupts by using the chip
1251  * feature that says that writing 0 to a bit in *clear that is set in
1252  * *status will cause an interrupt to be generated again (if allowed by
1253  * the *mask value).
1254  * This is in chip-specific code because of all of the register accesses,
1255  * even though the details are similar on most chips.
1256  */
1257 static void qib_7220_clear_freeze(struct qib_devdata *dd)
1258 {
1259 	/* disable error interrupts, to avoid confusion */
1260 	qib_write_kreg(dd, kr_errmask, 0ULL);
1261 
1262 	/* also disable interrupts; errormask is sometimes overwriten */
1263 	qib_7220_set_intr_state(dd, 0);
1264 
1265 	qib_cancel_sends(dd->pport);
1266 
1267 	/* clear the freeze, and be sure chip saw it */
1268 	qib_write_kreg(dd, kr_control, dd->control);
1269 	qib_read_kreg32(dd, kr_scratch);
1270 
1271 	/* force in-memory update now we are out of freeze */
1272 	qib_force_pio_avail_update(dd);
1273 
1274 	/*
1275 	 * force new interrupt if any hwerr, error or interrupt bits are
1276 	 * still set, and clear "safe" send packet errors related to freeze
1277 	 * and cancelling sends.  Re-enable error interrupts before possible
1278 	 * force of re-interrupt on pending interrupts.
1279 	 */
1280 	qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1281 	qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1282 	qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1283 	qib_7220_set_intr_state(dd, 1);
1284 }
1285 
1286 /**
1287  * qib_7220_handle_hwerrors - display hardware errors.
1288  * @dd: the qlogic_ib device
1289  * @msg: the output buffer
1290  * @msgl: the size of the output buffer
1291  *
1292  * Use same msg buffer as regular errors to avoid excessive stack
1293  * use.  Most hardware errors are catastrophic, but for right now,
1294  * we'll print them and continue.  We reuse the same message buffer as
1295  * handle_7220_errors() to avoid excessive stack usage.
1296  */
1297 static void qib_7220_handle_hwerrors(struct qib_devdata *dd, char *msg,
1298 				     size_t msgl)
1299 {
1300 	u64 hwerrs;
1301 	u32 bits, ctrl;
1302 	int isfatal = 0;
1303 	char *bitsmsg;
1304 	int log_idx;
1305 
1306 	hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1307 	if (!hwerrs)
1308 		goto bail;
1309 	if (hwerrs == ~0ULL) {
1310 		qib_dev_err(dd,
1311 			"Read of hardware error status failed (all bits set); ignoring\n");
1312 		goto bail;
1313 	}
1314 	qib_stats.sps_hwerrs++;
1315 
1316 	/*
1317 	 * Always clear the error status register, except MEMBISTFAIL,
1318 	 * regardless of whether we continue or stop using the chip.
1319 	 * We want that set so we know it failed, even across driver reload.
1320 	 * We'll still ignore it in the hwerrmask.  We do this partly for
1321 	 * diagnostics, but also for support.
1322 	 */
1323 	qib_write_kreg(dd, kr_hwerrclear,
1324 		       hwerrs & ~HWE_MASK(PowerOnBISTFailed));
1325 
1326 	hwerrs &= dd->cspec->hwerrmask;
1327 
1328 	/* We log some errors to EEPROM, check if we have any of those. */
1329 	for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1330 		if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log)
1331 			qib_inc_eeprom_err(dd, log_idx, 1);
1332 	if (hwerrs & ~(TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC |
1333 		       RXE_PARITY))
1334 		qib_devinfo(dd->pcidev,
1335 			"Hardware error: hwerr=0x%llx (cleared)\n",
1336 			(unsigned long long) hwerrs);
1337 
1338 	if (hwerrs & ~IB_HWE_BITSEXTANT)
1339 		qib_dev_err(dd,
1340 			"hwerror interrupt with unknown errors %llx set\n",
1341 			(unsigned long long) (hwerrs & ~IB_HWE_BITSEXTANT));
1342 
1343 	if (hwerrs & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR)
1344 		qib_sd7220_clr_ibpar(dd);
1345 
1346 	ctrl = qib_read_kreg32(dd, kr_control);
1347 	if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) {
1348 		/*
1349 		 * Parity errors in send memory are recoverable by h/w
1350 		 * just do housekeeping, exit freeze mode and continue.
1351 		 */
1352 		if (hwerrs & (TXEMEMPARITYERR_PIOBUF |
1353 			      TXEMEMPARITYERR_PIOPBC)) {
1354 			qib_7220_txe_recover(dd);
1355 			hwerrs &= ~(TXEMEMPARITYERR_PIOBUF |
1356 				    TXEMEMPARITYERR_PIOPBC);
1357 		}
1358 		if (hwerrs)
1359 			isfatal = 1;
1360 		else
1361 			qib_7220_clear_freeze(dd);
1362 	}
1363 
1364 	*msg = '\0';
1365 
1366 	if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
1367 		isfatal = 1;
1368 		strlcat(msg,
1369 			"[Memory BIST test failed, InfiniPath hardware unusable]",
1370 			msgl);
1371 		/* ignore from now on, so disable until driver reloaded */
1372 		dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
1373 		qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1374 	}
1375 
1376 	qib_format_hwerrors(hwerrs, qib_7220_hwerror_msgs,
1377 			    ARRAY_SIZE(qib_7220_hwerror_msgs), msg, msgl);
1378 
1379 	bitsmsg = dd->cspec->bitsmsgbuf;
1380 	if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK <<
1381 		      QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) {
1382 		bits = (u32) ((hwerrs >>
1383 			       QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) &
1384 			      QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK);
1385 		snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
1386 			 "[PCIe Mem Parity Errs %x] ", bits);
1387 		strlcat(msg, bitsmsg, msgl);
1388 	}
1389 
1390 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP |   \
1391 			 QLOGIC_IB_HWE_COREPLL_RFSLIP)
1392 
1393 	if (hwerrs & _QIB_PLL_FAIL) {
1394 		isfatal = 1;
1395 		snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf),
1396 			 "[PLL failed (%llx), InfiniPath hardware unusable]",
1397 			 (unsigned long long) hwerrs & _QIB_PLL_FAIL);
1398 		strlcat(msg, bitsmsg, msgl);
1399 		/* ignore from now on, so disable until driver reloaded */
1400 		dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
1401 		qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1402 	}
1403 
1404 	if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) {
1405 		/*
1406 		 * If it occurs, it is left masked since the eternal
1407 		 * interface is unused.
1408 		 */
1409 		dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
1410 		qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1411 	}
1412 
1413 	qib_dev_err(dd, "%s hardware error\n", msg);
1414 
1415 	if (isfatal && !dd->diag_client) {
1416 		qib_dev_err(dd,
1417 			"Fatal Hardware Error, no longer usable, SN %.16s\n",
1418 			dd->serial);
1419 		/*
1420 		 * For /sys status file and user programs to print; if no
1421 		 * trailing brace is copied, we'll know it was truncated.
1422 		 */
1423 		if (dd->freezemsg)
1424 			snprintf(dd->freezemsg, dd->freezelen,
1425 				 "{%s}", msg);
1426 		qib_disable_after_error(dd);
1427 	}
1428 bail:;
1429 }
1430 
1431 /**
1432  * qib_7220_init_hwerrors - enable hardware errors
1433  * @dd: the qlogic_ib device
1434  *
1435  * now that we have finished initializing everything that might reasonably
1436  * cause a hardware error, and cleared those errors bits as they occur,
1437  * we can enable hardware errors in the mask (potentially enabling
1438  * freeze mode), and enable hardware errors as errors (along with
1439  * everything else) in errormask
1440  */
1441 static void qib_7220_init_hwerrors(struct qib_devdata *dd)
1442 {
1443 	u64 val;
1444 	u64 extsval;
1445 
1446 	extsval = qib_read_kreg64(dd, kr_extstatus);
1447 
1448 	if (!(extsval & (QLOGIC_IB_EXTS_MEMBIST_ENDTEST |
1449 			 QLOGIC_IB_EXTS_MEMBIST_DISABLED)))
1450 		qib_dev_err(dd, "MemBIST did not complete!\n");
1451 	if (extsval & QLOGIC_IB_EXTS_MEMBIST_DISABLED)
1452 		qib_devinfo(dd->pcidev, "MemBIST is disabled.\n");
1453 
1454 	val = ~0ULL;    /* default to all hwerrors become interrupts, */
1455 
1456 	val &= ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
1457 	dd->cspec->hwerrmask = val;
1458 
1459 	qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
1460 	qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1461 
1462 	/* clear all */
1463 	qib_write_kreg(dd, kr_errclear, ~0ULL);
1464 	/* enable errors that are masked, at least this first time. */
1465 	qib_write_kreg(dd, kr_errmask, ~0ULL);
1466 	dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1467 	/* clear any interrupts up to this point (ints still not enabled) */
1468 	qib_write_kreg(dd, kr_intclear, ~0ULL);
1469 }
1470 
1471 /*
1472  * Disable and enable the armlaunch error.  Used for PIO bandwidth testing
1473  * on chips that are count-based, rather than trigger-based.  There is no
1474  * reference counting, but that's also fine, given the intended use.
1475  * Only chip-specific because it's all register accesses
1476  */
1477 static void qib_set_7220_armlaunch(struct qib_devdata *dd, u32 enable)
1478 {
1479 	if (enable) {
1480 		qib_write_kreg(dd, kr_errclear, ERR_MASK(SendPioArmLaunchErr));
1481 		dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1482 	} else
1483 		dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1484 	qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1485 }
1486 
1487 /*
1488  * Formerly took parameter <which> in pre-shifted,
1489  * pre-merged form with LinkCmd and LinkInitCmd
1490  * together, and assuming the zero was NOP.
1491  */
1492 static void qib_set_ib_7220_lstate(struct qib_pportdata *ppd, u16 linkcmd,
1493 				   u16 linitcmd)
1494 {
1495 	u64 mod_wd;
1496 	struct qib_devdata *dd = ppd->dd;
1497 	unsigned long flags;
1498 
1499 	if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
1500 		/*
1501 		 * If we are told to disable, note that so link-recovery
1502 		 * code does not attempt to bring us back up.
1503 		 */
1504 		spin_lock_irqsave(&ppd->lflags_lock, flags);
1505 		ppd->lflags |= QIBL_IB_LINK_DISABLED;
1506 		spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1507 	} else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
1508 		/*
1509 		 * Any other linkinitcmd will lead to LINKDOWN and then
1510 		 * to INIT (if all is well), so clear flag to let
1511 		 * link-recovery code attempt to bring us back up.
1512 		 */
1513 		spin_lock_irqsave(&ppd->lflags_lock, flags);
1514 		ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
1515 		spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1516 	}
1517 
1518 	mod_wd = (linkcmd << IBA7220_IBCC_LINKCMD_SHIFT) |
1519 		(linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1520 
1521 	qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl | mod_wd);
1522 	/* write to chip to prevent back-to-back writes of ibc reg */
1523 	qib_write_kreg(dd, kr_scratch, 0);
1524 }
1525 
1526 /*
1527  * All detailed interaction with the SerDes has been moved to qib_sd7220.c
1528  *
1529  * The portion of IBA7220-specific bringup_serdes() that actually deals with
1530  * registers and memory within the SerDes itself is qib_sd7220_init().
1531  */
1532 
1533 /**
1534  * qib_7220_bringup_serdes - bring up the serdes
1535  * @ppd: physical port on the qlogic_ib device
1536  */
1537 static int qib_7220_bringup_serdes(struct qib_pportdata *ppd)
1538 {
1539 	struct qib_devdata *dd = ppd->dd;
1540 	u64 val, prev_val, guid, ibc;
1541 	int ret = 0;
1542 
1543 	/* Put IBC in reset, sends disabled */
1544 	dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1545 	qib_write_kreg(dd, kr_control, 0ULL);
1546 
1547 	if (qib_compat_ddr_negotiate) {
1548 		ppd->cpspec->ibdeltainprog = 1;
1549 		ppd->cpspec->ibsymsnap = read_7220_creg32(dd, cr_ibsymbolerr);
1550 		ppd->cpspec->iblnkerrsnap =
1551 			read_7220_creg32(dd, cr_iblinkerrrecov);
1552 	}
1553 
1554 	/* flowcontrolwatermark is in units of KBytes */
1555 	ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark);
1556 	/*
1557 	 * How often flowctrl sent.  More or less in usecs; balance against
1558 	 * watermark value, so that in theory senders always get a flow
1559 	 * control update in time to not let the IB link go idle.
1560 	 */
1561 	ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod);
1562 	/* max error tolerance */
1563 	ibc |= 0xfULL << SYM_LSB(IBCCtrl, PhyerrThreshold);
1564 	/* use "real" buffer space for */
1565 	ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale);
1566 	/* IB credit flow control. */
1567 	ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold);
1568 	/*
1569 	 * set initial max size pkt IBC will send, including ICRC; it's the
1570 	 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1571 	 */
1572 	ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen);
1573 	ppd->cpspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */
1574 
1575 	/* initially come up waiting for TS1, without sending anything. */
1576 	val = ppd->cpspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
1577 		QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
1578 	qib_write_kreg(dd, kr_ibcctrl, val);
1579 
1580 	if (!ppd->cpspec->ibcddrctrl) {
1581 		/* not on re-init after reset */
1582 		ppd->cpspec->ibcddrctrl = qib_read_kreg64(dd, kr_ibcddrctrl);
1583 
1584 		if (ppd->link_speed_enabled == (QIB_IB_SDR | QIB_IB_DDR))
1585 			ppd->cpspec->ibcddrctrl |=
1586 				IBA7220_IBC_SPEED_AUTONEG_MASK |
1587 				IBA7220_IBC_IBTA_1_2_MASK;
1588 		else
1589 			ppd->cpspec->ibcddrctrl |=
1590 				ppd->link_speed_enabled == QIB_IB_DDR ?
1591 				IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
1592 		if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
1593 		    (IB_WIDTH_1X | IB_WIDTH_4X))
1594 			ppd->cpspec->ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
1595 		else
1596 			ppd->cpspec->ibcddrctrl |=
1597 				ppd->link_width_enabled == IB_WIDTH_4X ?
1598 				IBA7220_IBC_WIDTH_4X_ONLY :
1599 				IBA7220_IBC_WIDTH_1X_ONLY;
1600 
1601 		/* always enable these on driver reload, not sticky */
1602 		ppd->cpspec->ibcddrctrl |=
1603 			IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
1604 		ppd->cpspec->ibcddrctrl |=
1605 			IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
1606 
1607 		/* enable automatic lane reversal detection for receive */
1608 		ppd->cpspec->ibcddrctrl |= IBA7220_IBC_LANE_REV_SUPPORTED;
1609 	} else
1610 		/* write to chip to prevent back-to-back writes of ibc reg */
1611 		qib_write_kreg(dd, kr_scratch, 0);
1612 
1613 	qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
1614 	qib_write_kreg(dd, kr_scratch, 0);
1615 
1616 	qib_write_kreg(dd, kr_ncmodectrl, 0Ull);
1617 	qib_write_kreg(dd, kr_scratch, 0);
1618 
1619 	ret = qib_sd7220_init(dd);
1620 
1621 	val = qib_read_kreg64(dd, kr_xgxs_cfg);
1622 	prev_val = val;
1623 	val |= QLOGIC_IB_XGXS_FC_SAFE;
1624 	if (val != prev_val) {
1625 		qib_write_kreg(dd, kr_xgxs_cfg, val);
1626 		qib_read_kreg32(dd, kr_scratch);
1627 	}
1628 	if (val & QLOGIC_IB_XGXS_RESET)
1629 		val &= ~QLOGIC_IB_XGXS_RESET;
1630 	if (val != prev_val)
1631 		qib_write_kreg(dd, kr_xgxs_cfg, val);
1632 
1633 	/* first time through, set port guid */
1634 	if (!ppd->guid)
1635 		ppd->guid = dd->base_guid;
1636 	guid = be64_to_cpu(ppd->guid);
1637 
1638 	qib_write_kreg(dd, kr_hrtbt_guid, guid);
1639 	if (!ret) {
1640 		dd->control |= QLOGIC_IB_C_LINKENABLE;
1641 		qib_write_kreg(dd, kr_control, dd->control);
1642 	} else
1643 		/* write to chip to prevent back-to-back writes of ibc reg */
1644 		qib_write_kreg(dd, kr_scratch, 0);
1645 	return ret;
1646 }
1647 
1648 /**
1649  * qib_7220_quiet_serdes - set serdes to txidle
1650  * @ppd: physical port of the qlogic_ib device
1651  * Called when driver is being unloaded
1652  */
1653 static void qib_7220_quiet_serdes(struct qib_pportdata *ppd)
1654 {
1655 	u64 val;
1656 	struct qib_devdata *dd = ppd->dd;
1657 	unsigned long flags;
1658 
1659 	/* disable IBC */
1660 	dd->control &= ~QLOGIC_IB_C_LINKENABLE;
1661 	qib_write_kreg(dd, kr_control,
1662 		       dd->control | QLOGIC_IB_C_FREEZEMODE);
1663 
1664 	ppd->cpspec->chase_end = 0;
1665 	if (ppd->cpspec->chase_timer.data) /* if initted */
1666 		del_timer_sync(&ppd->cpspec->chase_timer);
1667 
1668 	if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
1669 	    ppd->cpspec->ibdeltainprog) {
1670 		u64 diagc;
1671 
1672 		/* enable counter writes */
1673 		diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1674 		qib_write_kreg(dd, kr_hwdiagctrl,
1675 			       diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
1676 
1677 		if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
1678 			val = read_7220_creg32(dd, cr_ibsymbolerr);
1679 			if (ppd->cpspec->ibdeltainprog)
1680 				val -= val - ppd->cpspec->ibsymsnap;
1681 			val -= ppd->cpspec->ibsymdelta;
1682 			write_7220_creg(dd, cr_ibsymbolerr, val);
1683 		}
1684 		if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
1685 			val = read_7220_creg32(dd, cr_iblinkerrrecov);
1686 			if (ppd->cpspec->ibdeltainprog)
1687 				val -= val - ppd->cpspec->iblnkerrsnap;
1688 			val -= ppd->cpspec->iblnkerrdelta;
1689 			write_7220_creg(dd, cr_iblinkerrrecov, val);
1690 		}
1691 
1692 		/* and disable counter writes */
1693 		qib_write_kreg(dd, kr_hwdiagctrl, diagc);
1694 	}
1695 	qib_set_ib_7220_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1696 
1697 	spin_lock_irqsave(&ppd->lflags_lock, flags);
1698 	ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
1699 	spin_unlock_irqrestore(&ppd->lflags_lock, flags);
1700 	wake_up(&ppd->cpspec->autoneg_wait);
1701 	cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
1702 
1703 	shutdown_7220_relock_poll(ppd->dd);
1704 	val = qib_read_kreg64(ppd->dd, kr_xgxs_cfg);
1705 	val |= QLOGIC_IB_XGXS_RESET;
1706 	qib_write_kreg(ppd->dd, kr_xgxs_cfg, val);
1707 }
1708 
1709 /**
1710  * qib_setup_7220_setextled - set the state of the two external LEDs
1711  * @dd: the qlogic_ib device
1712  * @on: whether the link is up or not
1713  *
1714  * The exact combo of LEDs if on is true is determined by looking
1715  * at the ibcstatus.
1716  *
1717  * These LEDs indicate the physical and logical state of IB link.
1718  * For this chip (at least with recommended board pinouts), LED1
1719  * is Yellow (logical state) and LED2 is Green (physical state),
1720  *
1721  * Note:  We try to match the Mellanox HCA LED behavior as best
1722  * we can.  Green indicates physical link state is OK (something is
1723  * plugged in, and we can train).
1724  * Amber indicates the link is logically up (ACTIVE).
1725  * Mellanox further blinks the amber LED to indicate data packet
1726  * activity, but we have no hardware support for that, so it would
1727  * require waking up every 10-20 msecs and checking the counters
1728  * on the chip, and then turning the LED off if appropriate.  That's
1729  * visible overhead, so not something we will do.
1730  *
1731  */
1732 static void qib_setup_7220_setextled(struct qib_pportdata *ppd, u32 on)
1733 {
1734 	struct qib_devdata *dd = ppd->dd;
1735 	u64 extctl, ledblink = 0, val, lst, ltst;
1736 	unsigned long flags;
1737 
1738 	/*
1739 	 * The diags use the LED to indicate diag info, so we leave
1740 	 * the external LED alone when the diags are running.
1741 	 */
1742 	if (dd->diag_client)
1743 		return;
1744 
1745 	if (ppd->led_override) {
1746 		ltst = (ppd->led_override & QIB_LED_PHYS) ?
1747 			IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED,
1748 		lst = (ppd->led_override & QIB_LED_LOG) ?
1749 			IB_PORT_ACTIVE : IB_PORT_DOWN;
1750 	} else if (on) {
1751 		val = qib_read_kreg64(dd, kr_ibcstatus);
1752 		ltst = qib_7220_phys_portstate(val);
1753 		lst = qib_7220_iblink_state(val);
1754 	} else {
1755 		ltst = 0;
1756 		lst = 0;
1757 	}
1758 
1759 	spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1760 	extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1761 				 SYM_MASK(EXTCtrl, LEDPriPortYellowOn));
1762 	if (ltst == IB_PHYSPORTSTATE_LINKUP) {
1763 		extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn);
1764 		/*
1765 		 * counts are in chip clock (4ns) periods.
1766 		 * This is 1/16 sec (66.6ms) on,
1767 		 * 3/16 sec (187.5 ms) off, with packets rcvd
1768 		 */
1769 		ledblink = ((66600 * 1000UL / 4) << IBA7220_LEDBLINK_ON_SHIFT)
1770 			| ((187500 * 1000UL / 4) << IBA7220_LEDBLINK_OFF_SHIFT);
1771 	}
1772 	if (lst == IB_PORT_ACTIVE)
1773 		extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn);
1774 	dd->cspec->extctrl = extctl;
1775 	qib_write_kreg(dd, kr_extctrl, extctl);
1776 	spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1777 
1778 	if (ledblink) /* blink the LED on packet receive */
1779 		qib_write_kreg(dd, kr_rcvpktledcnt, ledblink);
1780 }
1781 
1782 static void qib_7220_free_irq(struct qib_devdata *dd)
1783 {
1784 	if (dd->cspec->irq) {
1785 		free_irq(dd->cspec->irq, dd);
1786 		dd->cspec->irq = 0;
1787 	}
1788 	qib_nomsi(dd);
1789 }
1790 
1791 /*
1792  * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1793  * @dd: the qlogic_ib device
1794  *
1795  * This is called during driver unload.
1796  *
1797  */
1798 static void qib_setup_7220_cleanup(struct qib_devdata *dd)
1799 {
1800 	qib_7220_free_irq(dd);
1801 	kfree(dd->cspec->cntrs);
1802 	kfree(dd->cspec->portcntrs);
1803 }
1804 
1805 /*
1806  * This is only called for SDmaInt.
1807  * SDmaDisabled is handled on the error path.
1808  */
1809 static void sdma_7220_intr(struct qib_pportdata *ppd, u64 istat)
1810 {
1811 	unsigned long flags;
1812 
1813 	spin_lock_irqsave(&ppd->sdma_lock, flags);
1814 
1815 	switch (ppd->sdma_state.current_state) {
1816 	case qib_sdma_state_s00_hw_down:
1817 		break;
1818 
1819 	case qib_sdma_state_s10_hw_start_up_wait:
1820 		__qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
1821 		break;
1822 
1823 	case qib_sdma_state_s20_idle:
1824 		break;
1825 
1826 	case qib_sdma_state_s30_sw_clean_up_wait:
1827 		break;
1828 
1829 	case qib_sdma_state_s40_hw_clean_up_wait:
1830 		break;
1831 
1832 	case qib_sdma_state_s50_hw_halt_wait:
1833 		__qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1834 		break;
1835 
1836 	case qib_sdma_state_s99_running:
1837 		/* too chatty to print here */
1838 		__qib_sdma_intr(ppd);
1839 		break;
1840 	}
1841 	spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1842 }
1843 
1844 static void qib_wantpiobuf_7220_intr(struct qib_devdata *dd, u32 needint)
1845 {
1846 	unsigned long flags;
1847 
1848 	spin_lock_irqsave(&dd->sendctrl_lock, flags);
1849 	if (needint) {
1850 		if (!(dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
1851 			goto done;
1852 		/*
1853 		 * blip the availupd off, next write will be on, so
1854 		 * we ensure an avail update, regardless of threshold or
1855 		 * buffers becoming free, whenever we want an interrupt
1856 		 */
1857 		qib_write_kreg(dd, kr_sendctrl, dd->sendctrl &
1858 			~SYM_MASK(SendCtrl, SendBufAvailUpd));
1859 		qib_write_kreg(dd, kr_scratch, 0ULL);
1860 		dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
1861 	} else
1862 		dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
1863 	qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
1864 	qib_write_kreg(dd, kr_scratch, 0ULL);
1865 done:
1866 	spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
1867 }
1868 
1869 /*
1870  * Handle errors and unusual events first, separate function
1871  * to improve cache hits for fast path interrupt handling.
1872  */
1873 static noinline void unlikely_7220_intr(struct qib_devdata *dd, u64 istat)
1874 {
1875 	if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT))
1876 		qib_dev_err(dd,
1877 			    "interrupt with unknown interrupts %Lx set\n",
1878 			    istat & ~QLOGIC_IB_I_BITSEXTANT);
1879 
1880 	if (istat & QLOGIC_IB_I_GPIO) {
1881 		u32 gpiostatus;
1882 
1883 		/*
1884 		 * Boards for this chip currently don't use GPIO interrupts,
1885 		 * so clear by writing GPIOstatus to GPIOclear, and complain
1886 		 * to alert developer. To avoid endless repeats, clear
1887 		 * the bits in the mask, since there is some kind of
1888 		 * programming error or chip problem.
1889 		 */
1890 		gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
1891 		/*
1892 		 * In theory, writing GPIOstatus to GPIOclear could
1893 		 * have a bad side-effect on some diagnostic that wanted
1894 		 * to poll for a status-change, but the various shadows
1895 		 * make that problematic at best. Diags will just suppress
1896 		 * all GPIO interrupts during such tests.
1897 		 */
1898 		qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
1899 
1900 		if (gpiostatus) {
1901 			const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
1902 			u32 gpio_irq = mask & gpiostatus;
1903 
1904 			/*
1905 			 * A bit set in status and (chip) Mask register
1906 			 * would cause an interrupt. Since we are not
1907 			 * expecting any, report it. Also check that the
1908 			 * chip reflects our shadow, report issues,
1909 			 * and refresh from the shadow.
1910 			 */
1911 			/*
1912 			 * Clear any troublemakers, and update chip
1913 			 * from shadow
1914 			 */
1915 			dd->cspec->gpio_mask &= ~gpio_irq;
1916 			qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
1917 		}
1918 	}
1919 
1920 	if (istat & QLOGIC_IB_I_ERROR) {
1921 		u64 estat;
1922 
1923 		qib_stats.sps_errints++;
1924 		estat = qib_read_kreg64(dd, kr_errstatus);
1925 		if (!estat)
1926 			qib_devinfo(dd->pcidev,
1927 				"error interrupt (%Lx), but no error bits set!\n",
1928 				istat);
1929 		else
1930 			handle_7220_errors(dd, estat);
1931 	}
1932 }
1933 
1934 static irqreturn_t qib_7220intr(int irq, void *data)
1935 {
1936 	struct qib_devdata *dd = data;
1937 	irqreturn_t ret;
1938 	u64 istat;
1939 	u64 ctxtrbits;
1940 	u64 rmask;
1941 	unsigned i;
1942 
1943 	if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
1944 		/*
1945 		 * This return value is not great, but we do not want the
1946 		 * interrupt core code to remove our interrupt handler
1947 		 * because we don't appear to be handling an interrupt
1948 		 * during a chip reset.
1949 		 */
1950 		ret = IRQ_HANDLED;
1951 		goto bail;
1952 	}
1953 
1954 	istat = qib_read_kreg64(dd, kr_intstatus);
1955 
1956 	if (unlikely(!istat)) {
1957 		ret = IRQ_NONE; /* not our interrupt, or already handled */
1958 		goto bail;
1959 	}
1960 	if (unlikely(istat == -1)) {
1961 		qib_bad_intrstatus(dd);
1962 		/* don't know if it was our interrupt or not */
1963 		ret = IRQ_NONE;
1964 		goto bail;
1965 	}
1966 
1967 	this_cpu_inc(*dd->int_counter);
1968 	if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT |
1969 			      QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR)))
1970 		unlikely_7220_intr(dd, istat);
1971 
1972 	/*
1973 	 * Clear the interrupt bits we found set, relatively early, so we
1974 	 * "know" know the chip will have seen this by the time we process
1975 	 * the queue, and will re-interrupt if necessary.  The processor
1976 	 * itself won't take the interrupt again until we return.
1977 	 */
1978 	qib_write_kreg(dd, kr_intclear, istat);
1979 
1980 	/*
1981 	 * Handle kernel receive queues before checking for pio buffers
1982 	 * available since receives can overflow; piobuf waiters can afford
1983 	 * a few extra cycles, since they were waiting anyway.
1984 	 */
1985 	ctxtrbits = istat &
1986 		((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1987 		 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT));
1988 	if (ctxtrbits) {
1989 		rmask = (1ULL << QLOGIC_IB_I_RCVAVAIL_SHIFT) |
1990 			(1ULL << QLOGIC_IB_I_RCVURG_SHIFT);
1991 		for (i = 0; i < dd->first_user_ctxt; i++) {
1992 			if (ctxtrbits & rmask) {
1993 				ctxtrbits &= ~rmask;
1994 				qib_kreceive(dd->rcd[i], NULL, NULL);
1995 			}
1996 			rmask <<= 1;
1997 		}
1998 		if (ctxtrbits) {
1999 			ctxtrbits =
2000 				(ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) |
2001 				(ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT);
2002 			qib_handle_urcv(dd, ctxtrbits);
2003 		}
2004 	}
2005 
2006 	/* only call for SDmaInt */
2007 	if (istat & QLOGIC_IB_I_SDMAINT)
2008 		sdma_7220_intr(dd->pport, istat);
2009 
2010 	if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2011 		qib_ib_piobufavail(dd);
2012 
2013 	ret = IRQ_HANDLED;
2014 bail:
2015 	return ret;
2016 }
2017 
2018 /*
2019  * Set up our chip-specific interrupt handler.
2020  * The interrupt type has already been setup, so
2021  * we just need to do the registration and error checking.
2022  * If we are using MSI interrupts, we may fall back to
2023  * INTx later, if the interrupt handler doesn't get called
2024  * within 1/2 second (see verify_interrupt()).
2025  */
2026 static void qib_setup_7220_interrupt(struct qib_devdata *dd)
2027 {
2028 	if (!dd->cspec->irq)
2029 		qib_dev_err(dd,
2030 			"irq is 0, BIOS error?  Interrupts won't work\n");
2031 	else {
2032 		int ret = request_irq(dd->cspec->irq, qib_7220intr,
2033 			dd->msi_lo ? 0 : IRQF_SHARED,
2034 			QIB_DRV_NAME, dd);
2035 
2036 		if (ret)
2037 			qib_dev_err(dd,
2038 				"Couldn't setup %s interrupt (irq=%d): %d\n",
2039 				dd->msi_lo ?  "MSI" : "INTx",
2040 				dd->cspec->irq, ret);
2041 	}
2042 }
2043 
2044 /**
2045  * qib_7220_boardname - fill in the board name
2046  * @dd: the qlogic_ib device
2047  *
2048  * info is based on the board revision register
2049  */
2050 static void qib_7220_boardname(struct qib_devdata *dd)
2051 {
2052 	char *n;
2053 	u32 boardid, namelen;
2054 
2055 	boardid = SYM_FIELD(dd->revision, Revision,
2056 			    BoardID);
2057 
2058 	switch (boardid) {
2059 	case 1:
2060 		n = "InfiniPath_QLE7240";
2061 		break;
2062 	case 2:
2063 		n = "InfiniPath_QLE7280";
2064 		break;
2065 	default:
2066 		qib_dev_err(dd, "Unknown 7220 board with ID %u\n", boardid);
2067 		n = "Unknown_InfiniPath_7220";
2068 		break;
2069 	}
2070 
2071 	namelen = strlen(n) + 1;
2072 	dd->boardname = kmalloc(namelen, GFP_KERNEL);
2073 	if (!dd->boardname)
2074 		qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
2075 	else
2076 		snprintf(dd->boardname, namelen, "%s", n);
2077 
2078 	if (dd->majrev != 5 || !dd->minrev || dd->minrev > 2)
2079 		qib_dev_err(dd,
2080 			"Unsupported InfiniPath hardware revision %u.%u!\n",
2081 			dd->majrev, dd->minrev);
2082 
2083 	snprintf(dd->boardversion, sizeof(dd->boardversion),
2084 		 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
2085 		 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
2086 		 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
2087 		 dd->majrev, dd->minrev,
2088 		 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
2089 }
2090 
2091 /*
2092  * This routine sleeps, so it can only be called from user context, not
2093  * from interrupt context.
2094  */
2095 static int qib_setup_7220_reset(struct qib_devdata *dd)
2096 {
2097 	u64 val;
2098 	int i;
2099 	int ret;
2100 	u16 cmdval;
2101 	u8 int_line, clinesz;
2102 	unsigned long flags;
2103 
2104 	qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
2105 
2106 	/* Use dev_err so it shows up in logs, etc. */
2107 	qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
2108 
2109 	/* no interrupts till re-initted */
2110 	qib_7220_set_intr_state(dd, 0);
2111 
2112 	dd->pport->cpspec->ibdeltainprog = 0;
2113 	dd->pport->cpspec->ibsymdelta = 0;
2114 	dd->pport->cpspec->iblnkerrdelta = 0;
2115 
2116 	/*
2117 	 * Keep chip from being accessed until we are ready.  Use
2118 	 * writeq() directly, to allow the write even though QIB_PRESENT
2119 	 * isn't set.
2120 	 */
2121 	dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
2122 	/* so we check interrupts work again */
2123 	dd->z_int_counter = qib_int_counter(dd);
2124 	val = dd->control | QLOGIC_IB_C_RESET;
2125 	writeq(val, &dd->kregbase[kr_control]);
2126 	mb(); /* prevent compiler reordering around actual reset */
2127 
2128 	for (i = 1; i <= 5; i++) {
2129 		/*
2130 		 * Allow MBIST, etc. to complete; longer on each retry.
2131 		 * We sometimes get machine checks from bus timeout if no
2132 		 * response, so for now, make it *really* long.
2133 		 */
2134 		msleep(1000 + (1 + i) * 2000);
2135 
2136 		qib_pcie_reenable(dd, cmdval, int_line, clinesz);
2137 
2138 		/*
2139 		 * Use readq directly, so we don't need to mark it as PRESENT
2140 		 * until we get a successful indication that all is well.
2141 		 */
2142 		val = readq(&dd->kregbase[kr_revision]);
2143 		if (val == dd->revision) {
2144 			dd->flags |= QIB_PRESENT; /* it's back */
2145 			ret = qib_reinit_intr(dd);
2146 			goto bail;
2147 		}
2148 	}
2149 	ret = 0; /* failed */
2150 
2151 bail:
2152 	if (ret) {
2153 		if (qib_pcie_params(dd, dd->lbus_width, NULL, NULL))
2154 			qib_dev_err(dd,
2155 				"Reset failed to setup PCIe or interrupts; continuing anyway\n");
2156 
2157 		/* hold IBC in reset, no sends, etc till later */
2158 		qib_write_kreg(dd, kr_control, 0ULL);
2159 
2160 		/* clear the reset error, init error/hwerror mask */
2161 		qib_7220_init_hwerrors(dd);
2162 
2163 		/* do setup similar to speed or link-width changes */
2164 		if (dd->pport->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK)
2165 			dd->cspec->presets_needed = 1;
2166 		spin_lock_irqsave(&dd->pport->lflags_lock, flags);
2167 		dd->pport->lflags |= QIBL_IB_FORCE_NOTIFY;
2168 		dd->pport->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2169 		spin_unlock_irqrestore(&dd->pport->lflags_lock, flags);
2170 	}
2171 
2172 	return ret;
2173 }
2174 
2175 /**
2176  * qib_7220_put_tid - write a TID to the chip
2177  * @dd: the qlogic_ib device
2178  * @tidptr: pointer to the expected TID (in chip) to update
2179  * @tidtype: 0 for eager, 1 for expected
2180  * @pa: physical address of in memory buffer; tidinvalid if freeing
2181  */
2182 static void qib_7220_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
2183 			     u32 type, unsigned long pa)
2184 {
2185 	if (pa != dd->tidinvalid) {
2186 		u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
2187 
2188 		/* paranoia checks */
2189 		if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
2190 			qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
2191 				    pa);
2192 			return;
2193 		}
2194 		if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
2195 			qib_dev_err(dd,
2196 				"Physical page address 0x%lx larger than supported\n",
2197 				pa);
2198 			return;
2199 		}
2200 
2201 		if (type == RCVHQ_RCV_TYPE_EAGER)
2202 			chippa |= dd->tidtemplate;
2203 		else /* for now, always full 4KB page */
2204 			chippa |= IBA7220_TID_SZ_4K;
2205 		pa = chippa;
2206 	}
2207 	writeq(pa, tidptr);
2208 	mmiowb();
2209 }
2210 
2211 /**
2212  * qib_7220_clear_tids - clear all TID entries for a ctxt, expected and eager
2213  * @dd: the qlogic_ib device
2214  * @ctxt: the ctxt
2215  *
2216  * clear all TID entries for a ctxt, expected and eager.
2217  * Used from qib_close().  On this chip, TIDs are only 32 bits,
2218  * not 64, but they are still on 64 bit boundaries, so tidbase
2219  * is declared as u64 * for the pointer math, even though we write 32 bits
2220  */
2221 static void qib_7220_clear_tids(struct qib_devdata *dd,
2222 				struct qib_ctxtdata *rcd)
2223 {
2224 	u64 __iomem *tidbase;
2225 	unsigned long tidinv;
2226 	u32 ctxt;
2227 	int i;
2228 
2229 	if (!dd->kregbase || !rcd)
2230 		return;
2231 
2232 	ctxt = rcd->ctxt;
2233 
2234 	tidinv = dd->tidinvalid;
2235 	tidbase = (u64 __iomem *)
2236 		((char __iomem *)(dd->kregbase) +
2237 		 dd->rcvtidbase +
2238 		 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
2239 
2240 	for (i = 0; i < dd->rcvtidcnt; i++)
2241 		qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
2242 				 tidinv);
2243 
2244 	tidbase = (u64 __iomem *)
2245 		((char __iomem *)(dd->kregbase) +
2246 		 dd->rcvegrbase +
2247 		 rcd->rcvegr_tid_base * sizeof(*tidbase));
2248 
2249 	for (i = 0; i < rcd->rcvegrcnt; i++)
2250 		qib_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
2251 				 tidinv);
2252 }
2253 
2254 /**
2255  * qib_7220_tidtemplate - setup constants for TID updates
2256  * @dd: the qlogic_ib device
2257  *
2258  * We setup stuff that we use a lot, to avoid calculating each time
2259  */
2260 static void qib_7220_tidtemplate(struct qib_devdata *dd)
2261 {
2262 	if (dd->rcvegrbufsize == 2048)
2263 		dd->tidtemplate = IBA7220_TID_SZ_2K;
2264 	else if (dd->rcvegrbufsize == 4096)
2265 		dd->tidtemplate = IBA7220_TID_SZ_4K;
2266 	dd->tidinvalid = 0;
2267 }
2268 
2269 /**
2270  * qib_init_7220_get_base_info - set chip-specific flags for user code
2271  * @rcd: the qlogic_ib ctxt
2272  * @kbase: qib_base_info pointer
2273  *
2274  * We set the PCIE flag because the lower bandwidth on PCIe vs
2275  * HyperTransport can affect some user packet algorithims.
2276  */
2277 static int qib_7220_get_base_info(struct qib_ctxtdata *rcd,
2278 				  struct qib_base_info *kinfo)
2279 {
2280 	kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE |
2281 		QIB_RUNTIME_NODMA_RTAIL | QIB_RUNTIME_SDMA;
2282 
2283 	if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
2284 		kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
2285 
2286 	return 0;
2287 }
2288 
2289 static struct qib_message_header *
2290 qib_7220_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
2291 {
2292 	u32 offset = qib_hdrget_offset(rhf_addr);
2293 
2294 	return (struct qib_message_header *)
2295 		(rhf_addr - dd->rhf_offset + offset);
2296 }
2297 
2298 static void qib_7220_config_ctxts(struct qib_devdata *dd)
2299 {
2300 	unsigned long flags;
2301 	u32 nchipctxts;
2302 
2303 	nchipctxts = qib_read_kreg32(dd, kr_portcnt);
2304 	dd->cspec->numctxts = nchipctxts;
2305 	if (qib_n_krcv_queues > 1) {
2306 		dd->qpn_mask = 0x3e;
2307 		dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
2308 		if (dd->first_user_ctxt > nchipctxts)
2309 			dd->first_user_ctxt = nchipctxts;
2310 	} else
2311 		dd->first_user_ctxt = dd->num_pports;
2312 	dd->n_krcv_queues = dd->first_user_ctxt;
2313 
2314 	if (!qib_cfgctxts) {
2315 		int nctxts = dd->first_user_ctxt + num_online_cpus();
2316 
2317 		if (nctxts <= 5)
2318 			dd->ctxtcnt = 5;
2319 		else if (nctxts <= 9)
2320 			dd->ctxtcnt = 9;
2321 		else if (nctxts <= nchipctxts)
2322 			dd->ctxtcnt = nchipctxts;
2323 	} else if (qib_cfgctxts <= nchipctxts)
2324 		dd->ctxtcnt = qib_cfgctxts;
2325 	if (!dd->ctxtcnt) /* none of the above, set to max */
2326 		dd->ctxtcnt = nchipctxts;
2327 
2328 	/*
2329 	 * Chip can be configured for 5, 9, or 17 ctxts, and choice
2330 	 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
2331 	 * Lock to be paranoid about later motion, etc.
2332 	 */
2333 	spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2334 	if (dd->ctxtcnt > 9)
2335 		dd->rcvctrl |= 2ULL << IBA7220_R_CTXTCFG_SHIFT;
2336 	else if (dd->ctxtcnt > 5)
2337 		dd->rcvctrl |= 1ULL << IBA7220_R_CTXTCFG_SHIFT;
2338 	/* else configure for default 5 receive ctxts */
2339 	if (dd->qpn_mask)
2340 		dd->rcvctrl |= 1ULL << QIB_7220_RcvCtrl_RcvQPMapEnable_LSB;
2341 	qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2342 	spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2343 
2344 	/* kr_rcvegrcnt changes based on the number of contexts enabled */
2345 	dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
2346 	dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, IBA7220_KRCVEGRCNT);
2347 }
2348 
2349 static int qib_7220_get_ib_cfg(struct qib_pportdata *ppd, int which)
2350 {
2351 	int lsb, ret = 0;
2352 	u64 maskr; /* right-justified mask */
2353 
2354 	switch (which) {
2355 	case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
2356 		ret = ppd->link_width_enabled;
2357 		goto done;
2358 
2359 	case QIB_IB_CFG_LWID: /* Get currently active Link-width */
2360 		ret = ppd->link_width_active;
2361 		goto done;
2362 
2363 	case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
2364 		ret = ppd->link_speed_enabled;
2365 		goto done;
2366 
2367 	case QIB_IB_CFG_SPD: /* Get current Link spd */
2368 		ret = ppd->link_speed_active;
2369 		goto done;
2370 
2371 	case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
2372 		lsb = IBA7220_IBC_RXPOL_SHIFT;
2373 		maskr = IBA7220_IBC_RXPOL_MASK;
2374 		break;
2375 
2376 	case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
2377 		lsb = IBA7220_IBC_LREV_SHIFT;
2378 		maskr = IBA7220_IBC_LREV_MASK;
2379 		break;
2380 
2381 	case QIB_IB_CFG_LINKLATENCY:
2382 		ret = qib_read_kreg64(ppd->dd, kr_ibcddrstatus)
2383 			& IBA7220_DDRSTAT_LINKLAT_MASK;
2384 		goto done;
2385 
2386 	case QIB_IB_CFG_OP_VLS:
2387 		ret = ppd->vls_operational;
2388 		goto done;
2389 
2390 	case QIB_IB_CFG_VL_HIGH_CAP:
2391 		ret = 0;
2392 		goto done;
2393 
2394 	case QIB_IB_CFG_VL_LOW_CAP:
2395 		ret = 0;
2396 		goto done;
2397 
2398 	case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2399 		ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2400 				OverrunThreshold);
2401 		goto done;
2402 
2403 	case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2404 		ret = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2405 				PhyerrThreshold);
2406 		goto done;
2407 
2408 	case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2409 		/* will only take effect when the link state changes */
2410 		ret = (ppd->cpspec->ibcctrl &
2411 		       SYM_MASK(IBCCtrl, LinkDownDefaultState)) ?
2412 			IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
2413 		goto done;
2414 
2415 	case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2416 		lsb = IBA7220_IBC_HRTBT_SHIFT;
2417 		maskr = IBA7220_IBC_HRTBT_MASK;
2418 		break;
2419 
2420 	case QIB_IB_CFG_PMA_TICKS:
2421 		/*
2422 		 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
2423 		 * Since the clock is always 250MHz, the value is 1 or 0.
2424 		 */
2425 		ret = (ppd->link_speed_active == QIB_IB_DDR);
2426 		goto done;
2427 
2428 	default:
2429 		ret = -EINVAL;
2430 		goto done;
2431 	}
2432 	ret = (int)((ppd->cpspec->ibcddrctrl >> lsb) & maskr);
2433 done:
2434 	return ret;
2435 }
2436 
2437 static int qib_7220_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
2438 {
2439 	struct qib_devdata *dd = ppd->dd;
2440 	u64 maskr; /* right-justified mask */
2441 	int lsb, ret = 0, setforce = 0;
2442 	u16 lcmd, licmd;
2443 	unsigned long flags;
2444 	u32 tmp = 0;
2445 
2446 	switch (which) {
2447 	case QIB_IB_CFG_LIDLMC:
2448 		/*
2449 		 * Set LID and LMC. Combined to avoid possible hazard
2450 		 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2451 		 */
2452 		lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2453 		maskr = IBA7220_IBC_DLIDLMC_MASK;
2454 		break;
2455 
2456 	case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
2457 		/*
2458 		 * As with speed, only write the actual register if
2459 		 * the link is currently down, otherwise takes effect
2460 		 * on next link change.
2461 		 */
2462 		ppd->link_width_enabled = val;
2463 		if (!(ppd->lflags & QIBL_LINKDOWN))
2464 			goto bail;
2465 		/*
2466 		 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2467 		 * will get called because we want update
2468 		 * link_width_active, and the change may not take
2469 		 * effect for some time (if we are in POLL), so this
2470 		 * flag will force the updown routine to be called
2471 		 * on the next ibstatuschange down interrupt, even
2472 		 * if it's not an down->up transition.
2473 		 */
2474 		val--; /* convert from IB to chip */
2475 		maskr = IBA7220_IBC_WIDTH_MASK;
2476 		lsb = IBA7220_IBC_WIDTH_SHIFT;
2477 		setforce = 1;
2478 		break;
2479 
2480 	case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2481 		/*
2482 		 * If we turn off IB1.2, need to preset SerDes defaults,
2483 		 * but not right now. Set a flag for the next time
2484 		 * we command the link down.  As with width, only write the
2485 		 * actual register if the link is currently down, otherwise
2486 		 * takes effect on next link change.  Since setting is being
2487 		 * explicitly requested (via MAD or sysfs), clear autoneg
2488 		 * failure status if speed autoneg is enabled.
2489 		 */
2490 		ppd->link_speed_enabled = val;
2491 		if ((ppd->cpspec->ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK) &&
2492 		    !(val & (val - 1)))
2493 			dd->cspec->presets_needed = 1;
2494 		if (!(ppd->lflags & QIBL_LINKDOWN))
2495 			goto bail;
2496 		/*
2497 		 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2498 		 * will get called because we want update
2499 		 * link_speed_active, and the change may not take
2500 		 * effect for some time (if we are in POLL), so this
2501 		 * flag will force the updown routine to be called
2502 		 * on the next ibstatuschange down interrupt, even
2503 		 * if it's not an down->up transition.
2504 		 */
2505 		if (val == (QIB_IB_SDR | QIB_IB_DDR)) {
2506 			val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2507 				IBA7220_IBC_IBTA_1_2_MASK;
2508 			spin_lock_irqsave(&ppd->lflags_lock, flags);
2509 			ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
2510 			spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2511 		} else
2512 			val = val == QIB_IB_DDR ?
2513 				IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2514 		maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2515 			IBA7220_IBC_IBTA_1_2_MASK;
2516 		/* IBTA 1.2 mode + speed bits are contiguous */
2517 		lsb = SYM_LSB(IBCDDRCtrl, IB_ENHANCED_MODE);
2518 		setforce = 1;
2519 		break;
2520 
2521 	case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2522 		lsb = IBA7220_IBC_RXPOL_SHIFT;
2523 		maskr = IBA7220_IBC_RXPOL_MASK;
2524 		break;
2525 
2526 	case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2527 		lsb = IBA7220_IBC_LREV_SHIFT;
2528 		maskr = IBA7220_IBC_LREV_MASK;
2529 		break;
2530 
2531 	case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
2532 		maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2533 				  OverrunThreshold);
2534 		if (maskr != val) {
2535 			ppd->cpspec->ibcctrl &=
2536 				~SYM_MASK(IBCCtrl, OverrunThreshold);
2537 			ppd->cpspec->ibcctrl |= (u64) val <<
2538 				SYM_LSB(IBCCtrl, OverrunThreshold);
2539 			qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2540 			qib_write_kreg(dd, kr_scratch, 0);
2541 		}
2542 		goto bail;
2543 
2544 	case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
2545 		maskr = SYM_FIELD(ppd->cpspec->ibcctrl, IBCCtrl,
2546 				  PhyerrThreshold);
2547 		if (maskr != val) {
2548 			ppd->cpspec->ibcctrl &=
2549 				~SYM_MASK(IBCCtrl, PhyerrThreshold);
2550 			ppd->cpspec->ibcctrl |= (u64) val <<
2551 				SYM_LSB(IBCCtrl, PhyerrThreshold);
2552 			qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2553 			qib_write_kreg(dd, kr_scratch, 0);
2554 		}
2555 		goto bail;
2556 
2557 	case QIB_IB_CFG_PKEYS: /* update pkeys */
2558 		maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
2559 			((u64) ppd->pkeys[2] << 32) |
2560 			((u64) ppd->pkeys[3] << 48);
2561 		qib_write_kreg(dd, kr_partitionkey, maskr);
2562 		goto bail;
2563 
2564 	case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
2565 		/* will only take effect when the link state changes */
2566 		if (val == IB_LINKINITCMD_POLL)
2567 			ppd->cpspec->ibcctrl &=
2568 				~SYM_MASK(IBCCtrl, LinkDownDefaultState);
2569 		else /* SLEEP */
2570 			ppd->cpspec->ibcctrl |=
2571 				SYM_MASK(IBCCtrl, LinkDownDefaultState);
2572 		qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2573 		qib_write_kreg(dd, kr_scratch, 0);
2574 		goto bail;
2575 
2576 	case QIB_IB_CFG_MTU: /* update the MTU in IBC */
2577 		/*
2578 		 * Update our housekeeping variables, and set IBC max
2579 		 * size, same as init code; max IBC is max we allow in
2580 		 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2581 		 * Set even if it's unchanged, print debug message only
2582 		 * on changes.
2583 		 */
2584 		val = (ppd->ibmaxlen >> 2) + 1;
2585 		ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen);
2586 		ppd->cpspec->ibcctrl |= (u64)val << SYM_LSB(IBCCtrl, MaxPktLen);
2587 		qib_write_kreg(dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2588 		qib_write_kreg(dd, kr_scratch, 0);
2589 		goto bail;
2590 
2591 	case QIB_IB_CFG_LSTATE: /* set the IB link state */
2592 		switch (val & 0xffff0000) {
2593 		case IB_LINKCMD_DOWN:
2594 			lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
2595 			if (!ppd->cpspec->ibdeltainprog &&
2596 			    qib_compat_ddr_negotiate) {
2597 				ppd->cpspec->ibdeltainprog = 1;
2598 				ppd->cpspec->ibsymsnap =
2599 					read_7220_creg32(dd, cr_ibsymbolerr);
2600 				ppd->cpspec->iblnkerrsnap =
2601 					read_7220_creg32(dd, cr_iblinkerrrecov);
2602 			}
2603 			break;
2604 
2605 		case IB_LINKCMD_ARMED:
2606 			lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
2607 			break;
2608 
2609 		case IB_LINKCMD_ACTIVE:
2610 			lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
2611 			break;
2612 
2613 		default:
2614 			ret = -EINVAL;
2615 			qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
2616 			goto bail;
2617 		}
2618 		switch (val & 0xffff) {
2619 		case IB_LINKINITCMD_NOP:
2620 			licmd = 0;
2621 			break;
2622 
2623 		case IB_LINKINITCMD_POLL:
2624 			licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
2625 			break;
2626 
2627 		case IB_LINKINITCMD_SLEEP:
2628 			licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
2629 			break;
2630 
2631 		case IB_LINKINITCMD_DISABLE:
2632 			licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
2633 			ppd->cpspec->chase_end = 0;
2634 			/*
2635 			 * stop state chase counter and timer, if running.
2636 			 * wait forpending timer, but don't clear .data (ppd)!
2637 			 */
2638 			if (ppd->cpspec->chase_timer.expires) {
2639 				del_timer_sync(&ppd->cpspec->chase_timer);
2640 				ppd->cpspec->chase_timer.expires = 0;
2641 			}
2642 			break;
2643 
2644 		default:
2645 			ret = -EINVAL;
2646 			qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
2647 				    val & 0xffff);
2648 			goto bail;
2649 		}
2650 		qib_set_ib_7220_lstate(ppd, lcmd, licmd);
2651 
2652 		maskr = IBA7220_IBC_WIDTH_MASK;
2653 		lsb = IBA7220_IBC_WIDTH_SHIFT;
2654 		tmp = (ppd->cpspec->ibcddrctrl >> lsb) & maskr;
2655 		/* If the width active on the chip does not match the
2656 		 * width in the shadow register, write the new active
2657 		 * width to the chip.
2658 		 * We don't have to worry about speed as the speed is taken
2659 		 * care of by set_7220_ibspeed_fast called by ib_updown.
2660 		 */
2661 		if (ppd->link_width_enabled-1 != tmp) {
2662 			ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2663 			ppd->cpspec->ibcddrctrl |=
2664 				(((u64)(ppd->link_width_enabled-1) & maskr) <<
2665 				 lsb);
2666 			qib_write_kreg(dd, kr_ibcddrctrl,
2667 				       ppd->cpspec->ibcddrctrl);
2668 			qib_write_kreg(dd, kr_scratch, 0);
2669 			spin_lock_irqsave(&ppd->lflags_lock, flags);
2670 			ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2671 			spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2672 		}
2673 		goto bail;
2674 
2675 	case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2676 		if (val > IBA7220_IBC_HRTBT_MASK) {
2677 			ret = -EINVAL;
2678 			goto bail;
2679 		}
2680 		lsb = IBA7220_IBC_HRTBT_SHIFT;
2681 		maskr = IBA7220_IBC_HRTBT_MASK;
2682 		break;
2683 
2684 	default:
2685 		ret = -EINVAL;
2686 		goto bail;
2687 	}
2688 	ppd->cpspec->ibcddrctrl &= ~(maskr << lsb);
2689 	ppd->cpspec->ibcddrctrl |= (((u64) val & maskr) << lsb);
2690 	qib_write_kreg(dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
2691 	qib_write_kreg(dd, kr_scratch, 0);
2692 	if (setforce) {
2693 		spin_lock_irqsave(&ppd->lflags_lock, flags);
2694 		ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
2695 		spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2696 	}
2697 bail:
2698 	return ret;
2699 }
2700 
2701 static int qib_7220_set_loopback(struct qib_pportdata *ppd, const char *what)
2702 {
2703 	int ret = 0;
2704 	u64 val, ddr;
2705 
2706 	if (!strncmp(what, "ibc", 3)) {
2707 		ppd->cpspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback);
2708 		val = 0; /* disable heart beat, so link will come up */
2709 		qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
2710 			 ppd->dd->unit, ppd->port);
2711 	} else if (!strncmp(what, "off", 3)) {
2712 		ppd->cpspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback);
2713 		/* enable heart beat again */
2714 		val = IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
2715 		qib_devinfo(ppd->dd->pcidev,
2716 			"Disabling IB%u:%u IBC loopback (normal)\n",
2717 			ppd->dd->unit, ppd->port);
2718 	} else
2719 		ret = -EINVAL;
2720 	if (!ret) {
2721 		qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->cpspec->ibcctrl);
2722 		ddr = ppd->cpspec->ibcddrctrl & ~(IBA7220_IBC_HRTBT_MASK
2723 					     << IBA7220_IBC_HRTBT_SHIFT);
2724 		ppd->cpspec->ibcddrctrl = ddr | val;
2725 		qib_write_kreg(ppd->dd, kr_ibcddrctrl,
2726 			       ppd->cpspec->ibcddrctrl);
2727 		qib_write_kreg(ppd->dd, kr_scratch, 0);
2728 	}
2729 	return ret;
2730 }
2731 
2732 static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
2733 				    u32 updegr, u32 egrhd, u32 npkts)
2734 {
2735 	if (updegr)
2736 		qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
2737 	mmiowb();
2738 	qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
2739 	mmiowb();
2740 }
2741 
2742 static u32 qib_7220_hdrqempty(struct qib_ctxtdata *rcd)
2743 {
2744 	u32 head, tail;
2745 
2746 	head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
2747 	if (rcd->rcvhdrtail_kvaddr)
2748 		tail = qib_get_rcvhdrtail(rcd);
2749 	else
2750 		tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
2751 	return head == tail;
2752 }
2753 
2754 /*
2755  * Modify the RCVCTRL register in chip-specific way. This
2756  * is a function because bit positions and (future) register
2757  * location is chip-specifc, but the needed operations are
2758  * generic. <op> is a bit-mask because we often want to
2759  * do multiple modifications.
2760  */
2761 static void rcvctrl_7220_mod(struct qib_pportdata *ppd, unsigned int op,
2762 			     int ctxt)
2763 {
2764 	struct qib_devdata *dd = ppd->dd;
2765 	u64 mask, val;
2766 	unsigned long flags;
2767 
2768 	spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2769 	if (op & QIB_RCVCTRL_TAILUPD_ENB)
2770 		dd->rcvctrl |= (1ULL << IBA7220_R_TAILUPD_SHIFT);
2771 	if (op & QIB_RCVCTRL_TAILUPD_DIS)
2772 		dd->rcvctrl &= ~(1ULL << IBA7220_R_TAILUPD_SHIFT);
2773 	if (op & QIB_RCVCTRL_PKEY_ENB)
2774 		dd->rcvctrl &= ~(1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2775 	if (op & QIB_RCVCTRL_PKEY_DIS)
2776 		dd->rcvctrl |= (1ULL << IBA7220_R_PKEY_DIS_SHIFT);
2777 	if (ctxt < 0)
2778 		mask = (1ULL << dd->ctxtcnt) - 1;
2779 	else
2780 		mask = (1ULL << ctxt);
2781 	if (op & QIB_RCVCTRL_CTXT_ENB) {
2782 		/* always done for specific ctxt */
2783 		dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable));
2784 		if (!(dd->flags & QIB_NODMA_RTAIL))
2785 			dd->rcvctrl |= 1ULL << IBA7220_R_TAILUPD_SHIFT;
2786 		/* Write these registers before the context is enabled. */
2787 		qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt,
2788 			dd->rcd[ctxt]->rcvhdrqtailaddr_phys);
2789 		qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt,
2790 			dd->rcd[ctxt]->rcvhdrq_phys);
2791 		dd->rcd[ctxt]->seq_cnt = 1;
2792 	}
2793 	if (op & QIB_RCVCTRL_CTXT_DIS)
2794 		dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable));
2795 	if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
2796 		dd->rcvctrl |= (mask << IBA7220_R_INTRAVAIL_SHIFT);
2797 	if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
2798 		dd->rcvctrl &= ~(mask << IBA7220_R_INTRAVAIL_SHIFT);
2799 	qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
2800 	if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) {
2801 		/* arm rcv interrupt */
2802 		val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) |
2803 			dd->rhdrhead_intr_off;
2804 		qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2805 	}
2806 	if (op & QIB_RCVCTRL_CTXT_ENB) {
2807 		/*
2808 		 * Init the context registers also; if we were
2809 		 * disabled, tail and head should both be zero
2810 		 * already from the enable, but since we don't
2811 		 * know, we have to do it explicitly.
2812 		 */
2813 		val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2814 		qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
2815 
2816 		val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
2817 		dd->rcd[ctxt]->head = val;
2818 		/* If kctxt, interrupt on next receive. */
2819 		if (ctxt < dd->first_user_ctxt)
2820 			val |= dd->rhdrhead_intr_off;
2821 		qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
2822 	}
2823 	if (op & QIB_RCVCTRL_CTXT_DIS) {
2824 		if (ctxt >= 0) {
2825 			qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, 0);
2826 			qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, 0);
2827 		} else {
2828 			unsigned i;
2829 
2830 			for (i = 0; i < dd->cfgctxts; i++) {
2831 				qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr,
2832 						    i, 0);
2833 				qib_write_kreg_ctxt(dd, kr_rcvhdraddr, i, 0);
2834 			}
2835 		}
2836 	}
2837 	spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2838 }
2839 
2840 /*
2841  * Modify the SENDCTRL register in chip-specific way. This
2842  * is a function there may be multiple such registers with
2843  * slightly different layouts. To start, we assume the
2844  * "canonical" register layout of the first chips.
2845  * Chip requires no back-back sendctrl writes, so write
2846  * scratch register after writing sendctrl
2847  */
2848 static void sendctrl_7220_mod(struct qib_pportdata *ppd, u32 op)
2849 {
2850 	struct qib_devdata *dd = ppd->dd;
2851 	u64 tmp_dd_sendctrl;
2852 	unsigned long flags;
2853 
2854 	spin_lock_irqsave(&dd->sendctrl_lock, flags);
2855 
2856 	/* First the ones that are "sticky", saved in shadow */
2857 	if (op & QIB_SENDCTRL_CLEAR)
2858 		dd->sendctrl = 0;
2859 	if (op & QIB_SENDCTRL_SEND_DIS)
2860 		dd->sendctrl &= ~SYM_MASK(SendCtrl, SPioEnable);
2861 	else if (op & QIB_SENDCTRL_SEND_ENB) {
2862 		dd->sendctrl |= SYM_MASK(SendCtrl, SPioEnable);
2863 		if (dd->flags & QIB_USE_SPCL_TRIG)
2864 			dd->sendctrl |= SYM_MASK(SendCtrl,
2865 						 SSpecialTriggerEn);
2866 	}
2867 	if (op & QIB_SENDCTRL_AVAIL_DIS)
2868 		dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2869 	else if (op & QIB_SENDCTRL_AVAIL_ENB)
2870 		dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
2871 
2872 	if (op & QIB_SENDCTRL_DISARM_ALL) {
2873 		u32 i, last;
2874 
2875 		tmp_dd_sendctrl = dd->sendctrl;
2876 		/*
2877 		 * disarm any that are not yet launched, disabling sends
2878 		 * and updates until done.
2879 		 */
2880 		last = dd->piobcnt2k + dd->piobcnt4k;
2881 		tmp_dd_sendctrl &=
2882 			~(SYM_MASK(SendCtrl, SPioEnable) |
2883 			  SYM_MASK(SendCtrl, SendBufAvailUpd));
2884 		for (i = 0; i < last; i++) {
2885 			qib_write_kreg(dd, kr_sendctrl,
2886 				       tmp_dd_sendctrl |
2887 				       SYM_MASK(SendCtrl, Disarm) | i);
2888 			qib_write_kreg(dd, kr_scratch, 0);
2889 		}
2890 	}
2891 
2892 	tmp_dd_sendctrl = dd->sendctrl;
2893 
2894 	if (op & QIB_SENDCTRL_FLUSH)
2895 		tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort);
2896 	if (op & QIB_SENDCTRL_DISARM)
2897 		tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
2898 			((op & QIB_7220_SendCtrl_DisarmPIOBuf_RMASK) <<
2899 			 SYM_LSB(SendCtrl, DisarmPIOBuf));
2900 	if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
2901 	    (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
2902 		tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
2903 
2904 	qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
2905 	qib_write_kreg(dd, kr_scratch, 0);
2906 
2907 	if (op & QIB_SENDCTRL_AVAIL_BLIP) {
2908 		qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2909 		qib_write_kreg(dd, kr_scratch, 0);
2910 	}
2911 
2912 	spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2913 
2914 	if (op & QIB_SENDCTRL_FLUSH) {
2915 		u32 v;
2916 		/*
2917 		 * ensure writes have hit chip, then do a few
2918 		 * more reads, to allow DMA of pioavail registers
2919 		 * to occur, so in-memory copy is in sync with
2920 		 * the chip.  Not always safe to sleep.
2921 		 */
2922 		v = qib_read_kreg32(dd, kr_scratch);
2923 		qib_write_kreg(dd, kr_scratch, v);
2924 		v = qib_read_kreg32(dd, kr_scratch);
2925 		qib_write_kreg(dd, kr_scratch, v);
2926 		qib_read_kreg32(dd, kr_scratch);
2927 	}
2928 }
2929 
2930 /**
2931  * qib_portcntr_7220 - read a per-port counter
2932  * @dd: the qlogic_ib device
2933  * @creg: the counter to snapshot
2934  */
2935 static u64 qib_portcntr_7220(struct qib_pportdata *ppd, u32 reg)
2936 {
2937 	u64 ret = 0ULL;
2938 	struct qib_devdata *dd = ppd->dd;
2939 	u16 creg;
2940 	/* 0xffff for unimplemented or synthesized counters */
2941 	static const u16 xlator[] = {
2942 		[QIBPORTCNTR_PKTSEND] = cr_pktsend,
2943 		[QIBPORTCNTR_WORDSEND] = cr_wordsend,
2944 		[QIBPORTCNTR_PSXMITDATA] = cr_psxmitdatacount,
2945 		[QIBPORTCNTR_PSXMITPKTS] = cr_psxmitpktscount,
2946 		[QIBPORTCNTR_PSXMITWAIT] = cr_psxmitwaitcount,
2947 		[QIBPORTCNTR_SENDSTALL] = cr_sendstall,
2948 		[QIBPORTCNTR_PKTRCV] = cr_pktrcv,
2949 		[QIBPORTCNTR_PSRCVDATA] = cr_psrcvdatacount,
2950 		[QIBPORTCNTR_PSRCVPKTS] = cr_psrcvpktscount,
2951 		[QIBPORTCNTR_RCVEBP] = cr_rcvebp,
2952 		[QIBPORTCNTR_RCVOVFL] = cr_rcvovfl,
2953 		[QIBPORTCNTR_WORDRCV] = cr_wordrcv,
2954 		[QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt,
2955 		[QIBPORTCNTR_RXLOCALPHYERR] = cr_rxotherlocalphyerr,
2956 		[QIBPORTCNTR_RXVLERR] = cr_rxvlerr,
2957 		[QIBPORTCNTR_ERRICRC] = cr_erricrc,
2958 		[QIBPORTCNTR_ERRVCRC] = cr_errvcrc,
2959 		[QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc,
2960 		[QIBPORTCNTR_BADFORMAT] = cr_badformat,
2961 		[QIBPORTCNTR_ERR_RLEN] = cr_err_rlen,
2962 		[QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr,
2963 		[QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen,
2964 		[QIBPORTCNTR_UNSUPVL] = cr_txunsupvl,
2965 		[QIBPORTCNTR_EXCESSBUFOVFL] = cr_excessbufferovfl,
2966 		[QIBPORTCNTR_ERRLINK] = cr_errlink,
2967 		[QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown,
2968 		[QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov,
2969 		[QIBPORTCNTR_LLI] = cr_locallinkintegrityerr,
2970 		[QIBPORTCNTR_PSINTERVAL] = cr_psinterval,
2971 		[QIBPORTCNTR_PSSTART] = cr_psstart,
2972 		[QIBPORTCNTR_PSSTAT] = cr_psstat,
2973 		[QIBPORTCNTR_VL15PKTDROP] = cr_vl15droppedpkt,
2974 		[QIBPORTCNTR_ERRPKEY] = cr_errpkey,
2975 		[QIBPORTCNTR_KHDROVFL] = 0xffff,
2976 	};
2977 
2978 	if (reg >= ARRAY_SIZE(xlator)) {
2979 		qib_devinfo(ppd->dd->pcidev,
2980 			 "Unimplemented portcounter %u\n", reg);
2981 		goto done;
2982 	}
2983 	creg = xlator[reg];
2984 
2985 	if (reg == QIBPORTCNTR_KHDROVFL) {
2986 		int i;
2987 
2988 		/* sum over all kernel contexts */
2989 		for (i = 0; i < dd->first_user_ctxt; i++)
2990 			ret += read_7220_creg32(dd, cr_portovfl + i);
2991 	}
2992 	if (creg == 0xffff)
2993 		goto done;
2994 
2995 	/*
2996 	 * only fast incrementing counters are 64bit; use 32 bit reads to
2997 	 * avoid two independent reads when on opteron
2998 	 */
2999 	if ((creg == cr_wordsend || creg == cr_wordrcv ||
3000 	     creg == cr_pktsend || creg == cr_pktrcv))
3001 		ret = read_7220_creg(dd, creg);
3002 	else
3003 		ret = read_7220_creg32(dd, creg);
3004 	if (creg == cr_ibsymbolerr) {
3005 		if (dd->pport->cpspec->ibdeltainprog)
3006 			ret -= ret - ppd->cpspec->ibsymsnap;
3007 		ret -= dd->pport->cpspec->ibsymdelta;
3008 	} else if (creg == cr_iblinkerrrecov) {
3009 		if (dd->pport->cpspec->ibdeltainprog)
3010 			ret -= ret - ppd->cpspec->iblnkerrsnap;
3011 		ret -= dd->pport->cpspec->iblnkerrdelta;
3012 	}
3013 done:
3014 	return ret;
3015 }
3016 
3017 /*
3018  * Device counter names (not port-specific), one line per stat,
3019  * single string.  Used by utilities like ipathstats to print the stats
3020  * in a way which works for different versions of drivers, without changing
3021  * the utility.  Names need to be 12 chars or less (w/o newline), for proper
3022  * display by utility.
3023  * Non-error counters are first.
3024  * Start of "error" conters is indicated by a leading "E " on the first
3025  * "error" counter, and doesn't count in label length.
3026  * The EgrOvfl list needs to be last so we truncate them at the configured
3027  * context count for the device.
3028  * cntr7220indices contains the corresponding register indices.
3029  */
3030 static const char cntr7220names[] =
3031 	"Interrupts\n"
3032 	"HostBusStall\n"
3033 	"E RxTIDFull\n"
3034 	"RxTIDInvalid\n"
3035 	"Ctxt0EgrOvfl\n"
3036 	"Ctxt1EgrOvfl\n"
3037 	"Ctxt2EgrOvfl\n"
3038 	"Ctxt3EgrOvfl\n"
3039 	"Ctxt4EgrOvfl\n"
3040 	"Ctxt5EgrOvfl\n"
3041 	"Ctxt6EgrOvfl\n"
3042 	"Ctxt7EgrOvfl\n"
3043 	"Ctxt8EgrOvfl\n"
3044 	"Ctxt9EgrOvfl\n"
3045 	"Ctx10EgrOvfl\n"
3046 	"Ctx11EgrOvfl\n"
3047 	"Ctx12EgrOvfl\n"
3048 	"Ctx13EgrOvfl\n"
3049 	"Ctx14EgrOvfl\n"
3050 	"Ctx15EgrOvfl\n"
3051 	"Ctx16EgrOvfl\n";
3052 
3053 static const size_t cntr7220indices[] = {
3054 	cr_lbint,
3055 	cr_lbflowstall,
3056 	cr_errtidfull,
3057 	cr_errtidvalid,
3058 	cr_portovfl + 0,
3059 	cr_portovfl + 1,
3060 	cr_portovfl + 2,
3061 	cr_portovfl + 3,
3062 	cr_portovfl + 4,
3063 	cr_portovfl + 5,
3064 	cr_portovfl + 6,
3065 	cr_portovfl + 7,
3066 	cr_portovfl + 8,
3067 	cr_portovfl + 9,
3068 	cr_portovfl + 10,
3069 	cr_portovfl + 11,
3070 	cr_portovfl + 12,
3071 	cr_portovfl + 13,
3072 	cr_portovfl + 14,
3073 	cr_portovfl + 15,
3074 	cr_portovfl + 16,
3075 };
3076 
3077 /*
3078  * same as cntr7220names and cntr7220indices, but for port-specific counters.
3079  * portcntr7220indices is somewhat complicated by some registers needing
3080  * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
3081  */
3082 static const char portcntr7220names[] =
3083 	"TxPkt\n"
3084 	"TxFlowPkt\n"
3085 	"TxWords\n"
3086 	"RxPkt\n"
3087 	"RxFlowPkt\n"
3088 	"RxWords\n"
3089 	"TxFlowStall\n"
3090 	"TxDmaDesc\n"  /* 7220 and 7322-only */
3091 	"E RxDlidFltr\n"  /* 7220 and 7322-only */
3092 	"IBStatusChng\n"
3093 	"IBLinkDown\n"
3094 	"IBLnkRecov\n"
3095 	"IBRxLinkErr\n"
3096 	"IBSymbolErr\n"
3097 	"RxLLIErr\n"
3098 	"RxBadFormat\n"
3099 	"RxBadLen\n"
3100 	"RxBufOvrfl\n"
3101 	"RxEBP\n"
3102 	"RxFlowCtlErr\n"
3103 	"RxICRCerr\n"
3104 	"RxLPCRCerr\n"
3105 	"RxVCRCerr\n"
3106 	"RxInvalLen\n"
3107 	"RxInvalPKey\n"
3108 	"RxPktDropped\n"
3109 	"TxBadLength\n"
3110 	"TxDropped\n"
3111 	"TxInvalLen\n"
3112 	"TxUnderrun\n"
3113 	"TxUnsupVL\n"
3114 	"RxLclPhyErr\n" /* 7220 and 7322-only */
3115 	"RxVL15Drop\n" /* 7220 and 7322-only */
3116 	"RxVlErr\n" /* 7220 and 7322-only */
3117 	"XcessBufOvfl\n" /* 7220 and 7322-only */
3118 	;
3119 
3120 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
3121 static const size_t portcntr7220indices[] = {
3122 	QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
3123 	cr_pktsendflow,
3124 	QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
3125 	QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
3126 	cr_pktrcvflowctrl,
3127 	QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
3128 	QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
3129 	cr_txsdmadesc,
3130 	cr_rxdlidfltr,
3131 	cr_ibstatuschange,
3132 	QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
3133 	QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
3134 	QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
3135 	QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
3136 	QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
3137 	QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
3138 	QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
3139 	QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
3140 	QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
3141 	cr_rcvflowctrl_err,
3142 	QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
3143 	QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
3144 	QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
3145 	QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
3146 	QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
3147 	QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
3148 	cr_invalidslen,
3149 	cr_senddropped,
3150 	cr_errslen,
3151 	cr_sendunderrun,
3152 	cr_txunsupvl,
3153 	QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
3154 	QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
3155 	QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
3156 	QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
3157 };
3158 
3159 /* do all the setup to make the counter reads efficient later */
3160 static void init_7220_cntrnames(struct qib_devdata *dd)
3161 {
3162 	int i, j = 0;
3163 	char *s;
3164 
3165 	for (i = 0, s = (char *)cntr7220names; s && j <= dd->cfgctxts;
3166 	     i++) {
3167 		/* we always have at least one counter before the egrovfl */
3168 		if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
3169 			j = 1;
3170 		s = strchr(s + 1, '\n');
3171 		if (s && j)
3172 			j++;
3173 	}
3174 	dd->cspec->ncntrs = i;
3175 	if (!s)
3176 		/* full list; size is without terminating null */
3177 		dd->cspec->cntrnamelen = sizeof(cntr7220names) - 1;
3178 	else
3179 		dd->cspec->cntrnamelen = 1 + s - cntr7220names;
3180 	dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
3181 		* sizeof(u64), GFP_KERNEL);
3182 	if (!dd->cspec->cntrs)
3183 		qib_dev_err(dd, "Failed allocation for counters\n");
3184 
3185 	for (i = 0, s = (char *)portcntr7220names; s; i++)
3186 		s = strchr(s + 1, '\n');
3187 	dd->cspec->nportcntrs = i - 1;
3188 	dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1;
3189 	dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
3190 		* sizeof(u64), GFP_KERNEL);
3191 	if (!dd->cspec->portcntrs)
3192 		qib_dev_err(dd, "Failed allocation for portcounters\n");
3193 }
3194 
3195 static u32 qib_read_7220cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
3196 			      u64 **cntrp)
3197 {
3198 	u32 ret;
3199 
3200 	if (!dd->cspec->cntrs) {
3201 		ret = 0;
3202 		goto done;
3203 	}
3204 
3205 	if (namep) {
3206 		*namep = (char *)cntr7220names;
3207 		ret = dd->cspec->cntrnamelen;
3208 		if (pos >= ret)
3209 			ret = 0; /* final read after getting everything */
3210 	} else {
3211 		u64 *cntr = dd->cspec->cntrs;
3212 		int i;
3213 
3214 		ret = dd->cspec->ncntrs * sizeof(u64);
3215 		if (!cntr || pos >= ret) {
3216 			/* everything read, or couldn't get memory */
3217 			ret = 0;
3218 			goto done;
3219 		}
3220 
3221 		*cntrp = cntr;
3222 		for (i = 0; i < dd->cspec->ncntrs; i++)
3223 			*cntr++ = read_7220_creg32(dd, cntr7220indices[i]);
3224 	}
3225 done:
3226 	return ret;
3227 }
3228 
3229 static u32 qib_read_7220portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
3230 				  char **namep, u64 **cntrp)
3231 {
3232 	u32 ret;
3233 
3234 	if (!dd->cspec->portcntrs) {
3235 		ret = 0;
3236 		goto done;
3237 	}
3238 	if (namep) {
3239 		*namep = (char *)portcntr7220names;
3240 		ret = dd->cspec->portcntrnamelen;
3241 		if (pos >= ret)
3242 			ret = 0; /* final read after getting everything */
3243 	} else {
3244 		u64 *cntr = dd->cspec->portcntrs;
3245 		struct qib_pportdata *ppd = &dd->pport[port];
3246 		int i;
3247 
3248 		ret = dd->cspec->nportcntrs * sizeof(u64);
3249 		if (!cntr || pos >= ret) {
3250 			/* everything read, or couldn't get memory */
3251 			ret = 0;
3252 			goto done;
3253 		}
3254 		*cntrp = cntr;
3255 		for (i = 0; i < dd->cspec->nportcntrs; i++) {
3256 			if (portcntr7220indices[i] & _PORT_VIRT_FLAG)
3257 				*cntr++ = qib_portcntr_7220(ppd,
3258 					portcntr7220indices[i] &
3259 					~_PORT_VIRT_FLAG);
3260 			else
3261 				*cntr++ = read_7220_creg32(dd,
3262 					   portcntr7220indices[i]);
3263 		}
3264 	}
3265 done:
3266 	return ret;
3267 }
3268 
3269 /**
3270  * qib_get_7220_faststats - get word counters from chip before they overflow
3271  * @opaque - contains a pointer to the qlogic_ib device qib_devdata
3272  *
3273  * This needs more work; in particular, decision on whether we really
3274  * need traffic_wds done the way it is
3275  * called from add_timer
3276  */
3277 static void qib_get_7220_faststats(unsigned long opaque)
3278 {
3279 	struct qib_devdata *dd = (struct qib_devdata *) opaque;
3280 	struct qib_pportdata *ppd = dd->pport;
3281 	unsigned long flags;
3282 	u64 traffic_wds;
3283 
3284 	/*
3285 	 * don't access the chip while running diags, or memory diags can
3286 	 * fail
3287 	 */
3288 	if (!(dd->flags & QIB_INITTED) || dd->diag_client)
3289 		/* but re-arm the timer, for diags case; won't hurt other */
3290 		goto done;
3291 
3292 	/*
3293 	 * We now try to maintain an activity timer, based on traffic
3294 	 * exceeding a threshold, so we need to check the word-counts
3295 	 * even if they are 64-bit.
3296 	 */
3297 	traffic_wds = qib_portcntr_7220(ppd, cr_wordsend) +
3298 		qib_portcntr_7220(ppd, cr_wordrcv);
3299 	spin_lock_irqsave(&dd->eep_st_lock, flags);
3300 	traffic_wds -= dd->traffic_wds;
3301 	dd->traffic_wds += traffic_wds;
3302 	spin_unlock_irqrestore(&dd->eep_st_lock, flags);
3303 done:
3304 	mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
3305 }
3306 
3307 /*
3308  * If we are using MSI, try to fallback to INTx.
3309  */
3310 static int qib_7220_intr_fallback(struct qib_devdata *dd)
3311 {
3312 	if (!dd->msi_lo)
3313 		return 0;
3314 
3315 	qib_devinfo(dd->pcidev,
3316 		"MSI interrupt not detected, trying INTx interrupts\n");
3317 	qib_7220_free_irq(dd);
3318 	qib_enable_intx(dd->pcidev);
3319 	/*
3320 	 * Some newer kernels require free_irq before disable_msi,
3321 	 * and irq can be changed during disable and INTx enable
3322 	 * and we need to therefore use the pcidev->irq value,
3323 	 * not our saved MSI value.
3324 	 */
3325 	dd->cspec->irq = dd->pcidev->irq;
3326 	qib_setup_7220_interrupt(dd);
3327 	return 1;
3328 }
3329 
3330 /*
3331  * Reset the XGXS (between serdes and IBC).  Slightly less intrusive
3332  * than resetting the IBC or external link state, and useful in some
3333  * cases to cause some retraining.  To do this right, we reset IBC
3334  * as well.
3335  */
3336 static void qib_7220_xgxs_reset(struct qib_pportdata *ppd)
3337 {
3338 	u64 val, prev_val;
3339 	struct qib_devdata *dd = ppd->dd;
3340 
3341 	prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
3342 	val = prev_val | QLOGIC_IB_XGXS_RESET;
3343 	prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */
3344 	qib_write_kreg(dd, kr_control,
3345 		       dd->control & ~QLOGIC_IB_C_LINKENABLE);
3346 	qib_write_kreg(dd, kr_xgxs_cfg, val);
3347 	qib_read_kreg32(dd, kr_scratch);
3348 	qib_write_kreg(dd, kr_xgxs_cfg, prev_val);
3349 	qib_write_kreg(dd, kr_control, dd->control);
3350 }
3351 
3352 /*
3353  * For this chip, we want to use the same buffer every time
3354  * when we are trying to bring the link up (they are always VL15
3355  * packets).  At that link state the packet should always go out immediately
3356  * (or at least be discarded at the tx interface if the link is down).
3357  * If it doesn't, and the buffer isn't available, that means some other
3358  * sender has gotten ahead of us, and is preventing our packet from going
3359  * out.  In that case, we flush all packets, and try again.  If that still
3360  * fails, we fail the request, and hope things work the next time around.
3361  *
3362  * We don't need very complicated heuristics on whether the packet had
3363  * time to go out or not, since even at SDR 1X, it goes out in very short
3364  * time periods, covered by the chip reads done here and as part of the
3365  * flush.
3366  */
3367 static u32 __iomem *get_7220_link_buf(struct qib_pportdata *ppd, u32 *bnum)
3368 {
3369 	u32 __iomem *buf;
3370 	u32 lbuf = ppd->dd->cspec->lastbuf_for_pio;
3371 	int do_cleanup;
3372 	unsigned long flags;
3373 
3374 	/*
3375 	 * always blip to get avail list updated, since it's almost
3376 	 * always needed, and is fairly cheap.
3377 	 */
3378 	sendctrl_7220_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
3379 	qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3380 	buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3381 	if (buf)
3382 		goto done;
3383 
3384 	spin_lock_irqsave(&ppd->sdma_lock, flags);
3385 	if (ppd->sdma_state.current_state == qib_sdma_state_s20_idle &&
3386 	    ppd->sdma_state.current_state != qib_sdma_state_s00_hw_down) {
3387 		__qib_sdma_process_event(ppd, qib_sdma_event_e00_go_hw_down);
3388 		do_cleanup = 0;
3389 	} else {
3390 		do_cleanup = 1;
3391 		qib_7220_sdma_hw_clean_up(ppd);
3392 	}
3393 	spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3394 
3395 	if (do_cleanup) {
3396 		qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3397 		buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf);
3398 	}
3399 done:
3400 	return buf;
3401 }
3402 
3403 /*
3404  * This code for non-IBTA-compliant IB speed negotiation is only known to
3405  * work for the SDR to DDR transition, and only between an HCA and a switch
3406  * with recent firmware.  It is based on observed heuristics, rather than
3407  * actual knowledge of the non-compliant speed negotiation.
3408  * It has a number of hard-coded fields, since the hope is to rewrite this
3409  * when a spec is available on how the negoation is intended to work.
3410  */
3411 static void autoneg_7220_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
3412 				 u32 dcnt, u32 *data)
3413 {
3414 	int i;
3415 	u64 pbc;
3416 	u32 __iomem *piobuf;
3417 	u32 pnum;
3418 	struct qib_devdata *dd = ppd->dd;
3419 
3420 	i = 0;
3421 	pbc = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
3422 	pbc |= PBC_7220_VL15_SEND;
3423 	while (!(piobuf = get_7220_link_buf(ppd, &pnum))) {
3424 		if (i++ > 5)
3425 			return;
3426 		udelay(2);
3427 	}
3428 	sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_DISARM_BUF(pnum));
3429 	writeq(pbc, piobuf);
3430 	qib_flush_wc();
3431 	qib_pio_copy(piobuf + 2, hdr, 7);
3432 	qib_pio_copy(piobuf + 9, data, dcnt);
3433 	if (dd->flags & QIB_USE_SPCL_TRIG) {
3434 		u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
3435 
3436 		qib_flush_wc();
3437 		__raw_writel(0xaebecede, piobuf + spcl_off);
3438 	}
3439 	qib_flush_wc();
3440 	qib_sendbuf_done(dd, pnum);
3441 }
3442 
3443 /*
3444  * _start packet gets sent twice at start, _done gets sent twice at end
3445  */
3446 static void autoneg_7220_send(struct qib_pportdata *ppd, int which)
3447 {
3448 	struct qib_devdata *dd = ppd->dd;
3449 	static u32 swapped;
3450 	u32 dw, i, hcnt, dcnt, *data;
3451 	static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
3452 	static u32 madpayload_start[0x40] = {
3453 		0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3454 		0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3455 		0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
3456 		};
3457 	static u32 madpayload_done[0x40] = {
3458 		0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3459 		0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3460 		0x40000001, 0x1388, 0x15e, /* rest 0's */
3461 		};
3462 
3463 	dcnt = ARRAY_SIZE(madpayload_start);
3464 	hcnt = ARRAY_SIZE(hdr);
3465 	if (!swapped) {
3466 		/* for maintainability, do it at runtime */
3467 		for (i = 0; i < hcnt; i++) {
3468 			dw = (__force u32) cpu_to_be32(hdr[i]);
3469 			hdr[i] = dw;
3470 		}
3471 		for (i = 0; i < dcnt; i++) {
3472 			dw = (__force u32) cpu_to_be32(madpayload_start[i]);
3473 			madpayload_start[i] = dw;
3474 			dw = (__force u32) cpu_to_be32(madpayload_done[i]);
3475 			madpayload_done[i] = dw;
3476 		}
3477 		swapped = 1;
3478 	}
3479 
3480 	data = which ? madpayload_done : madpayload_start;
3481 
3482 	autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3483 	qib_read_kreg64(dd, kr_scratch);
3484 	udelay(2);
3485 	autoneg_7220_sendpkt(ppd, hdr, dcnt, data);
3486 	qib_read_kreg64(dd, kr_scratch);
3487 	udelay(2);
3488 }
3489 
3490 /*
3491  * Do the absolute minimum to cause an IB speed change, and make it
3492  * ready, but don't actually trigger the change.   The caller will
3493  * do that when ready (if link is in Polling training state, it will
3494  * happen immediately, otherwise when link next goes down)
3495  *
3496  * This routine should only be used as part of the DDR autonegotation
3497  * code for devices that are not compliant with IB 1.2 (or code that
3498  * fixes things up for same).
3499  *
3500  * When link has gone down, and autoneg enabled, or autoneg has
3501  * failed and we give up until next time we set both speeds, and
3502  * then we want IBTA enabled as well as "use max enabled speed.
3503  */
3504 static void set_7220_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
3505 {
3506 	ppd->cpspec->ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
3507 		IBA7220_IBC_IBTA_1_2_MASK);
3508 
3509 	if (speed == (QIB_IB_SDR | QIB_IB_DDR))
3510 		ppd->cpspec->ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
3511 			IBA7220_IBC_IBTA_1_2_MASK;
3512 	else
3513 		ppd->cpspec->ibcddrctrl |= speed == QIB_IB_DDR ?
3514 			IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
3515 
3516 	qib_write_kreg(ppd->dd, kr_ibcddrctrl, ppd->cpspec->ibcddrctrl);
3517 	qib_write_kreg(ppd->dd, kr_scratch, 0);
3518 }
3519 
3520 /*
3521  * This routine is only used when we are not talking to another
3522  * IB 1.2-compliant device that we think can do DDR.
3523  * (This includes all existing switch chips as of Oct 2007.)
3524  * 1.2-compliant devices go directly to DDR prior to reaching INIT
3525  */
3526 static void try_7220_autoneg(struct qib_pportdata *ppd)
3527 {
3528 	unsigned long flags;
3529 
3530 	/*
3531 	 * Required for older non-IB1.2 DDR switches.  Newer
3532 	 * non-IB-compliant switches don't need it, but so far,
3533 	 * aren't bothered by it either.  "Magic constant"
3534 	 */
3535 	qib_write_kreg(ppd->dd, kr_ncmodectrl, 0x3b9dc07);
3536 
3537 	spin_lock_irqsave(&ppd->lflags_lock, flags);
3538 	ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
3539 	spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3540 	autoneg_7220_send(ppd, 0);
3541 	set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3542 
3543 	toggle_7220_rclkrls(ppd->dd);
3544 	/* 2 msec is minimum length of a poll cycle */
3545 	queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
3546 			   msecs_to_jiffies(2));
3547 }
3548 
3549 /*
3550  * Handle the empirically determined mechanism for auto-negotiation
3551  * of DDR speed with switches.
3552  */
3553 static void autoneg_7220_work(struct work_struct *work)
3554 {
3555 	struct qib_pportdata *ppd;
3556 	struct qib_devdata *dd;
3557 	u64 startms;
3558 	u32 i;
3559 	unsigned long flags;
3560 
3561 	ppd = &container_of(work, struct qib_chippport_specific,
3562 			    autoneg_work.work)->pportdata;
3563 	dd = ppd->dd;
3564 
3565 	startms = jiffies_to_msecs(jiffies);
3566 
3567 	/*
3568 	 * Busy wait for this first part, it should be at most a
3569 	 * few hundred usec, since we scheduled ourselves for 2msec.
3570 	 */
3571 	for (i = 0; i < 25; i++) {
3572 		if (SYM_FIELD(ppd->lastibcstat, IBCStatus, LinkTrainingState)
3573 		     == IB_7220_LT_STATE_POLLQUIET) {
3574 			qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
3575 			break;
3576 		}
3577 		udelay(100);
3578 	}
3579 
3580 	if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3581 		goto done; /* we got there early or told to stop */
3582 
3583 	/* we expect this to timeout */
3584 	if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3585 			       !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3586 			       msecs_to_jiffies(90)))
3587 		goto done;
3588 
3589 	toggle_7220_rclkrls(dd);
3590 
3591 	/* we expect this to timeout */
3592 	if (wait_event_timeout(ppd->cpspec->autoneg_wait,
3593 			       !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3594 			       msecs_to_jiffies(1700)))
3595 		goto done;
3596 
3597 	set_7220_ibspeed_fast(ppd, QIB_IB_SDR);
3598 	toggle_7220_rclkrls(dd);
3599 
3600 	/*
3601 	 * Wait up to 250 msec for link to train and get to INIT at DDR;
3602 	 * this should terminate early.
3603 	 */
3604 	wait_event_timeout(ppd->cpspec->autoneg_wait,
3605 		!(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
3606 		msecs_to_jiffies(250));
3607 done:
3608 	if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
3609 		spin_lock_irqsave(&ppd->lflags_lock, flags);
3610 		ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
3611 		if (dd->cspec->autoneg_tries == AUTONEG_TRIES) {
3612 			ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
3613 			dd->cspec->autoneg_tries = 0;
3614 		}
3615 		spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3616 		set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3617 	}
3618 }
3619 
3620 static u32 qib_7220_iblink_state(u64 ibcs)
3621 {
3622 	u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState);
3623 
3624 	switch (state) {
3625 	case IB_7220_L_STATE_INIT:
3626 		state = IB_PORT_INIT;
3627 		break;
3628 	case IB_7220_L_STATE_ARM:
3629 		state = IB_PORT_ARMED;
3630 		break;
3631 	case IB_7220_L_STATE_ACTIVE:
3632 		/* fall through */
3633 	case IB_7220_L_STATE_ACT_DEFER:
3634 		state = IB_PORT_ACTIVE;
3635 		break;
3636 	default: /* fall through */
3637 	case IB_7220_L_STATE_DOWN:
3638 		state = IB_PORT_DOWN;
3639 		break;
3640 	}
3641 	return state;
3642 }
3643 
3644 /* returns the IBTA port state, rather than the IBC link training state */
3645 static u8 qib_7220_phys_portstate(u64 ibcs)
3646 {
3647 	u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState);
3648 	return qib_7220_physportstate[state];
3649 }
3650 
3651 static int qib_7220_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
3652 {
3653 	int ret = 0, symadj = 0;
3654 	struct qib_devdata *dd = ppd->dd;
3655 	unsigned long flags;
3656 
3657 	spin_lock_irqsave(&ppd->lflags_lock, flags);
3658 	ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
3659 	spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3660 
3661 	if (!ibup) {
3662 		/*
3663 		 * When the link goes down we don't want AEQ running, so it
3664 		 * won't interfere with IBC training, etc., and we need
3665 		 * to go back to the static SerDes preset values.
3666 		 */
3667 		if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3668 				     QIBL_IB_AUTONEG_INPROG)))
3669 			set_7220_ibspeed_fast(ppd, ppd->link_speed_enabled);
3670 		if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3671 			qib_sd7220_presets(dd);
3672 			qib_cancel_sends(ppd); /* initial disarm, etc. */
3673 			spin_lock_irqsave(&ppd->sdma_lock, flags);
3674 			if (__qib_sdma_running(ppd))
3675 				__qib_sdma_process_event(ppd,
3676 					qib_sdma_event_e70_go_idle);
3677 			spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3678 		}
3679 		/* this might better in qib_sd7220_presets() */
3680 		set_7220_relock_poll(dd, ibup);
3681 	} else {
3682 		if (qib_compat_ddr_negotiate &&
3683 		    !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
3684 				     QIBL_IB_AUTONEG_INPROG)) &&
3685 		    ppd->link_speed_active == QIB_IB_SDR &&
3686 		    (ppd->link_speed_enabled & (QIB_IB_DDR | QIB_IB_SDR)) ==
3687 		    (QIB_IB_DDR | QIB_IB_SDR) &&
3688 		    dd->cspec->autoneg_tries < AUTONEG_TRIES) {
3689 			/* we are SDR, and DDR auto-negotiation enabled */
3690 			++dd->cspec->autoneg_tries;
3691 			if (!ppd->cpspec->ibdeltainprog) {
3692 				ppd->cpspec->ibdeltainprog = 1;
3693 				ppd->cpspec->ibsymsnap = read_7220_creg32(dd,
3694 					cr_ibsymbolerr);
3695 				ppd->cpspec->iblnkerrsnap = read_7220_creg32(dd,
3696 					cr_iblinkerrrecov);
3697 			}
3698 			try_7220_autoneg(ppd);
3699 			ret = 1; /* no other IB status change processing */
3700 		} else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3701 			   ppd->link_speed_active == QIB_IB_SDR) {
3702 			autoneg_7220_send(ppd, 1);
3703 			set_7220_ibspeed_fast(ppd, QIB_IB_DDR);
3704 			udelay(2);
3705 			toggle_7220_rclkrls(dd);
3706 			ret = 1; /* no other IB status change processing */
3707 		} else {
3708 			if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
3709 			    (ppd->link_speed_active & QIB_IB_DDR)) {
3710 				spin_lock_irqsave(&ppd->lflags_lock, flags);
3711 				ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
3712 						 QIBL_IB_AUTONEG_FAILED);
3713 				spin_unlock_irqrestore(&ppd->lflags_lock,
3714 						       flags);
3715 				dd->cspec->autoneg_tries = 0;
3716 				/* re-enable SDR, for next link down */
3717 				set_7220_ibspeed_fast(ppd,
3718 						      ppd->link_speed_enabled);
3719 				wake_up(&ppd->cpspec->autoneg_wait);
3720 				symadj = 1;
3721 			} else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
3722 				/*
3723 				 * Clear autoneg failure flag, and do setup
3724 				 * so we'll try next time link goes down and
3725 				 * back to INIT (possibly connected to a
3726 				 * different device).
3727 				 */
3728 				spin_lock_irqsave(&ppd->lflags_lock, flags);
3729 				ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3730 				spin_unlock_irqrestore(&ppd->lflags_lock,
3731 						       flags);
3732 				ppd->cpspec->ibcddrctrl |=
3733 					IBA7220_IBC_IBTA_1_2_MASK;
3734 				qib_write_kreg(dd, kr_ncmodectrl, 0);
3735 				symadj = 1;
3736 			}
3737 		}
3738 
3739 		if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
3740 			symadj = 1;
3741 
3742 		if (!ret) {
3743 			ppd->delay_mult = rate_to_delay
3744 			    [(ibcs >> IBA7220_LINKSPEED_SHIFT) & 1]
3745 			    [(ibcs >> IBA7220_LINKWIDTH_SHIFT) & 1];
3746 
3747 			set_7220_relock_poll(dd, ibup);
3748 			spin_lock_irqsave(&ppd->sdma_lock, flags);
3749 			/*
3750 			 * Unlike 7322, the 7220 needs this, due to lack of
3751 			 * interrupt in some cases when we have sdma active
3752 			 * when the link goes down.
3753 			 */
3754 			if (ppd->sdma_state.current_state !=
3755 			    qib_sdma_state_s20_idle)
3756 				__qib_sdma_process_event(ppd,
3757 					qib_sdma_event_e00_go_hw_down);
3758 			spin_unlock_irqrestore(&ppd->sdma_lock, flags);
3759 		}
3760 	}
3761 
3762 	if (symadj) {
3763 		if (ppd->cpspec->ibdeltainprog) {
3764 			ppd->cpspec->ibdeltainprog = 0;
3765 			ppd->cpspec->ibsymdelta += read_7220_creg32(ppd->dd,
3766 				cr_ibsymbolerr) - ppd->cpspec->ibsymsnap;
3767 			ppd->cpspec->iblnkerrdelta += read_7220_creg32(ppd->dd,
3768 				cr_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
3769 		}
3770 	} else if (!ibup && qib_compat_ddr_negotiate &&
3771 		   !ppd->cpspec->ibdeltainprog &&
3772 			!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
3773 		ppd->cpspec->ibdeltainprog = 1;
3774 		ppd->cpspec->ibsymsnap = read_7220_creg32(ppd->dd,
3775 							  cr_ibsymbolerr);
3776 		ppd->cpspec->iblnkerrsnap = read_7220_creg32(ppd->dd,
3777 						     cr_iblinkerrrecov);
3778 	}
3779 
3780 	if (!ret)
3781 		qib_setup_7220_setextled(ppd, ibup);
3782 	return ret;
3783 }
3784 
3785 /*
3786  * Does read/modify/write to appropriate registers to
3787  * set output and direction bits selected by mask.
3788  * these are in their canonical postions (e.g. lsb of
3789  * dir will end up in D48 of extctrl on existing chips).
3790  * returns contents of GP Inputs.
3791  */
3792 static int gpio_7220_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
3793 {
3794 	u64 read_val, new_out;
3795 	unsigned long flags;
3796 
3797 	if (mask) {
3798 		/* some bits being written, lock access to GPIO */
3799 		dir &= mask;
3800 		out &= mask;
3801 		spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3802 		dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3803 		dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3804 		new_out = (dd->cspec->gpio_out & ~mask) | out;
3805 
3806 		qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3807 		qib_write_kreg(dd, kr_gpio_out, new_out);
3808 		dd->cspec->gpio_out = new_out;
3809 		spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3810 	}
3811 	/*
3812 	 * It is unlikely that a read at this time would get valid
3813 	 * data on a pin whose direction line was set in the same
3814 	 * call to this function. We include the read here because
3815 	 * that allows us to potentially combine a change on one pin with
3816 	 * a read on another, and because the old code did something like
3817 	 * this.
3818 	 */
3819 	read_val = qib_read_kreg64(dd, kr_extstatus);
3820 	return SYM_FIELD(read_val, EXTStatus, GPIOIn);
3821 }
3822 
3823 /*
3824  * Read fundamental info we need to use the chip.  These are
3825  * the registers that describe chip capabilities, and are
3826  * saved in shadow registers.
3827  */
3828 static void get_7220_chip_params(struct qib_devdata *dd)
3829 {
3830 	u64 val;
3831 	u32 piobufs;
3832 	int mtu;
3833 
3834 	dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
3835 
3836 	dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
3837 	dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
3838 	dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
3839 	dd->palign = qib_read_kreg32(dd, kr_palign);
3840 	dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3841 	dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
3842 
3843 	val = qib_read_kreg64(dd, kr_sendpiosize);
3844 	dd->piosize2k = val & ~0U;
3845 	dd->piosize4k = val >> 32;
3846 
3847 	mtu = ib_mtu_enum_to_int(qib_ibmtu);
3848 	if (mtu == -1)
3849 		mtu = QIB_DEFAULT_MTU;
3850 	dd->pport->ibmtu = (u32)mtu;
3851 
3852 	val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3853 	dd->piobcnt2k = val & ~0U;
3854 	dd->piobcnt4k = val >> 32;
3855 	/* these may be adjusted in init_chip_wc_pat() */
3856 	dd->pio2kbase = (u32 __iomem *)
3857 		((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
3858 	if (dd->piobcnt4k) {
3859 		dd->pio4kbase = (u32 __iomem *)
3860 			((char __iomem *) dd->kregbase +
3861 			 (dd->piobufbase >> 32));
3862 		/*
3863 		 * 4K buffers take 2 pages; we use roundup just to be
3864 		 * paranoid; we calculate it once here, rather than on
3865 		 * ever buf allocate
3866 		 */
3867 		dd->align4k = ALIGN(dd->piosize4k, dd->palign);
3868 	}
3869 
3870 	piobufs = dd->piobcnt4k + dd->piobcnt2k;
3871 
3872 	dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
3873 		(sizeof(u64) * BITS_PER_BYTE / 2);
3874 }
3875 
3876 /*
3877  * The chip base addresses in cspec and cpspec have to be set
3878  * after possible init_chip_wc_pat(), rather than in
3879  * qib_get_7220_chip_params(), so split out as separate function
3880  */
3881 static void set_7220_baseaddrs(struct qib_devdata *dd)
3882 {
3883 	u32 cregbase;
3884 	/* init after possible re-map in init_chip_wc_pat() */
3885 	cregbase = qib_read_kreg32(dd, kr_counterregbase);
3886 	dd->cspec->cregbase = (u64 __iomem *)
3887 		((char __iomem *) dd->kregbase + cregbase);
3888 
3889 	dd->egrtidbase = (u64 __iomem *)
3890 		((char __iomem *) dd->kregbase + dd->rcvegrbase);
3891 }
3892 
3893 
3894 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl, SendIntBufAvail) |	\
3895 			   SYM_MASK(SendCtrl, SPioEnable) |		\
3896 			   SYM_MASK(SendCtrl, SSpecialTriggerEn) |	\
3897 			   SYM_MASK(SendCtrl, SendBufAvailUpd) |	\
3898 			   SYM_MASK(SendCtrl, AvailUpdThld) |		\
3899 			   SYM_MASK(SendCtrl, SDmaEnable) |		\
3900 			   SYM_MASK(SendCtrl, SDmaIntEnable) |		\
3901 			   SYM_MASK(SendCtrl, SDmaHalt) |		\
3902 			   SYM_MASK(SendCtrl, SDmaSingleDescriptor))
3903 
3904 static int sendctrl_hook(struct qib_devdata *dd,
3905 			 const struct diag_observer *op,
3906 			 u32 offs, u64 *data, u64 mask, int only_32)
3907 {
3908 	unsigned long flags;
3909 	unsigned idx = offs / sizeof(u64);
3910 	u64 local_data, all_bits;
3911 
3912 	if (idx != kr_sendctrl) {
3913 		qib_dev_err(dd, "SendCtrl Hook called with offs %X, %s-bit\n",
3914 			    offs, only_32 ? "32" : "64");
3915 		return 0;
3916 	}
3917 
3918 	all_bits = ~0ULL;
3919 	if (only_32)
3920 		all_bits >>= 32;
3921 	spin_lock_irqsave(&dd->sendctrl_lock, flags);
3922 	if ((mask & all_bits) != all_bits) {
3923 		/*
3924 		 * At least some mask bits are zero, so we need
3925 		 * to read. The judgement call is whether from
3926 		 * reg or shadow. First-cut: read reg, and complain
3927 		 * if any bits which should be shadowed are different
3928 		 * from their shadowed value.
3929 		 */
3930 		if (only_32)
3931 			local_data = (u64)qib_read_kreg32(dd, idx);
3932 		else
3933 			local_data = qib_read_kreg64(dd, idx);
3934 		qib_dev_err(dd, "Sendctrl -> %X, Shad -> %X\n",
3935 			    (u32)local_data, (u32)dd->sendctrl);
3936 		if ((local_data & SENDCTRL_SHADOWED) !=
3937 		    (dd->sendctrl & SENDCTRL_SHADOWED))
3938 			qib_dev_err(dd, "Sendctrl read: %X shadow is %X\n",
3939 				(u32)local_data, (u32) dd->sendctrl);
3940 		*data = (local_data & ~mask) | (*data & mask);
3941 	}
3942 	if (mask) {
3943 		/*
3944 		 * At least some mask bits are one, so we need
3945 		 * to write, but only shadow some bits.
3946 		 */
3947 		u64 sval, tval; /* Shadowed, transient */
3948 
3949 		/*
3950 		 * New shadow val is bits we don't want to touch,
3951 		 * ORed with bits we do, that are intended for shadow.
3952 		 */
3953 		sval = (dd->sendctrl & ~mask);
3954 		sval |= *data & SENDCTRL_SHADOWED & mask;
3955 		dd->sendctrl = sval;
3956 		tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
3957 		qib_dev_err(dd, "Sendctrl <- %X, Shad <- %X\n",
3958 			    (u32)tval, (u32)sval);
3959 		qib_write_kreg(dd, kr_sendctrl, tval);
3960 		qib_write_kreg(dd, kr_scratch, 0Ull);
3961 	}
3962 	spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
3963 
3964 	return only_32 ? 4 : 8;
3965 }
3966 
3967 static const struct diag_observer sendctrl_observer = {
3968 	sendctrl_hook, kr_sendctrl * sizeof(u64),
3969 	kr_sendctrl * sizeof(u64)
3970 };
3971 
3972 /*
3973  * write the final few registers that depend on some of the
3974  * init setup.  Done late in init, just before bringing up
3975  * the serdes.
3976  */
3977 static int qib_late_7220_initreg(struct qib_devdata *dd)
3978 {
3979 	int ret = 0;
3980 	u64 val;
3981 
3982 	qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
3983 	qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
3984 	qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
3985 	qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
3986 	val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3987 	if (val != dd->pioavailregs_phys) {
3988 		qib_dev_err(dd,
3989 			"Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3990 			(unsigned long) dd->pioavailregs_phys,
3991 			(unsigned long long) val);
3992 		ret = -EINVAL;
3993 	}
3994 	qib_register_observer(dd, &sendctrl_observer);
3995 	return ret;
3996 }
3997 
3998 static int qib_init_7220_variables(struct qib_devdata *dd)
3999 {
4000 	struct qib_chippport_specific *cpspec;
4001 	struct qib_pportdata *ppd;
4002 	int ret = 0;
4003 	u32 sbufs, updthresh;
4004 
4005 	cpspec = (struct qib_chippport_specific *)(dd + 1);
4006 	ppd = &cpspec->pportdata;
4007 	dd->pport = ppd;
4008 	dd->num_pports = 1;
4009 
4010 	dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports);
4011 	ppd->cpspec = cpspec;
4012 
4013 	spin_lock_init(&dd->cspec->sdepb_lock);
4014 	spin_lock_init(&dd->cspec->rcvmod_lock);
4015 	spin_lock_init(&dd->cspec->gpio_lock);
4016 
4017 	/* we haven't yet set QIB_PRESENT, so use read directly */
4018 	dd->revision = readq(&dd->kregbase[kr_revision]);
4019 
4020 	if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
4021 		qib_dev_err(dd,
4022 			"Revision register read failure, giving up initialization\n");
4023 		ret = -ENODEV;
4024 		goto bail;
4025 	}
4026 	dd->flags |= QIB_PRESENT;  /* now register routines work */
4027 
4028 	dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4029 				    ChipRevMajor);
4030 	dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R,
4031 				    ChipRevMinor);
4032 
4033 	get_7220_chip_params(dd);
4034 	qib_7220_boardname(dd);
4035 
4036 	/*
4037 	 * GPIO bits for TWSI data and clock,
4038 	 * used for serial EEPROM.
4039 	 */
4040 	dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
4041 	dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
4042 	dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
4043 
4044 	dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
4045 		QIB_NODMA_RTAIL | QIB_HAS_THRESH_UPDATE;
4046 	dd->flags |= qib_special_trigger ?
4047 		QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
4048 
4049 	/*
4050 	 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
4051 	 * 2 is Some Misc, 3 is reserved for future.
4052 	 */
4053 	dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr);
4054 
4055 	dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr);
4056 
4057 	dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated);
4058 
4059 	init_waitqueue_head(&cpspec->autoneg_wait);
4060 	INIT_DELAYED_WORK(&cpspec->autoneg_work, autoneg_7220_work);
4061 
4062 	ret = qib_init_pportdata(ppd, dd, 0, 1);
4063 	if (ret)
4064 		goto bail;
4065 	ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
4066 	ppd->link_speed_supported = QIB_IB_SDR | QIB_IB_DDR;
4067 
4068 	ppd->link_width_enabled = ppd->link_width_supported;
4069 	ppd->link_speed_enabled = ppd->link_speed_supported;
4070 	/*
4071 	 * Set the initial values to reasonable default, will be set
4072 	 * for real when link is up.
4073 	 */
4074 	ppd->link_width_active = IB_WIDTH_4X;
4075 	ppd->link_speed_active = QIB_IB_SDR;
4076 	ppd->delay_mult = rate_to_delay[0][1];
4077 	ppd->vls_supported = IB_VL_VL0;
4078 	ppd->vls_operational = ppd->vls_supported;
4079 
4080 	if (!qib_mini_init)
4081 		qib_write_kreg(dd, kr_rcvbthqp, QIB_KD_QP);
4082 
4083 	init_timer(&ppd->cpspec->chase_timer);
4084 	ppd->cpspec->chase_timer.function = reenable_7220_chase;
4085 	ppd->cpspec->chase_timer.data = (unsigned long)ppd;
4086 
4087 	qib_num_cfg_vls = 1; /* if any 7220's, only one VL */
4088 
4089 	dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
4090 	dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
4091 	dd->rhf_offset =
4092 		dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
4093 
4094 	/* we always allocate at least 2048 bytes for eager buffers */
4095 	ret = ib_mtu_enum_to_int(qib_ibmtu);
4096 	dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU;
4097 	BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
4098 	dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
4099 
4100 	qib_7220_tidtemplate(dd);
4101 
4102 	/*
4103 	 * We can request a receive interrupt for 1 or
4104 	 * more packets from current offset.  For now, we set this
4105 	 * up for a single packet.
4106 	 */
4107 	dd->rhdrhead_intr_off = 1ULL << 32;
4108 
4109 	/* setup the stats timer; the add_timer is done at end of init */
4110 	init_timer(&dd->stats_timer);
4111 	dd->stats_timer.function = qib_get_7220_faststats;
4112 	dd->stats_timer.data = (unsigned long) dd;
4113 	dd->stats_timer.expires = jiffies + ACTIVITY_TIMER * HZ;
4114 
4115 	/*
4116 	 * Control[4] has been added to change the arbitration within
4117 	 * the SDMA engine between favoring data fetches over descriptor
4118 	 * fetches.  qib_sdma_fetch_arb==0 gives data fetches priority.
4119 	 */
4120 	if (qib_sdma_fetch_arb)
4121 		dd->control |= 1 << 4;
4122 
4123 	dd->ureg_align = 0x10000;  /* 64KB alignment */
4124 
4125 	dd->piosize2kmax_dwords = (dd->piosize2k >> 2)-1;
4126 	qib_7220_config_ctxts(dd);
4127 	qib_set_ctxtcnt(dd);  /* needed for PAT setup */
4128 
4129 	ret = init_chip_wc_pat(dd, 0);
4130 	if (ret)
4131 		goto bail;
4132 	set_7220_baseaddrs(dd); /* set chip access pointers now */
4133 
4134 	ret = 0;
4135 	if (qib_mini_init)
4136 		goto bail;
4137 
4138 	ret = qib_create_ctxts(dd);
4139 	init_7220_cntrnames(dd);
4140 
4141 	/* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
4142 	 * reserve the update threshold amount for other kernel use, such
4143 	 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
4144 	 * unless we aren't enabling SDMA, in which case we want to use
4145 	 * all the 4k bufs for the kernel.
4146 	 * if this was less than the update threshold, we could wait
4147 	 * a long time for an update.  Coded this way because we
4148 	 * sometimes change the update threshold for various reasons,
4149 	 * and we want this to remain robust.
4150 	 */
4151 	updthresh = 8U; /* update threshold */
4152 	if (dd->flags & QIB_HAS_SEND_DMA) {
4153 		dd->cspec->sdmabufcnt =  dd->piobcnt4k;
4154 		sbufs = updthresh > 3 ? updthresh : 3;
4155 	} else {
4156 		dd->cspec->sdmabufcnt = 0;
4157 		sbufs = dd->piobcnt4k;
4158 	}
4159 
4160 	dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
4161 		dd->cspec->sdmabufcnt;
4162 	dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
4163 	dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
4164 	dd->last_pio = dd->cspec->lastbuf_for_pio;
4165 	dd->pbufsctxt = dd->lastctxt_piobuf /
4166 		(dd->cfgctxts - dd->first_user_ctxt);
4167 
4168 	/*
4169 	 * if we are at 16 user contexts, we will have one 7 sbufs
4170 	 * per context, so drop the update threshold to match.  We
4171 	 * want to update before we actually run out, at low pbufs/ctxt
4172 	 * so give ourselves some margin
4173 	 */
4174 	if ((dd->pbufsctxt - 2) < updthresh)
4175 		updthresh = dd->pbufsctxt - 2;
4176 
4177 	dd->cspec->updthresh_dflt = updthresh;
4178 	dd->cspec->updthresh = updthresh;
4179 
4180 	/* before full enable, no interrupts, no locking needed */
4181 	dd->sendctrl |= (updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
4182 			     << SYM_LSB(SendCtrl, AvailUpdThld);
4183 
4184 	dd->psxmitwait_supported = 1;
4185 	dd->psxmitwait_check_rate = QIB_7220_PSXMITWAIT_CHECK_RATE;
4186 bail:
4187 	return ret;
4188 }
4189 
4190 static u32 __iomem *qib_7220_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
4191 					u32 *pbufnum)
4192 {
4193 	u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
4194 	struct qib_devdata *dd = ppd->dd;
4195 	u32 __iomem *buf;
4196 
4197 	if (((pbc >> 32) & PBC_7220_VL15_SEND_CTRL) &&
4198 		!(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE)))
4199 		buf = get_7220_link_buf(ppd, pbufnum);
4200 	else {
4201 		if ((plen + 1) > dd->piosize2kmax_dwords)
4202 			first = dd->piobcnt2k;
4203 		else
4204 			first = 0;
4205 		/* try 4k if all 2k busy, so same last for both sizes */
4206 		last = dd->cspec->lastbuf_for_pio;
4207 		buf = qib_getsendbuf_range(dd, pbufnum, first, last);
4208 	}
4209 	return buf;
4210 }
4211 
4212 /* these 2 "counters" are really control registers, and are always RW */
4213 static void qib_set_cntr_7220_sample(struct qib_pportdata *ppd, u32 intv,
4214 				     u32 start)
4215 {
4216 	write_7220_creg(ppd->dd, cr_psinterval, intv);
4217 	write_7220_creg(ppd->dd, cr_psstart, start);
4218 }
4219 
4220 /*
4221  * NOTE: no real attempt is made to generalize the SDMA stuff.
4222  * At some point "soon" we will have a new more generalized
4223  * set of sdma interface, and then we'll clean this up.
4224  */
4225 
4226 /* Must be called with sdma_lock held, or before init finished */
4227 static void qib_sdma_update_7220_tail(struct qib_pportdata *ppd, u16 tail)
4228 {
4229 	/* Commit writes to memory and advance the tail on the chip */
4230 	wmb();
4231 	ppd->sdma_descq_tail = tail;
4232 	qib_write_kreg(ppd->dd, kr_senddmatail, tail);
4233 }
4234 
4235 static void qib_sdma_set_7220_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
4236 {
4237 }
4238 
4239 static struct sdma_set_state_action sdma_7220_action_table[] = {
4240 	[qib_sdma_state_s00_hw_down] = {
4241 		.op_enable = 0,
4242 		.op_intenable = 0,
4243 		.op_halt = 0,
4244 		.go_s99_running_tofalse = 1,
4245 	},
4246 	[qib_sdma_state_s10_hw_start_up_wait] = {
4247 		.op_enable = 1,
4248 		.op_intenable = 1,
4249 		.op_halt = 1,
4250 	},
4251 	[qib_sdma_state_s20_idle] = {
4252 		.op_enable = 1,
4253 		.op_intenable = 1,
4254 		.op_halt = 1,
4255 	},
4256 	[qib_sdma_state_s30_sw_clean_up_wait] = {
4257 		.op_enable = 0,
4258 		.op_intenable = 1,
4259 		.op_halt = 0,
4260 	},
4261 	[qib_sdma_state_s40_hw_clean_up_wait] = {
4262 		.op_enable = 1,
4263 		.op_intenable = 1,
4264 		.op_halt = 1,
4265 	},
4266 	[qib_sdma_state_s50_hw_halt_wait] = {
4267 		.op_enable = 1,
4268 		.op_intenable = 1,
4269 		.op_halt = 1,
4270 	},
4271 	[qib_sdma_state_s99_running] = {
4272 		.op_enable = 1,
4273 		.op_intenable = 1,
4274 		.op_halt = 0,
4275 		.go_s99_running_totrue = 1,
4276 	},
4277 };
4278 
4279 static void qib_7220_sdma_init_early(struct qib_pportdata *ppd)
4280 {
4281 	ppd->sdma_state.set_state_action = sdma_7220_action_table;
4282 }
4283 
4284 static int init_sdma_7220_regs(struct qib_pportdata *ppd)
4285 {
4286 	struct qib_devdata *dd = ppd->dd;
4287 	unsigned i, n;
4288 	u64 senddmabufmask[3] = { 0 };
4289 
4290 	/* Set SendDmaBase */
4291 	qib_write_kreg(dd, kr_senddmabase, ppd->sdma_descq_phys);
4292 	qib_sdma_7220_setlengen(ppd);
4293 	qib_sdma_update_7220_tail(ppd, 0); /* Set SendDmaTail */
4294 	/* Set SendDmaHeadAddr */
4295 	qib_write_kreg(dd, kr_senddmaheadaddr, ppd->sdma_head_phys);
4296 
4297 	/*
4298 	 * Reserve all the former "kernel" piobufs, using high number range
4299 	 * so we get as many 4K buffers as possible
4300 	 */
4301 	n = dd->piobcnt2k + dd->piobcnt4k;
4302 	i = n - dd->cspec->sdmabufcnt;
4303 
4304 	for (; i < n; ++i) {
4305 		unsigned word = i / 64;
4306 		unsigned bit = i & 63;
4307 
4308 		BUG_ON(word >= 3);
4309 		senddmabufmask[word] |= 1ULL << bit;
4310 	}
4311 	qib_write_kreg(dd, kr_senddmabufmask0, senddmabufmask[0]);
4312 	qib_write_kreg(dd, kr_senddmabufmask1, senddmabufmask[1]);
4313 	qib_write_kreg(dd, kr_senddmabufmask2, senddmabufmask[2]);
4314 
4315 	ppd->sdma_state.first_sendbuf = i;
4316 	ppd->sdma_state.last_sendbuf = n;
4317 
4318 	return 0;
4319 }
4320 
4321 /* sdma_lock must be held */
4322 static u16 qib_sdma_7220_gethead(struct qib_pportdata *ppd)
4323 {
4324 	struct qib_devdata *dd = ppd->dd;
4325 	int sane;
4326 	int use_dmahead;
4327 	u16 swhead;
4328 	u16 swtail;
4329 	u16 cnt;
4330 	u16 hwhead;
4331 
4332 	use_dmahead = __qib_sdma_running(ppd) &&
4333 		(dd->flags & QIB_HAS_SDMA_TIMEOUT);
4334 retry:
4335 	hwhead = use_dmahead ?
4336 		(u16)le64_to_cpu(*ppd->sdma_head_dma) :
4337 		(u16)qib_read_kreg32(dd, kr_senddmahead);
4338 
4339 	swhead = ppd->sdma_descq_head;
4340 	swtail = ppd->sdma_descq_tail;
4341 	cnt = ppd->sdma_descq_cnt;
4342 
4343 	if (swhead < swtail) {
4344 		/* not wrapped */
4345 		sane = (hwhead >= swhead) & (hwhead <= swtail);
4346 	} else if (swhead > swtail) {
4347 		/* wrapped around */
4348 		sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
4349 			(hwhead <= swtail);
4350 	} else {
4351 		/* empty */
4352 		sane = (hwhead == swhead);
4353 	}
4354 
4355 	if (unlikely(!sane)) {
4356 		if (use_dmahead) {
4357 			/* try one more time, directly from the register */
4358 			use_dmahead = 0;
4359 			goto retry;
4360 		}
4361 		/* assume no progress */
4362 		hwhead = swhead;
4363 	}
4364 
4365 	return hwhead;
4366 }
4367 
4368 static int qib_sdma_7220_busy(struct qib_pportdata *ppd)
4369 {
4370 	u64 hwstatus = qib_read_kreg64(ppd->dd, kr_senddmastatus);
4371 
4372 	return (hwstatus & SYM_MASK(SendDmaStatus, ScoreBoardDrainInProg)) ||
4373 	       (hwstatus & SYM_MASK(SendDmaStatus, AbortInProg)) ||
4374 	       (hwstatus & SYM_MASK(SendDmaStatus, InternalSDmaEnable)) ||
4375 	       !(hwstatus & SYM_MASK(SendDmaStatus, ScbEmpty));
4376 }
4377 
4378 /*
4379  * Compute the amount of delay before sending the next packet if the
4380  * port's send rate differs from the static rate set for the QP.
4381  * Since the delay affects this packet but the amount of the delay is
4382  * based on the length of the previous packet, use the last delay computed
4383  * and save the delay count for this packet to be used next time
4384  * we get here.
4385  */
4386 static u32 qib_7220_setpbc_control(struct qib_pportdata *ppd, u32 plen,
4387 				   u8 srate, u8 vl)
4388 {
4389 	u8 snd_mult = ppd->delay_mult;
4390 	u8 rcv_mult = ib_rate_to_delay[srate];
4391 	u32 ret = ppd->cpspec->last_delay_mult;
4392 
4393 	ppd->cpspec->last_delay_mult = (rcv_mult > snd_mult) ?
4394 		(plen * (rcv_mult - snd_mult) + 1) >> 1 : 0;
4395 
4396 	/* Indicate VL15, if necessary */
4397 	if (vl == 15)
4398 		ret |= PBC_7220_VL15_SEND_CTRL;
4399 	return ret;
4400 }
4401 
4402 static void qib_7220_initvl15_bufs(struct qib_devdata *dd)
4403 {
4404 }
4405 
4406 static void qib_7220_init_ctxt(struct qib_ctxtdata *rcd)
4407 {
4408 	if (!rcd->ctxt) {
4409 		rcd->rcvegrcnt = IBA7220_KRCVEGRCNT;
4410 		rcd->rcvegr_tid_base = 0;
4411 	} else {
4412 		rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
4413 		rcd->rcvegr_tid_base = IBA7220_KRCVEGRCNT +
4414 			(rcd->ctxt - 1) * rcd->rcvegrcnt;
4415 	}
4416 }
4417 
4418 static void qib_7220_txchk_change(struct qib_devdata *dd, u32 start,
4419 				  u32 len, u32 which, struct qib_ctxtdata *rcd)
4420 {
4421 	int i;
4422 	unsigned long flags;
4423 
4424 	switch (which) {
4425 	case TXCHK_CHG_TYPE_KERN:
4426 		/* see if we need to raise avail update threshold */
4427 		spin_lock_irqsave(&dd->uctxt_lock, flags);
4428 		for (i = dd->first_user_ctxt;
4429 		     dd->cspec->updthresh != dd->cspec->updthresh_dflt
4430 		     && i < dd->cfgctxts; i++)
4431 			if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
4432 			   ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
4433 			   < dd->cspec->updthresh_dflt)
4434 				break;
4435 		spin_unlock_irqrestore(&dd->uctxt_lock, flags);
4436 		if (i == dd->cfgctxts) {
4437 			spin_lock_irqsave(&dd->sendctrl_lock, flags);
4438 			dd->cspec->updthresh = dd->cspec->updthresh_dflt;
4439 			dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4440 			dd->sendctrl |= (dd->cspec->updthresh &
4441 					 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
4442 					   SYM_LSB(SendCtrl, AvailUpdThld);
4443 			spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4444 			sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4445 		}
4446 		break;
4447 	case TXCHK_CHG_TYPE_USER:
4448 		spin_lock_irqsave(&dd->sendctrl_lock, flags);
4449 		if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
4450 			/ rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
4451 			dd->cspec->updthresh = (rcd->piocnt /
4452 						rcd->subctxt_cnt) - 1;
4453 			dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
4454 			dd->sendctrl |= (dd->cspec->updthresh &
4455 					SYM_RMASK(SendCtrl, AvailUpdThld))
4456 					<< SYM_LSB(SendCtrl, AvailUpdThld);
4457 			spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4458 			sendctrl_7220_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
4459 		} else
4460 			spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4461 		break;
4462 	}
4463 }
4464 
4465 static void writescratch(struct qib_devdata *dd, u32 val)
4466 {
4467 	qib_write_kreg(dd, kr_scratch, val);
4468 }
4469 
4470 #define VALID_TS_RD_REG_MASK 0xBF
4471 /**
4472  * qib_7220_tempsense_read - read register of temp sensor via TWSI
4473  * @dd: the qlogic_ib device
4474  * @regnum: register to read from
4475  *
4476  * returns reg contents (0..255) or < 0 for error
4477  */
4478 static int qib_7220_tempsense_rd(struct qib_devdata *dd, int regnum)
4479 {
4480 	int ret;
4481 	u8 rdata;
4482 
4483 	if (regnum > 7) {
4484 		ret = -EINVAL;
4485 		goto bail;
4486 	}
4487 
4488 	/* return a bogus value for (the one) register we do not have */
4489 	if (!((1 << regnum) & VALID_TS_RD_REG_MASK)) {
4490 		ret = 0;
4491 		goto bail;
4492 	}
4493 
4494 	ret = mutex_lock_interruptible(&dd->eep_lock);
4495 	if (ret)
4496 		goto bail;
4497 
4498 	ret = qib_twsi_blk_rd(dd, QIB_TWSI_TEMP_DEV, regnum, &rdata, 1);
4499 	if (!ret)
4500 		ret = rdata;
4501 
4502 	mutex_unlock(&dd->eep_lock);
4503 
4504 	/*
4505 	 * There are three possibilities here:
4506 	 * ret is actual value (0..255)
4507 	 * ret is -ENXIO or -EINVAL from twsi code or this file
4508 	 * ret is -EINTR from mutex_lock_interruptible.
4509 	 */
4510 bail:
4511 	return ret;
4512 }
4513 
4514 #ifdef CONFIG_INFINIBAND_QIB_DCA
4515 static int qib_7220_notify_dca(struct qib_devdata *dd, unsigned long event)
4516 {
4517 	return 0;
4518 }
4519 #endif
4520 
4521 /* Dummy function, as 7220 boards never disable EEPROM Write */
4522 static int qib_7220_eeprom_wen(struct qib_devdata *dd, int wen)
4523 {
4524 	return 1;
4525 }
4526 
4527 /**
4528  * qib_init_iba7220_funcs - set up the chip-specific function pointers
4529  * @dev: the pci_dev for qlogic_ib device
4530  * @ent: pci_device_id struct for this dev
4531  *
4532  * This is global, and is called directly at init to set up the
4533  * chip-specific function pointers for later use.
4534  */
4535 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *pdev,
4536 					   const struct pci_device_id *ent)
4537 {
4538 	struct qib_devdata *dd;
4539 	int ret;
4540 	u32 boardid, minwidth;
4541 
4542 	dd = qib_alloc_devdata(pdev, sizeof(struct qib_chip_specific) +
4543 		sizeof(struct qib_chippport_specific));
4544 	if (IS_ERR(dd))
4545 		goto bail;
4546 
4547 	dd->f_bringup_serdes    = qib_7220_bringup_serdes;
4548 	dd->f_cleanup           = qib_setup_7220_cleanup;
4549 	dd->f_clear_tids        = qib_7220_clear_tids;
4550 	dd->f_free_irq          = qib_7220_free_irq;
4551 	dd->f_get_base_info     = qib_7220_get_base_info;
4552 	dd->f_get_msgheader     = qib_7220_get_msgheader;
4553 	dd->f_getsendbuf        = qib_7220_getsendbuf;
4554 	dd->f_gpio_mod          = gpio_7220_mod;
4555 	dd->f_eeprom_wen        = qib_7220_eeprom_wen;
4556 	dd->f_hdrqempty         = qib_7220_hdrqempty;
4557 	dd->f_ib_updown         = qib_7220_ib_updown;
4558 	dd->f_init_ctxt         = qib_7220_init_ctxt;
4559 	dd->f_initvl15_bufs     = qib_7220_initvl15_bufs;
4560 	dd->f_intr_fallback     = qib_7220_intr_fallback;
4561 	dd->f_late_initreg      = qib_late_7220_initreg;
4562 	dd->f_setpbc_control    = qib_7220_setpbc_control;
4563 	dd->f_portcntr          = qib_portcntr_7220;
4564 	dd->f_put_tid           = qib_7220_put_tid;
4565 	dd->f_quiet_serdes      = qib_7220_quiet_serdes;
4566 	dd->f_rcvctrl           = rcvctrl_7220_mod;
4567 	dd->f_read_cntrs        = qib_read_7220cntrs;
4568 	dd->f_read_portcntrs    = qib_read_7220portcntrs;
4569 	dd->f_reset             = qib_setup_7220_reset;
4570 	dd->f_init_sdma_regs    = init_sdma_7220_regs;
4571 	dd->f_sdma_busy         = qib_sdma_7220_busy;
4572 	dd->f_sdma_gethead      = qib_sdma_7220_gethead;
4573 	dd->f_sdma_sendctrl     = qib_7220_sdma_sendctrl;
4574 	dd->f_sdma_set_desc_cnt = qib_sdma_set_7220_desc_cnt;
4575 	dd->f_sdma_update_tail  = qib_sdma_update_7220_tail;
4576 	dd->f_sdma_hw_clean_up  = qib_7220_sdma_hw_clean_up;
4577 	dd->f_sdma_hw_start_up  = qib_7220_sdma_hw_start_up;
4578 	dd->f_sdma_init_early   = qib_7220_sdma_init_early;
4579 	dd->f_sendctrl          = sendctrl_7220_mod;
4580 	dd->f_set_armlaunch     = qib_set_7220_armlaunch;
4581 	dd->f_set_cntr_sample   = qib_set_cntr_7220_sample;
4582 	dd->f_iblink_state      = qib_7220_iblink_state;
4583 	dd->f_ibphys_portstate  = qib_7220_phys_portstate;
4584 	dd->f_get_ib_cfg        = qib_7220_get_ib_cfg;
4585 	dd->f_set_ib_cfg        = qib_7220_set_ib_cfg;
4586 	dd->f_set_ib_loopback   = qib_7220_set_loopback;
4587 	dd->f_set_intr_state    = qib_7220_set_intr_state;
4588 	dd->f_setextled         = qib_setup_7220_setextled;
4589 	dd->f_txchk_change      = qib_7220_txchk_change;
4590 	dd->f_update_usrhead    = qib_update_7220_usrhead;
4591 	dd->f_wantpiobuf_intr   = qib_wantpiobuf_7220_intr;
4592 	dd->f_xgxs_reset        = qib_7220_xgxs_reset;
4593 	dd->f_writescratch      = writescratch;
4594 	dd->f_tempsense_rd	= qib_7220_tempsense_rd;
4595 #ifdef CONFIG_INFINIBAND_QIB_DCA
4596 	dd->f_notify_dca = qib_7220_notify_dca;
4597 #endif
4598 	/*
4599 	 * Do remaining pcie setup and save pcie values in dd.
4600 	 * Any error printing is already done by the init code.
4601 	 * On return, we have the chip mapped, but chip registers
4602 	 * are not set up until start of qib_init_7220_variables.
4603 	 */
4604 	ret = qib_pcie_ddinit(dd, pdev, ent);
4605 	if (ret < 0)
4606 		goto bail_free;
4607 
4608 	/* initialize chip-specific variables */
4609 	ret = qib_init_7220_variables(dd);
4610 	if (ret)
4611 		goto bail_cleanup;
4612 
4613 	if (qib_mini_init)
4614 		goto bail;
4615 
4616 	boardid = SYM_FIELD(dd->revision, Revision,
4617 			    BoardID);
4618 	switch (boardid) {
4619 	case 0:
4620 	case 2:
4621 	case 10:
4622 	case 12:
4623 		minwidth = 16; /* x16 capable boards */
4624 		break;
4625 	default:
4626 		minwidth = 8; /* x8 capable boards */
4627 		break;
4628 	}
4629 	if (qib_pcie_params(dd, minwidth, NULL, NULL))
4630 		qib_dev_err(dd,
4631 			"Failed to setup PCIe or interrupts; continuing anyway\n");
4632 
4633 	/* save IRQ for possible later use */
4634 	dd->cspec->irq = pdev->irq;
4635 
4636 	if (qib_read_kreg64(dd, kr_hwerrstatus) &
4637 	    QLOGIC_IB_HWE_SERDESPLLFAILED)
4638 		qib_write_kreg(dd, kr_hwerrclear,
4639 			       QLOGIC_IB_HWE_SERDESPLLFAILED);
4640 
4641 	/* setup interrupt handler (interrupt type handled above) */
4642 	qib_setup_7220_interrupt(dd);
4643 	qib_7220_init_hwerrors(dd);
4644 
4645 	/* clear diagctrl register, in case diags were running and crashed */
4646 	qib_write_kreg(dd, kr_hwdiagctrl, 0);
4647 
4648 	goto bail;
4649 
4650 bail_cleanup:
4651 	qib_pcie_ddcleanup(dd);
4652 bail_free:
4653 	qib_free_devdata(dd);
4654 	dd = ERR_PTR(ret);
4655 bail:
4656 	return dd;
4657 }
4658