1 /* 2 * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved. 3 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation. 4 * All rights reserved. 5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 /* 36 * This file contains all of the code that is specific to the 37 * QLogic_IB 6120 PCIe chip. 38 */ 39 40 #include <linux/interrupt.h> 41 #include <linux/pci.h> 42 #include <linux/delay.h> 43 #include <rdma/ib_verbs.h> 44 45 #include "qib.h" 46 #include "qib_6120_regs.h" 47 48 static void qib_6120_setup_setextled(struct qib_pportdata *, u32); 49 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op); 50 static u8 qib_6120_phys_portstate(u64); 51 static u32 qib_6120_iblink_state(u64); 52 53 /* 54 * This file contains all the chip-specific register information and 55 * access functions for the Intel Intel_IB PCI-Express chip. 56 * 57 */ 58 59 /* KREG_IDX uses machine-generated #defines */ 60 #define KREG_IDX(regname) (QIB_6120_##regname##_OFFS / sizeof(u64)) 61 62 /* Use defines to tie machine-generated names to lower-case names */ 63 #define kr_extctrl KREG_IDX(EXTCtrl) 64 #define kr_extstatus KREG_IDX(EXTStatus) 65 #define kr_gpio_clear KREG_IDX(GPIOClear) 66 #define kr_gpio_mask KREG_IDX(GPIOMask) 67 #define kr_gpio_out KREG_IDX(GPIOOut) 68 #define kr_gpio_status KREG_IDX(GPIOStatus) 69 #define kr_rcvctrl KREG_IDX(RcvCtrl) 70 #define kr_sendctrl KREG_IDX(SendCtrl) 71 #define kr_partitionkey KREG_IDX(RcvPartitionKey) 72 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl) 73 #define kr_ibcstatus KREG_IDX(IBCStatus) 74 #define kr_ibcctrl KREG_IDX(IBCCtrl) 75 #define kr_sendbuffererror KREG_IDX(SendBufErr0) 76 #define kr_rcvbthqp KREG_IDX(RcvBTHQP) 77 #define kr_counterregbase KREG_IDX(CntrRegBase) 78 #define kr_palign KREG_IDX(PageAlign) 79 #define kr_rcvegrbase KREG_IDX(RcvEgrBase) 80 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt) 81 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt) 82 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize) 83 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize) 84 #define kr_rcvtidbase KREG_IDX(RcvTIDBase) 85 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt) 86 #define kr_scratch KREG_IDX(Scratch) 87 #define kr_sendctrl KREG_IDX(SendCtrl) 88 #define kr_sendpioavailaddr KREG_IDX(SendPIOAvailAddr) 89 #define kr_sendpiobufbase KREG_IDX(SendPIOBufBase) 90 #define kr_sendpiobufcnt KREG_IDX(SendPIOBufCnt) 91 #define kr_sendpiosize KREG_IDX(SendPIOSize) 92 #define kr_sendregbase KREG_IDX(SendRegBase) 93 #define kr_userregbase KREG_IDX(UserRegBase) 94 #define kr_control KREG_IDX(Control) 95 #define kr_intclear KREG_IDX(IntClear) 96 #define kr_intmask KREG_IDX(IntMask) 97 #define kr_intstatus KREG_IDX(IntStatus) 98 #define kr_errclear KREG_IDX(ErrClear) 99 #define kr_errmask KREG_IDX(ErrMask) 100 #define kr_errstatus KREG_IDX(ErrStatus) 101 #define kr_hwerrclear KREG_IDX(HwErrClear) 102 #define kr_hwerrmask KREG_IDX(HwErrMask) 103 #define kr_hwerrstatus KREG_IDX(HwErrStatus) 104 #define kr_revision KREG_IDX(Revision) 105 #define kr_portcnt KREG_IDX(PortCnt) 106 #define kr_serdes_cfg0 KREG_IDX(SerdesCfg0) 107 #define kr_serdes_cfg1 (kr_serdes_cfg0 + 1) 108 #define kr_serdes_stat KREG_IDX(SerdesStat) 109 #define kr_xgxs_cfg KREG_IDX(XGXSCfg) 110 111 /* These must only be written via qib_write_kreg_ctxt() */ 112 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0) 113 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0) 114 115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \ 116 QIB_6120_LBIntCnt_OFFS) / sizeof(u64)) 117 118 #define cr_badformat CREG_IDX(RxBadFormatCnt) 119 #define cr_erricrc CREG_IDX(RxICRCErrCnt) 120 #define cr_errlink CREG_IDX(RxLinkProblemCnt) 121 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt) 122 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt) 123 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlErrCnt) 124 #define cr_err_rlen CREG_IDX(RxLenErrCnt) 125 #define cr_errslen CREG_IDX(TxLenErrCnt) 126 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt) 127 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt) 128 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt) 129 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt) 130 #define cr_lbint CREG_IDX(LBIntCnt) 131 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt) 132 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt) 133 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt) 134 #define cr_pktrcv CREG_IDX(RxDataPktCnt) 135 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt) 136 #define cr_pktsend CREG_IDX(TxDataPktCnt) 137 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt) 138 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt) 139 #define cr_rcvebp CREG_IDX(RxEBPCnt) 140 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt) 141 #define cr_senddropped CREG_IDX(TxDroppedPktCnt) 142 #define cr_sendstall CREG_IDX(TxFlowStallCnt) 143 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt) 144 #define cr_wordrcv CREG_IDX(RxDwordCnt) 145 #define cr_wordsend CREG_IDX(TxDwordCnt) 146 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt) 147 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt) 148 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt) 149 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt) 150 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt) 151 152 #define SYM_RMASK(regname, fldname) ((u64) \ 153 QIB_6120_##regname##_##fldname##_RMASK) 154 #define SYM_MASK(regname, fldname) ((u64) \ 155 QIB_6120_##regname##_##fldname##_RMASK << \ 156 QIB_6120_##regname##_##fldname##_LSB) 157 #define SYM_LSB(regname, fldname) (QIB_6120_##regname##_##fldname##_LSB) 158 159 #define SYM_FIELD(value, regname, fldname) ((u64) \ 160 (((value) >> SYM_LSB(regname, fldname)) & \ 161 SYM_RMASK(regname, fldname))) 162 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask) 163 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask) 164 165 /* link training states, from IBC */ 166 #define IB_6120_LT_STATE_DISABLED 0x00 167 #define IB_6120_LT_STATE_LINKUP 0x01 168 #define IB_6120_LT_STATE_POLLACTIVE 0x02 169 #define IB_6120_LT_STATE_POLLQUIET 0x03 170 #define IB_6120_LT_STATE_SLEEPDELAY 0x04 171 #define IB_6120_LT_STATE_SLEEPQUIET 0x05 172 #define IB_6120_LT_STATE_CFGDEBOUNCE 0x08 173 #define IB_6120_LT_STATE_CFGRCVFCFG 0x09 174 #define IB_6120_LT_STATE_CFGWAITRMT 0x0a 175 #define IB_6120_LT_STATE_CFGIDLE 0x0b 176 #define IB_6120_LT_STATE_RECOVERRETRAIN 0x0c 177 #define IB_6120_LT_STATE_RECOVERWAITRMT 0x0e 178 #define IB_6120_LT_STATE_RECOVERIDLE 0x0f 179 180 /* link state machine states from IBC */ 181 #define IB_6120_L_STATE_DOWN 0x0 182 #define IB_6120_L_STATE_INIT 0x1 183 #define IB_6120_L_STATE_ARM 0x2 184 #define IB_6120_L_STATE_ACTIVE 0x3 185 #define IB_6120_L_STATE_ACT_DEFER 0x4 186 187 static const u8 qib_6120_physportstate[0x20] = { 188 [IB_6120_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED, 189 [IB_6120_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP, 190 [IB_6120_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL, 191 [IB_6120_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL, 192 [IB_6120_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP, 193 [IB_6120_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP, 194 [IB_6120_LT_STATE_CFGDEBOUNCE] = 195 IB_PHYSPORTSTATE_CFG_TRAIN, 196 [IB_6120_LT_STATE_CFGRCVFCFG] = 197 IB_PHYSPORTSTATE_CFG_TRAIN, 198 [IB_6120_LT_STATE_CFGWAITRMT] = 199 IB_PHYSPORTSTATE_CFG_TRAIN, 200 [IB_6120_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_TRAIN, 201 [IB_6120_LT_STATE_RECOVERRETRAIN] = 202 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 203 [IB_6120_LT_STATE_RECOVERWAITRMT] = 204 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 205 [IB_6120_LT_STATE_RECOVERIDLE] = 206 IB_PHYSPORTSTATE_LINK_ERR_RECOVER, 207 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN, 208 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN, 209 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN, 210 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN, 211 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN, 212 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN, 213 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN, 214 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN 215 }; 216 217 218 struct qib_chip_specific { 219 u64 __iomem *cregbase; 220 u64 *cntrs; 221 u64 *portcntrs; 222 void *dummy_hdrq; /* used after ctxt close */ 223 dma_addr_t dummy_hdrq_phys; 224 spinlock_t kernel_tid_lock; /* no back to back kernel TID writes */ 225 spinlock_t user_tid_lock; /* no back to back user TID writes */ 226 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */ 227 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */ 228 u64 hwerrmask; 229 u64 errormask; 230 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */ 231 u64 gpio_mask; /* shadow the gpio mask register */ 232 u64 extctrl; /* shadow the gpio output enable, etc... */ 233 /* 234 * these 5 fields are used to establish deltas for IB symbol 235 * errors and linkrecovery errors. They can be reported on 236 * some chips during link negotiation prior to INIT, and with 237 * DDR when faking DDR negotiations with non-IBTA switches. 238 * The chip counters are adjusted at driver unload if there is 239 * a non-zero delta. 240 */ 241 u64 ibdeltainprog; 242 u64 ibsymdelta; 243 u64 ibsymsnap; 244 u64 iblnkerrdelta; 245 u64 iblnkerrsnap; 246 u64 ibcctrl; /* shadow for kr_ibcctrl */ 247 u32 lastlinkrecov; /* link recovery issue */ 248 u32 cntrnamelen; 249 u32 portcntrnamelen; 250 u32 ncntrs; 251 u32 nportcntrs; 252 /* used with gpio interrupts to implement IB counters */ 253 u32 rxfc_unsupvl_errs; 254 u32 overrun_thresh_errs; 255 /* 256 * these count only cases where _successive_ LocalLinkIntegrity 257 * errors were seen in the receive headers of IB standard packets 258 */ 259 u32 lli_errs; 260 u32 lli_counter; 261 u64 lli_thresh; 262 u64 sword; /* total dwords sent (sample result) */ 263 u64 rword; /* total dwords received (sample result) */ 264 u64 spkts; /* total packets sent (sample result) */ 265 u64 rpkts; /* total packets received (sample result) */ 266 u64 xmit_wait; /* # of ticks no data sent (sample result) */ 267 struct timer_list pma_timer; 268 char emsgbuf[128]; 269 char bitsmsgbuf[64]; 270 u8 pma_sample_status; 271 }; 272 273 /* ibcctrl bits */ 274 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1 275 /* cycle through TS1/TS2 till OK */ 276 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2 277 /* wait for TS1, then go on */ 278 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3 279 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16 280 281 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */ 282 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */ 283 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */ 284 #define QLOGIC_IB_IBCC_LINKCMD_SHIFT 18 285 286 /* 287 * We could have a single register get/put routine, that takes a group type, 288 * but this is somewhat clearer and cleaner. It also gives us some error 289 * checking. 64 bit register reads should always work, but are inefficient 290 * on opteron (the northbridge always generates 2 separate HT 32 bit reads), 291 * so we use kreg32 wherever possible. User register and counter register 292 * reads are always 32 bit reads, so only one form of those routines. 293 */ 294 295 /** 296 * qib_read_ureg32 - read 32-bit virtualized per-context register 297 * @dd: device 298 * @regno: register number 299 * @ctxt: context number 300 * 301 * Return the contents of a register that is virtualized to be per context. 302 * Returns -1 on errors (not distinguishable from valid contents at 303 * runtime; we may add a separate error variable at some point). 304 */ 305 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, 306 enum qib_ureg regno, int ctxt) 307 { 308 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 309 return 0; 310 311 if (dd->userbase) 312 return readl(regno + (u64 __iomem *) 313 ((char __iomem *)dd->userbase + 314 dd->ureg_align * ctxt)); 315 else 316 return readl(regno + (u64 __iomem *) 317 (dd->uregbase + 318 (char __iomem *)dd->kregbase + 319 dd->ureg_align * ctxt)); 320 } 321 322 /** 323 * qib_write_ureg - write 32-bit virtualized per-context register 324 * @dd: device 325 * @regno: register number 326 * @value: value 327 * @ctxt: context 328 * 329 * Write the contents of a register that is virtualized to be per context. 330 */ 331 static inline void qib_write_ureg(const struct qib_devdata *dd, 332 enum qib_ureg regno, u64 value, int ctxt) 333 { 334 u64 __iomem *ubase; 335 336 if (dd->userbase) 337 ubase = (u64 __iomem *) 338 ((char __iomem *) dd->userbase + 339 dd->ureg_align * ctxt); 340 else 341 ubase = (u64 __iomem *) 342 (dd->uregbase + 343 (char __iomem *) dd->kregbase + 344 dd->ureg_align * ctxt); 345 346 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 347 writeq(value, &ubase[regno]); 348 } 349 350 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, 351 const u16 regno) 352 { 353 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 354 return -1; 355 return readl((u32 __iomem *)&dd->kregbase[regno]); 356 } 357 358 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, 359 const u16 regno) 360 { 361 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) 362 return -1; 363 364 return readq(&dd->kregbase[regno]); 365 } 366 367 static inline void qib_write_kreg(const struct qib_devdata *dd, 368 const u16 regno, u64 value) 369 { 370 if (dd->kregbase && (dd->flags & QIB_PRESENT)) 371 writeq(value, &dd->kregbase[regno]); 372 } 373 374 /** 375 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register 376 * @dd: the qlogic_ib device 377 * @regno: the register number to write 378 * @ctxt: the context containing the register 379 * @value: the value to write 380 */ 381 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, 382 const u16 regno, unsigned ctxt, 383 u64 value) 384 { 385 qib_write_kreg(dd, regno + ctxt, value); 386 } 387 388 static inline void write_6120_creg(const struct qib_devdata *dd, 389 u16 regno, u64 value) 390 { 391 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT)) 392 writeq(value, &dd->cspec->cregbase[regno]); 393 } 394 395 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno) 396 { 397 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 398 return 0; 399 return readq(&dd->cspec->cregbase[regno]); 400 } 401 402 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno) 403 { 404 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) 405 return 0; 406 return readl(&dd->cspec->cregbase[regno]); 407 } 408 409 /* kr_control bits */ 410 #define QLOGIC_IB_C_RESET 1U 411 412 /* kr_intstatus, kr_intclear, kr_intmask bits */ 413 #define QLOGIC_IB_I_RCVURG_MASK ((1U << 5) - 1) 414 #define QLOGIC_IB_I_RCVURG_SHIFT 0 415 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1U << 5) - 1) 416 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 12 417 418 #define QLOGIC_IB_C_FREEZEMODE 0x00000002 419 #define QLOGIC_IB_C_LINKENABLE 0x00000004 420 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL 421 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL 422 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL 423 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL 424 #define QLOGIC_IB_I_BITSEXTANT \ 425 ((QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \ 426 (QLOGIC_IB_I_RCVAVAIL_MASK << \ 427 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \ 428 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \ 429 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO) 430 431 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ 432 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL 433 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0 434 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL 435 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL 436 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL 437 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL 438 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL 439 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL 440 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL 441 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL 442 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL 443 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL 444 445 446 /* kr_extstatus bits */ 447 #define QLOGIC_IB_EXTS_FREQSEL 0x2 448 #define QLOGIC_IB_EXTS_SERDESSEL 0x4 449 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000 450 #define QLOGIC_IB_EXTS_MEMBIST_FOUND 0x0000000000008000 451 452 /* kr_xgxsconfig bits */ 453 #define QLOGIC_IB_XGXS_RESET 0x5ULL 454 455 #define _QIB_GPIO_SDA_NUM 1 456 #define _QIB_GPIO_SCL_NUM 0 457 458 /* Bits in GPIO for the added IB link interrupts */ 459 #define GPIO_RXUVL_BIT 3 460 #define GPIO_OVRUN_BIT 4 461 #define GPIO_LLI_BIT 5 462 #define GPIO_ERRINTR_MASK 0x38 463 464 465 #define QLOGIC_IB_RT_BUFSIZE_MASK 0xe0000000ULL 466 #define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) \ 467 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) >> 29) + 11 - 1) 468 #define QLOGIC_IB_RT_BUFSIZE(tid) (1 << QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid)) 469 #define QLOGIC_IB_RT_IS_VALID(tid) \ 470 (((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) && \ 471 ((((tid) & QLOGIC_IB_RT_BUFSIZE_MASK) != QLOGIC_IB_RT_BUFSIZE_MASK))) 472 #define QLOGIC_IB_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */ 473 #define QLOGIC_IB_RT_ADDR_SHIFT 10 474 475 #define QLOGIC_IB_R_INTRAVAIL_SHIFT 16 476 #define QLOGIC_IB_R_TAILUPD_SHIFT 31 477 #define IBA6120_R_PKEY_DIS_SHIFT 30 478 479 #define PBC_6120_VL15_SEND_CTRL (1ULL << 31) /* pbc; VL15; link_buf only */ 480 481 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr) 482 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr) 483 484 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \ 485 ((1ULL << (SYM_LSB(regname, fldname) + (bit))))) 486 487 #define TXEMEMPARITYERR_PIOBUF \ 488 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0) 489 #define TXEMEMPARITYERR_PIOPBC \ 490 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1) 491 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \ 492 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2) 493 494 #define RXEMEMPARITYERR_RCVBUF \ 495 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0) 496 #define RXEMEMPARITYERR_LOOKUPQ \ 497 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1) 498 #define RXEMEMPARITYERR_EXPTID \ 499 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2) 500 #define RXEMEMPARITYERR_EAGERTID \ 501 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3) 502 #define RXEMEMPARITYERR_FLAGBUF \ 503 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4) 504 #define RXEMEMPARITYERR_DATAINFO \ 505 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5) 506 #define RXEMEMPARITYERR_HDRINFO \ 507 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6) 508 509 /* 6120 specific hardware errors... */ 510 static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = { 511 /* generic hardware errors */ 512 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR, "QIB2IB Parity"), 513 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2QIB Parity"), 514 515 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF, 516 "TXE PIOBUF Memory Parity"), 517 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC, 518 "TXE PIOPBC Memory Parity"), 519 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO, 520 "TXE PIOLAUNCHFIFO Memory Parity"), 521 522 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF, 523 "RXE RCVBUF Memory Parity"), 524 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ, 525 "RXE LOOKUPQ Memory Parity"), 526 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID, 527 "RXE EAGERTID Memory Parity"), 528 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID, 529 "RXE EXPTID Memory Parity"), 530 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF, 531 "RXE FLAGBUF Memory Parity"), 532 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO, 533 "RXE DATAINFO Memory Parity"), 534 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO, 535 "RXE HDRINFO Memory Parity"), 536 537 /* chip-specific hardware errors */ 538 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP, 539 "PCIe Poisoned TLP"), 540 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT, 541 "PCIe completion timeout"), 542 /* 543 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus 544 * parity or memory parity error failures, because most likely we 545 * won't be able to talk to the core of the chip. Nonetheless, we 546 * might see them, if they are in parts of the PCIe core that aren't 547 * essential. 548 */ 549 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED, 550 "PCIePLL1"), 551 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED, 552 "PCIePLL0"), 553 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH, 554 "PCIe XTLH core parity"), 555 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM, 556 "PCIe ADM TX core parity"), 557 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM, 558 "PCIe ADM RX core parity"), 559 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED, 560 "SerDes PLL"), 561 }; 562 563 #define TXE_PIO_PARITY (TXEMEMPARITYERR_PIOBUF | TXEMEMPARITYERR_PIOPBC) 564 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \ 565 QLOGIC_IB_HWE_COREPLL_RFSLIP) 566 567 /* variables for sanity checking interrupt and errors */ 568 #define IB_HWE_BITSEXTANT \ 569 (HWE_MASK(RXEMemParityErr) | \ 570 HWE_MASK(TXEMemParityErr) | \ 571 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \ 572 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \ 573 QLOGIC_IB_HWE_PCIE1PLLFAILED | \ 574 QLOGIC_IB_HWE_PCIE0PLLFAILED | \ 575 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \ 576 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \ 577 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \ 578 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \ 579 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \ 580 HWE_MASK(PowerOnBISTFailed) | \ 581 QLOGIC_IB_HWE_COREPLL_FBSLIP | \ 582 QLOGIC_IB_HWE_COREPLL_RFSLIP | \ 583 QLOGIC_IB_HWE_SERDESPLLFAILED | \ 584 HWE_MASK(IBCBusToSPCParityErr) | \ 585 HWE_MASK(IBCBusFromSPCParityErr)) 586 587 #define IB_E_BITSEXTANT \ 588 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \ 589 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \ 590 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \ 591 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \ 592 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \ 593 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \ 594 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \ 595 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \ 596 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \ 597 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendMaxPktLenErr) | \ 598 ERR_MASK(SendUnderRunErr) | ERR_MASK(SendPktLenErr) | \ 599 ERR_MASK(SendDroppedSmpPktErr) | \ 600 ERR_MASK(SendDroppedDataPktErr) | \ 601 ERR_MASK(SendPioArmLaunchErr) | \ 602 ERR_MASK(SendUnexpectedPktNumErr) | \ 603 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(IBStatusChanged) | \ 604 ERR_MASK(InvalidAddrErr) | ERR_MASK(ResetNegated) | \ 605 ERR_MASK(HardwareErr)) 606 607 #define QLOGIC_IB_E_PKTERRS ( \ 608 ERR_MASK(SendPktLenErr) | \ 609 ERR_MASK(SendDroppedDataPktErr) | \ 610 ERR_MASK(RcvVCRCErr) | \ 611 ERR_MASK(RcvICRCErr) | \ 612 ERR_MASK(RcvShortPktLenErr) | \ 613 ERR_MASK(RcvEBPErr)) 614 615 /* These are all rcv-related errors which we want to count for stats */ 616 #define E_SUM_PKTERRS \ 617 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \ 618 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \ 619 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \ 620 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \ 621 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \ 622 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr)) 623 624 /* These are all send-related errors which we want to count for stats */ 625 #define E_SUM_ERRS \ 626 (ERR_MASK(SendPioArmLaunchErr) | \ 627 ERR_MASK(SendUnexpectedPktNumErr) | \ 628 ERR_MASK(SendDroppedDataPktErr) | \ 629 ERR_MASK(SendDroppedSmpPktErr) | \ 630 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \ 631 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \ 632 ERR_MASK(InvalidAddrErr)) 633 634 /* 635 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore 636 * errors not related to freeze and cancelling buffers. Can't ignore 637 * armlaunch because could get more while still cleaning up, and need 638 * to cancel those as they happen. 639 */ 640 #define E_SPKT_ERRS_IGNORE \ 641 (ERR_MASK(SendDroppedDataPktErr) | \ 642 ERR_MASK(SendDroppedSmpPktErr) | \ 643 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \ 644 ERR_MASK(SendPktLenErr)) 645 646 /* 647 * these are errors that can occur when the link changes state while 648 * a packet is being sent or received. This doesn't cover things 649 * like EBP or VCRC that can be the result of a sending having the 650 * link change state, so we receive a "known bad" packet. 651 */ 652 #define E_SUM_LINK_PKTERRS \ 653 (ERR_MASK(SendDroppedDataPktErr) | \ 654 ERR_MASK(SendDroppedSmpPktErr) | \ 655 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \ 656 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \ 657 ERR_MASK(RcvUnexpectedCharErr)) 658 659 static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *, 660 u32, unsigned long); 661 662 /* 663 * On platforms using this chip, and not having ordered WC stores, we 664 * can get TXE parity errors due to speculative reads to the PIO buffers, 665 * and this, due to a chip issue can result in (many) false parity error 666 * reports. So it's a debug print on those, and an info print on systems 667 * where the speculative reads don't occur. 668 */ 669 static void qib_6120_txe_recover(struct qib_devdata *dd) 670 { 671 if (!qib_unordered_wc()) 672 qib_devinfo(dd->pcidev, 673 "Recovering from TXE PIO parity error\n"); 674 } 675 676 /* enable/disable chip from delivering interrupts */ 677 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable) 678 { 679 if (enable) { 680 if (dd->flags & QIB_BADINTR) 681 return; 682 qib_write_kreg(dd, kr_intmask, ~0ULL); 683 /* force re-interrupt of any pending interrupts. */ 684 qib_write_kreg(dd, kr_intclear, 0ULL); 685 } else 686 qib_write_kreg(dd, kr_intmask, 0ULL); 687 } 688 689 /* 690 * Try to cleanup as much as possible for anything that might have gone 691 * wrong while in freeze mode, such as pio buffers being written by user 692 * processes (causing armlaunch), send errors due to going into freeze mode, 693 * etc., and try to avoid causing extra interrupts while doing so. 694 * Forcibly update the in-memory pioavail register copies after cleanup 695 * because the chip won't do it while in freeze mode (the register values 696 * themselves are kept correct). 697 * Make sure that we don't lose any important interrupts by using the chip 698 * feature that says that writing 0 to a bit in *clear that is set in 699 * *status will cause an interrupt to be generated again (if allowed by 700 * the *mask value). 701 * This is in chip-specific code because of all of the register accesses, 702 * even though the details are similar on most chips 703 */ 704 static void qib_6120_clear_freeze(struct qib_devdata *dd) 705 { 706 /* disable error interrupts, to avoid confusion */ 707 qib_write_kreg(dd, kr_errmask, 0ULL); 708 709 /* also disable interrupts; errormask is sometimes overwritten */ 710 qib_6120_set_intr_state(dd, 0); 711 712 qib_cancel_sends(dd->pport); 713 714 /* clear the freeze, and be sure chip saw it */ 715 qib_write_kreg(dd, kr_control, dd->control); 716 qib_read_kreg32(dd, kr_scratch); 717 718 /* force in-memory update now we are out of freeze */ 719 qib_force_pio_avail_update(dd); 720 721 /* 722 * force new interrupt if any hwerr, error or interrupt bits are 723 * still set, and clear "safe" send packet errors related to freeze 724 * and cancelling sends. Re-enable error interrupts before possible 725 * force of re-interrupt on pending interrupts. 726 */ 727 qib_write_kreg(dd, kr_hwerrclear, 0ULL); 728 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); 729 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 730 qib_6120_set_intr_state(dd, 1); 731 } 732 733 /** 734 * qib_handle_6120_hwerrors - display hardware errors. 735 * @dd: the qlogic_ib device 736 * @msg: the output buffer 737 * @msgl: the size of the output buffer 738 * 739 * Use same msg buffer as regular errors to avoid excessive stack 740 * use. Most hardware errors are catastrophic, but for right now, 741 * we'll print them and continue. Reuse the same message buffer as 742 * handle_6120_errors() to avoid excessive stack usage. 743 */ 744 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg, 745 size_t msgl) 746 { 747 u64 hwerrs; 748 u32 bits, ctrl; 749 int isfatal = 0; 750 char *bitsmsg; 751 int log_idx; 752 753 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 754 if (!hwerrs) 755 return; 756 if (hwerrs == ~0ULL) { 757 qib_dev_err(dd, 758 "Read of hardware error status failed (all bits set); ignoring\n"); 759 return; 760 } 761 qib_stats.sps_hwerrs++; 762 763 /* Always clear the error status register, except MEMBISTFAIL, 764 * regardless of whether we continue or stop using the chip. 765 * We want that set so we know it failed, even across driver reload. 766 * We'll still ignore it in the hwerrmask. We do this partly for 767 * diagnostics, but also for support */ 768 qib_write_kreg(dd, kr_hwerrclear, 769 hwerrs & ~HWE_MASK(PowerOnBISTFailed)); 770 771 hwerrs &= dd->cspec->hwerrmask; 772 773 /* We log some errors to EEPROM, check if we have any of those. */ 774 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx) 775 if (hwerrs & dd->eep_st_masks[log_idx].hwerrs_to_log) 776 qib_inc_eeprom_err(dd, log_idx, 1); 777 778 /* 779 * Make sure we get this much out, unless told to be quiet, 780 * or it's occurred within the last 5 seconds. 781 */ 782 if (hwerrs & ~(TXE_PIO_PARITY | RXEMEMPARITYERR_EAGERTID)) 783 qib_devinfo(dd->pcidev, 784 "Hardware error: hwerr=0x%llx (cleared)\n", 785 (unsigned long long) hwerrs); 786 787 if (hwerrs & ~IB_HWE_BITSEXTANT) 788 qib_dev_err(dd, 789 "hwerror interrupt with unknown errors %llx set\n", 790 (unsigned long long)(hwerrs & ~IB_HWE_BITSEXTANT)); 791 792 ctrl = qib_read_kreg32(dd, kr_control); 793 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) { 794 /* 795 * Parity errors in send memory are recoverable, 796 * just cancel the send (if indicated in * sendbuffererror), 797 * count the occurrence, unfreeze (if no other handled 798 * hardware error bits are set), and continue. They can 799 * occur if a processor speculative read is done to the PIO 800 * buffer while we are sending a packet, for example. 801 */ 802 if (hwerrs & TXE_PIO_PARITY) { 803 qib_6120_txe_recover(dd); 804 hwerrs &= ~TXE_PIO_PARITY; 805 } 806 807 if (!hwerrs) { 808 static u32 freeze_cnt; 809 810 freeze_cnt++; 811 qib_6120_clear_freeze(dd); 812 } else 813 isfatal = 1; 814 } 815 816 *msg = '\0'; 817 818 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) { 819 isfatal = 1; 820 strlcat(msg, 821 "[Memory BIST test failed, InfiniPath hardware unusable]", 822 msgl); 823 /* ignore from now on, so disable until driver reloaded */ 824 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); 825 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 826 } 827 828 qib_format_hwerrors(hwerrs, qib_6120_hwerror_msgs, 829 ARRAY_SIZE(qib_6120_hwerror_msgs), msg, msgl); 830 831 bitsmsg = dd->cspec->bitsmsgbuf; 832 if (hwerrs & (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << 833 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT)) { 834 bits = (u32) ((hwerrs >> 835 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) & 836 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK); 837 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf), 838 "[PCIe Mem Parity Errs %x] ", bits); 839 strlcat(msg, bitsmsg, msgl); 840 } 841 842 if (hwerrs & _QIB_PLL_FAIL) { 843 isfatal = 1; 844 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf), 845 "[PLL failed (%llx), InfiniPath hardware unusable]", 846 (unsigned long long) hwerrs & _QIB_PLL_FAIL); 847 strlcat(msg, bitsmsg, msgl); 848 /* ignore from now on, so disable until driver reloaded */ 849 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL); 850 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 851 } 852 853 if (hwerrs & QLOGIC_IB_HWE_SERDESPLLFAILED) { 854 /* 855 * If it occurs, it is left masked since the external 856 * interface is unused 857 */ 858 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED; 859 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 860 } 861 862 if (hwerrs) 863 /* 864 * if any set that we aren't ignoring; only 865 * make the complaint once, in case it's stuck 866 * or recurring, and we get here multiple 867 * times. 868 */ 869 qib_dev_err(dd, "%s hardware error\n", msg); 870 else 871 *msg = 0; /* recovered from all of them */ 872 873 if (isfatal && !dd->diag_client) { 874 qib_dev_err(dd, 875 "Fatal Hardware Error, no longer usable, SN %.16s\n", 876 dd->serial); 877 /* 878 * for /sys status file and user programs to print; if no 879 * trailing brace is copied, we'll know it was truncated. 880 */ 881 if (dd->freezemsg) 882 snprintf(dd->freezemsg, dd->freezelen, 883 "{%s}", msg); 884 qib_disable_after_error(dd); 885 } 886 } 887 888 /* 889 * Decode the error status into strings, deciding whether to always 890 * print * it or not depending on "normal packet errors" vs everything 891 * else. Return 1 if "real" errors, otherwise 0 if only packet 892 * errors, so caller can decide what to print with the string. 893 */ 894 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen, 895 u64 err) 896 { 897 int iserr = 1; 898 899 *buf = '\0'; 900 if (err & QLOGIC_IB_E_PKTERRS) { 901 if (!(err & ~QLOGIC_IB_E_PKTERRS)) 902 iserr = 0; 903 if ((err & ERR_MASK(RcvICRCErr)) && 904 !(err&(ERR_MASK(RcvVCRCErr)|ERR_MASK(RcvEBPErr)))) 905 strlcat(buf, "CRC ", blen); 906 if (!iserr) 907 goto done; 908 } 909 if (err & ERR_MASK(RcvHdrLenErr)) 910 strlcat(buf, "rhdrlen ", blen); 911 if (err & ERR_MASK(RcvBadTidErr)) 912 strlcat(buf, "rbadtid ", blen); 913 if (err & ERR_MASK(RcvBadVersionErr)) 914 strlcat(buf, "rbadversion ", blen); 915 if (err & ERR_MASK(RcvHdrErr)) 916 strlcat(buf, "rhdr ", blen); 917 if (err & ERR_MASK(RcvLongPktLenErr)) 918 strlcat(buf, "rlongpktlen ", blen); 919 if (err & ERR_MASK(RcvMaxPktLenErr)) 920 strlcat(buf, "rmaxpktlen ", blen); 921 if (err & ERR_MASK(RcvMinPktLenErr)) 922 strlcat(buf, "rminpktlen ", blen); 923 if (err & ERR_MASK(SendMinPktLenErr)) 924 strlcat(buf, "sminpktlen ", blen); 925 if (err & ERR_MASK(RcvFormatErr)) 926 strlcat(buf, "rformaterr ", blen); 927 if (err & ERR_MASK(RcvUnsupportedVLErr)) 928 strlcat(buf, "runsupvl ", blen); 929 if (err & ERR_MASK(RcvUnexpectedCharErr)) 930 strlcat(buf, "runexpchar ", blen); 931 if (err & ERR_MASK(RcvIBFlowErr)) 932 strlcat(buf, "ribflow ", blen); 933 if (err & ERR_MASK(SendUnderRunErr)) 934 strlcat(buf, "sunderrun ", blen); 935 if (err & ERR_MASK(SendPioArmLaunchErr)) 936 strlcat(buf, "spioarmlaunch ", blen); 937 if (err & ERR_MASK(SendUnexpectedPktNumErr)) 938 strlcat(buf, "sunexperrpktnum ", blen); 939 if (err & ERR_MASK(SendDroppedSmpPktErr)) 940 strlcat(buf, "sdroppedsmppkt ", blen); 941 if (err & ERR_MASK(SendMaxPktLenErr)) 942 strlcat(buf, "smaxpktlen ", blen); 943 if (err & ERR_MASK(SendUnsupportedVLErr)) 944 strlcat(buf, "sunsupVL ", blen); 945 if (err & ERR_MASK(InvalidAddrErr)) 946 strlcat(buf, "invalidaddr ", blen); 947 if (err & ERR_MASK(RcvEgrFullErr)) 948 strlcat(buf, "rcvegrfull ", blen); 949 if (err & ERR_MASK(RcvHdrFullErr)) 950 strlcat(buf, "rcvhdrfull ", blen); 951 if (err & ERR_MASK(IBStatusChanged)) 952 strlcat(buf, "ibcstatuschg ", blen); 953 if (err & ERR_MASK(RcvIBLostLinkErr)) 954 strlcat(buf, "riblostlink ", blen); 955 if (err & ERR_MASK(HardwareErr)) 956 strlcat(buf, "hardware ", blen); 957 if (err & ERR_MASK(ResetNegated)) 958 strlcat(buf, "reset ", blen); 959 done: 960 return iserr; 961 } 962 963 /* 964 * Called when we might have an error that is specific to a particular 965 * PIO buffer, and may need to cancel that buffer, so it can be re-used. 966 */ 967 static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd) 968 { 969 unsigned long sbuf[2]; 970 struct qib_devdata *dd = ppd->dd; 971 972 /* 973 * It's possible that sendbuffererror could have bits set; might 974 * have already done this as a result of hardware error handling. 975 */ 976 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror); 977 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1); 978 979 if (sbuf[0] || sbuf[1]) 980 qib_disarm_piobufs_set(dd, sbuf, 981 dd->piobcnt2k + dd->piobcnt4k); 982 } 983 984 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs) 985 { 986 int ret = 1; 987 u32 ibstate = qib_6120_iblink_state(ibcs); 988 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov); 989 990 if (linkrecov != dd->cspec->lastlinkrecov) { 991 /* and no more until active again */ 992 dd->cspec->lastlinkrecov = 0; 993 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN); 994 ret = 0; 995 } 996 if (ibstate == IB_PORT_ACTIVE) 997 dd->cspec->lastlinkrecov = 998 read_6120_creg32(dd, cr_iblinkerrrecov); 999 return ret; 1000 } 1001 1002 static void handle_6120_errors(struct qib_devdata *dd, u64 errs) 1003 { 1004 char *msg; 1005 u64 ignore_this_time = 0; 1006 u64 iserr = 0; 1007 int log_idx; 1008 struct qib_pportdata *ppd = dd->pport; 1009 u64 mask; 1010 1011 /* don't report errors that are masked */ 1012 errs &= dd->cspec->errormask; 1013 msg = dd->cspec->emsgbuf; 1014 1015 /* do these first, they are most important */ 1016 if (errs & ERR_MASK(HardwareErr)) 1017 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); 1018 else 1019 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx) 1020 if (errs & dd->eep_st_masks[log_idx].errs_to_log) 1021 qib_inc_eeprom_err(dd, log_idx, 1); 1022 1023 if (errs & ~IB_E_BITSEXTANT) 1024 qib_dev_err(dd, 1025 "error interrupt with unknown errors %llx set\n", 1026 (unsigned long long) (errs & ~IB_E_BITSEXTANT)); 1027 1028 if (errs & E_SUM_ERRS) { 1029 qib_disarm_6120_senderrbufs(ppd); 1030 if ((errs & E_SUM_LINK_PKTERRS) && 1031 !(ppd->lflags & QIBL_LINKACTIVE)) { 1032 /* 1033 * This can happen when trying to bring the link 1034 * up, but the IB link changes state at the "wrong" 1035 * time. The IB logic then complains that the packet 1036 * isn't valid. We don't want to confuse people, so 1037 * we just don't print them, except at debug 1038 */ 1039 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 1040 } 1041 } else if ((errs & E_SUM_LINK_PKTERRS) && 1042 !(ppd->lflags & QIBL_LINKACTIVE)) { 1043 /* 1044 * This can happen when SMA is trying to bring the link 1045 * up, but the IB link changes state at the "wrong" time. 1046 * The IB logic then complains that the packet isn't 1047 * valid. We don't want to confuse people, so we just 1048 * don't print them, except at debug 1049 */ 1050 ignore_this_time = errs & E_SUM_LINK_PKTERRS; 1051 } 1052 1053 qib_write_kreg(dd, kr_errclear, errs); 1054 1055 errs &= ~ignore_this_time; 1056 if (!errs) 1057 goto done; 1058 1059 /* 1060 * The ones we mask off are handled specially below 1061 * or above. 1062 */ 1063 mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) | 1064 ERR_MASK(RcvHdrFullErr) | ERR_MASK(HardwareErr); 1065 qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask); 1066 1067 if (errs & E_SUM_PKTERRS) 1068 qib_stats.sps_rcverrs++; 1069 if (errs & E_SUM_ERRS) 1070 qib_stats.sps_txerrs++; 1071 1072 iserr = errs & ~(E_SUM_PKTERRS | QLOGIC_IB_E_PKTERRS); 1073 1074 if (errs & ERR_MASK(IBStatusChanged)) { 1075 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus); 1076 u32 ibstate = qib_6120_iblink_state(ibcs); 1077 int handle = 1; 1078 1079 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov) 1080 handle = chk_6120_linkrecovery(dd, ibcs); 1081 /* 1082 * Since going into a recovery state causes the link state 1083 * to go down and since recovery is transitory, it is better 1084 * if we "miss" ever seeing the link training state go into 1085 * recovery (i.e., ignore this transition for link state 1086 * special handling purposes) without updating lastibcstat. 1087 */ 1088 if (handle && qib_6120_phys_portstate(ibcs) == 1089 IB_PHYSPORTSTATE_LINK_ERR_RECOVER) 1090 handle = 0; 1091 if (handle) 1092 qib_handle_e_ibstatuschanged(ppd, ibcs); 1093 } 1094 1095 if (errs & ERR_MASK(ResetNegated)) { 1096 qib_dev_err(dd, 1097 "Got reset, requires re-init (unload and reload driver)\n"); 1098 dd->flags &= ~QIB_INITTED; /* needs re-init */ 1099 /* mark as having had error */ 1100 *dd->devstatusp |= QIB_STATUS_HWERROR; 1101 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF; 1102 } 1103 1104 if (*msg && iserr) 1105 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); 1106 1107 if (ppd->state_wanted & ppd->lflags) 1108 wake_up_interruptible(&ppd->state_wait); 1109 1110 /* 1111 * If there were hdrq or egrfull errors, wake up any processes 1112 * waiting in poll. We used to try to check which contexts had 1113 * the overflow, but given the cost of that and the chip reads 1114 * to support it, it's better to just wake everybody up if we 1115 * get an overflow; waiters can poll again if it's not them. 1116 */ 1117 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) { 1118 qib_handle_urcv(dd, ~0U); 1119 if (errs & ERR_MASK(RcvEgrFullErr)) 1120 qib_stats.sps_buffull++; 1121 else 1122 qib_stats.sps_hdrfull++; 1123 } 1124 done: 1125 return; 1126 } 1127 1128 /** 1129 * qib_6120_init_hwerrors - enable hardware errors 1130 * @dd: the qlogic_ib device 1131 * 1132 * now that we have finished initializing everything that might reasonably 1133 * cause a hardware error, and cleared those errors bits as they occur, 1134 * we can enable hardware errors in the mask (potentially enabling 1135 * freeze mode), and enable hardware errors as errors (along with 1136 * everything else) in errormask 1137 */ 1138 static void qib_6120_init_hwerrors(struct qib_devdata *dd) 1139 { 1140 u64 val; 1141 u64 extsval; 1142 1143 extsval = qib_read_kreg64(dd, kr_extstatus); 1144 1145 if (!(extsval & QLOGIC_IB_EXTS_MEMBIST_ENDTEST)) 1146 qib_dev_err(dd, "MemBIST did not complete!\n"); 1147 1148 /* init so all hwerrors interrupt, and enter freeze, ajdust below */ 1149 val = ~0ULL; 1150 if (dd->minrev < 2) { 1151 /* 1152 * Avoid problem with internal interface bus parity 1153 * checking. Fixed in Rev2. 1154 */ 1155 val &= ~QLOGIC_IB_HWE_PCIEBUSPARITYRADM; 1156 } 1157 /* avoid some intel cpu's speculative read freeze mode issue */ 1158 val &= ~TXEMEMPARITYERR_PIOBUF; 1159 1160 dd->cspec->hwerrmask = val; 1161 1162 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); 1163 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); 1164 1165 /* clear all */ 1166 qib_write_kreg(dd, kr_errclear, ~0ULL); 1167 /* enable errors that are masked, at least this first time. */ 1168 qib_write_kreg(dd, kr_errmask, ~0ULL); 1169 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); 1170 /* clear any interrupts up to this point (ints still not enabled) */ 1171 qib_write_kreg(dd, kr_intclear, ~0ULL); 1172 1173 qib_write_kreg(dd, kr_rcvbthqp, 1174 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) | 1175 QIB_KD_QP); 1176 } 1177 1178 /* 1179 * Disable and enable the armlaunch error. Used for PIO bandwidth testing 1180 * on chips that are count-based, rather than trigger-based. There is no 1181 * reference counting, but that's also fine, given the intended use. 1182 * Only chip-specific because it's all register accesses 1183 */ 1184 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable) 1185 { 1186 if (enable) { 1187 qib_write_kreg(dd, kr_errclear, 1188 ERR_MASK(SendPioArmLaunchErr)); 1189 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr); 1190 } else 1191 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr); 1192 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); 1193 } 1194 1195 /* 1196 * Formerly took parameter <which> in pre-shifted, 1197 * pre-merged form with LinkCmd and LinkInitCmd 1198 * together, and assuming the zero was NOP. 1199 */ 1200 static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd, 1201 u16 linitcmd) 1202 { 1203 u64 mod_wd; 1204 struct qib_devdata *dd = ppd->dd; 1205 unsigned long flags; 1206 1207 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) { 1208 /* 1209 * If we are told to disable, note that so link-recovery 1210 * code does not attempt to bring us back up. 1211 */ 1212 spin_lock_irqsave(&ppd->lflags_lock, flags); 1213 ppd->lflags |= QIBL_IB_LINK_DISABLED; 1214 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 1215 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) { 1216 /* 1217 * Any other linkinitcmd will lead to LINKDOWN and then 1218 * to INIT (if all is well), so clear flag to let 1219 * link-recovery code attempt to bring us back up. 1220 */ 1221 spin_lock_irqsave(&ppd->lflags_lock, flags); 1222 ppd->lflags &= ~QIBL_IB_LINK_DISABLED; 1223 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 1224 } 1225 1226 mod_wd = (linkcmd << QLOGIC_IB_IBCC_LINKCMD_SHIFT) | 1227 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 1228 1229 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd); 1230 /* write to chip to prevent back-to-back writes of control reg */ 1231 qib_write_kreg(dd, kr_scratch, 0); 1232 } 1233 1234 /** 1235 * qib_6120_bringup_serdes - bring up the serdes 1236 * @dd: the qlogic_ib device 1237 */ 1238 static int qib_6120_bringup_serdes(struct qib_pportdata *ppd) 1239 { 1240 struct qib_devdata *dd = ppd->dd; 1241 u64 val, config1, prev_val, hwstat, ibc; 1242 1243 /* Put IBC in reset, sends disabled */ 1244 dd->control &= ~QLOGIC_IB_C_LINKENABLE; 1245 qib_write_kreg(dd, kr_control, 0ULL); 1246 1247 dd->cspec->ibdeltainprog = 1; 1248 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr); 1249 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov); 1250 1251 /* flowcontrolwatermark is in units of KBytes */ 1252 ibc = 0x5ULL << SYM_LSB(IBCCtrl, FlowCtrlWaterMark); 1253 /* 1254 * How often flowctrl sent. More or less in usecs; balance against 1255 * watermark value, so that in theory senders always get a flow 1256 * control update in time to not let the IB link go idle. 1257 */ 1258 ibc |= 0x3ULL << SYM_LSB(IBCCtrl, FlowCtrlPeriod); 1259 /* max error tolerance */ 1260 dd->cspec->lli_thresh = 0xf; 1261 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold); 1262 /* use "real" buffer space for */ 1263 ibc |= 4ULL << SYM_LSB(IBCCtrl, CreditScale); 1264 /* IB credit flow control. */ 1265 ibc |= 0xfULL << SYM_LSB(IBCCtrl, OverrunThreshold); 1266 /* 1267 * set initial max size pkt IBC will send, including ICRC; it's the 1268 * PIO buffer size in dwords, less 1; also see qib_set_mtu() 1269 */ 1270 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << SYM_LSB(IBCCtrl, MaxPktLen); 1271 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */ 1272 1273 /* initially come up waiting for TS1, without sending anything. */ 1274 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << 1275 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT); 1276 qib_write_kreg(dd, kr_ibcctrl, val); 1277 1278 val = qib_read_kreg64(dd, kr_serdes_cfg0); 1279 config1 = qib_read_kreg64(dd, kr_serdes_cfg1); 1280 1281 /* 1282 * Force reset on, also set rxdetect enable. Must do before reading 1283 * serdesstatus at least for simulation, or some of the bits in 1284 * serdes status will come back as undefined and cause simulation 1285 * failures 1286 */ 1287 val |= SYM_MASK(SerdesCfg0, ResetPLL) | 1288 SYM_MASK(SerdesCfg0, RxDetEnX) | 1289 (SYM_MASK(SerdesCfg0, L1PwrDnA) | 1290 SYM_MASK(SerdesCfg0, L1PwrDnB) | 1291 SYM_MASK(SerdesCfg0, L1PwrDnC) | 1292 SYM_MASK(SerdesCfg0, L1PwrDnD)); 1293 qib_write_kreg(dd, kr_serdes_cfg0, val); 1294 /* be sure chip saw it */ 1295 qib_read_kreg64(dd, kr_scratch); 1296 udelay(5); /* need pll reset set at least for a bit */ 1297 /* 1298 * after PLL is reset, set the per-lane Resets and TxIdle and 1299 * clear the PLL reset and rxdetect (to get falling edge). 1300 * Leave L1PWR bits set (permanently) 1301 */ 1302 val &= ~(SYM_MASK(SerdesCfg0, RxDetEnX) | 1303 SYM_MASK(SerdesCfg0, ResetPLL) | 1304 (SYM_MASK(SerdesCfg0, L1PwrDnA) | 1305 SYM_MASK(SerdesCfg0, L1PwrDnB) | 1306 SYM_MASK(SerdesCfg0, L1PwrDnC) | 1307 SYM_MASK(SerdesCfg0, L1PwrDnD))); 1308 val |= (SYM_MASK(SerdesCfg0, ResetA) | 1309 SYM_MASK(SerdesCfg0, ResetB) | 1310 SYM_MASK(SerdesCfg0, ResetC) | 1311 SYM_MASK(SerdesCfg0, ResetD)) | 1312 SYM_MASK(SerdesCfg0, TxIdeEnX); 1313 qib_write_kreg(dd, kr_serdes_cfg0, val); 1314 /* be sure chip saw it */ 1315 (void) qib_read_kreg64(dd, kr_scratch); 1316 /* need PLL reset clear for at least 11 usec before lane 1317 * resets cleared; give it a few more to be sure */ 1318 udelay(15); 1319 val &= ~((SYM_MASK(SerdesCfg0, ResetA) | 1320 SYM_MASK(SerdesCfg0, ResetB) | 1321 SYM_MASK(SerdesCfg0, ResetC) | 1322 SYM_MASK(SerdesCfg0, ResetD)) | 1323 SYM_MASK(SerdesCfg0, TxIdeEnX)); 1324 1325 qib_write_kreg(dd, kr_serdes_cfg0, val); 1326 /* be sure chip saw it */ 1327 (void) qib_read_kreg64(dd, kr_scratch); 1328 1329 val = qib_read_kreg64(dd, kr_xgxs_cfg); 1330 prev_val = val; 1331 if (val & QLOGIC_IB_XGXS_RESET) 1332 val &= ~QLOGIC_IB_XGXS_RESET; 1333 if (SYM_FIELD(val, XGXSCfg, polarity_inv) != ppd->rx_pol_inv) { 1334 /* need to compensate for Tx inversion in partner */ 1335 val &= ~SYM_MASK(XGXSCfg, polarity_inv); 1336 val |= (u64)ppd->rx_pol_inv << SYM_LSB(XGXSCfg, polarity_inv); 1337 } 1338 if (val != prev_val) 1339 qib_write_kreg(dd, kr_xgxs_cfg, val); 1340 1341 val = qib_read_kreg64(dd, kr_serdes_cfg0); 1342 1343 /* clear current and de-emphasis bits */ 1344 config1 &= ~0x0ffffffff00ULL; 1345 /* set current to 20ma */ 1346 config1 |= 0x00000000000ULL; 1347 /* set de-emphasis to -5.68dB */ 1348 config1 |= 0x0cccc000000ULL; 1349 qib_write_kreg(dd, kr_serdes_cfg1, config1); 1350 1351 /* base and port guid same for single port */ 1352 ppd->guid = dd->base_guid; 1353 1354 /* 1355 * the process of setting and un-resetting the serdes normally 1356 * causes a serdes PLL error, so check for that and clear it 1357 * here. Also clearr hwerr bit in errstatus, but not others. 1358 */ 1359 hwstat = qib_read_kreg64(dd, kr_hwerrstatus); 1360 if (hwstat) { 1361 /* should just have PLL, clear all set, in an case */ 1362 qib_write_kreg(dd, kr_hwerrclear, hwstat); 1363 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr)); 1364 } 1365 1366 dd->control |= QLOGIC_IB_C_LINKENABLE; 1367 dd->control &= ~QLOGIC_IB_C_FREEZEMODE; 1368 qib_write_kreg(dd, kr_control, dd->control); 1369 1370 return 0; 1371 } 1372 1373 /** 1374 * qib_6120_quiet_serdes - set serdes to txidle 1375 * @ppd: physical port of the qlogic_ib device 1376 * Called when driver is being unloaded 1377 */ 1378 static void qib_6120_quiet_serdes(struct qib_pportdata *ppd) 1379 { 1380 struct qib_devdata *dd = ppd->dd; 1381 u64 val; 1382 1383 qib_set_ib_6120_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1384 1385 /* disable IBC */ 1386 dd->control &= ~QLOGIC_IB_C_LINKENABLE; 1387 qib_write_kreg(dd, kr_control, 1388 dd->control | QLOGIC_IB_C_FREEZEMODE); 1389 1390 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta || 1391 dd->cspec->ibdeltainprog) { 1392 u64 diagc; 1393 1394 /* enable counter writes */ 1395 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); 1396 qib_write_kreg(dd, kr_hwdiagctrl, 1397 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable)); 1398 1399 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) { 1400 val = read_6120_creg32(dd, cr_ibsymbolerr); 1401 if (dd->cspec->ibdeltainprog) 1402 val -= val - dd->cspec->ibsymsnap; 1403 val -= dd->cspec->ibsymdelta; 1404 write_6120_creg(dd, cr_ibsymbolerr, val); 1405 } 1406 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) { 1407 val = read_6120_creg32(dd, cr_iblinkerrrecov); 1408 if (dd->cspec->ibdeltainprog) 1409 val -= val - dd->cspec->iblnkerrsnap; 1410 val -= dd->cspec->iblnkerrdelta; 1411 write_6120_creg(dd, cr_iblinkerrrecov, val); 1412 } 1413 1414 /* and disable counter writes */ 1415 qib_write_kreg(dd, kr_hwdiagctrl, diagc); 1416 } 1417 1418 val = qib_read_kreg64(dd, kr_serdes_cfg0); 1419 val |= SYM_MASK(SerdesCfg0, TxIdeEnX); 1420 qib_write_kreg(dd, kr_serdes_cfg0, val); 1421 } 1422 1423 /** 1424 * qib_6120_setup_setextled - set the state of the two external LEDs 1425 * @dd: the qlogic_ib device 1426 * @on: whether the link is up or not 1427 * 1428 * The exact combo of LEDs if on is true is determined by looking 1429 * at the ibcstatus. 1430 1431 * These LEDs indicate the physical and logical state of IB link. 1432 * For this chip (at least with recommended board pinouts), LED1 1433 * is Yellow (logical state) and LED2 is Green (physical state), 1434 * 1435 * Note: We try to match the Mellanox HCA LED behavior as best 1436 * we can. Green indicates physical link state is OK (something is 1437 * plugged in, and we can train). 1438 * Amber indicates the link is logically up (ACTIVE). 1439 * Mellanox further blinks the amber LED to indicate data packet 1440 * activity, but we have no hardware support for that, so it would 1441 * require waking up every 10-20 msecs and checking the counters 1442 * on the chip, and then turning the LED off if appropriate. That's 1443 * visible overhead, so not something we will do. 1444 * 1445 */ 1446 static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on) 1447 { 1448 u64 extctl, val, lst, ltst; 1449 unsigned long flags; 1450 struct qib_devdata *dd = ppd->dd; 1451 1452 /* 1453 * The diags use the LED to indicate diag info, so we leave 1454 * the external LED alone when the diags are running. 1455 */ 1456 if (dd->diag_client) 1457 return; 1458 1459 /* Allow override of LED display for, e.g. Locating system in rack */ 1460 if (ppd->led_override) { 1461 ltst = (ppd->led_override & QIB_LED_PHYS) ? 1462 IB_PHYSPORTSTATE_LINKUP : IB_PHYSPORTSTATE_DISABLED, 1463 lst = (ppd->led_override & QIB_LED_LOG) ? 1464 IB_PORT_ACTIVE : IB_PORT_DOWN; 1465 } else if (on) { 1466 val = qib_read_kreg64(dd, kr_ibcstatus); 1467 ltst = qib_6120_phys_portstate(val); 1468 lst = qib_6120_iblink_state(val); 1469 } else { 1470 ltst = 0; 1471 lst = 0; 1472 } 1473 1474 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 1475 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) | 1476 SYM_MASK(EXTCtrl, LEDPriPortYellowOn)); 1477 1478 if (ltst == IB_PHYSPORTSTATE_LINKUP) 1479 extctl |= SYM_MASK(EXTCtrl, LEDPriPortYellowOn); 1480 if (lst == IB_PORT_ACTIVE) 1481 extctl |= SYM_MASK(EXTCtrl, LEDPriPortGreenOn); 1482 dd->cspec->extctrl = extctl; 1483 qib_write_kreg(dd, kr_extctrl, extctl); 1484 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 1485 } 1486 1487 /** 1488 * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff 1489 * @dd: the qlogic_ib device 1490 * 1491 * This is called during driver unload. 1492 */ 1493 static void qib_6120_setup_cleanup(struct qib_devdata *dd) 1494 { 1495 qib_free_irq(dd); 1496 kfree(dd->cspec->cntrs); 1497 kfree(dd->cspec->portcntrs); 1498 if (dd->cspec->dummy_hdrq) { 1499 dma_free_coherent(&dd->pcidev->dev, 1500 ALIGN(dd->rcvhdrcnt * 1501 dd->rcvhdrentsize * 1502 sizeof(u32), PAGE_SIZE), 1503 dd->cspec->dummy_hdrq, 1504 dd->cspec->dummy_hdrq_phys); 1505 dd->cspec->dummy_hdrq = NULL; 1506 } 1507 } 1508 1509 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint) 1510 { 1511 unsigned long flags; 1512 1513 spin_lock_irqsave(&dd->sendctrl_lock, flags); 1514 if (needint) 1515 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail); 1516 else 1517 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail); 1518 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 1519 qib_write_kreg(dd, kr_scratch, 0ULL); 1520 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 1521 } 1522 1523 /* 1524 * handle errors and unusual events first, separate function 1525 * to improve cache hits for fast path interrupt handling 1526 */ 1527 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat) 1528 { 1529 if (unlikely(istat & ~QLOGIC_IB_I_BITSEXTANT)) 1530 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n", 1531 istat & ~QLOGIC_IB_I_BITSEXTANT); 1532 1533 if (istat & QLOGIC_IB_I_ERROR) { 1534 u64 estat = 0; 1535 1536 qib_stats.sps_errints++; 1537 estat = qib_read_kreg64(dd, kr_errstatus); 1538 if (!estat) 1539 qib_devinfo(dd->pcidev, 1540 "error interrupt (%Lx), but no error bits set!\n", 1541 istat); 1542 handle_6120_errors(dd, estat); 1543 } 1544 1545 if (istat & QLOGIC_IB_I_GPIO) { 1546 u32 gpiostatus; 1547 u32 to_clear = 0; 1548 1549 /* 1550 * GPIO_3..5 on IBA6120 Rev2 chips indicate 1551 * errors that we need to count. 1552 */ 1553 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); 1554 /* First the error-counter case. */ 1555 if (gpiostatus & GPIO_ERRINTR_MASK) { 1556 /* want to clear the bits we see asserted. */ 1557 to_clear |= (gpiostatus & GPIO_ERRINTR_MASK); 1558 1559 /* 1560 * Count appropriately, clear bits out of our copy, 1561 * as they have been "handled". 1562 */ 1563 if (gpiostatus & (1 << GPIO_RXUVL_BIT)) 1564 dd->cspec->rxfc_unsupvl_errs++; 1565 if (gpiostatus & (1 << GPIO_OVRUN_BIT)) 1566 dd->cspec->overrun_thresh_errs++; 1567 if (gpiostatus & (1 << GPIO_LLI_BIT)) 1568 dd->cspec->lli_errs++; 1569 gpiostatus &= ~GPIO_ERRINTR_MASK; 1570 } 1571 if (gpiostatus) { 1572 /* 1573 * Some unexpected bits remain. If they could have 1574 * caused the interrupt, complain and clear. 1575 * To avoid repetition of this condition, also clear 1576 * the mask. It is almost certainly due to error. 1577 */ 1578 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); 1579 1580 /* 1581 * Also check that the chip reflects our shadow, 1582 * and report issues, If they caused the interrupt. 1583 * we will suppress by refreshing from the shadow. 1584 */ 1585 if (mask & gpiostatus) { 1586 to_clear |= (gpiostatus & mask); 1587 dd->cspec->gpio_mask &= ~(gpiostatus & mask); 1588 qib_write_kreg(dd, kr_gpio_mask, 1589 dd->cspec->gpio_mask); 1590 } 1591 } 1592 if (to_clear) 1593 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear); 1594 } 1595 } 1596 1597 static irqreturn_t qib_6120intr(int irq, void *data) 1598 { 1599 struct qib_devdata *dd = data; 1600 irqreturn_t ret; 1601 u32 istat, ctxtrbits, rmask, crcs = 0; 1602 unsigned i; 1603 1604 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { 1605 /* 1606 * This return value is not great, but we do not want the 1607 * interrupt core code to remove our interrupt handler 1608 * because we don't appear to be handling an interrupt 1609 * during a chip reset. 1610 */ 1611 ret = IRQ_HANDLED; 1612 goto bail; 1613 } 1614 1615 istat = qib_read_kreg32(dd, kr_intstatus); 1616 1617 if (unlikely(!istat)) { 1618 ret = IRQ_NONE; /* not our interrupt, or already handled */ 1619 goto bail; 1620 } 1621 if (unlikely(istat == -1)) { 1622 qib_bad_intrstatus(dd); 1623 /* don't know if it was our interrupt or not */ 1624 ret = IRQ_NONE; 1625 goto bail; 1626 } 1627 1628 this_cpu_inc(*dd->int_counter); 1629 1630 if (unlikely(istat & (~QLOGIC_IB_I_BITSEXTANT | 1631 QLOGIC_IB_I_GPIO | QLOGIC_IB_I_ERROR))) 1632 unlikely_6120_intr(dd, istat); 1633 1634 /* 1635 * Clear the interrupt bits we found set, relatively early, so we 1636 * "know" know the chip will have seen this by the time we process 1637 * the queue, and will re-interrupt if necessary. The processor 1638 * itself won't take the interrupt again until we return. 1639 */ 1640 qib_write_kreg(dd, kr_intclear, istat); 1641 1642 /* 1643 * Handle kernel receive queues before checking for pio buffers 1644 * available since receives can overflow; piobuf waiters can afford 1645 * a few extra cycles, since they were waiting anyway. 1646 */ 1647 ctxtrbits = istat & 1648 ((QLOGIC_IB_I_RCVAVAIL_MASK << QLOGIC_IB_I_RCVAVAIL_SHIFT) | 1649 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT)); 1650 if (ctxtrbits) { 1651 rmask = (1U << QLOGIC_IB_I_RCVAVAIL_SHIFT) | 1652 (1U << QLOGIC_IB_I_RCVURG_SHIFT); 1653 for (i = 0; i < dd->first_user_ctxt; i++) { 1654 if (ctxtrbits & rmask) { 1655 ctxtrbits &= ~rmask; 1656 crcs += qib_kreceive(dd->rcd[i], 1657 &dd->cspec->lli_counter, 1658 NULL); 1659 } 1660 rmask <<= 1; 1661 } 1662 if (crcs) { 1663 u32 cntr = dd->cspec->lli_counter; 1664 1665 cntr += crcs; 1666 if (cntr) { 1667 if (cntr > dd->cspec->lli_thresh) { 1668 dd->cspec->lli_counter = 0; 1669 dd->cspec->lli_errs++; 1670 } else 1671 dd->cspec->lli_counter += cntr; 1672 } 1673 } 1674 1675 1676 if (ctxtrbits) { 1677 ctxtrbits = 1678 (ctxtrbits >> QLOGIC_IB_I_RCVAVAIL_SHIFT) | 1679 (ctxtrbits >> QLOGIC_IB_I_RCVURG_SHIFT); 1680 qib_handle_urcv(dd, ctxtrbits); 1681 } 1682 } 1683 1684 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) 1685 qib_ib_piobufavail(dd); 1686 1687 ret = IRQ_HANDLED; 1688 bail: 1689 return ret; 1690 } 1691 1692 /* 1693 * Set up our chip-specific interrupt handler 1694 * The interrupt type has already been setup, so 1695 * we just need to do the registration and error checking. 1696 */ 1697 static void qib_setup_6120_interrupt(struct qib_devdata *dd) 1698 { 1699 int ret; 1700 1701 /* 1702 * If the chip supports added error indication via GPIO pins, 1703 * enable interrupts on those bits so the interrupt routine 1704 * can count the events. Also set flag so interrupt routine 1705 * can know they are expected. 1706 */ 1707 if (SYM_FIELD(dd->revision, Revision_R, 1708 ChipRevMinor) > 1) { 1709 /* Rev2+ reports extra errors via internal GPIO pins */ 1710 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK; 1711 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 1712 } 1713 1714 ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd, 1715 QIB_DRV_NAME); 1716 if (ret) 1717 qib_dev_err(dd, 1718 "Couldn't setup interrupt (irq=%d): %d\n", 1719 pci_irq_vector(dd->pcidev, 0), ret); 1720 } 1721 1722 /** 1723 * pe_boardname - fill in the board name 1724 * @dd: the qlogic_ib device 1725 * 1726 * info is based on the board revision register 1727 */ 1728 static void pe_boardname(struct qib_devdata *dd) 1729 { 1730 u32 boardid; 1731 1732 boardid = SYM_FIELD(dd->revision, Revision, 1733 BoardID); 1734 1735 switch (boardid) { 1736 case 2: 1737 dd->boardname = "InfiniPath_QLE7140"; 1738 break; 1739 default: 1740 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid); 1741 dd->boardname = "Unknown_InfiniPath_6120"; 1742 break; 1743 } 1744 1745 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2) 1746 qib_dev_err(dd, 1747 "Unsupported InfiniPath hardware revision %u.%u!\n", 1748 dd->majrev, dd->minrev); 1749 1750 snprintf(dd->boardversion, sizeof(dd->boardversion), 1751 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n", 1752 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, 1753 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch), 1754 dd->majrev, dd->minrev, 1755 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW)); 1756 } 1757 1758 /* 1759 * This routine sleeps, so it can only be called from user context, not 1760 * from interrupt context. If we need interrupt context, we can split 1761 * it into two routines. 1762 */ 1763 static int qib_6120_setup_reset(struct qib_devdata *dd) 1764 { 1765 u64 val; 1766 int i; 1767 int ret; 1768 u16 cmdval; 1769 u8 int_line, clinesz; 1770 1771 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); 1772 1773 /* Use ERROR so it shows up in logs, etc. */ 1774 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); 1775 1776 /* no interrupts till re-initted */ 1777 qib_6120_set_intr_state(dd, 0); 1778 1779 dd->cspec->ibdeltainprog = 0; 1780 dd->cspec->ibsymdelta = 0; 1781 dd->cspec->iblnkerrdelta = 0; 1782 1783 /* 1784 * Keep chip from being accessed until we are ready. Use 1785 * writeq() directly, to allow the write even though QIB_PRESENT 1786 * isn't set. 1787 */ 1788 dd->flags &= ~(QIB_INITTED | QIB_PRESENT); 1789 /* so we check interrupts work again */ 1790 dd->z_int_counter = qib_int_counter(dd); 1791 val = dd->control | QLOGIC_IB_C_RESET; 1792 writeq(val, &dd->kregbase[kr_control]); 1793 mb(); /* prevent compiler re-ordering around actual reset */ 1794 1795 for (i = 1; i <= 5; i++) { 1796 /* 1797 * Allow MBIST, etc. to complete; longer on each retry. 1798 * We sometimes get machine checks from bus timeout if no 1799 * response, so for now, make it *really* long. 1800 */ 1801 msleep(1000 + (1 + i) * 2000); 1802 1803 qib_pcie_reenable(dd, cmdval, int_line, clinesz); 1804 1805 /* 1806 * Use readq directly, so we don't need to mark it as PRESENT 1807 * until we get a successful indication that all is well. 1808 */ 1809 val = readq(&dd->kregbase[kr_revision]); 1810 if (val == dd->revision) { 1811 dd->flags |= QIB_PRESENT; /* it's back */ 1812 ret = qib_reinit_intr(dd); 1813 goto bail; 1814 } 1815 } 1816 ret = 0; /* failed */ 1817 1818 bail: 1819 if (ret) { 1820 if (qib_pcie_params(dd, dd->lbus_width, NULL)) 1821 qib_dev_err(dd, 1822 "Reset failed to setup PCIe or interrupts; continuing anyway\n"); 1823 /* clear the reset error, init error/hwerror mask */ 1824 qib_6120_init_hwerrors(dd); 1825 /* for Rev2 error interrupts; nop for rev 1 */ 1826 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); 1827 /* clear the reset error, init error/hwerror mask */ 1828 qib_6120_init_hwerrors(dd); 1829 } 1830 return ret; 1831 } 1832 1833 /** 1834 * qib_6120_put_tid - write a TID in chip 1835 * @dd: the qlogic_ib device 1836 * @tidptr: pointer to the expected TID (in chip) to update 1837 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) 1838 * for expected 1839 * @pa: physical address of in memory buffer; tidinvalid if freeing 1840 * 1841 * This exists as a separate routine to allow for special locking etc. 1842 * It's used for both the full cleanup on exit, as well as the normal 1843 * setup and teardown. 1844 */ 1845 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, 1846 u32 type, unsigned long pa) 1847 { 1848 u32 __iomem *tidp32 = (u32 __iomem *)tidptr; 1849 unsigned long flags; 1850 int tidx; 1851 spinlock_t *tidlockp; /* select appropriate spinlock */ 1852 1853 if (!dd->kregbase) 1854 return; 1855 1856 if (pa != dd->tidinvalid) { 1857 if (pa & ((1U << 11) - 1)) { 1858 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", 1859 pa); 1860 return; 1861 } 1862 pa >>= 11; 1863 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) { 1864 qib_dev_err(dd, 1865 "Physical page address 0x%lx larger than supported\n", 1866 pa); 1867 return; 1868 } 1869 1870 if (type == RCVHQ_RCV_TYPE_EAGER) 1871 pa |= dd->tidtemplate; 1872 else /* for now, always full 4KB page */ 1873 pa |= 2 << 29; 1874 } 1875 1876 /* 1877 * Avoid chip issue by writing the scratch register 1878 * before and after the TID, and with an io write barrier. 1879 * We use a spinlock around the writes, so they can't intermix 1880 * with other TID (eager or expected) writes (the chip problem 1881 * is triggered by back to back TID writes). Unfortunately, this 1882 * call can be done from interrupt level for the ctxt 0 eager TIDs, 1883 * so we have to use irqsave locks. 1884 */ 1885 /* 1886 * Assumes tidptr always > egrtidbase 1887 * if type == RCVHQ_RCV_TYPE_EAGER. 1888 */ 1889 tidx = tidptr - dd->egrtidbase; 1890 1891 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt) 1892 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock; 1893 spin_lock_irqsave(tidlockp, flags); 1894 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf); 1895 writel(pa, tidp32); 1896 qib_write_kreg(dd, kr_scratch, 0xdeadbeef); 1897 mmiowb(); 1898 spin_unlock_irqrestore(tidlockp, flags); 1899 } 1900 1901 /** 1902 * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher 1903 * @dd: the qlogic_ib device 1904 * @tidptr: pointer to the expected TID (in chip) to update 1905 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) 1906 * for expected 1907 * @pa: physical address of in memory buffer; tidinvalid if freeing 1908 * 1909 * This exists as a separate routine to allow for selection of the 1910 * appropriate "flavor". The static calls in cleanup just use the 1911 * revision-agnostic form, as they are not performance critical. 1912 */ 1913 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr, 1914 u32 type, unsigned long pa) 1915 { 1916 u32 __iomem *tidp32 = (u32 __iomem *)tidptr; 1917 u32 tidx; 1918 1919 if (!dd->kregbase) 1920 return; 1921 1922 if (pa != dd->tidinvalid) { 1923 if (pa & ((1U << 11) - 1)) { 1924 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", 1925 pa); 1926 return; 1927 } 1928 pa >>= 11; 1929 if (pa & ~QLOGIC_IB_RT_ADDR_MASK) { 1930 qib_dev_err(dd, 1931 "Physical page address 0x%lx larger than supported\n", 1932 pa); 1933 return; 1934 } 1935 1936 if (type == RCVHQ_RCV_TYPE_EAGER) 1937 pa |= dd->tidtemplate; 1938 else /* for now, always full 4KB page */ 1939 pa |= 2 << 29; 1940 } 1941 tidx = tidptr - dd->egrtidbase; 1942 writel(pa, tidp32); 1943 mmiowb(); 1944 } 1945 1946 1947 /** 1948 * qib_6120_clear_tids - clear all TID entries for a context, expected and eager 1949 * @dd: the qlogic_ib device 1950 * @ctxt: the context 1951 * 1952 * clear all TID entries for a context, expected and eager. 1953 * Used from qib_close(). On this chip, TIDs are only 32 bits, 1954 * not 64, but they are still on 64 bit boundaries, so tidbase 1955 * is declared as u64 * for the pointer math, even though we write 32 bits 1956 */ 1957 static void qib_6120_clear_tids(struct qib_devdata *dd, 1958 struct qib_ctxtdata *rcd) 1959 { 1960 u64 __iomem *tidbase; 1961 unsigned long tidinv; 1962 u32 ctxt; 1963 int i; 1964 1965 if (!dd->kregbase || !rcd) 1966 return; 1967 1968 ctxt = rcd->ctxt; 1969 1970 tidinv = dd->tidinvalid; 1971 tidbase = (u64 __iomem *) 1972 ((char __iomem *)(dd->kregbase) + 1973 dd->rcvtidbase + 1974 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); 1975 1976 for (i = 0; i < dd->rcvtidcnt; i++) 1977 /* use func pointer because could be one of two funcs */ 1978 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, 1979 tidinv); 1980 1981 tidbase = (u64 __iomem *) 1982 ((char __iomem *)(dd->kregbase) + 1983 dd->rcvegrbase + 1984 rcd->rcvegr_tid_base * sizeof(*tidbase)); 1985 1986 for (i = 0; i < rcd->rcvegrcnt; i++) 1987 /* use func pointer because could be one of two funcs */ 1988 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, 1989 tidinv); 1990 } 1991 1992 /** 1993 * qib_6120_tidtemplate - setup constants for TID updates 1994 * @dd: the qlogic_ib device 1995 * 1996 * We setup stuff that we use a lot, to avoid calculating each time 1997 */ 1998 static void qib_6120_tidtemplate(struct qib_devdata *dd) 1999 { 2000 u32 egrsize = dd->rcvegrbufsize; 2001 2002 /* 2003 * For now, we always allocate 4KB buffers (at init) so we can 2004 * receive max size packets. We may want a module parameter to 2005 * specify 2KB or 4KB and/or make be per ctxt instead of per device 2006 * for those who want to reduce memory footprint. Note that the 2007 * rcvhdrentsize size must be large enough to hold the largest 2008 * IB header (currently 96 bytes) that we expect to handle (plus of 2009 * course the 2 dwords of RHF). 2010 */ 2011 if (egrsize == 2048) 2012 dd->tidtemplate = 1U << 29; 2013 else if (egrsize == 4096) 2014 dd->tidtemplate = 2U << 29; 2015 dd->tidinvalid = 0; 2016 } 2017 2018 int __attribute__((weak)) qib_unordered_wc(void) 2019 { 2020 return 0; 2021 } 2022 2023 /** 2024 * qib_6120_get_base_info - set chip-specific flags for user code 2025 * @rcd: the qlogic_ib ctxt 2026 * @kbase: qib_base_info pointer 2027 * 2028 * We set the PCIE flag because the lower bandwidth on PCIe vs 2029 * HyperTransport can affect some user packet algorithms. 2030 */ 2031 static int qib_6120_get_base_info(struct qib_ctxtdata *rcd, 2032 struct qib_base_info *kinfo) 2033 { 2034 if (qib_unordered_wc()) 2035 kinfo->spi_runtime_flags |= QIB_RUNTIME_FORCE_WC_ORDER; 2036 2037 kinfo->spi_runtime_flags |= QIB_RUNTIME_PCIE | 2038 QIB_RUNTIME_FORCE_PIOAVAIL | QIB_RUNTIME_PIO_REGSWAPPED; 2039 return 0; 2040 } 2041 2042 2043 static struct qib_message_header * 2044 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) 2045 { 2046 return (struct qib_message_header *) 2047 &rhf_addr[sizeof(u64) / sizeof(u32)]; 2048 } 2049 2050 static void qib_6120_config_ctxts(struct qib_devdata *dd) 2051 { 2052 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt); 2053 if (qib_n_krcv_queues > 1) { 2054 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports; 2055 if (dd->first_user_ctxt > dd->ctxtcnt) 2056 dd->first_user_ctxt = dd->ctxtcnt; 2057 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6; 2058 } else 2059 dd->first_user_ctxt = dd->num_pports; 2060 dd->n_krcv_queues = dd->first_user_ctxt; 2061 } 2062 2063 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd, 2064 u32 updegr, u32 egrhd, u32 npkts) 2065 { 2066 if (updegr) 2067 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); 2068 mmiowb(); 2069 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 2070 mmiowb(); 2071 } 2072 2073 static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd) 2074 { 2075 u32 head, tail; 2076 2077 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); 2078 if (rcd->rcvhdrtail_kvaddr) 2079 tail = qib_get_rcvhdrtail(rcd); 2080 else 2081 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); 2082 return head == tail; 2083 } 2084 2085 /* 2086 * Used when we close any ctxt, for DMA already in flight 2087 * at close. Can't be done until we know hdrq size, so not 2088 * early in chip init. 2089 */ 2090 static void alloc_dummy_hdrq(struct qib_devdata *dd) 2091 { 2092 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev, 2093 dd->rcd[0]->rcvhdrq_size, 2094 &dd->cspec->dummy_hdrq_phys, 2095 GFP_ATOMIC | __GFP_COMP); 2096 if (!dd->cspec->dummy_hdrq) { 2097 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n"); 2098 /* fallback to just 0'ing */ 2099 dd->cspec->dummy_hdrq_phys = 0UL; 2100 } 2101 } 2102 2103 /* 2104 * Modify the RCVCTRL register in chip-specific way. This 2105 * is a function because bit positions and (future) register 2106 * location is chip-specific, but the needed operations are 2107 * generic. <op> is a bit-mask because we often want to 2108 * do multiple modifications. 2109 */ 2110 static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op, 2111 int ctxt) 2112 { 2113 struct qib_devdata *dd = ppd->dd; 2114 u64 mask, val; 2115 unsigned long flags; 2116 2117 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); 2118 2119 if (op & QIB_RCVCTRL_TAILUPD_ENB) 2120 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT); 2121 if (op & QIB_RCVCTRL_TAILUPD_DIS) 2122 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT); 2123 if (op & QIB_RCVCTRL_PKEY_ENB) 2124 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT); 2125 if (op & QIB_RCVCTRL_PKEY_DIS) 2126 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT); 2127 if (ctxt < 0) 2128 mask = (1ULL << dd->ctxtcnt) - 1; 2129 else 2130 mask = (1ULL << ctxt); 2131 if (op & QIB_RCVCTRL_CTXT_ENB) { 2132 /* always done for specific ctxt */ 2133 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable)); 2134 if (!(dd->flags & QIB_NODMA_RTAIL)) 2135 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT; 2136 /* Write these registers before the context is enabled. */ 2137 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, 2138 dd->rcd[ctxt]->rcvhdrqtailaddr_phys); 2139 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, 2140 dd->rcd[ctxt]->rcvhdrq_phys); 2141 2142 if (ctxt == 0 && !dd->cspec->dummy_hdrq) 2143 alloc_dummy_hdrq(dd); 2144 } 2145 if (op & QIB_RCVCTRL_CTXT_DIS) 2146 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable)); 2147 if (op & QIB_RCVCTRL_INTRAVAIL_ENB) 2148 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); 2149 if (op & QIB_RCVCTRL_INTRAVAIL_DIS) 2150 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); 2151 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); 2152 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) { 2153 /* arm rcv interrupt */ 2154 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) | 2155 dd->rhdrhead_intr_off; 2156 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 2157 } 2158 if (op & QIB_RCVCTRL_CTXT_ENB) { 2159 /* 2160 * Init the context registers also; if we were 2161 * disabled, tail and head should both be zero 2162 * already from the enable, but since we don't 2163 * know, we have to do it explicitly. 2164 */ 2165 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); 2166 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); 2167 2168 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); 2169 dd->rcd[ctxt]->head = val; 2170 /* If kctxt, interrupt on next receive. */ 2171 if (ctxt < dd->first_user_ctxt) 2172 val |= dd->rhdrhead_intr_off; 2173 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); 2174 } 2175 if (op & QIB_RCVCTRL_CTXT_DIS) { 2176 /* 2177 * Be paranoid, and never write 0's to these, just use an 2178 * unused page. Of course, 2179 * rcvhdraddr points to a large chunk of memory, so this 2180 * could still trash things, but at least it won't trash 2181 * page 0, and by disabling the ctxt, it should stop "soon", 2182 * even if a packet or two is in already in flight after we 2183 * disabled the ctxt. Only 6120 has this issue. 2184 */ 2185 if (ctxt >= 0) { 2186 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, 2187 dd->cspec->dummy_hdrq_phys); 2188 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, 2189 dd->cspec->dummy_hdrq_phys); 2190 } else { 2191 unsigned i; 2192 2193 for (i = 0; i < dd->cfgctxts; i++) { 2194 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, 2195 i, dd->cspec->dummy_hdrq_phys); 2196 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, 2197 i, dd->cspec->dummy_hdrq_phys); 2198 } 2199 } 2200 } 2201 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); 2202 } 2203 2204 /* 2205 * Modify the SENDCTRL register in chip-specific way. This 2206 * is a function there may be multiple such registers with 2207 * slightly different layouts. Only operations actually used 2208 * are implemented yet. 2209 * Chip requires no back-back sendctrl writes, so write 2210 * scratch register after writing sendctrl 2211 */ 2212 static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op) 2213 { 2214 struct qib_devdata *dd = ppd->dd; 2215 u64 tmp_dd_sendctrl; 2216 unsigned long flags; 2217 2218 spin_lock_irqsave(&dd->sendctrl_lock, flags); 2219 2220 /* First the ones that are "sticky", saved in shadow */ 2221 if (op & QIB_SENDCTRL_CLEAR) 2222 dd->sendctrl = 0; 2223 if (op & QIB_SENDCTRL_SEND_DIS) 2224 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable); 2225 else if (op & QIB_SENDCTRL_SEND_ENB) 2226 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable); 2227 if (op & QIB_SENDCTRL_AVAIL_DIS) 2228 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd); 2229 else if (op & QIB_SENDCTRL_AVAIL_ENB) 2230 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd); 2231 2232 if (op & QIB_SENDCTRL_DISARM_ALL) { 2233 u32 i, last; 2234 2235 tmp_dd_sendctrl = dd->sendctrl; 2236 /* 2237 * disarm any that are not yet launched, disabling sends 2238 * and updates until done. 2239 */ 2240 last = dd->piobcnt2k + dd->piobcnt4k; 2241 tmp_dd_sendctrl &= 2242 ~(SYM_MASK(SendCtrl, PIOEnable) | 2243 SYM_MASK(SendCtrl, PIOBufAvailUpd)); 2244 for (i = 0; i < last; i++) { 2245 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl | 2246 SYM_MASK(SendCtrl, Disarm) | i); 2247 qib_write_kreg(dd, kr_scratch, 0); 2248 } 2249 } 2250 2251 tmp_dd_sendctrl = dd->sendctrl; 2252 2253 if (op & QIB_SENDCTRL_FLUSH) 2254 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Abort); 2255 if (op & QIB_SENDCTRL_DISARM) 2256 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) | 2257 ((op & QIB_6120_SendCtrl_DisarmPIOBuf_RMASK) << 2258 SYM_LSB(SendCtrl, DisarmPIOBuf)); 2259 if (op & QIB_SENDCTRL_AVAIL_BLIP) 2260 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd); 2261 2262 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); 2263 qib_write_kreg(dd, kr_scratch, 0); 2264 2265 if (op & QIB_SENDCTRL_AVAIL_BLIP) { 2266 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); 2267 qib_write_kreg(dd, kr_scratch, 0); 2268 } 2269 2270 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); 2271 2272 if (op & QIB_SENDCTRL_FLUSH) { 2273 u32 v; 2274 /* 2275 * ensure writes have hit chip, then do a few 2276 * more reads, to allow DMA of pioavail registers 2277 * to occur, so in-memory copy is in sync with 2278 * the chip. Not always safe to sleep. 2279 */ 2280 v = qib_read_kreg32(dd, kr_scratch); 2281 qib_write_kreg(dd, kr_scratch, v); 2282 v = qib_read_kreg32(dd, kr_scratch); 2283 qib_write_kreg(dd, kr_scratch, v); 2284 qib_read_kreg32(dd, kr_scratch); 2285 } 2286 } 2287 2288 /** 2289 * qib_portcntr_6120 - read a per-port counter 2290 * @dd: the qlogic_ib device 2291 * @creg: the counter to snapshot 2292 */ 2293 static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg) 2294 { 2295 u64 ret = 0ULL; 2296 struct qib_devdata *dd = ppd->dd; 2297 u16 creg; 2298 /* 0xffff for unimplemented or synthesized counters */ 2299 static const u16 xlator[] = { 2300 [QIBPORTCNTR_PKTSEND] = cr_pktsend, 2301 [QIBPORTCNTR_WORDSEND] = cr_wordsend, 2302 [QIBPORTCNTR_PSXMITDATA] = 0xffff, 2303 [QIBPORTCNTR_PSXMITPKTS] = 0xffff, 2304 [QIBPORTCNTR_PSXMITWAIT] = 0xffff, 2305 [QIBPORTCNTR_SENDSTALL] = cr_sendstall, 2306 [QIBPORTCNTR_PKTRCV] = cr_pktrcv, 2307 [QIBPORTCNTR_PSRCVDATA] = 0xffff, 2308 [QIBPORTCNTR_PSRCVPKTS] = 0xffff, 2309 [QIBPORTCNTR_RCVEBP] = cr_rcvebp, 2310 [QIBPORTCNTR_RCVOVFL] = cr_rcvovfl, 2311 [QIBPORTCNTR_WORDRCV] = cr_wordrcv, 2312 [QIBPORTCNTR_RXDROPPKT] = cr_rxdroppkt, 2313 [QIBPORTCNTR_RXLOCALPHYERR] = 0xffff, 2314 [QIBPORTCNTR_RXVLERR] = 0xffff, 2315 [QIBPORTCNTR_ERRICRC] = cr_erricrc, 2316 [QIBPORTCNTR_ERRVCRC] = cr_errvcrc, 2317 [QIBPORTCNTR_ERRLPCRC] = cr_errlpcrc, 2318 [QIBPORTCNTR_BADFORMAT] = cr_badformat, 2319 [QIBPORTCNTR_ERR_RLEN] = cr_err_rlen, 2320 [QIBPORTCNTR_IBSYMBOLERR] = cr_ibsymbolerr, 2321 [QIBPORTCNTR_INVALIDRLEN] = cr_invalidrlen, 2322 [QIBPORTCNTR_UNSUPVL] = cr_txunsupvl, 2323 [QIBPORTCNTR_EXCESSBUFOVFL] = 0xffff, 2324 [QIBPORTCNTR_ERRLINK] = cr_errlink, 2325 [QIBPORTCNTR_IBLINKDOWN] = cr_iblinkdown, 2326 [QIBPORTCNTR_IBLINKERRRECOV] = cr_iblinkerrrecov, 2327 [QIBPORTCNTR_LLI] = 0xffff, 2328 [QIBPORTCNTR_PSINTERVAL] = 0xffff, 2329 [QIBPORTCNTR_PSSTART] = 0xffff, 2330 [QIBPORTCNTR_PSSTAT] = 0xffff, 2331 [QIBPORTCNTR_VL15PKTDROP] = 0xffff, 2332 [QIBPORTCNTR_ERRPKEY] = cr_errpkey, 2333 [QIBPORTCNTR_KHDROVFL] = 0xffff, 2334 }; 2335 2336 if (reg >= ARRAY_SIZE(xlator)) { 2337 qib_devinfo(ppd->dd->pcidev, 2338 "Unimplemented portcounter %u\n", reg); 2339 goto done; 2340 } 2341 creg = xlator[reg]; 2342 2343 /* handle counters requests not implemented as chip counters */ 2344 if (reg == QIBPORTCNTR_LLI) 2345 ret = dd->cspec->lli_errs; 2346 else if (reg == QIBPORTCNTR_EXCESSBUFOVFL) 2347 ret = dd->cspec->overrun_thresh_errs; 2348 else if (reg == QIBPORTCNTR_KHDROVFL) { 2349 int i; 2350 2351 /* sum over all kernel contexts */ 2352 for (i = 0; i < dd->first_user_ctxt; i++) 2353 ret += read_6120_creg32(dd, cr_portovfl + i); 2354 } else if (reg == QIBPORTCNTR_PSSTAT) 2355 ret = dd->cspec->pma_sample_status; 2356 if (creg == 0xffff) 2357 goto done; 2358 2359 /* 2360 * only fast incrementing counters are 64bit; use 32 bit reads to 2361 * avoid two independent reads when on opteron 2362 */ 2363 if (creg == cr_wordsend || creg == cr_wordrcv || 2364 creg == cr_pktsend || creg == cr_pktrcv) 2365 ret = read_6120_creg(dd, creg); 2366 else 2367 ret = read_6120_creg32(dd, creg); 2368 if (creg == cr_ibsymbolerr) { 2369 if (dd->cspec->ibdeltainprog) 2370 ret -= ret - dd->cspec->ibsymsnap; 2371 ret -= dd->cspec->ibsymdelta; 2372 } else if (creg == cr_iblinkerrrecov) { 2373 if (dd->cspec->ibdeltainprog) 2374 ret -= ret - dd->cspec->iblnkerrsnap; 2375 ret -= dd->cspec->iblnkerrdelta; 2376 } 2377 if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */ 2378 ret += dd->cspec->rxfc_unsupvl_errs; 2379 2380 done: 2381 return ret; 2382 } 2383 2384 /* 2385 * Device counter names (not port-specific), one line per stat, 2386 * single string. Used by utilities like ipathstats to print the stats 2387 * in a way which works for different versions of drivers, without changing 2388 * the utility. Names need to be 12 chars or less (w/o newline), for proper 2389 * display by utility. 2390 * Non-error counters are first. 2391 * Start of "error" conters is indicated by a leading "E " on the first 2392 * "error" counter, and doesn't count in label length. 2393 * The EgrOvfl list needs to be last so we truncate them at the configured 2394 * context count for the device. 2395 * cntr6120indices contains the corresponding register indices. 2396 */ 2397 static const char cntr6120names[] = 2398 "Interrupts\n" 2399 "HostBusStall\n" 2400 "E RxTIDFull\n" 2401 "RxTIDInvalid\n" 2402 "Ctxt0EgrOvfl\n" 2403 "Ctxt1EgrOvfl\n" 2404 "Ctxt2EgrOvfl\n" 2405 "Ctxt3EgrOvfl\n" 2406 "Ctxt4EgrOvfl\n"; 2407 2408 static const size_t cntr6120indices[] = { 2409 cr_lbint, 2410 cr_lbflowstall, 2411 cr_errtidfull, 2412 cr_errtidvalid, 2413 cr_portovfl + 0, 2414 cr_portovfl + 1, 2415 cr_portovfl + 2, 2416 cr_portovfl + 3, 2417 cr_portovfl + 4, 2418 }; 2419 2420 /* 2421 * same as cntr6120names and cntr6120indices, but for port-specific counters. 2422 * portcntr6120indices is somewhat complicated by some registers needing 2423 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG 2424 */ 2425 static const char portcntr6120names[] = 2426 "TxPkt\n" 2427 "TxFlowPkt\n" 2428 "TxWords\n" 2429 "RxPkt\n" 2430 "RxFlowPkt\n" 2431 "RxWords\n" 2432 "TxFlowStall\n" 2433 "E IBStatusChng\n" 2434 "IBLinkDown\n" 2435 "IBLnkRecov\n" 2436 "IBRxLinkErr\n" 2437 "IBSymbolErr\n" 2438 "RxLLIErr\n" 2439 "RxBadFormat\n" 2440 "RxBadLen\n" 2441 "RxBufOvrfl\n" 2442 "RxEBP\n" 2443 "RxFlowCtlErr\n" 2444 "RxICRCerr\n" 2445 "RxLPCRCerr\n" 2446 "RxVCRCerr\n" 2447 "RxInvalLen\n" 2448 "RxInvalPKey\n" 2449 "RxPktDropped\n" 2450 "TxBadLength\n" 2451 "TxDropped\n" 2452 "TxInvalLen\n" 2453 "TxUnderrun\n" 2454 "TxUnsupVL\n" 2455 ; 2456 2457 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */ 2458 static const size_t portcntr6120indices[] = { 2459 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG, 2460 cr_pktsendflow, 2461 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG, 2462 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG, 2463 cr_pktrcvflowctrl, 2464 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG, 2465 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG, 2466 cr_ibstatuschange, 2467 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG, 2468 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG, 2469 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG, 2470 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG, 2471 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG, 2472 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG, 2473 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG, 2474 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG, 2475 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG, 2476 cr_rcvflowctrl_err, 2477 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG, 2478 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG, 2479 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG, 2480 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG, 2481 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG, 2482 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG, 2483 cr_invalidslen, 2484 cr_senddropped, 2485 cr_errslen, 2486 cr_sendunderrun, 2487 cr_txunsupvl, 2488 }; 2489 2490 /* do all the setup to make the counter reads efficient later */ 2491 static void init_6120_cntrnames(struct qib_devdata *dd) 2492 { 2493 int i, j = 0; 2494 char *s; 2495 2496 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts; 2497 i++) { 2498 /* we always have at least one counter before the egrovfl */ 2499 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12)) 2500 j = 1; 2501 s = strchr(s + 1, '\n'); 2502 if (s && j) 2503 j++; 2504 } 2505 dd->cspec->ncntrs = i; 2506 if (!s) 2507 /* full list; size is without terminating null */ 2508 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1; 2509 else 2510 dd->cspec->cntrnamelen = 1 + s - cntr6120names; 2511 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs 2512 * sizeof(u64), GFP_KERNEL); 2513 2514 for (i = 0, s = (char *)portcntr6120names; s; i++) 2515 s = strchr(s + 1, '\n'); 2516 dd->cspec->nportcntrs = i - 1; 2517 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1; 2518 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs 2519 * sizeof(u64), GFP_KERNEL); 2520 } 2521 2522 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep, 2523 u64 **cntrp) 2524 { 2525 u32 ret; 2526 2527 if (namep) { 2528 ret = dd->cspec->cntrnamelen; 2529 if (pos >= ret) 2530 ret = 0; /* final read after getting everything */ 2531 else 2532 *namep = (char *)cntr6120names; 2533 } else { 2534 u64 *cntr = dd->cspec->cntrs; 2535 int i; 2536 2537 ret = dd->cspec->ncntrs * sizeof(u64); 2538 if (!cntr || pos >= ret) { 2539 /* everything read, or couldn't get memory */ 2540 ret = 0; 2541 goto done; 2542 } 2543 if (pos >= ret) { 2544 ret = 0; /* final read after getting everything */ 2545 goto done; 2546 } 2547 *cntrp = cntr; 2548 for (i = 0; i < dd->cspec->ncntrs; i++) 2549 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]); 2550 } 2551 done: 2552 return ret; 2553 } 2554 2555 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, 2556 char **namep, u64 **cntrp) 2557 { 2558 u32 ret; 2559 2560 if (namep) { 2561 ret = dd->cspec->portcntrnamelen; 2562 if (pos >= ret) 2563 ret = 0; /* final read after getting everything */ 2564 else 2565 *namep = (char *)portcntr6120names; 2566 } else { 2567 u64 *cntr = dd->cspec->portcntrs; 2568 struct qib_pportdata *ppd = &dd->pport[port]; 2569 int i; 2570 2571 ret = dd->cspec->nportcntrs * sizeof(u64); 2572 if (!cntr || pos >= ret) { 2573 /* everything read, or couldn't get memory */ 2574 ret = 0; 2575 goto done; 2576 } 2577 *cntrp = cntr; 2578 for (i = 0; i < dd->cspec->nportcntrs; i++) { 2579 if (portcntr6120indices[i] & _PORT_VIRT_FLAG) 2580 *cntr++ = qib_portcntr_6120(ppd, 2581 portcntr6120indices[i] & 2582 ~_PORT_VIRT_FLAG); 2583 else 2584 *cntr++ = read_6120_creg32(dd, 2585 portcntr6120indices[i]); 2586 } 2587 } 2588 done: 2589 return ret; 2590 } 2591 2592 static void qib_chk_6120_errormask(struct qib_devdata *dd) 2593 { 2594 static u32 fixed; 2595 u32 ctrl; 2596 unsigned long errormask; 2597 unsigned long hwerrs; 2598 2599 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED)) 2600 return; 2601 2602 errormask = qib_read_kreg64(dd, kr_errmask); 2603 2604 if (errormask == dd->cspec->errormask) 2605 return; 2606 fixed++; 2607 2608 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); 2609 ctrl = qib_read_kreg32(dd, kr_control); 2610 2611 qib_write_kreg(dd, kr_errmask, 2612 dd->cspec->errormask); 2613 2614 if ((hwerrs & dd->cspec->hwerrmask) || 2615 (ctrl & QLOGIC_IB_C_FREEZEMODE)) { 2616 qib_write_kreg(dd, kr_hwerrclear, 0ULL); 2617 qib_write_kreg(dd, kr_errclear, 0ULL); 2618 /* force re-interrupt of pending events, just in case */ 2619 qib_write_kreg(dd, kr_intclear, 0ULL); 2620 qib_devinfo(dd->pcidev, 2621 "errormask fixed(%u) %lx->%lx, ctrl %x hwerr %lx\n", 2622 fixed, errormask, (unsigned long)dd->cspec->errormask, 2623 ctrl, hwerrs); 2624 } 2625 } 2626 2627 /** 2628 * qib_get_faststats - get word counters from chip before they overflow 2629 * @opaque - contains a pointer to the qlogic_ib device qib_devdata 2630 * 2631 * This needs more work; in particular, decision on whether we really 2632 * need traffic_wds done the way it is 2633 * called from add_timer 2634 */ 2635 static void qib_get_6120_faststats(unsigned long opaque) 2636 { 2637 struct qib_devdata *dd = (struct qib_devdata *) opaque; 2638 struct qib_pportdata *ppd = dd->pport; 2639 unsigned long flags; 2640 u64 traffic_wds; 2641 2642 /* 2643 * don't access the chip while running diags, or memory diags can 2644 * fail 2645 */ 2646 if (!(dd->flags & QIB_INITTED) || dd->diag_client) 2647 /* but re-arm the timer, for diags case; won't hurt other */ 2648 goto done; 2649 2650 /* 2651 * We now try to maintain an activity timer, based on traffic 2652 * exceeding a threshold, so we need to check the word-counts 2653 * even if they are 64-bit. 2654 */ 2655 traffic_wds = qib_portcntr_6120(ppd, cr_wordsend) + 2656 qib_portcntr_6120(ppd, cr_wordrcv); 2657 spin_lock_irqsave(&dd->eep_st_lock, flags); 2658 traffic_wds -= dd->traffic_wds; 2659 dd->traffic_wds += traffic_wds; 2660 spin_unlock_irqrestore(&dd->eep_st_lock, flags); 2661 2662 qib_chk_6120_errormask(dd); 2663 done: 2664 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); 2665 } 2666 2667 /* no interrupt fallback for these chips */ 2668 static int qib_6120_nointr_fallback(struct qib_devdata *dd) 2669 { 2670 return 0; 2671 } 2672 2673 /* 2674 * reset the XGXS (between serdes and IBC). Slightly less intrusive 2675 * than resetting the IBC or external link state, and useful in some 2676 * cases to cause some retraining. To do this right, we reset IBC 2677 * as well. 2678 */ 2679 static void qib_6120_xgxs_reset(struct qib_pportdata *ppd) 2680 { 2681 u64 val, prev_val; 2682 struct qib_devdata *dd = ppd->dd; 2683 2684 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg); 2685 val = prev_val | QLOGIC_IB_XGXS_RESET; 2686 prev_val &= ~QLOGIC_IB_XGXS_RESET; /* be sure */ 2687 qib_write_kreg(dd, kr_control, 2688 dd->control & ~QLOGIC_IB_C_LINKENABLE); 2689 qib_write_kreg(dd, kr_xgxs_cfg, val); 2690 qib_read_kreg32(dd, kr_scratch); 2691 qib_write_kreg(dd, kr_xgxs_cfg, prev_val); 2692 qib_write_kreg(dd, kr_control, dd->control); 2693 } 2694 2695 static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which) 2696 { 2697 int ret; 2698 2699 switch (which) { 2700 case QIB_IB_CFG_LWID: 2701 ret = ppd->link_width_active; 2702 break; 2703 2704 case QIB_IB_CFG_SPD: 2705 ret = ppd->link_speed_active; 2706 break; 2707 2708 case QIB_IB_CFG_LWID_ENB: 2709 ret = ppd->link_width_enabled; 2710 break; 2711 2712 case QIB_IB_CFG_SPD_ENB: 2713 ret = ppd->link_speed_enabled; 2714 break; 2715 2716 case QIB_IB_CFG_OP_VLS: 2717 ret = ppd->vls_operational; 2718 break; 2719 2720 case QIB_IB_CFG_VL_HIGH_CAP: 2721 ret = 0; 2722 break; 2723 2724 case QIB_IB_CFG_VL_LOW_CAP: 2725 ret = 0; 2726 break; 2727 2728 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 2729 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl, 2730 OverrunThreshold); 2731 break; 2732 2733 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 2734 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl, 2735 PhyerrThreshold); 2736 break; 2737 2738 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 2739 /* will only take effect when the link state changes */ 2740 ret = (ppd->dd->cspec->ibcctrl & 2741 SYM_MASK(IBCCtrl, LinkDownDefaultState)) ? 2742 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL; 2743 break; 2744 2745 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */ 2746 ret = 0; /* no heartbeat on this chip */ 2747 break; 2748 2749 case QIB_IB_CFG_PMA_TICKS: 2750 ret = 250; /* 1 usec. */ 2751 break; 2752 2753 default: 2754 ret = -EINVAL; 2755 break; 2756 } 2757 return ret; 2758 } 2759 2760 /* 2761 * We assume range checking is already done, if needed. 2762 */ 2763 static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) 2764 { 2765 struct qib_devdata *dd = ppd->dd; 2766 int ret = 0; 2767 u64 val64; 2768 u16 lcmd, licmd; 2769 2770 switch (which) { 2771 case QIB_IB_CFG_LWID_ENB: 2772 ppd->link_width_enabled = val; 2773 break; 2774 2775 case QIB_IB_CFG_SPD_ENB: 2776 ppd->link_speed_enabled = val; 2777 break; 2778 2779 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */ 2780 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl, 2781 OverrunThreshold); 2782 if (val64 != val) { 2783 dd->cspec->ibcctrl &= 2784 ~SYM_MASK(IBCCtrl, OverrunThreshold); 2785 dd->cspec->ibcctrl |= (u64) val << 2786 SYM_LSB(IBCCtrl, OverrunThreshold); 2787 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); 2788 qib_write_kreg(dd, kr_scratch, 0); 2789 } 2790 break; 2791 2792 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */ 2793 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl, 2794 PhyerrThreshold); 2795 if (val64 != val) { 2796 dd->cspec->ibcctrl &= 2797 ~SYM_MASK(IBCCtrl, PhyerrThreshold); 2798 dd->cspec->ibcctrl |= (u64) val << 2799 SYM_LSB(IBCCtrl, PhyerrThreshold); 2800 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); 2801 qib_write_kreg(dd, kr_scratch, 0); 2802 } 2803 break; 2804 2805 case QIB_IB_CFG_PKEYS: /* update pkeys */ 2806 val64 = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | 2807 ((u64) ppd->pkeys[2] << 32) | 2808 ((u64) ppd->pkeys[3] << 48); 2809 qib_write_kreg(dd, kr_partitionkey, val64); 2810 break; 2811 2812 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */ 2813 /* will only take effect when the link state changes */ 2814 if (val == IB_LINKINITCMD_POLL) 2815 dd->cspec->ibcctrl &= 2816 ~SYM_MASK(IBCCtrl, LinkDownDefaultState); 2817 else /* SLEEP */ 2818 dd->cspec->ibcctrl |= 2819 SYM_MASK(IBCCtrl, LinkDownDefaultState); 2820 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); 2821 qib_write_kreg(dd, kr_scratch, 0); 2822 break; 2823 2824 case QIB_IB_CFG_MTU: /* update the MTU in IBC */ 2825 /* 2826 * Update our housekeeping variables, and set IBC max 2827 * size, same as init code; max IBC is max we allow in 2828 * buffer, less the qword pbc, plus 1 for ICRC, in dwords 2829 * Set even if it's unchanged, print debug message only 2830 * on changes. 2831 */ 2832 val = (ppd->ibmaxlen >> 2) + 1; 2833 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen); 2834 dd->cspec->ibcctrl |= (u64)val << 2835 SYM_LSB(IBCCtrl, MaxPktLen); 2836 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); 2837 qib_write_kreg(dd, kr_scratch, 0); 2838 break; 2839 2840 case QIB_IB_CFG_LSTATE: /* set the IB link state */ 2841 switch (val & 0xffff0000) { 2842 case IB_LINKCMD_DOWN: 2843 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN; 2844 if (!dd->cspec->ibdeltainprog) { 2845 dd->cspec->ibdeltainprog = 1; 2846 dd->cspec->ibsymsnap = 2847 read_6120_creg32(dd, cr_ibsymbolerr); 2848 dd->cspec->iblnkerrsnap = 2849 read_6120_creg32(dd, cr_iblinkerrrecov); 2850 } 2851 break; 2852 2853 case IB_LINKCMD_ARMED: 2854 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED; 2855 break; 2856 2857 case IB_LINKCMD_ACTIVE: 2858 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE; 2859 break; 2860 2861 default: 2862 ret = -EINVAL; 2863 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); 2864 goto bail; 2865 } 2866 switch (val & 0xffff) { 2867 case IB_LINKINITCMD_NOP: 2868 licmd = 0; 2869 break; 2870 2871 case IB_LINKINITCMD_POLL: 2872 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL; 2873 break; 2874 2875 case IB_LINKINITCMD_SLEEP: 2876 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP; 2877 break; 2878 2879 case IB_LINKINITCMD_DISABLE: 2880 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE; 2881 break; 2882 2883 default: 2884 ret = -EINVAL; 2885 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", 2886 val & 0xffff); 2887 goto bail; 2888 } 2889 qib_set_ib_6120_lstate(ppd, lcmd, licmd); 2890 goto bail; 2891 2892 case QIB_IB_CFG_HRTBT: 2893 ret = -EINVAL; 2894 break; 2895 2896 default: 2897 ret = -EINVAL; 2898 } 2899 bail: 2900 return ret; 2901 } 2902 2903 static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what) 2904 { 2905 int ret = 0; 2906 2907 if (!strncmp(what, "ibc", 3)) { 2908 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback); 2909 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", 2910 ppd->dd->unit, ppd->port); 2911 } else if (!strncmp(what, "off", 3)) { 2912 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback); 2913 qib_devinfo(ppd->dd->pcidev, 2914 "Disabling IB%u:%u IBC loopback (normal)\n", 2915 ppd->dd->unit, ppd->port); 2916 } else 2917 ret = -EINVAL; 2918 if (!ret) { 2919 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl); 2920 qib_write_kreg(ppd->dd, kr_scratch, 0); 2921 } 2922 return ret; 2923 } 2924 2925 static void pma_6120_timer(unsigned long data) 2926 { 2927 struct qib_pportdata *ppd = (struct qib_pportdata *)data; 2928 struct qib_chip_specific *cs = ppd->dd->cspec; 2929 struct qib_ibport *ibp = &ppd->ibport_data; 2930 unsigned long flags; 2931 2932 spin_lock_irqsave(&ibp->rvp.lock, flags); 2933 if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED) { 2934 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING; 2935 qib_snapshot_counters(ppd, &cs->sword, &cs->rword, 2936 &cs->spkts, &cs->rpkts, &cs->xmit_wait); 2937 mod_timer(&cs->pma_timer, 2938 jiffies + usecs_to_jiffies(ibp->rvp.pma_sample_interval)); 2939 } else if (cs->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) { 2940 u64 ta, tb, tc, td, te; 2941 2942 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE; 2943 qib_snapshot_counters(ppd, &ta, &tb, &tc, &td, &te); 2944 2945 cs->sword = ta - cs->sword; 2946 cs->rword = tb - cs->rword; 2947 cs->spkts = tc - cs->spkts; 2948 cs->rpkts = td - cs->rpkts; 2949 cs->xmit_wait = te - cs->xmit_wait; 2950 } 2951 spin_unlock_irqrestore(&ibp->rvp.lock, flags); 2952 } 2953 2954 /* 2955 * Note that the caller has the ibp->rvp.lock held. 2956 */ 2957 static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv, 2958 u32 start) 2959 { 2960 struct qib_chip_specific *cs = ppd->dd->cspec; 2961 2962 if (start && intv) { 2963 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_STARTED; 2964 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(start)); 2965 } else if (intv) { 2966 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING; 2967 qib_snapshot_counters(ppd, &cs->sword, &cs->rword, 2968 &cs->spkts, &cs->rpkts, &cs->xmit_wait); 2969 mod_timer(&cs->pma_timer, jiffies + usecs_to_jiffies(intv)); 2970 } else { 2971 cs->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE; 2972 cs->sword = 0; 2973 cs->rword = 0; 2974 cs->spkts = 0; 2975 cs->rpkts = 0; 2976 cs->xmit_wait = 0; 2977 } 2978 } 2979 2980 static u32 qib_6120_iblink_state(u64 ibcs) 2981 { 2982 u32 state = (u32)SYM_FIELD(ibcs, IBCStatus, LinkState); 2983 2984 switch (state) { 2985 case IB_6120_L_STATE_INIT: 2986 state = IB_PORT_INIT; 2987 break; 2988 case IB_6120_L_STATE_ARM: 2989 state = IB_PORT_ARMED; 2990 break; 2991 case IB_6120_L_STATE_ACTIVE: 2992 /* fall through */ 2993 case IB_6120_L_STATE_ACT_DEFER: 2994 state = IB_PORT_ACTIVE; 2995 break; 2996 default: /* fall through */ 2997 case IB_6120_L_STATE_DOWN: 2998 state = IB_PORT_DOWN; 2999 break; 3000 } 3001 return state; 3002 } 3003 3004 /* returns the IBTA port state, rather than the IBC link training state */ 3005 static u8 qib_6120_phys_portstate(u64 ibcs) 3006 { 3007 u8 state = (u8)SYM_FIELD(ibcs, IBCStatus, LinkTrainingState); 3008 return qib_6120_physportstate[state]; 3009 } 3010 3011 static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) 3012 { 3013 unsigned long flags; 3014 3015 spin_lock_irqsave(&ppd->lflags_lock, flags); 3016 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; 3017 spin_unlock_irqrestore(&ppd->lflags_lock, flags); 3018 3019 if (ibup) { 3020 if (ppd->dd->cspec->ibdeltainprog) { 3021 ppd->dd->cspec->ibdeltainprog = 0; 3022 ppd->dd->cspec->ibsymdelta += 3023 read_6120_creg32(ppd->dd, cr_ibsymbolerr) - 3024 ppd->dd->cspec->ibsymsnap; 3025 ppd->dd->cspec->iblnkerrdelta += 3026 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) - 3027 ppd->dd->cspec->iblnkerrsnap; 3028 } 3029 qib_hol_init(ppd); 3030 } else { 3031 ppd->dd->cspec->lli_counter = 0; 3032 if (!ppd->dd->cspec->ibdeltainprog) { 3033 ppd->dd->cspec->ibdeltainprog = 1; 3034 ppd->dd->cspec->ibsymsnap = 3035 read_6120_creg32(ppd->dd, cr_ibsymbolerr); 3036 ppd->dd->cspec->iblnkerrsnap = 3037 read_6120_creg32(ppd->dd, cr_iblinkerrrecov); 3038 } 3039 qib_hol_down(ppd); 3040 } 3041 3042 qib_6120_setup_setextled(ppd, ibup); 3043 3044 return 0; 3045 } 3046 3047 /* Does read/modify/write to appropriate registers to 3048 * set output and direction bits selected by mask. 3049 * these are in their canonical postions (e.g. lsb of 3050 * dir will end up in D48 of extctrl on existing chips). 3051 * returns contents of GP Inputs. 3052 */ 3053 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) 3054 { 3055 u64 read_val, new_out; 3056 unsigned long flags; 3057 3058 if (mask) { 3059 /* some bits being written, lock access to GPIO */ 3060 dir &= mask; 3061 out &= mask; 3062 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); 3063 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); 3064 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); 3065 new_out = (dd->cspec->gpio_out & ~mask) | out; 3066 3067 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); 3068 qib_write_kreg(dd, kr_gpio_out, new_out); 3069 dd->cspec->gpio_out = new_out; 3070 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); 3071 } 3072 /* 3073 * It is unlikely that a read at this time would get valid 3074 * data on a pin whose direction line was set in the same 3075 * call to this function. We include the read here because 3076 * that allows us to potentially combine a change on one pin with 3077 * a read on another, and because the old code did something like 3078 * this. 3079 */ 3080 read_val = qib_read_kreg64(dd, kr_extstatus); 3081 return SYM_FIELD(read_val, EXTStatus, GPIOIn); 3082 } 3083 3084 /* 3085 * Read fundamental info we need to use the chip. These are 3086 * the registers that describe chip capabilities, and are 3087 * saved in shadow registers. 3088 */ 3089 static void get_6120_chip_params(struct qib_devdata *dd) 3090 { 3091 u64 val; 3092 u32 piobufs; 3093 int mtu; 3094 3095 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); 3096 3097 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); 3098 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); 3099 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); 3100 dd->palign = qib_read_kreg32(dd, kr_palign); 3101 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); 3102 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; 3103 3104 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); 3105 3106 val = qib_read_kreg64(dd, kr_sendpiosize); 3107 dd->piosize2k = val & ~0U; 3108 dd->piosize4k = val >> 32; 3109 3110 mtu = ib_mtu_enum_to_int(qib_ibmtu); 3111 if (mtu == -1) 3112 mtu = QIB_DEFAULT_MTU; 3113 dd->pport->ibmtu = (u32)mtu; 3114 3115 val = qib_read_kreg64(dd, kr_sendpiobufcnt); 3116 dd->piobcnt2k = val & ~0U; 3117 dd->piobcnt4k = val >> 32; 3118 dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1; 3119 /* these may be adjusted in init_chip_wc_pat() */ 3120 dd->pio2kbase = (u32 __iomem *) 3121 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase); 3122 if (dd->piobcnt4k) { 3123 dd->pio4kbase = (u32 __iomem *) 3124 (((char __iomem *) dd->kregbase) + 3125 (dd->piobufbase >> 32)); 3126 /* 3127 * 4K buffers take 2 pages; we use roundup just to be 3128 * paranoid; we calculate it once here, rather than on 3129 * ever buf allocate 3130 */ 3131 dd->align4k = ALIGN(dd->piosize4k, dd->palign); 3132 } 3133 3134 piobufs = dd->piobcnt4k + dd->piobcnt2k; 3135 3136 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / 3137 (sizeof(u64) * BITS_PER_BYTE / 2); 3138 } 3139 3140 /* 3141 * The chip base addresses in cspec and cpspec have to be set 3142 * after possible init_chip_wc_pat(), rather than in 3143 * get_6120_chip_params(), so split out as separate function 3144 */ 3145 static void set_6120_baseaddrs(struct qib_devdata *dd) 3146 { 3147 u32 cregbase; 3148 3149 cregbase = qib_read_kreg32(dd, kr_counterregbase); 3150 dd->cspec->cregbase = (u64 __iomem *) 3151 ((char __iomem *) dd->kregbase + cregbase); 3152 3153 dd->egrtidbase = (u64 __iomem *) 3154 ((char __iomem *) dd->kregbase + dd->rcvegrbase); 3155 } 3156 3157 /* 3158 * Write the final few registers that depend on some of the 3159 * init setup. Done late in init, just before bringing up 3160 * the serdes. 3161 */ 3162 static int qib_late_6120_initreg(struct qib_devdata *dd) 3163 { 3164 int ret = 0; 3165 u64 val; 3166 3167 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); 3168 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); 3169 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); 3170 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); 3171 val = qib_read_kreg64(dd, kr_sendpioavailaddr); 3172 if (val != dd->pioavailregs_phys) { 3173 qib_dev_err(dd, 3174 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n", 3175 (unsigned long) dd->pioavailregs_phys, 3176 (unsigned long long) val); 3177 ret = -EINVAL; 3178 } 3179 return ret; 3180 } 3181 3182 static int init_6120_variables(struct qib_devdata *dd) 3183 { 3184 int ret = 0; 3185 struct qib_pportdata *ppd; 3186 u32 sbufs; 3187 3188 ppd = (struct qib_pportdata *)(dd + 1); 3189 dd->pport = ppd; 3190 dd->num_pports = 1; 3191 3192 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports); 3193 ppd->cpspec = NULL; /* not used in this chip */ 3194 3195 spin_lock_init(&dd->cspec->kernel_tid_lock); 3196 spin_lock_init(&dd->cspec->user_tid_lock); 3197 spin_lock_init(&dd->cspec->rcvmod_lock); 3198 spin_lock_init(&dd->cspec->gpio_lock); 3199 3200 /* we haven't yet set QIB_PRESENT, so use read directly */ 3201 dd->revision = readq(&dd->kregbase[kr_revision]); 3202 3203 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { 3204 qib_dev_err(dd, 3205 "Revision register read failure, giving up initialization\n"); 3206 ret = -ENODEV; 3207 goto bail; 3208 } 3209 dd->flags |= QIB_PRESENT; /* now register routines work */ 3210 3211 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, 3212 ChipRevMajor); 3213 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, 3214 ChipRevMinor); 3215 3216 get_6120_chip_params(dd); 3217 pe_boardname(dd); /* fill in boardname */ 3218 3219 /* 3220 * GPIO bits for TWSI data and clock, 3221 * used for serial EEPROM. 3222 */ 3223 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; 3224 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; 3225 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV; 3226 3227 if (qib_unordered_wc()) 3228 dd->flags |= QIB_PIO_FLUSH_WC; 3229 3230 /* 3231 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity. 3232 * 2 is Some Misc, 3 is reserved for future. 3233 */ 3234 dd->eep_st_masks[0].hwerrs_to_log = HWE_MASK(TXEMemParityErr); 3235 3236 /* Ignore errors in PIO/PBC on systems with unordered write-combining */ 3237 if (qib_unordered_wc()) 3238 dd->eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY; 3239 3240 dd->eep_st_masks[1].hwerrs_to_log = HWE_MASK(RXEMemParityErr); 3241 3242 dd->eep_st_masks[2].errs_to_log = ERR_MASK(ResetNegated); 3243 3244 ret = qib_init_pportdata(ppd, dd, 0, 1); 3245 if (ret) 3246 goto bail; 3247 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; 3248 ppd->link_speed_supported = QIB_IB_SDR; 3249 ppd->link_width_enabled = IB_WIDTH_4X; 3250 ppd->link_speed_enabled = ppd->link_speed_supported; 3251 /* these can't change for this chip, so set once */ 3252 ppd->link_width_active = ppd->link_width_enabled; 3253 ppd->link_speed_active = ppd->link_speed_enabled; 3254 ppd->vls_supported = IB_VL_VL0; 3255 ppd->vls_operational = ppd->vls_supported; 3256 3257 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE; 3258 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE; 3259 dd->rhf_offset = 0; 3260 3261 /* we always allocate at least 2048 bytes for eager buffers */ 3262 ret = ib_mtu_enum_to_int(qib_ibmtu); 3263 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU; 3264 BUG_ON(!is_power_of_2(dd->rcvegrbufsize)); 3265 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); 3266 3267 qib_6120_tidtemplate(dd); 3268 3269 /* 3270 * We can request a receive interrupt for 1 or 3271 * more packets from current offset. For now, we set this 3272 * up for a single packet. 3273 */ 3274 dd->rhdrhead_intr_off = 1ULL << 32; 3275 3276 /* setup the stats timer; the add_timer is done at end of init */ 3277 setup_timer(&dd->stats_timer, qib_get_6120_faststats, 3278 (unsigned long)dd); 3279 3280 setup_timer(&dd->cspec->pma_timer, pma_6120_timer, 3281 (unsigned long)ppd); 3282 3283 dd->ureg_align = qib_read_kreg32(dd, kr_palign); 3284 3285 dd->piosize2kmax_dwords = dd->piosize2k >> 2; 3286 qib_6120_config_ctxts(dd); 3287 qib_set_ctxtcnt(dd); 3288 3289 ret = init_chip_wc_pat(dd, 0); 3290 if (ret) 3291 goto bail; 3292 set_6120_baseaddrs(dd); /* set chip access pointers now */ 3293 3294 ret = 0; 3295 if (qib_mini_init) 3296 goto bail; 3297 3298 qib_num_cfg_vls = 1; /* if any 6120's, only one VL */ 3299 3300 ret = qib_create_ctxts(dd); 3301 init_6120_cntrnames(dd); 3302 3303 /* use all of 4KB buffers for the kernel, otherwise 16 */ 3304 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16; 3305 3306 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs; 3307 dd->pbufsctxt = dd->lastctxt_piobuf / 3308 (dd->cfgctxts - dd->first_user_ctxt); 3309 3310 if (ret) 3311 goto bail; 3312 bail: 3313 return ret; 3314 } 3315 3316 /* 3317 * For this chip, we want to use the same buffer every time 3318 * when we are trying to bring the link up (they are always VL15 3319 * packets). At that link state the packet should always go out immediately 3320 * (or at least be discarded at the tx interface if the link is down). 3321 * If it doesn't, and the buffer isn't available, that means some other 3322 * sender has gotten ahead of us, and is preventing our packet from going 3323 * out. In that case, we flush all packets, and try again. If that still 3324 * fails, we fail the request, and hope things work the next time around. 3325 * 3326 * We don't need very complicated heuristics on whether the packet had 3327 * time to go out or not, since even at SDR 1X, it goes out in very short 3328 * time periods, covered by the chip reads done here and as part of the 3329 * flush. 3330 */ 3331 static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum) 3332 { 3333 u32 __iomem *buf; 3334 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1; 3335 3336 /* 3337 * always blip to get avail list updated, since it's almost 3338 * always needed, and is fairly cheap. 3339 */ 3340 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 3341 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */ 3342 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf); 3343 if (buf) 3344 goto done; 3345 3346 sendctrl_6120_mod(ppd, QIB_SENDCTRL_DISARM_ALL | QIB_SENDCTRL_FLUSH | 3347 QIB_SENDCTRL_AVAIL_BLIP); 3348 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */ 3349 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */ 3350 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf); 3351 done: 3352 return buf; 3353 } 3354 3355 static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc, 3356 u32 *pbufnum) 3357 { 3358 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK; 3359 struct qib_devdata *dd = ppd->dd; 3360 u32 __iomem *buf; 3361 3362 if (((pbc >> 32) & PBC_6120_VL15_SEND_CTRL) && 3363 !(ppd->lflags & (QIBL_IB_AUTONEG_INPROG | QIBL_LINKACTIVE))) 3364 buf = get_6120_link_buf(ppd, pbufnum); 3365 else { 3366 3367 if ((plen + 1) > dd->piosize2kmax_dwords) 3368 first = dd->piobcnt2k; 3369 else 3370 first = 0; 3371 /* try 4k if all 2k busy, so same last for both sizes */ 3372 last = dd->piobcnt2k + dd->piobcnt4k - 1; 3373 buf = qib_getsendbuf_range(dd, pbufnum, first, last); 3374 } 3375 return buf; 3376 } 3377 3378 static int init_sdma_6120_regs(struct qib_pportdata *ppd) 3379 { 3380 return -ENODEV; 3381 } 3382 3383 static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd) 3384 { 3385 return 0; 3386 } 3387 3388 static int qib_sdma_6120_busy(struct qib_pportdata *ppd) 3389 { 3390 return 0; 3391 } 3392 3393 static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail) 3394 { 3395 } 3396 3397 static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) 3398 { 3399 } 3400 3401 static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) 3402 { 3403 } 3404 3405 /* 3406 * the pbc doesn't need a VL15 indicator, but we need it for link_buf. 3407 * The chip ignores the bit if set. 3408 */ 3409 static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen, 3410 u8 srate, u8 vl) 3411 { 3412 return vl == 15 ? PBC_6120_VL15_SEND_CTRL : 0; 3413 } 3414 3415 static void qib_6120_initvl15_bufs(struct qib_devdata *dd) 3416 { 3417 } 3418 3419 static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd) 3420 { 3421 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt; 3422 rcd->rcvegr_tid_base = rcd->ctxt * rcd->rcvegrcnt; 3423 } 3424 3425 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start, 3426 u32 len, u32 avail, struct qib_ctxtdata *rcd) 3427 { 3428 } 3429 3430 static void writescratch(struct qib_devdata *dd, u32 val) 3431 { 3432 (void) qib_write_kreg(dd, kr_scratch, val); 3433 } 3434 3435 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum) 3436 { 3437 return -ENXIO; 3438 } 3439 3440 #ifdef CONFIG_INFINIBAND_QIB_DCA 3441 static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event) 3442 { 3443 return 0; 3444 } 3445 #endif 3446 3447 /* Dummy function, as 6120 boards never disable EEPROM Write */ 3448 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen) 3449 { 3450 return 1; 3451 } 3452 3453 /** 3454 * qib_init_iba6120_funcs - set up the chip-specific function pointers 3455 * @pdev: pci_dev of the qlogic_ib device 3456 * @ent: pci_device_id matching this chip 3457 * 3458 * This is global, and is called directly at init to set up the 3459 * chip-specific function pointers for later use. 3460 * 3461 * It also allocates/partially-inits the qib_devdata struct for 3462 * this device. 3463 */ 3464 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev, 3465 const struct pci_device_id *ent) 3466 { 3467 struct qib_devdata *dd; 3468 int ret; 3469 3470 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) + 3471 sizeof(struct qib_chip_specific)); 3472 if (IS_ERR(dd)) 3473 goto bail; 3474 3475 dd->f_bringup_serdes = qib_6120_bringup_serdes; 3476 dd->f_cleanup = qib_6120_setup_cleanup; 3477 dd->f_clear_tids = qib_6120_clear_tids; 3478 dd->f_free_irq = qib_free_irq; 3479 dd->f_get_base_info = qib_6120_get_base_info; 3480 dd->f_get_msgheader = qib_6120_get_msgheader; 3481 dd->f_getsendbuf = qib_6120_getsendbuf; 3482 dd->f_gpio_mod = gpio_6120_mod; 3483 dd->f_eeprom_wen = qib_6120_eeprom_wen; 3484 dd->f_hdrqempty = qib_6120_hdrqempty; 3485 dd->f_ib_updown = qib_6120_ib_updown; 3486 dd->f_init_ctxt = qib_6120_init_ctxt; 3487 dd->f_initvl15_bufs = qib_6120_initvl15_bufs; 3488 dd->f_intr_fallback = qib_6120_nointr_fallback; 3489 dd->f_late_initreg = qib_late_6120_initreg; 3490 dd->f_setpbc_control = qib_6120_setpbc_control; 3491 dd->f_portcntr = qib_portcntr_6120; 3492 dd->f_put_tid = (dd->minrev >= 2) ? 3493 qib_6120_put_tid_2 : 3494 qib_6120_put_tid; 3495 dd->f_quiet_serdes = qib_6120_quiet_serdes; 3496 dd->f_rcvctrl = rcvctrl_6120_mod; 3497 dd->f_read_cntrs = qib_read_6120cntrs; 3498 dd->f_read_portcntrs = qib_read_6120portcntrs; 3499 dd->f_reset = qib_6120_setup_reset; 3500 dd->f_init_sdma_regs = init_sdma_6120_regs; 3501 dd->f_sdma_busy = qib_sdma_6120_busy; 3502 dd->f_sdma_gethead = qib_sdma_6120_gethead; 3503 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl; 3504 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt; 3505 dd->f_sdma_update_tail = qib_sdma_update_6120_tail; 3506 dd->f_sendctrl = sendctrl_6120_mod; 3507 dd->f_set_armlaunch = qib_set_6120_armlaunch; 3508 dd->f_set_cntr_sample = qib_set_cntr_6120_sample; 3509 dd->f_iblink_state = qib_6120_iblink_state; 3510 dd->f_ibphys_portstate = qib_6120_phys_portstate; 3511 dd->f_get_ib_cfg = qib_6120_get_ib_cfg; 3512 dd->f_set_ib_cfg = qib_6120_set_ib_cfg; 3513 dd->f_set_ib_loopback = qib_6120_set_loopback; 3514 dd->f_set_intr_state = qib_6120_set_intr_state; 3515 dd->f_setextled = qib_6120_setup_setextled; 3516 dd->f_txchk_change = qib_6120_txchk_change; 3517 dd->f_update_usrhead = qib_update_6120_usrhead; 3518 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr; 3519 dd->f_xgxs_reset = qib_6120_xgxs_reset; 3520 dd->f_writescratch = writescratch; 3521 dd->f_tempsense_rd = qib_6120_tempsense_rd; 3522 #ifdef CONFIG_INFINIBAND_QIB_DCA 3523 dd->f_notify_dca = qib_6120_notify_dca; 3524 #endif 3525 /* 3526 * Do remaining pcie setup and save pcie values in dd. 3527 * Any error printing is already done by the init code. 3528 * On return, we have the chip mapped and accessible, 3529 * but chip registers are not set up until start of 3530 * init_6120_variables. 3531 */ 3532 ret = qib_pcie_ddinit(dd, pdev, ent); 3533 if (ret < 0) 3534 goto bail_free; 3535 3536 /* initialize chip-specific variables */ 3537 ret = init_6120_variables(dd); 3538 if (ret) 3539 goto bail_cleanup; 3540 3541 if (qib_mini_init) 3542 goto bail; 3543 3544 if (qib_pcie_params(dd, 8, NULL)) 3545 qib_dev_err(dd, 3546 "Failed to setup PCIe or interrupts; continuing anyway\n"); 3547 /* clear diagctrl register, in case diags were running and crashed */ 3548 qib_write_kreg(dd, kr_hwdiagctrl, 0); 3549 3550 if (qib_read_kreg64(dd, kr_hwerrstatus) & 3551 QLOGIC_IB_HWE_SERDESPLLFAILED) 3552 qib_write_kreg(dd, kr_hwerrclear, 3553 QLOGIC_IB_HWE_SERDESPLLFAILED); 3554 3555 /* setup interrupt handler (interrupt type handled above) */ 3556 qib_setup_6120_interrupt(dd); 3557 /* Note that qpn_mask is set by qib_6120_config_ctxts() first */ 3558 qib_6120_init_hwerrors(dd); 3559 3560 goto bail; 3561 3562 bail_cleanup: 3563 qib_pcie_ddcleanup(dd); 3564 bail_free: 3565 qib_free_devdata(dd); 3566 dd = ERR_PTR(ret); 3567 bail: 3568 return dd; 3569 } 3570