1 #ifndef _QIB_KERNEL_H 2 #define _QIB_KERNEL_H 3 /* 4 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved. 5 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. 6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 /* 38 * This header file is the base header file for qlogic_ib kernel code 39 * qib_user.h serves a similar purpose for user code. 40 */ 41 42 #include <linux/interrupt.h> 43 #include <linux/pci.h> 44 #include <linux/dma-mapping.h> 45 #include <linux/mutex.h> 46 #include <linux/list.h> 47 #include <linux/scatterlist.h> 48 #include <linux/slab.h> 49 #include <linux/io.h> 50 #include <linux/fs.h> 51 #include <linux/completion.h> 52 #include <linux/kref.h> 53 #include <linux/sched.h> 54 #include <linux/kthread.h> 55 56 #include "qib_common.h" 57 #include "qib_verbs.h" 58 59 /* only s/w major version of QLogic_IB we can handle */ 60 #define QIB_CHIP_VERS_MAJ 2U 61 62 /* don't care about this except printing */ 63 #define QIB_CHIP_VERS_MIN 0U 64 65 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 66 #define QIB_OUI 0x001175 67 #define QIB_OUI_LSB 40 68 69 /* 70 * per driver stats, either not device nor port-specific, or 71 * summed over all of the devices and ports. 72 * They are described by name via ipathfs filesystem, so layout 73 * and number of elements can change without breaking compatibility. 74 * If members are added or deleted qib_statnames[] in qib_fs.c must 75 * change to match. 76 */ 77 struct qlogic_ib_stats { 78 __u64 sps_ints; /* number of interrupts handled */ 79 __u64 sps_errints; /* number of error interrupts */ 80 __u64 sps_txerrs; /* tx-related packet errors */ 81 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 82 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 83 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 84 __u64 sps_ctxts; /* number of contexts currently open */ 85 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 86 __u64 sps_buffull; 87 __u64 sps_hdrfull; 88 }; 89 90 extern struct qlogic_ib_stats qib_stats; 91 extern const struct pci_error_handlers qib_pci_err_handler; 92 93 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ 94 /* 95 * First-cut critierion for "device is active" is 96 * two thousand dwords combined Tx, Rx traffic per 97 * 5-second interval. SMA packets are 64 dwords, 98 * and occur "a few per second", presumably each way. 99 */ 100 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000) 101 102 /* 103 * Struct used to indicate which errors are logged in each of the 104 * error-counters that are logged to EEPROM. A counter is incremented 105 * _once_ (saturating at 255) for each event with any bits set in 106 * the error or hwerror register masks below. 107 */ 108 #define QIB_EEP_LOG_CNT (4) 109 struct qib_eep_log_mask { 110 u64 errs_to_log; 111 u64 hwerrs_to_log; 112 }; 113 114 /* 115 * Below contains all data related to a single context (formerly called port). 116 */ 117 118 #ifdef CONFIG_DEBUG_FS 119 struct qib_opcode_stats_perctx; 120 #endif 121 122 struct qib_ctxtdata { 123 void **rcvegrbuf; 124 dma_addr_t *rcvegrbuf_phys; 125 /* rcvhdrq base, needs mmap before useful */ 126 void *rcvhdrq; 127 /* kernel virtual address where hdrqtail is updated */ 128 void *rcvhdrtail_kvaddr; 129 /* 130 * temp buffer for expected send setup, allocated at open, instead 131 * of each setup call 132 */ 133 void *tid_pg_list; 134 /* 135 * Shared page for kernel to signal user processes that send buffers 136 * need disarming. The process should call QIB_CMD_DISARM_BUFS 137 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 138 */ 139 unsigned long *user_event_mask; 140 /* when waiting for rcv or pioavail */ 141 wait_queue_head_t wait; 142 /* 143 * rcvegr bufs base, physical, must fit 144 * in 44 bits so 32 bit programs mmap64 44 bit works) 145 */ 146 dma_addr_t rcvegr_phys; 147 /* mmap of hdrq, must fit in 44 bits */ 148 dma_addr_t rcvhdrq_phys; 149 dma_addr_t rcvhdrqtailaddr_phys; 150 151 /* 152 * number of opens (including slave sub-contexts) on this instance 153 * (ignoring forks, dup, etc. for now) 154 */ 155 int cnt; 156 /* 157 * how much space to leave at start of eager TID entries for 158 * protocol use, on each TID 159 */ 160 /* instead of calculating it */ 161 unsigned ctxt; 162 /* local node of context */ 163 int node_id; 164 /* non-zero if ctxt is being shared. */ 165 u16 subctxt_cnt; 166 /* non-zero if ctxt is being shared. */ 167 u16 subctxt_id; 168 /* number of eager TID entries. */ 169 u16 rcvegrcnt; 170 /* index of first eager TID entry. */ 171 u16 rcvegr_tid_base; 172 /* number of pio bufs for this ctxt (all procs, if shared) */ 173 u32 piocnt; 174 /* first pio buffer for this ctxt */ 175 u32 pio_base; 176 /* chip offset of PIO buffers for this ctxt */ 177 u32 piobufs; 178 /* how many alloc_pages() chunks in rcvegrbuf_pages */ 179 u32 rcvegrbuf_chunks; 180 /* how many egrbufs per chunk */ 181 u16 rcvegrbufs_perchunk; 182 /* ilog2 of above */ 183 u16 rcvegrbufs_perchunk_shift; 184 /* order for rcvegrbuf_pages */ 185 size_t rcvegrbuf_size; 186 /* rcvhdrq size (for freeing) */ 187 size_t rcvhdrq_size; 188 /* per-context flags for fileops/intr communication */ 189 unsigned long flag; 190 /* next expected TID to check when looking for free */ 191 u32 tidcursor; 192 /* WAIT_RCV that timed out, no interrupt */ 193 u32 rcvwait_to; 194 /* WAIT_PIO that timed out, no interrupt */ 195 u32 piowait_to; 196 /* WAIT_RCV already happened, no wait */ 197 u32 rcvnowait; 198 /* WAIT_PIO already happened, no wait */ 199 u32 pionowait; 200 /* total number of polled urgent packets */ 201 u32 urgent; 202 /* saved total number of polled urgent packets for poll edge trigger */ 203 u32 urgent_poll; 204 /* pid of process using this ctxt */ 205 pid_t pid; 206 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT]; 207 /* same size as task_struct .comm[], command that opened context */ 208 char comm[16]; 209 /* pkeys set by this use of this ctxt */ 210 u16 pkeys[4]; 211 /* so file ops can get at unit */ 212 struct qib_devdata *dd; 213 /* so funcs that need physical port can get it easily */ 214 struct qib_pportdata *ppd; 215 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 216 void *subctxt_uregbase; 217 /* An array of pages for the eager receive buffers * N */ 218 void *subctxt_rcvegrbuf; 219 /* An array of pages for the eager header queue entries * N */ 220 void *subctxt_rcvhdr_base; 221 /* The version of the library which opened this ctxt */ 222 u32 userversion; 223 /* Bitmask of active slaves */ 224 u32 active_slaves; 225 /* Type of packets or conditions we want to poll for */ 226 u16 poll_type; 227 /* receive packet sequence counter */ 228 u8 seq_cnt; 229 u8 redirect_seq_cnt; 230 /* ctxt rcvhdrq head offset */ 231 u32 head; 232 /* lookaside fields */ 233 struct qib_qp *lookaside_qp; 234 u32 lookaside_qpn; 235 /* QPs waiting for context processing */ 236 struct list_head qp_wait_list; 237 #ifdef CONFIG_DEBUG_FS 238 /* verbs stats per CTX */ 239 struct qib_opcode_stats_perctx *opstats; 240 #endif 241 }; 242 243 struct qib_sge_state; 244 245 struct qib_sdma_txreq { 246 int flags; 247 int sg_count; 248 dma_addr_t addr; 249 void (*callback)(struct qib_sdma_txreq *, int); 250 u16 start_idx; /* sdma private */ 251 u16 next_descq_idx; /* sdma private */ 252 struct list_head list; /* sdma private */ 253 }; 254 255 struct qib_sdma_desc { 256 __le64 qw[2]; 257 }; 258 259 struct qib_verbs_txreq { 260 struct qib_sdma_txreq txreq; 261 struct qib_qp *qp; 262 struct qib_swqe *wqe; 263 u32 dwords; 264 u16 hdr_dwords; 265 u16 hdr_inx; 266 struct qib_pio_header *align_buf; 267 struct qib_mregion *mr; 268 struct qib_sge_state *ss; 269 }; 270 271 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1 272 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2 273 #define QIB_SDMA_TXREQ_F_INTREQ 0x4 274 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8 275 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10 276 277 #define QIB_SDMA_TXREQ_S_OK 0 278 #define QIB_SDMA_TXREQ_S_SENDERROR 1 279 #define QIB_SDMA_TXREQ_S_ABORTED 2 280 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3 281 282 /* 283 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 284 * Mostly for MADs that set or query link parameters, also ipath 285 * config interfaces 286 */ 287 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 288 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 289 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */ 290 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 291 #define QIB_IB_CFG_SPD 5 /* current Link spd */ 292 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 293 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 294 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 295 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 296 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */ 297 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 298 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 299 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 300 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 301 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 302 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */ 303 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */ 304 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */ 305 #define QIB_IB_CFG_VL_HIGH_LIMIT 19 306 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 307 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */ 308 309 /* 310 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16 311 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for 312 * QIB_IB_CFG_LINKDEFAULT cmd 313 */ 314 #define IB_LINKCMD_DOWN (0 << 16) 315 #define IB_LINKCMD_ARMED (1 << 16) 316 #define IB_LINKCMD_ACTIVE (2 << 16) 317 #define IB_LINKINITCMD_NOP 0 318 #define IB_LINKINITCMD_POLL 1 319 #define IB_LINKINITCMD_SLEEP 2 320 #define IB_LINKINITCMD_DISABLE 3 321 322 /* 323 * valid states passed to qib_set_linkstate() user call 324 */ 325 #define QIB_IB_LINKDOWN 0 326 #define QIB_IB_LINKARM 1 327 #define QIB_IB_LINKACTIVE 2 328 #define QIB_IB_LINKDOWN_ONLY 3 329 #define QIB_IB_LINKDOWN_SLEEP 4 330 #define QIB_IB_LINKDOWN_DISABLE 5 331 332 /* 333 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed 334 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg 335 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They 336 * are also the the possible values for qib_link_speed_enabled and active 337 * The values were chosen to match values used within the IB spec. 338 */ 339 #define QIB_IB_SDR 1 340 #define QIB_IB_DDR 2 341 #define QIB_IB_QDR 4 342 343 #define QIB_DEFAULT_MTU 4096 344 345 /* max number of IB ports supported per HCA */ 346 #define QIB_MAX_IB_PORTS 2 347 348 /* 349 * Possible IB config parameters for f_get/set_ib_table() 350 */ 351 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */ 352 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */ 353 354 /* 355 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 356 * these are bits so they can be combined, e.g. 357 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB 358 */ 359 #define QIB_RCVCTRL_TAILUPD_ENB 0x01 360 #define QIB_RCVCTRL_TAILUPD_DIS 0x02 361 #define QIB_RCVCTRL_CTXT_ENB 0x04 362 #define QIB_RCVCTRL_CTXT_DIS 0x08 363 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10 364 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20 365 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 366 #define QIB_RCVCTRL_PKEY_DIS 0x80 367 #define QIB_RCVCTRL_BP_ENB 0x0100 368 #define QIB_RCVCTRL_BP_DIS 0x0200 369 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400 370 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800 371 372 /* 373 * Possible "operations" for f_sendctrl(ppd, op, var) 374 * these are bits so they can be combined, e.g. 375 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB 376 * Some operations (e.g. DISARM, ABORT) are known to 377 * be "one-shot", so do not modify shadow. 378 */ 379 #define QIB_SENDCTRL_DISARM (0x1000) 380 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM) 381 /* available (0x2000) */ 382 #define QIB_SENDCTRL_AVAIL_DIS (0x4000) 383 #define QIB_SENDCTRL_AVAIL_ENB (0x8000) 384 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000) 385 #define QIB_SENDCTRL_SEND_DIS (0x20000) 386 #define QIB_SENDCTRL_SEND_ENB (0x40000) 387 #define QIB_SENDCTRL_FLUSH (0x80000) 388 #define QIB_SENDCTRL_CLEAR (0x100000) 389 #define QIB_SENDCTRL_DISARM_ALL (0x200000) 390 391 /* 392 * These are the generic indices for requesting per-port 393 * counter values via the f_portcntr function. They 394 * are always returned as 64 bit values, although most 395 * are 32 bit counters. 396 */ 397 /* send-related counters */ 398 #define QIBPORTCNTR_PKTSEND 0U 399 #define QIBPORTCNTR_WORDSEND 1U 400 #define QIBPORTCNTR_PSXMITDATA 2U 401 #define QIBPORTCNTR_PSXMITPKTS 3U 402 #define QIBPORTCNTR_PSXMITWAIT 4U 403 #define QIBPORTCNTR_SENDSTALL 5U 404 /* receive-related counters */ 405 #define QIBPORTCNTR_PKTRCV 6U 406 #define QIBPORTCNTR_PSRCVDATA 7U 407 #define QIBPORTCNTR_PSRCVPKTS 8U 408 #define QIBPORTCNTR_RCVEBP 9U 409 #define QIBPORTCNTR_RCVOVFL 10U 410 #define QIBPORTCNTR_WORDRCV 11U 411 /* IB link related error counters */ 412 #define QIBPORTCNTR_RXLOCALPHYERR 12U 413 #define QIBPORTCNTR_RXVLERR 13U 414 #define QIBPORTCNTR_ERRICRC 14U 415 #define QIBPORTCNTR_ERRVCRC 15U 416 #define QIBPORTCNTR_ERRLPCRC 16U 417 #define QIBPORTCNTR_BADFORMAT 17U 418 #define QIBPORTCNTR_ERR_RLEN 18U 419 #define QIBPORTCNTR_IBSYMBOLERR 19U 420 #define QIBPORTCNTR_INVALIDRLEN 20U 421 #define QIBPORTCNTR_UNSUPVL 21U 422 #define QIBPORTCNTR_EXCESSBUFOVFL 22U 423 #define QIBPORTCNTR_ERRLINK 23U 424 #define QIBPORTCNTR_IBLINKDOWN 24U 425 #define QIBPORTCNTR_IBLINKERRRECOV 25U 426 #define QIBPORTCNTR_LLI 26U 427 /* other error counters */ 428 #define QIBPORTCNTR_RXDROPPKT 27U 429 #define QIBPORTCNTR_VL15PKTDROP 28U 430 #define QIBPORTCNTR_ERRPKEY 29U 431 #define QIBPORTCNTR_KHDROVFL 30U 432 /* sampling counters (these are actually control registers) */ 433 #define QIBPORTCNTR_PSINTERVAL 31U 434 #define QIBPORTCNTR_PSSTART 32U 435 #define QIBPORTCNTR_PSSTAT 33U 436 437 /* how often we check for packet activity for "power on hours (in seconds) */ 438 #define ACTIVITY_TIMER 5 439 440 #define MAX_NAME_SIZE 64 441 442 #ifdef CONFIG_INFINIBAND_QIB_DCA 443 struct qib_irq_notify; 444 #endif 445 446 struct qib_msix_entry { 447 struct msix_entry msix; 448 void *arg; 449 #ifdef CONFIG_INFINIBAND_QIB_DCA 450 int dca; 451 int rcv; 452 struct qib_irq_notify *notifier; 453 #endif 454 char name[MAX_NAME_SIZE]; 455 cpumask_var_t mask; 456 }; 457 458 /* Below is an opaque struct. Each chip (device) can maintain 459 * private data needed for its operation, but not germane to the 460 * rest of the driver. For convenience, we define another that 461 * is chip-specific, per-port 462 */ 463 struct qib_chip_specific; 464 struct qib_chipport_specific; 465 466 enum qib_sdma_states { 467 qib_sdma_state_s00_hw_down, 468 qib_sdma_state_s10_hw_start_up_wait, 469 qib_sdma_state_s20_idle, 470 qib_sdma_state_s30_sw_clean_up_wait, 471 qib_sdma_state_s40_hw_clean_up_wait, 472 qib_sdma_state_s50_hw_halt_wait, 473 qib_sdma_state_s99_running, 474 }; 475 476 enum qib_sdma_events { 477 qib_sdma_event_e00_go_hw_down, 478 qib_sdma_event_e10_go_hw_start, 479 qib_sdma_event_e20_hw_started, 480 qib_sdma_event_e30_go_running, 481 qib_sdma_event_e40_sw_cleaned, 482 qib_sdma_event_e50_hw_cleaned, 483 qib_sdma_event_e60_hw_halted, 484 qib_sdma_event_e70_go_idle, 485 qib_sdma_event_e7220_err_halted, 486 qib_sdma_event_e7322_err_halted, 487 qib_sdma_event_e90_timer_tick, 488 }; 489 490 extern char *qib_sdma_state_names[]; 491 extern char *qib_sdma_event_names[]; 492 493 struct sdma_set_state_action { 494 unsigned op_enable:1; 495 unsigned op_intenable:1; 496 unsigned op_halt:1; 497 unsigned op_drain:1; 498 unsigned go_s99_running_tofalse:1; 499 unsigned go_s99_running_totrue:1; 500 }; 501 502 struct qib_sdma_state { 503 struct kref kref; 504 struct completion comp; 505 enum qib_sdma_states current_state; 506 struct sdma_set_state_action *set_state_action; 507 unsigned current_op; 508 unsigned go_s99_running; 509 unsigned first_sendbuf; 510 unsigned last_sendbuf; /* really last +1 */ 511 /* debugging/devel */ 512 enum qib_sdma_states previous_state; 513 unsigned previous_op; 514 enum qib_sdma_events last_event; 515 }; 516 517 struct xmit_wait { 518 struct timer_list timer; 519 u64 counter; 520 u8 flags; 521 struct cache { 522 u64 psxmitdata; 523 u64 psrcvdata; 524 u64 psxmitpkts; 525 u64 psrcvpkts; 526 u64 psxmitwait; 527 } counter_cache; 528 }; 529 530 /* 531 * The structure below encapsulates data relevant to a physical IB Port. 532 * Current chips support only one such port, but the separation 533 * clarifies things a bit. Note that to conform to IB conventions, 534 * port-numbers are one-based. The first or only port is port1. 535 */ 536 struct qib_pportdata { 537 struct qib_ibport ibport_data; 538 539 struct qib_devdata *dd; 540 struct qib_chippport_specific *cpspec; /* chip-specific per-port */ 541 struct kobject pport_kobj; 542 struct kobject pport_cc_kobj; 543 struct kobject sl2vl_kobj; 544 struct kobject diagc_kobj; 545 546 /* GUID for this interface, in network order */ 547 __be64 guid; 548 549 /* QIB_POLL, etc. link-state specific flags, per port */ 550 u32 lflags; 551 /* qib_lflags driver is waiting for */ 552 u32 state_wanted; 553 spinlock_t lflags_lock; 554 555 /* ref count for each pkey */ 556 atomic_t pkeyrefs[4]; 557 558 /* 559 * this address is mapped readonly into user processes so they can 560 * get status cheaply, whenever they want. One qword of status per port 561 */ 562 u64 *statusp; 563 564 /* SendDMA related entries */ 565 566 /* read mostly */ 567 struct qib_sdma_desc *sdma_descq; 568 struct workqueue_struct *qib_wq; 569 struct qib_sdma_state sdma_state; 570 dma_addr_t sdma_descq_phys; 571 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */ 572 dma_addr_t sdma_head_phys; 573 u16 sdma_descq_cnt; 574 575 /* read/write using lock */ 576 spinlock_t sdma_lock ____cacheline_aligned_in_smp; 577 struct list_head sdma_activelist; 578 struct list_head sdma_userpending; 579 u64 sdma_descq_added; 580 u64 sdma_descq_removed; 581 u16 sdma_descq_tail; 582 u16 sdma_descq_head; 583 u8 sdma_generation; 584 u8 sdma_intrequest; 585 586 struct tasklet_struct sdma_sw_clean_up_task 587 ____cacheline_aligned_in_smp; 588 589 wait_queue_head_t state_wait; /* for state_wanted */ 590 591 /* HoL blocking for SMP replies */ 592 unsigned hol_state; 593 struct timer_list hol_timer; 594 595 /* 596 * Shadow copies of registers; size indicates read access size. 597 * Most of them are readonly, but some are write-only register, 598 * where we manipulate the bits in the shadow copy, and then write 599 * the shadow copy to qlogic_ib. 600 * 601 * We deliberately make most of these 32 bits, since they have 602 * restricted range. For any that we read, we won't to generate 32 603 * bit accesses, since Opteron will generate 2 separate 32 bit HT 604 * transactions for a 64 bit read, and we want to avoid unnecessary 605 * bus transactions. 606 */ 607 608 /* This is the 64 bit group */ 609 /* last ibcstatus. opaque outside chip-specific code */ 610 u64 lastibcstat; 611 612 /* these are the "32 bit" regs */ 613 614 /* 615 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 616 * all expect bit fields to be "unsigned long" 617 */ 618 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */ 619 unsigned long p_sendctrl; /* shadow per-port sendctrl */ 620 621 u32 ibmtu; /* The MTU programmed for this unit */ 622 /* 623 * Current max size IB packet (in bytes) including IB headers, that 624 * we can send. Changes when ibmtu changes. 625 */ 626 u32 ibmaxlen; 627 /* 628 * ibmaxlen at init time, limited by chip and by receive buffer 629 * size. Not changed after init. 630 */ 631 u32 init_ibmaxlen; 632 /* LID programmed for this instance */ 633 u16 lid; 634 /* list of pkeys programmed; 0 if not set */ 635 u16 pkeys[4]; 636 /* LID mask control */ 637 u8 lmc; 638 u8 link_width_supported; 639 u8 link_speed_supported; 640 u8 link_width_enabled; 641 u8 link_speed_enabled; 642 u8 link_width_active; 643 u8 link_speed_active; 644 u8 vls_supported; 645 u8 vls_operational; 646 /* Rx Polarity inversion (compensate for ~tx on partner) */ 647 u8 rx_pol_inv; 648 649 u8 hw_pidx; /* physical port index */ 650 u8 port; /* IB port number and index into dd->pports - 1 */ 651 652 u8 delay_mult; 653 654 /* used to override LED behavior */ 655 u8 led_override; /* Substituted for normal value, if non-zero */ 656 u16 led_override_timeoff; /* delta to next timer event */ 657 u8 led_override_vals[2]; /* Alternates per blink-frame */ 658 u8 led_override_phase; /* Just counts, LSB picks from vals[] */ 659 atomic_t led_override_timer_active; 660 /* Used to flash LEDs in override mode */ 661 struct timer_list led_override_timer; 662 struct xmit_wait cong_stats; 663 struct timer_list symerr_clear_timer; 664 665 /* Synchronize access between driver writes and sysfs reads */ 666 spinlock_t cc_shadow_lock 667 ____cacheline_aligned_in_smp; 668 669 /* Shadow copy of the congestion control table */ 670 struct cc_table_shadow *ccti_entries_shadow; 671 672 /* Shadow copy of the congestion control entries */ 673 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow; 674 675 /* List of congestion control table entries */ 676 struct ib_cc_table_entry_shadow *ccti_entries; 677 678 /* 16 congestion entries with each entry corresponding to a SL */ 679 struct ib_cc_congestion_entry_shadow *congestion_entries; 680 681 /* Maximum number of congestion control entries that the agent expects 682 * the manager to send. 683 */ 684 u16 cc_supported_table_entries; 685 686 /* Total number of congestion control table entries */ 687 u16 total_cct_entry; 688 689 /* Bit map identifying service level */ 690 u16 cc_sl_control_map; 691 692 /* maximum congestion control table index */ 693 u16 ccti_limit; 694 695 /* CA's max number of 64 entry units in the congestion control table */ 696 u8 cc_max_table_entries; 697 }; 698 699 /* Observers. Not to be taken lightly, possibly not to ship. */ 700 /* 701 * If a diag read or write is to (bottom <= offset <= top), 702 * the "hoook" is called, allowing, e.g. shadows to be 703 * updated in sync with the driver. struct diag_observer 704 * is the "visible" part. 705 */ 706 struct diag_observer; 707 708 typedef int (*diag_hook) (struct qib_devdata *dd, 709 const struct diag_observer *op, 710 u32 offs, u64 *data, u64 mask, int only_32); 711 712 struct diag_observer { 713 diag_hook hook; 714 u32 bottom; 715 u32 top; 716 }; 717 718 extern int qib_register_observer(struct qib_devdata *dd, 719 const struct diag_observer *op); 720 721 /* Only declared here, not defined. Private to diags */ 722 struct diag_observer_list_elt; 723 724 /* device data struct now contains only "general per-device" info. 725 * fields related to a physical IB port are in a qib_pportdata struct, 726 * described above) while fields only used by a particular chip-type are in 727 * a qib_chipdata struct, whose contents are opaque to this file. 728 */ 729 struct qib_devdata { 730 struct qib_ibdev verbs_dev; /* must be first */ 731 struct list_head list; 732 /* pointers to related structs for this device */ 733 /* pci access data structure */ 734 struct pci_dev *pcidev; 735 struct cdev *user_cdev; 736 struct cdev *diag_cdev; 737 struct device *user_device; 738 struct device *diag_device; 739 740 /* mem-mapped pointer to base of chip regs */ 741 u64 __iomem *kregbase; 742 /* end of mem-mapped chip space excluding sendbuf and user regs */ 743 u64 __iomem *kregend; 744 /* physical address of chip for io_remap, etc. */ 745 resource_size_t physaddr; 746 /* qib_cfgctxts pointers */ 747 struct qib_ctxtdata **rcd; /* Receive Context Data */ 748 749 /* qib_pportdata, points to array of (physical) port-specific 750 * data structs, indexed by pidx (0..n-1) 751 */ 752 struct qib_pportdata *pport; 753 struct qib_chip_specific *cspec; /* chip-specific */ 754 755 /* kvirt address of 1st 2k pio buffer */ 756 void __iomem *pio2kbase; 757 /* kvirt address of 1st 4k pio buffer */ 758 void __iomem *pio4kbase; 759 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */ 760 void __iomem *piobase; 761 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */ 762 u64 __iomem *userbase; 763 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */ 764 /* 765 * points to area where PIOavail registers will be DMA'ed. 766 * Has to be on a page of it's own, because the page will be 767 * mapped into user program space. This copy is *ONLY* ever 768 * written by DMA, not by the driver! Need a copy per device 769 * when we get to multiple devices 770 */ 771 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */ 772 /* physical address where updates occur */ 773 dma_addr_t pioavailregs_phys; 774 775 /* device-specific implementations of functions needed by 776 * common code. Contrary to previous consensus, we can't 777 * really just point to a device-specific table, because we 778 * may need to "bend", e.g. *_f_put_tid 779 */ 780 /* fallback to alternate interrupt type if possible */ 781 int (*f_intr_fallback)(struct qib_devdata *); 782 /* hard reset chip */ 783 int (*f_reset)(struct qib_devdata *); 784 void (*f_quiet_serdes)(struct qib_pportdata *); 785 int (*f_bringup_serdes)(struct qib_pportdata *); 786 int (*f_early_init)(struct qib_devdata *); 787 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *); 788 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*, 789 u32, unsigned long); 790 void (*f_cleanup)(struct qib_devdata *); 791 void (*f_setextled)(struct qib_pportdata *, u32); 792 /* fill out chip-specific fields */ 793 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *); 794 /* free irq */ 795 void (*f_free_irq)(struct qib_devdata *); 796 struct qib_message_header *(*f_get_msgheader) 797 (struct qib_devdata *, __le32 *); 798 void (*f_config_ctxts)(struct qib_devdata *); 799 int (*f_get_ib_cfg)(struct qib_pportdata *, int); 800 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32); 801 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *); 802 int (*f_get_ib_table)(struct qib_pportdata *, int, void *); 803 int (*f_set_ib_table)(struct qib_pportdata *, int, void *); 804 u32 (*f_iblink_state)(u64); 805 u8 (*f_ibphys_portstate)(u64); 806 void (*f_xgxs_reset)(struct qib_pportdata *); 807 /* per chip actions needed for IB Link up/down changes */ 808 int (*f_ib_updown)(struct qib_pportdata *, int, u64); 809 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *); 810 /* Read/modify/write of GPIO pins (potentially chip-specific */ 811 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir, 812 u32 mask); 813 /* Enable writes to config EEPROM (if supported) */ 814 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen); 815 /* 816 * modify rcvctrl shadow[s] and write to appropriate chip-regs. 817 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations. 818 * (ctxt == -1) means "all contexts", only meaningful for 819 * clearing. Could remove if chip_spec shutdown properly done. 820 */ 821 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op, 822 int ctxt); 823 /* Read/modify/write sendctrl appropriately for op and port. */ 824 void (*f_sendctrl)(struct qib_pportdata *, u32 op); 825 void (*f_set_intr_state)(struct qib_devdata *, u32); 826 void (*f_set_armlaunch)(struct qib_devdata *, u32); 827 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32); 828 int (*f_late_initreg)(struct qib_devdata *); 829 int (*f_init_sdma_regs)(struct qib_pportdata *); 830 u16 (*f_sdma_gethead)(struct qib_pportdata *); 831 int (*f_sdma_busy)(struct qib_pportdata *); 832 void (*f_sdma_update_tail)(struct qib_pportdata *, u16); 833 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned); 834 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned); 835 void (*f_sdma_hw_clean_up)(struct qib_pportdata *); 836 void (*f_sdma_hw_start_up)(struct qib_pportdata *); 837 void (*f_sdma_init_early)(struct qib_pportdata *); 838 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 839 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32); 840 u32 (*f_hdrqempty)(struct qib_ctxtdata *); 841 u64 (*f_portcntr)(struct qib_pportdata *, u32); 842 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **, 843 u64 **); 844 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32, 845 char **, u64 **); 846 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8); 847 void (*f_initvl15_bufs)(struct qib_devdata *); 848 void (*f_init_ctxt)(struct qib_ctxtdata *); 849 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32, 850 struct qib_ctxtdata *); 851 void (*f_writescratch)(struct qib_devdata *, u32); 852 int (*f_tempsense_rd)(struct qib_devdata *, int regnum); 853 #ifdef CONFIG_INFINIBAND_QIB_DCA 854 int (*f_notify_dca)(struct qib_devdata *, unsigned long event); 855 #endif 856 857 char *boardname; /* human readable board info */ 858 859 /* template for writing TIDs */ 860 u64 tidtemplate; 861 /* value to write to free TIDs */ 862 u64 tidinvalid; 863 864 /* number of registers used for pioavail */ 865 u32 pioavregs; 866 /* device (not port) flags, basically device capabilities */ 867 u32 flags; 868 /* last buffer for user use */ 869 u32 lastctxt_piobuf; 870 871 /* reset value */ 872 u64 z_int_counter; 873 /* percpu intcounter */ 874 u64 __percpu *int_counter; 875 876 /* pio bufs allocated per ctxt */ 877 u32 pbufsctxt; 878 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */ 879 u32 ctxts_extrabuf; 880 /* 881 * number of ctxts configured as max; zero is set to number chip 882 * supports, less gives more pio bufs/ctxt, etc. 883 */ 884 u32 cfgctxts; 885 /* 886 * number of ctxts available for PSM open 887 */ 888 u32 freectxts; 889 890 /* 891 * hint that we should update pioavailshadow before 892 * looking for a PIO buffer 893 */ 894 u32 upd_pio_shadow; 895 896 /* internal debugging stats */ 897 u32 maxpkts_call; 898 u32 avgpkts_call; 899 u64 nopiobufs; 900 901 /* PCI Vendor ID (here for NodeInfo) */ 902 u16 vendorid; 903 /* PCI Device ID (here for NodeInfo) */ 904 u16 deviceid; 905 /* for write combining settings */ 906 unsigned long wc_cookie; 907 unsigned long wc_base; 908 unsigned long wc_len; 909 910 /* shadow copy of struct page *'s for exp tid pages */ 911 struct page **pageshadow; 912 /* shadow copy of dma handles for exp tid pages */ 913 dma_addr_t *physshadow; 914 u64 __iomem *egrtidbase; 915 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */ 916 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 917 spinlock_t uctxt_lock; /* rcd and user context changes */ 918 /* 919 * per unit status, see also portdata statusp 920 * mapped readonly into user processes so they can get unit and 921 * IB link status cheaply 922 */ 923 u64 *devstatusp; 924 char *freezemsg; /* freeze msg if hw error put chip in freeze */ 925 u32 freezelen; /* max length of freezemsg */ 926 /* timer used to prevent stats overflow, error throttling, etc. */ 927 struct timer_list stats_timer; 928 929 /* timer to verify interrupts work, and fallback if possible */ 930 struct timer_list intrchk_timer; 931 unsigned long ureg_align; /* user register alignment */ 932 933 /* 934 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and 935 * pio_writing. 936 */ 937 spinlock_t pioavail_lock; 938 /* 939 * index of last buffer to optimize search for next 940 */ 941 u32 last_pio; 942 /* 943 * min kernel pio buffer to optimize search 944 */ 945 u32 min_kernel_pio; 946 /* 947 * Shadow copies of registers; size indicates read access size. 948 * Most of them are readonly, but some are write-only register, 949 * where we manipulate the bits in the shadow copy, and then write 950 * the shadow copy to qlogic_ib. 951 * 952 * We deliberately make most of these 32 bits, since they have 953 * restricted range. For any that we read, we won't to generate 32 954 * bit accesses, since Opteron will generate 2 separate 32 bit HT 955 * transactions for a 64 bit read, and we want to avoid unnecessary 956 * bus transactions. 957 */ 958 959 /* This is the 64 bit group */ 960 961 unsigned long pioavailshadow[6]; 962 /* bitmap of send buffers available for the kernel to use with PIO. */ 963 unsigned long pioavailkernel[6]; 964 /* bitmap of send buffers which need to be disarmed. */ 965 unsigned long pio_need_disarm[3]; 966 /* bitmap of send buffers which are being written to. */ 967 unsigned long pio_writing[3]; 968 /* kr_revision shadow */ 969 u64 revision; 970 /* Base GUID for device (from eeprom, network order) */ 971 __be64 base_guid; 972 973 /* 974 * kr_sendpiobufbase value (chip offset of pio buffers), and the 975 * base of the 2KB buffer s(user processes only use 2K) 976 */ 977 u64 piobufbase; 978 u32 pio2k_bufbase; 979 980 /* these are the "32 bit" regs */ 981 982 /* number of GUIDs in the flash for this interface */ 983 u32 nguid; 984 /* 985 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 986 * all expect bit fields to be "unsigned long" 987 */ 988 unsigned long rcvctrl; /* shadow per device rcvctrl */ 989 unsigned long sendctrl; /* shadow per device sendctrl */ 990 991 /* value we put in kr_rcvhdrcnt */ 992 u32 rcvhdrcnt; 993 /* value we put in kr_rcvhdrsize */ 994 u32 rcvhdrsize; 995 /* value we put in kr_rcvhdrentsize */ 996 u32 rcvhdrentsize; 997 /* kr_ctxtcnt value */ 998 u32 ctxtcnt; 999 /* kr_pagealign value */ 1000 u32 palign; 1001 /* number of "2KB" PIO buffers */ 1002 u32 piobcnt2k; 1003 /* size in bytes of "2KB" PIO buffers */ 1004 u32 piosize2k; 1005 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */ 1006 u32 piosize2kmax_dwords; 1007 /* number of "4KB" PIO buffers */ 1008 u32 piobcnt4k; 1009 /* size in bytes of "4KB" PIO buffers */ 1010 u32 piosize4k; 1011 /* kr_rcvegrbase value */ 1012 u32 rcvegrbase; 1013 /* kr_rcvtidbase value */ 1014 u32 rcvtidbase; 1015 /* kr_rcvtidcnt value */ 1016 u32 rcvtidcnt; 1017 /* kr_userregbase */ 1018 u32 uregbase; 1019 /* shadow the control register contents */ 1020 u32 control; 1021 1022 /* chip address space used by 4k pio buffers */ 1023 u32 align4k; 1024 /* size of each rcvegrbuffer */ 1025 u16 rcvegrbufsize; 1026 /* log2 of above */ 1027 u16 rcvegrbufsize_shift; 1028 /* localbus width (1, 2,4,8,16,32) from config space */ 1029 u32 lbus_width; 1030 /* localbus speed in MHz */ 1031 u32 lbus_speed; 1032 int unit; /* unit # of this chip */ 1033 1034 /* start of CHIP_SPEC move to chipspec, but need code changes */ 1035 /* low and high portions of MSI capability/vector */ 1036 u32 msi_lo; 1037 /* saved after PCIe init for restore after reset */ 1038 u32 msi_hi; 1039 /* MSI data (vector) saved for restore */ 1040 u16 msi_data; 1041 /* so we can rewrite it after a chip reset */ 1042 u32 pcibar0; 1043 /* so we can rewrite it after a chip reset */ 1044 u32 pcibar1; 1045 u64 rhdrhead_intr_off; 1046 1047 /* 1048 * ASCII serial number, from flash, large enough for original 1049 * all digit strings, and longer QLogic serial number format 1050 */ 1051 u8 serial[16]; 1052 /* human readable board version */ 1053 u8 boardversion[96]; 1054 u8 lbus_info[32]; /* human readable localbus info */ 1055 /* chip major rev, from qib_revision */ 1056 u8 majrev; 1057 /* chip minor rev, from qib_revision */ 1058 u8 minrev; 1059 1060 /* Misc small ints */ 1061 /* Number of physical ports available */ 1062 u8 num_pports; 1063 /* Lowest context number which can be used by user processes */ 1064 u8 first_user_ctxt; 1065 u8 n_krcv_queues; 1066 u8 qpn_mask; 1067 u8 skip_kctxt_mask; 1068 1069 u16 rhf_offset; /* offset of RHF within receive header entry */ 1070 1071 /* 1072 * GPIO pins for twsi-connected devices, and device code for eeprom 1073 */ 1074 u8 gpio_sda_num; 1075 u8 gpio_scl_num; 1076 u8 twsi_eeprom_dev; 1077 u8 board_atten; 1078 1079 /* Support (including locks) for EEPROM logging of errors and time */ 1080 /* control access to actual counters, timer */ 1081 spinlock_t eep_st_lock; 1082 /* control high-level access to EEPROM */ 1083 struct mutex eep_lock; 1084 uint64_t traffic_wds; 1085 /* active time is kept in seconds, but logged in hours */ 1086 atomic_t active_time; 1087 /* Below are nominal shadow of EEPROM, new since last EEPROM update */ 1088 uint8_t eep_st_errs[QIB_EEP_LOG_CNT]; 1089 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT]; 1090 uint16_t eep_hrs; 1091 /* 1092 * masks for which bits of errs, hwerrs that cause 1093 * each of the counters to increment. 1094 */ 1095 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT]; 1096 struct qib_diag_client *diag_client; 1097 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */ 1098 struct diag_observer_list_elt *diag_observer_list; 1099 1100 u8 psxmitwait_supported; 1101 /* cycle length of PS* counters in HW (in picoseconds) */ 1102 u16 psxmitwait_check_rate; 1103 /* high volume overflow errors defered to tasklet */ 1104 struct tasklet_struct error_tasklet; 1105 /* per device cq worker */ 1106 struct kthread_worker *worker; 1107 1108 int assigned_node_id; /* NUMA node closest to HCA */ 1109 }; 1110 1111 /* hol_state values */ 1112 #define QIB_HOL_UP 0 1113 #define QIB_HOL_INIT 1 1114 1115 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0) 1116 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1) 1117 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2) 1118 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3) 1119 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4) 1120 1121 /* operation types for f_txchk_change() */ 1122 #define TXCHK_CHG_TYPE_DIS1 3 1123 #define TXCHK_CHG_TYPE_ENAB1 2 1124 #define TXCHK_CHG_TYPE_KERN 1 1125 #define TXCHK_CHG_TYPE_USER 0 1126 1127 #define QIB_CHASE_TIME msecs_to_jiffies(145) 1128 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160) 1129 1130 /* Private data for file operations */ 1131 struct qib_filedata { 1132 struct qib_ctxtdata *rcd; 1133 unsigned subctxt; 1134 unsigned tidcursor; 1135 struct qib_user_sdma_queue *pq; 1136 int rec_cpu_num; /* for cpu affinity; -1 if none */ 1137 }; 1138 1139 extern struct list_head qib_dev_list; 1140 extern spinlock_t qib_devs_lock; 1141 extern struct qib_devdata *qib_lookup(int unit); 1142 extern u32 qib_cpulist_count; 1143 extern unsigned long *qib_cpulist; 1144 1145 extern unsigned qib_wc_pat; 1146 extern unsigned qib_cc_table_size; 1147 int qib_init(struct qib_devdata *, int); 1148 int init_chip_wc_pat(struct qib_devdata *dd, u32); 1149 int qib_enable_wc(struct qib_devdata *dd); 1150 void qib_disable_wc(struct qib_devdata *dd); 1151 int qib_count_units(int *npresentp, int *nupp); 1152 int qib_count_active_units(void); 1153 1154 int qib_cdev_init(int minor, const char *name, 1155 const struct file_operations *fops, 1156 struct cdev **cdevp, struct device **devp); 1157 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp); 1158 int qib_dev_init(void); 1159 void qib_dev_cleanup(void); 1160 1161 int qib_diag_add(struct qib_devdata *); 1162 void qib_diag_remove(struct qib_devdata *); 1163 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64); 1164 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */ 1165 1166 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err); 1167 void qib_bad_intrstatus(struct qib_devdata *); 1168 void qib_handle_urcv(struct qib_devdata *, u64); 1169 1170 /* clean up any per-chip chip-specific stuff */ 1171 void qib_chip_cleanup(struct qib_devdata *); 1172 /* clean up any chip type-specific stuff */ 1173 void qib_chip_done(void); 1174 1175 /* check to see if we have to force ordering for write combining */ 1176 int qib_unordered_wc(void); 1177 void qib_pio_copy(void __iomem *to, const void *from, size_t count); 1178 1179 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned); 1180 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *); 1181 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned); 1182 void qib_cancel_sends(struct qib_pportdata *); 1183 1184 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *); 1185 int qib_setup_eagerbufs(struct qib_ctxtdata *); 1186 void qib_set_ctxtcnt(struct qib_devdata *); 1187 int qib_create_ctxts(struct qib_devdata *dd); 1188 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int); 1189 int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8); 1190 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *); 1191 1192 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *); 1193 int qib_reset_device(int); 1194 int qib_wait_linkstate(struct qib_pportdata *, u32, int); 1195 int qib_set_linkstate(struct qib_pportdata *, u8); 1196 int qib_set_mtu(struct qib_pportdata *, u16); 1197 int qib_set_lid(struct qib_pportdata *, u32, u8); 1198 void qib_hol_down(struct qib_pportdata *); 1199 void qib_hol_init(struct qib_pportdata *); 1200 void qib_hol_up(struct qib_pportdata *); 1201 void qib_hol_event(unsigned long); 1202 void qib_disable_after_error(struct qib_devdata *); 1203 int qib_set_uevent_bits(struct qib_pportdata *, const int); 1204 1205 /* for use in system calls, where we want to know device type, etc. */ 1206 #define ctxt_fp(fp) \ 1207 (((struct qib_filedata *)(fp)->private_data)->rcd) 1208 #define subctxt_fp(fp) \ 1209 (((struct qib_filedata *)(fp)->private_data)->subctxt) 1210 #define tidcursor_fp(fp) \ 1211 (((struct qib_filedata *)(fp)->private_data)->tidcursor) 1212 #define user_sdma_queue_fp(fp) \ 1213 (((struct qib_filedata *)(fp)->private_data)->pq) 1214 1215 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd) 1216 { 1217 return ppd->dd; 1218 } 1219 1220 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev) 1221 { 1222 return container_of(dev, struct qib_devdata, verbs_dev); 1223 } 1224 1225 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev) 1226 { 1227 return dd_from_dev(to_idev(ibdev)); 1228 } 1229 1230 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp) 1231 { 1232 return container_of(ibp, struct qib_pportdata, ibport_data); 1233 } 1234 1235 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port) 1236 { 1237 struct qib_devdata *dd = dd_from_ibdev(ibdev); 1238 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1239 1240 WARN_ON(pidx >= dd->num_pports); 1241 return &dd->pport[pidx].ibport_data; 1242 } 1243 1244 /* 1245 * values for dd->flags (_device_ related flags) and 1246 */ 1247 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */ 1248 #define QIB_INITTED 0x2 /* chip and driver up and initted */ 1249 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */ 1250 #define QIB_PRESENT 0x8 /* chip accesses can be done */ 1251 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */ 1252 #define QIB_HAS_THRESH_UPDATE 0x40 1253 #define QIB_HAS_SDMA_TIMEOUT 0x80 1254 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */ 1255 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */ 1256 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */ 1257 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */ 1258 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */ 1259 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */ 1260 #define QIB_BADINTR 0x8000 /* severe interrupt problems */ 1261 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */ 1262 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */ 1263 1264 /* 1265 * values for ppd->lflags (_ib_port_ related flags) 1266 */ 1267 #define QIBL_LINKV 0x1 /* IB link state valid */ 1268 #define QIBL_LINKDOWN 0x8 /* IB link is down */ 1269 #define QIBL_LINKINIT 0x10 /* IB link level is up */ 1270 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */ 1271 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */ 1272 /* leave a gap for more IB-link state */ 1273 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */ 1274 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */ 1275 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced, 1276 * Do not try to bring up */ 1277 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */ 1278 1279 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1280 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1) 1281 1282 1283 /* ctxt_flag bit offsets */ 1284 /* waiting for a packet to arrive */ 1285 #define QIB_CTXT_WAITING_RCV 2 1286 /* master has not finished initializing */ 1287 #define QIB_CTXT_MASTER_UNINIT 4 1288 /* waiting for an urgent packet to arrive */ 1289 #define QIB_CTXT_WAITING_URG 5 1290 1291 /* free up any allocated data at closes */ 1292 void qib_free_data(struct qib_ctxtdata *dd); 1293 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned, 1294 u32, struct qib_ctxtdata *); 1295 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *, 1296 const struct pci_device_id *); 1297 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *, 1298 const struct pci_device_id *); 1299 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *, 1300 const struct pci_device_id *); 1301 void qib_free_devdata(struct qib_devdata *); 1302 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra); 1303 1304 #define QIB_TWSI_NO_DEV 0xFF 1305 /* Below qib_twsi_ functions must be called with eep_lock held */ 1306 int qib_twsi_reset(struct qib_devdata *dd); 1307 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer, 1308 int len); 1309 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 1310 const void *buffer, int len); 1311 void qib_get_eeprom_info(struct qib_devdata *); 1312 int qib_update_eeprom_log(struct qib_devdata *dd); 1313 void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr); 1314 void qib_dump_lookup_output_queue(struct qib_devdata *); 1315 void qib_force_pio_avail_update(struct qib_devdata *); 1316 void qib_clear_symerror_on_linkup(unsigned long opaque); 1317 1318 /* 1319 * Set LED override, only the two LSBs have "public" meaning, but 1320 * any non-zero value substitutes them for the Link and LinkTrain 1321 * LED states. 1322 */ 1323 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ 1324 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */ 1325 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val); 1326 1327 /* send dma routines */ 1328 int qib_setup_sdma(struct qib_pportdata *); 1329 void qib_teardown_sdma(struct qib_pportdata *); 1330 void __qib_sdma_intr(struct qib_pportdata *); 1331 void qib_sdma_intr(struct qib_pportdata *); 1332 void qib_user_sdma_send_desc(struct qib_pportdata *dd, 1333 struct list_head *pktlist); 1334 int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *, 1335 u32, struct qib_verbs_txreq *); 1336 /* ppd->sdma_lock should be locked before calling this. */ 1337 int qib_sdma_make_progress(struct qib_pportdata *dd); 1338 1339 static inline int qib_sdma_empty(const struct qib_pportdata *ppd) 1340 { 1341 return ppd->sdma_descq_added == ppd->sdma_descq_removed; 1342 } 1343 1344 /* must be called under qib_sdma_lock */ 1345 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd) 1346 { 1347 return ppd->sdma_descq_cnt - 1348 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1; 1349 } 1350 1351 static inline int __qib_sdma_running(struct qib_pportdata *ppd) 1352 { 1353 return ppd->sdma_state.current_state == qib_sdma_state_s99_running; 1354 } 1355 int qib_sdma_running(struct qib_pportdata *); 1356 void dump_sdma_state(struct qib_pportdata *ppd); 1357 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1358 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1359 1360 /* 1361 * number of words used for protocol header if not set by qib_userinit(); 1362 */ 1363 #define QIB_DFLT_RCVHDRSIZE 9 1364 1365 /* 1366 * We need to be able to handle an IB header of at least 24 dwords. 1367 * We need the rcvhdrq large enough to handle largest IB header, but 1368 * still have room for a 2KB MTU standard IB packet. 1369 * Additionally, some processor/memory controller combinations 1370 * benefit quite strongly from having the DMA'ed data be cacheline 1371 * aligned and a cacheline multiple, so we set the size to 32 dwords 1372 * (2 64-byte primary cachelines for pretty much all processors of 1373 * interest). The alignment hurts nothing, other than using somewhat 1374 * more memory. 1375 */ 1376 #define QIB_RCVHDR_ENTSIZE 32 1377 1378 int qib_get_user_pages(unsigned long, size_t, struct page **); 1379 void qib_release_user_pages(struct page **, size_t); 1380 int qib_eeprom_read(struct qib_devdata *, u8, void *, int); 1381 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int); 1382 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32); 1383 void qib_sendbuf_done(struct qib_devdata *, unsigned); 1384 1385 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd) 1386 { 1387 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL; 1388 } 1389 1390 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd) 1391 { 1392 /* 1393 * volatile because it's a DMA target from the chip, routine is 1394 * inlined, and don't want register caching or reordering. 1395 */ 1396 return (u32) le64_to_cpu( 1397 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */ 1398 } 1399 1400 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd) 1401 { 1402 const struct qib_devdata *dd = rcd->dd; 1403 u32 hdrqtail; 1404 1405 if (dd->flags & QIB_NODMA_RTAIL) { 1406 __le32 *rhf_addr; 1407 u32 seq; 1408 1409 rhf_addr = (__le32 *) rcd->rcvhdrq + 1410 rcd->head + dd->rhf_offset; 1411 seq = qib_hdrget_seq(rhf_addr); 1412 hdrqtail = rcd->head; 1413 if (seq == rcd->seq_cnt) 1414 hdrqtail++; 1415 } else 1416 hdrqtail = qib_get_rcvhdrtail(rcd); 1417 1418 return hdrqtail; 1419 } 1420 1421 /* 1422 * sysfs interface. 1423 */ 1424 1425 extern const char ib_qib_version[]; 1426 1427 int qib_device_create(struct qib_devdata *); 1428 void qib_device_remove(struct qib_devdata *); 1429 1430 int qib_create_port_files(struct ib_device *ibdev, u8 port_num, 1431 struct kobject *kobj); 1432 int qib_verbs_register_sysfs(struct qib_devdata *); 1433 void qib_verbs_unregister_sysfs(struct qib_devdata *); 1434 /* Hook for sysfs read of QSFP */ 1435 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len); 1436 1437 int __init qib_init_qibfs(void); 1438 int __exit qib_exit_qibfs(void); 1439 1440 int qibfs_add(struct qib_devdata *); 1441 int qibfs_remove(struct qib_devdata *); 1442 1443 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *); 1444 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *, 1445 const struct pci_device_id *); 1446 void qib_pcie_ddcleanup(struct qib_devdata *); 1447 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *); 1448 int qib_reinit_intr(struct qib_devdata *); 1449 void qib_enable_intx(struct pci_dev *); 1450 void qib_nomsi(struct qib_devdata *); 1451 void qib_nomsix(struct qib_devdata *); 1452 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *); 1453 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8); 1454 /* interrupts for device */ 1455 u64 qib_int_counter(struct qib_devdata *); 1456 /* interrupt for all devices */ 1457 u64 qib_sps_ints(void); 1458 1459 /* 1460 * dma_addr wrappers - all 0's invalid for hw 1461 */ 1462 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long, 1463 size_t, int); 1464 const char *qib_get_unit_name(int unit); 1465 1466 /* 1467 * Flush write combining store buffers (if present) and perform a write 1468 * barrier. 1469 */ 1470 #if defined(CONFIG_X86_64) 1471 #define qib_flush_wc() asm volatile("sfence" : : : "memory") 1472 #else 1473 #define qib_flush_wc() wmb() /* no reorder around wc flush */ 1474 #endif 1475 1476 /* global module parameter variables */ 1477 extern unsigned qib_ibmtu; 1478 extern ushort qib_cfgctxts; 1479 extern ushort qib_num_cfg_vls; 1480 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */ 1481 extern unsigned qib_n_krcv_queues; 1482 extern unsigned qib_sdma_fetch_arb; 1483 extern unsigned qib_compat_ddr_negotiate; 1484 extern int qib_special_trigger; 1485 extern unsigned qib_numa_aware; 1486 1487 extern struct mutex qib_mutex; 1488 1489 /* Number of seconds before our card status check... */ 1490 #define STATUS_TIMEOUT 60 1491 1492 #define QIB_DRV_NAME "ib_qib" 1493 #define QIB_USER_MINOR_BASE 0 1494 #define QIB_TRACE_MINOR 127 1495 #define QIB_DIAGPKT_MINOR 128 1496 #define QIB_DIAG_MINOR_BASE 129 1497 #define QIB_NMINORS 255 1498 1499 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 1500 #define PCI_VENDOR_ID_QLOGIC 0x1077 1501 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10 1502 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220 1503 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322 1504 1505 /* 1506 * qib_early_err is used (only!) to print early errors before devdata is 1507 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1508 * cleanup when devdata may have been freed, etc. qib_dev_porterr is 1509 * the same as qib_dev_err, but is used when the message really needs 1510 * the IB port# to be definitive as to what's happening.. 1511 * All of these go to the trace log, and the trace log entry is done 1512 * first to avoid possible serial port delays from printk. 1513 */ 1514 #define qib_early_err(dev, fmt, ...) \ 1515 dev_err(dev, fmt, ##__VA_ARGS__) 1516 1517 #define qib_dev_err(dd, fmt, ...) \ 1518 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1519 qib_get_unit_name((dd)->unit), ##__VA_ARGS__) 1520 1521 #define qib_dev_warn(dd, fmt, ...) \ 1522 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1523 qib_get_unit_name((dd)->unit), ##__VA_ARGS__) 1524 1525 #define qib_dev_porterr(dd, port, fmt, ...) \ 1526 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \ 1527 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \ 1528 ##__VA_ARGS__) 1529 1530 #define qib_devinfo(pcidev, fmt, ...) \ 1531 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__) 1532 1533 /* 1534 * this is used for formatting hw error messages... 1535 */ 1536 struct qib_hwerror_msgs { 1537 u64 mask; 1538 const char *msg; 1539 size_t sz; 1540 }; 1541 1542 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b } 1543 1544 /* in qib_intr.c... */ 1545 void qib_format_hwerrors(u64 hwerrs, 1546 const struct qib_hwerror_msgs *hwerrmsgs, 1547 size_t nhwerrmsgs, char *msg, size_t lmsg); 1548 #endif /* _QIB_KERNEL_H */ 1549