1 /* QLogic qedr NIC Driver
2  * Copyright (c) 2015-2016  QLogic Corporation
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and /or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef __QED_HSI_RDMA__
33 #define __QED_HSI_RDMA__
34 
35 #include <linux/qed/rdma_common.h>
36 
37 /* rdma completion notification queue element */
38 struct rdma_cnqe {
39 	struct regpair	cq_handle;
40 };
41 
42 struct rdma_cqe_responder {
43 	struct regpair srq_wr_id;
44 	struct regpair qp_handle;
45 	__le32 imm_data_or_inv_r_Key;
46 	__le32 length;
47 	__le32 imm_data_hi;
48 	__le16 rq_cons;
49 	u8 flags;
50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK  0x1
51 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0
52 #define RDMA_CQE_RESPONDER_TYPE_MASK        0x3
53 #define RDMA_CQE_RESPONDER_TYPE_SHIFT       1
54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK     0x1
55 #define RDMA_CQE_RESPONDER_INV_FLG_SHIFT    3
56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK     0x1
57 #define RDMA_CQE_RESPONDER_IMM_FLG_SHIFT    4
58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK    0x1
59 #define RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT   5
60 #define RDMA_CQE_RESPONDER_RESERVED2_MASK   0x3
61 #define RDMA_CQE_RESPONDER_RESERVED2_SHIFT  6
62 	u8 status;
63 };
64 
65 struct rdma_cqe_requester {
66 	__le16 sq_cons;
67 	__le16 reserved0;
68 	__le32 reserved1;
69 	struct regpair qp_handle;
70 	struct regpair reserved2;
71 	__le32 reserved3;
72 	__le16 reserved4;
73 	u8 flags;
74 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK  0x1
75 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0
76 #define RDMA_CQE_REQUESTER_TYPE_MASK        0x3
77 #define RDMA_CQE_REQUESTER_TYPE_SHIFT       1
78 #define RDMA_CQE_REQUESTER_RESERVED5_MASK   0x1F
79 #define RDMA_CQE_REQUESTER_RESERVED5_SHIFT  3
80 	u8 status;
81 };
82 
83 struct rdma_cqe_common {
84 	struct regpair reserved0;
85 	struct regpair qp_handle;
86 	__le16 reserved1[7];
87 	u8 flags;
88 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK  0x1
89 #define RDMA_CQE_COMMON_TOGGLE_BIT_SHIFT 0
90 #define RDMA_CQE_COMMON_TYPE_MASK        0x3
91 #define RDMA_CQE_COMMON_TYPE_SHIFT       1
92 #define RDMA_CQE_COMMON_RESERVED2_MASK   0x1F
93 #define RDMA_CQE_COMMON_RESERVED2_SHIFT  3
94 	u8 status;
95 };
96 
97 /* rdma completion queue element */
98 union rdma_cqe {
99 	struct rdma_cqe_responder resp;
100 	struct rdma_cqe_requester req;
101 	struct rdma_cqe_common cmn;
102 };
103 
104 /* * CQE requester status enumeration */
105 enum rdma_cqe_requester_status_enum {
106 	RDMA_CQE_REQ_STS_OK,
107 	RDMA_CQE_REQ_STS_BAD_RESPONSE_ERR,
108 	RDMA_CQE_REQ_STS_LOCAL_LENGTH_ERR,
109 	RDMA_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR,
110 	RDMA_CQE_REQ_STS_LOCAL_PROTECTION_ERR,
111 	RDMA_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR,
112 	RDMA_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR,
113 	RDMA_CQE_REQ_STS_REMOTE_ACCESS_ERR,
114 	RDMA_CQE_REQ_STS_REMOTE_OPERATION_ERR,
115 	RDMA_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR,
116 	RDMA_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR,
117 	RDMA_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR,
118 	MAX_RDMA_CQE_REQUESTER_STATUS_ENUM
119 };
120 
121 /* CQE responder status enumeration */
122 enum rdma_cqe_responder_status_enum {
123 	RDMA_CQE_RESP_STS_OK,
124 	RDMA_CQE_RESP_STS_LOCAL_ACCESS_ERR,
125 	RDMA_CQE_RESP_STS_LOCAL_LENGTH_ERR,
126 	RDMA_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR,
127 	RDMA_CQE_RESP_STS_LOCAL_PROTECTION_ERR,
128 	RDMA_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR,
129 	RDMA_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR,
130 	RDMA_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR,
131 	MAX_RDMA_CQE_RESPONDER_STATUS_ENUM
132 };
133 
134 /* CQE type enumeration */
135 enum rdma_cqe_type {
136 	RDMA_CQE_TYPE_REQUESTER,
137 	RDMA_CQE_TYPE_RESPONDER_RQ,
138 	RDMA_CQE_TYPE_RESPONDER_SRQ,
139 	RDMA_CQE_TYPE_INVALID,
140 	MAX_RDMA_CQE_TYPE
141 };
142 
143 struct rdma_sq_sge {
144 	__le32 length;
145 	struct regpair	addr;
146 	__le32 l_key;
147 };
148 
149 struct rdma_rq_sge {
150 	struct regpair addr;
151 	__le32 length;
152 	__le32 flags;
153 #define RDMA_RQ_SGE_L_KEY_MASK      0x3FFFFFF
154 #define RDMA_RQ_SGE_L_KEY_SHIFT     0
155 #define RDMA_RQ_SGE_NUM_SGES_MASK   0x7
156 #define RDMA_RQ_SGE_NUM_SGES_SHIFT  26
157 #define RDMA_RQ_SGE_RESERVED0_MASK  0x7
158 #define RDMA_RQ_SGE_RESERVED0_SHIFT 29
159 };
160 
161 struct rdma_srq_sge {
162 	struct regpair addr;
163 	__le32 length;
164 	__le32 l_key;
165 };
166 
167 /* Rdma doorbell data for flags update */
168 struct rdma_pwm_flags_data {
169 	__le16 icid; /* internal CID */
170 	u8 agg_flags; /* aggregative flags */
171 	u8 reserved;
172 };
173 
174 /* Rdma doorbell data for SQ and RQ */
175 struct rdma_pwm_val16_data {
176 	__le16 icid;
177 	__le16 value;
178 };
179 
180 union rdma_pwm_val16_data_union {
181 	struct rdma_pwm_val16_data as_struct;
182 	__le32 as_dword;
183 };
184 
185 /* Rdma doorbell data for CQ */
186 struct rdma_pwm_val32_data {
187 	__le16 icid;
188 	u8 agg_flags;
189 	u8 params;
190 #define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK		0x3
191 #define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT		0
192 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK		0x1
193 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT		2
194 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK	0x1
195 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT	3
196 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK		0x1
197 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_SHIFT		4
198 #define RDMA_PWM_VAL32_DATA_RESERVED_MASK		0x7
199 #define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT		5
200 	__le32 value;
201 };
202 
203 /* DIF Block size options */
204 enum rdma_dif_block_size {
205 	RDMA_DIF_BLOCK_512 = 0,
206 	RDMA_DIF_BLOCK_4096 = 1,
207 	MAX_RDMA_DIF_BLOCK_SIZE
208 };
209 
210 /* DIF CRC initial value */
211 enum rdma_dif_crc_seed {
212 	RDMA_DIF_CRC_SEED_0000 = 0,
213 	RDMA_DIF_CRC_SEED_FFFF = 1,
214 	MAX_RDMA_DIF_CRC_SEED
215 };
216 
217 /* RDMA DIF Error Result Structure */
218 struct rdma_dif_error_result {
219 	__le32 error_intervals;
220 	__le32 dif_error_1st_interval;
221 	u8 flags;
222 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK      0x1
223 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_SHIFT     0
224 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK  0x1
225 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_SHIFT 1
226 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK  0x1
227 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_SHIFT 2
228 #define RDMA_DIF_ERROR_RESULT_RESERVED0_MASK               0xF
229 #define RDMA_DIF_ERROR_RESULT_RESERVED0_SHIFT              3
230 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK              0x1
231 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_SHIFT             7
232 	u8 reserved1[55];
233 };
234 
235 /* DIF IO direction */
236 enum rdma_dif_io_direction_flg {
237 	RDMA_DIF_DIR_RX = 0,
238 	RDMA_DIF_DIR_TX = 1,
239 	MAX_RDMA_DIF_IO_DIRECTION_FLG
240 };
241 
242 /* RDMA DIF Runt Result Structure */
243 struct rdma_dif_runt_result {
244 	__le16 guard_tag;
245 	__le16 reserved[3];
246 };
247 
248 /* Memory window type enumeration */
249 enum rdma_mw_type {
250 	RDMA_MW_TYPE_1,
251 	RDMA_MW_TYPE_2A,
252 	MAX_RDMA_MW_TYPE
253 };
254 
255 struct rdma_sq_atomic_wqe {
256 	__le32 reserved1;
257 	__le32 length;
258 	__le32 xrc_srq;
259 	u8 req_type;
260 	u8 flags;
261 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_MASK         0x1
262 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_SHIFT        0
263 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK     0x1
264 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT    1
265 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK    0x1
266 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT   2
267 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_MASK           0x1
268 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_SHIFT          3
269 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_MASK       0x1
270 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT      4
271 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_MASK  0x1
272 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_SHIFT 5
273 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_MASK        0x3
274 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_SHIFT       6
275 	u8 wqe_size;
276 	u8 prev_wqe_size;
277 	struct regpair remote_va;
278 	__le32 r_key;
279 	__le32 reserved2;
280 	struct regpair cmp_data;
281 	struct regpair swap_data;
282 };
283 
284 /* First element (16 bytes) of atomic wqe */
285 struct rdma_sq_atomic_wqe_1st {
286 	__le32 reserved1;
287 	__le32 length;
288 	__le32 xrc_srq;
289 	u8 req_type;
290 	u8 flags;
291 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK       0x1
292 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT      0
293 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK   0x1
294 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT  1
295 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK  0x1
296 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2
297 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK         0x1
298 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT        3
299 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK     0x1
300 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT    4
301 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK      0x7
302 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT     5
303 	u8 wqe_size;
304 	u8 prev_wqe_size;
305 };
306 
307 /* Second element (16 bytes) of atomic wqe */
308 struct rdma_sq_atomic_wqe_2nd {
309 	struct regpair remote_va;
310 	__le32 r_key;
311 	__le32 reserved2;
312 };
313 
314 /* Third element (16 bytes) of atomic wqe */
315 struct rdma_sq_atomic_wqe_3rd {
316 	struct regpair cmp_data;
317 	struct regpair swap_data;
318 };
319 
320 struct rdma_sq_bind_wqe {
321 	struct regpair addr;
322 	__le32 l_key;
323 	u8 req_type;
324 	u8 flags;
325 #define RDMA_SQ_BIND_WQE_COMP_FLG_MASK       0x1
326 #define RDMA_SQ_BIND_WQE_COMP_FLG_SHIFT      0
327 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_MASK   0x1
328 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT  1
329 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_MASK  0x1
330 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2
331 #define RDMA_SQ_BIND_WQE_SE_FLG_MASK         0x1
332 #define RDMA_SQ_BIND_WQE_SE_FLG_SHIFT        3
333 #define RDMA_SQ_BIND_WQE_INLINE_FLG_MASK     0x1
334 #define RDMA_SQ_BIND_WQE_INLINE_FLG_SHIFT    4
335 #define RDMA_SQ_BIND_WQE_RESERVED0_MASK      0x7
336 #define RDMA_SQ_BIND_WQE_RESERVED0_SHIFT     5
337 	u8 wqe_size;
338 	u8 prev_wqe_size;
339 	u8 bind_ctrl;
340 #define RDMA_SQ_BIND_WQE_ZERO_BASED_MASK     0x1
341 #define RDMA_SQ_BIND_WQE_ZERO_BASED_SHIFT    0
342 #define RDMA_SQ_BIND_WQE_MW_TYPE_MASK        0x1
343 #define RDMA_SQ_BIND_WQE_MW_TYPE_SHIFT       1
344 #define RDMA_SQ_BIND_WQE_RESERVED1_MASK      0x3F
345 #define RDMA_SQ_BIND_WQE_RESERVED1_SHIFT     2
346 	u8 access_ctrl;
347 #define RDMA_SQ_BIND_WQE_REMOTE_READ_MASK    0x1
348 #define RDMA_SQ_BIND_WQE_REMOTE_READ_SHIFT   0
349 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_MASK   0x1
350 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_SHIFT  1
351 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_MASK  0x1
352 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2
353 #define RDMA_SQ_BIND_WQE_LOCAL_READ_MASK     0x1
354 #define RDMA_SQ_BIND_WQE_LOCAL_READ_SHIFT    3
355 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_MASK    0x1
356 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_SHIFT   4
357 #define RDMA_SQ_BIND_WQE_RESERVED2_MASK      0x7
358 #define RDMA_SQ_BIND_WQE_RESERVED2_SHIFT     5
359 	u8 reserved3;
360 	u8 length_hi;
361 	__le32 length_lo;
362 	__le32 parent_l_key;
363 	__le32 reserved4;
364 };
365 
366 /* First element (16 bytes) of bind wqe */
367 struct rdma_sq_bind_wqe_1st {
368 	struct regpair addr;
369 	__le32 l_key;
370 	u8 req_type;
371 	u8 flags;
372 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_MASK       0x1
373 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT      0
374 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK   0x1
375 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT  1
376 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK  0x1
377 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2
378 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_MASK         0x1
379 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_SHIFT        3
380 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_MASK     0x1
381 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT    4
382 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_MASK      0x7
383 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_SHIFT     5
384 	u8 wqe_size;
385 	u8 prev_wqe_size;
386 };
387 
388 /* Second element (16 bytes) of bind wqe */
389 struct rdma_sq_bind_wqe_2nd {
390 	u8 bind_ctrl;
391 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_MASK     0x1
392 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT    0
393 #define RDMA_SQ_BIND_WQE_2ND_MW_TYPE_MASK        0x1
394 #define RDMA_SQ_BIND_WQE_2ND_MW_TYPE_SHIFT       1
395 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_MASK      0x3F
396 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_SHIFT     2
397 	u8 access_ctrl;
398 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_MASK    0x1
399 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_SHIFT   0
400 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_MASK   0x1
401 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_SHIFT  1
402 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_MASK  0x1
403 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_SHIFT 2
404 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_MASK     0x1
405 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_SHIFT    3
406 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_MASK    0x1
407 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_SHIFT   4
408 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_MASK      0x7
409 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_SHIFT     5
410 	u8 reserved3;
411 	u8 length_hi;
412 	__le32 length_lo;
413 	__le32 parent_l_key;
414 	__le32 reserved4;
415 };
416 
417 /* Structure with only the SQ WQE common
418  * fields. Size is of one SQ element (16B)
419  */
420 struct rdma_sq_common_wqe {
421 	__le32 reserved1[3];
422 	u8 req_type;
423 	u8 flags;
424 #define RDMA_SQ_COMMON_WQE_COMP_FLG_MASK       0x1
425 #define RDMA_SQ_COMMON_WQE_COMP_FLG_SHIFT      0
426 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_MASK   0x1
427 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT  1
428 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_MASK  0x1
429 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2
430 #define RDMA_SQ_COMMON_WQE_SE_FLG_MASK         0x1
431 #define RDMA_SQ_COMMON_WQE_SE_FLG_SHIFT        3
432 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_MASK     0x1
433 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_SHIFT    4
434 #define RDMA_SQ_COMMON_WQE_RESERVED0_MASK      0x7
435 #define RDMA_SQ_COMMON_WQE_RESERVED0_SHIFT     5
436 	u8 wqe_size;
437 	u8 prev_wqe_size;
438 };
439 
440 struct rdma_sq_fmr_wqe {
441 	struct regpair addr;
442 	__le32 l_key;
443 	u8 req_type;
444 	u8 flags;
445 #define RDMA_SQ_FMR_WQE_COMP_FLG_MASK                0x1
446 #define RDMA_SQ_FMR_WQE_COMP_FLG_SHIFT               0
447 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_MASK            0x1
448 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT           1
449 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_MASK           0x1
450 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT          2
451 #define RDMA_SQ_FMR_WQE_SE_FLG_MASK                  0x1
452 #define RDMA_SQ_FMR_WQE_SE_FLG_SHIFT                 3
453 #define RDMA_SQ_FMR_WQE_INLINE_FLG_MASK              0x1
454 #define RDMA_SQ_FMR_WQE_INLINE_FLG_SHIFT             4
455 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_MASK         0x1
456 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_SHIFT        5
457 #define RDMA_SQ_FMR_WQE_RESERVED0_MASK               0x3
458 #define RDMA_SQ_FMR_WQE_RESERVED0_SHIFT              6
459 	u8 wqe_size;
460 	u8 prev_wqe_size;
461 	u8 fmr_ctrl;
462 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK           0x1F
463 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT          0
464 #define RDMA_SQ_FMR_WQE_ZERO_BASED_MASK              0x1
465 #define RDMA_SQ_FMR_WQE_ZERO_BASED_SHIFT             5
466 #define RDMA_SQ_FMR_WQE_BIND_EN_MASK                 0x1
467 #define RDMA_SQ_FMR_WQE_BIND_EN_SHIFT                6
468 #define RDMA_SQ_FMR_WQE_RESERVED1_MASK               0x1
469 #define RDMA_SQ_FMR_WQE_RESERVED1_SHIFT              7
470 	u8 access_ctrl;
471 #define RDMA_SQ_FMR_WQE_REMOTE_READ_MASK             0x1
472 #define RDMA_SQ_FMR_WQE_REMOTE_READ_SHIFT            0
473 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_MASK            0x1
474 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_SHIFT           1
475 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_MASK           0x1
476 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT          2
477 #define RDMA_SQ_FMR_WQE_LOCAL_READ_MASK              0x1
478 #define RDMA_SQ_FMR_WQE_LOCAL_READ_SHIFT             3
479 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_MASK             0x1
480 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_SHIFT            4
481 #define RDMA_SQ_FMR_WQE_RESERVED2_MASK               0x7
482 #define RDMA_SQ_FMR_WQE_RESERVED2_SHIFT              5
483 	u8 reserved3;
484 	u8 length_hi;
485 	__le32 length_lo;
486 	struct regpair pbl_addr;
487 	__le32 dif_base_ref_tag;
488 	__le16 dif_app_tag;
489 	__le16 dif_app_tag_mask;
490 	__le16 dif_runt_crc_value;
491 	__le16 dif_flags;
492 #define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_MASK	0x1
493 #define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_SHIFT	0
494 #define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_MASK		0x1
495 #define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_SHIFT		1
496 #define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_MASK		0x1
497 #define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_SHIFT	2
498 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_MASK	0x1
499 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_SHIFT	3
500 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_MASK	0x1
501 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_SHIFT	4
502 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_MASK	0x1
503 #define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT	5
504 #define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK		0x1
505 #define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT		6
506 #define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_MASK	0x1
507 #define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_SHIFT	7
508 #define RDMA_SQ_FMR_WQE_RESERVED4_MASK			0xFF
509 #define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT			8
510 	__le32 reserved5;
511 };
512 
513 /* First element (16 bytes) of fmr wqe */
514 struct rdma_sq_fmr_wqe_1st {
515 	struct regpair addr;
516 	__le32 l_key;
517 	u8 req_type;
518 	u8 flags;
519 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_MASK         0x1
520 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT        0
521 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK     0x1
522 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT    1
523 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK    0x1
524 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT   2
525 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_MASK           0x1
526 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_SHIFT          3
527 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_MASK       0x1
528 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT      4
529 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_MASK  0x1
530 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5
531 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_MASK        0x3
532 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_SHIFT       6
533 	u8 wqe_size;
534 	u8 prev_wqe_size;
535 };
536 
537 /* Second element (16 bytes) of fmr wqe */
538 struct rdma_sq_fmr_wqe_2nd {
539 	u8 fmr_ctrl;
540 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK  0x1F
541 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0
542 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_MASK     0x1
543 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT    5
544 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_MASK        0x1
545 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_SHIFT       6
546 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_MASK      0x1
547 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_SHIFT     7
548 	u8 access_ctrl;
549 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_MASK    0x1
550 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_SHIFT   0
551 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_MASK   0x1
552 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_SHIFT  1
553 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_MASK  0x1
554 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_SHIFT 2
555 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_MASK     0x1
556 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_SHIFT    3
557 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_MASK    0x1
558 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_SHIFT   4
559 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_MASK      0x7
560 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_SHIFT     5
561 	u8 reserved3;
562 	u8 length_hi;
563 	__le32 length_lo;
564 	struct regpair pbl_addr;
565 };
566 
567 /* Third element (16 bytes) of fmr wqe */
568 struct rdma_sq_fmr_wqe_3rd {
569 	__le32 dif_base_ref_tag;
570 	__le16 dif_app_tag;
571 	__le16 dif_app_tag_mask;
572 	__le16 dif_runt_crc_value;
573 	__le16 dif_flags;
574 #define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_MASK		0x1
575 #define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_SHIFT		0
576 #define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_MASK			0x1
577 #define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_SHIFT		1
578 #define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_MASK		0x1
579 #define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_SHIFT		2
580 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_MASK		0x1
581 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_SHIFT	3
582 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_MASK		0x1
583 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_SHIFT		4
584 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_MASK		0x1
585 #define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT		5
586 #define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK			0x1
587 #define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT			6
588 #define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_MASK		0x1
589 #define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_SHIFT		7
590 #define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK			0xFF
591 #define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT				8
592 	__le32 reserved5;
593 };
594 
595 struct rdma_sq_local_inv_wqe {
596 	struct regpair reserved;
597 	__le32 inv_l_key;
598 	u8 req_type;
599 	u8 flags;
600 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_MASK         0x1
601 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT        0
602 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK     0x1
603 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT    1
604 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK    0x1
605 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT   2
606 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_MASK           0x1
607 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT          3
608 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK       0x1
609 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT      4
610 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_MASK  0x1
611 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_SHIFT 5
612 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_MASK        0x3
613 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT       6
614 	u8 wqe_size;
615 	u8 prev_wqe_size;
616 };
617 
618 struct rdma_sq_rdma_wqe {
619 	__le32 imm_data;
620 	__le32 length;
621 	__le32 xrc_srq;
622 	u8 req_type;
623 	u8 flags;
624 #define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK		0x1
625 #define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT		0
626 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK	0x1
627 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT	1
628 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK	0x1
629 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT	2
630 #define RDMA_SQ_RDMA_WQE_SE_FLG_MASK		0x1
631 #define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT		3
632 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK	0x1
633 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT	4
634 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK	0x1
635 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT	5
636 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK	0x1
637 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_SHIFT	6
638 #define RDMA_SQ_RDMA_WQE_RESERVED0_MASK		0x1
639 #define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT	7
640 	u8 wqe_size;
641 	u8 prev_wqe_size;
642 	struct regpair remote_va;
643 	__le32 r_key;
644 	u8 dif_flags;
645 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_MASK            0x1
646 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_SHIFT           0
647 #define RDMA_SQ_RDMA_WQE_DIF_FIRST_RDMA_IN_IO_FLG_MASK  0x1
648 #define RDMA_SQ_RDMA_WQE_DIF_FIRST_RDMA_IN_IO_FLG_SHIFT 1
649 #define RDMA_SQ_RDMA_WQE_DIF_LAST_RDMA_IN_IO_FLG_MASK   0x1
650 #define RDMA_SQ_RDMA_WQE_DIF_LAST_RDMA_IN_IO_FLG_SHIFT  2
651 #define RDMA_SQ_RDMA_WQE_RESERVED1_MASK                 0x1F
652 #define RDMA_SQ_RDMA_WQE_RESERVED1_SHIFT                3
653 	u8 reserved2[3];
654 };
655 
656 /* First element (16 bytes) of rdma wqe */
657 struct rdma_sq_rdma_wqe_1st {
658 	__le32 imm_data;
659 	__le32 length;
660 	__le32 xrc_srq;
661 	u8 req_type;
662 	u8 flags;
663 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_MASK         0x1
664 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT        0
665 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK     0x1
666 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT    1
667 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK    0x1
668 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT   2
669 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_MASK           0x1
670 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT          3
671 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK       0x1
672 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT      4
673 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK  0x1
674 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5
675 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK     0x1
676 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_SHIFT    6
677 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK        0x1
678 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT       7
679 	u8 wqe_size;
680 	u8 prev_wqe_size;
681 };
682 
683 /* Second element (16 bytes) of rdma wqe */
684 struct rdma_sq_rdma_wqe_2nd {
685 	struct regpair remote_va;
686 	__le32 r_key;
687 	u8 dif_flags;
688 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_MASK         0x1
689 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_SHIFT        0
690 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_MASK  0x1
691 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_SHIFT 1
692 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_MASK   0x1
693 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_SHIFT  2
694 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_MASK              0x1F
695 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_SHIFT             3
696 	u8 reserved2[3];
697 };
698 
699 /* SQ WQE req type enumeration */
700 enum rdma_sq_req_type {
701 	RDMA_SQ_REQ_TYPE_SEND,
702 	RDMA_SQ_REQ_TYPE_SEND_WITH_IMM,
703 	RDMA_SQ_REQ_TYPE_SEND_WITH_INVALIDATE,
704 	RDMA_SQ_REQ_TYPE_RDMA_WR,
705 	RDMA_SQ_REQ_TYPE_RDMA_WR_WITH_IMM,
706 	RDMA_SQ_REQ_TYPE_RDMA_RD,
707 	RDMA_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP,
708 	RDMA_SQ_REQ_TYPE_ATOMIC_ADD,
709 	RDMA_SQ_REQ_TYPE_LOCAL_INVALIDATE,
710 	RDMA_SQ_REQ_TYPE_FAST_MR,
711 	RDMA_SQ_REQ_TYPE_BIND,
712 	RDMA_SQ_REQ_TYPE_INVALID,
713 	MAX_RDMA_SQ_REQ_TYPE
714 };
715 
716 struct rdma_sq_send_wqe {
717 	__le32 inv_key_or_imm_data;
718 	__le32 length;
719 	__le32 xrc_srq;
720 	u8 req_type;
721 	u8 flags;
722 #define RDMA_SQ_SEND_WQE_COMP_FLG_MASK         0x1
723 #define RDMA_SQ_SEND_WQE_COMP_FLG_SHIFT        0
724 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_MASK     0x1
725 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT    1
726 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_MASK    0x1
727 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT   2
728 #define RDMA_SQ_SEND_WQE_SE_FLG_MASK           0x1
729 #define RDMA_SQ_SEND_WQE_SE_FLG_SHIFT          3
730 #define RDMA_SQ_SEND_WQE_INLINE_FLG_MASK       0x1
731 #define RDMA_SQ_SEND_WQE_INLINE_FLG_SHIFT      4
732 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_MASK  0x1
733 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_SHIFT 5
734 #define RDMA_SQ_SEND_WQE_RESERVED0_MASK        0x3
735 #define RDMA_SQ_SEND_WQE_RESERVED0_SHIFT       6
736 	u8 wqe_size;
737 	u8 prev_wqe_size;
738 	__le32 reserved1[4];
739 };
740 
741 struct rdma_sq_send_wqe_1st {
742 	__le32 inv_key_or_imm_data;
743 	__le32 length;
744 	__le32 xrc_srq;
745 	u8 req_type;
746 	u8 flags;
747 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_MASK       0x1
748 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_SHIFT      0
749 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_MASK   0x1
750 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_SHIFT  1
751 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_MASK  0x1
752 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_SHIFT 2
753 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_MASK         0x1
754 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_SHIFT        3
755 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_MASK     0x1
756 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_SHIFT    4
757 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_MASK      0x7
758 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_SHIFT     5
759 	u8 wqe_size;
760 	u8 prev_wqe_size;
761 };
762 
763 struct rdma_sq_send_wqe_2st {
764 	__le32 reserved1[4];
765 };
766 
767 #endif /* __QED_HSI_RDMA__ */
768