1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QED_HSI_RDMA__ 33 #define __QED_HSI_RDMA__ 34 35 #include <linux/qed/rdma_common.h> 36 37 /* rdma completion notification queue element */ 38 struct rdma_cnqe { 39 struct regpair cq_handle; 40 }; 41 42 struct rdma_cqe_responder { 43 struct regpair srq_wr_id; 44 struct regpair qp_handle; 45 __le32 imm_data_or_inv_r_Key; 46 __le32 length; 47 __le32 imm_data_hi; 48 __le16 rq_cons_or_srq_id; 49 u8 flags; 50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 51 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0 52 #define RDMA_CQE_RESPONDER_TYPE_MASK 0x3 53 #define RDMA_CQE_RESPONDER_TYPE_SHIFT 1 54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1 55 #define RDMA_CQE_RESPONDER_INV_FLG_SHIFT 3 56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1 57 #define RDMA_CQE_RESPONDER_IMM_FLG_SHIFT 4 58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1 59 #define RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT 5 60 #define RDMA_CQE_RESPONDER_RESERVED2_MASK 0x3 61 #define RDMA_CQE_RESPONDER_RESERVED2_SHIFT 6 62 u8 status; 63 }; 64 65 struct rdma_cqe_requester { 66 __le16 sq_cons; 67 __le16 reserved0; 68 __le32 reserved1; 69 struct regpair qp_handle; 70 struct regpair reserved2; 71 __le32 reserved3; 72 __le16 reserved4; 73 u8 flags; 74 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1 75 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0 76 #define RDMA_CQE_REQUESTER_TYPE_MASK 0x3 77 #define RDMA_CQE_REQUESTER_TYPE_SHIFT 1 78 #define RDMA_CQE_REQUESTER_RESERVED5_MASK 0x1F 79 #define RDMA_CQE_REQUESTER_RESERVED5_SHIFT 3 80 u8 status; 81 }; 82 83 struct rdma_cqe_common { 84 struct regpair reserved0; 85 struct regpair qp_handle; 86 __le16 reserved1[7]; 87 u8 flags; 88 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK 0x1 89 #define RDMA_CQE_COMMON_TOGGLE_BIT_SHIFT 0 90 #define RDMA_CQE_COMMON_TYPE_MASK 0x3 91 #define RDMA_CQE_COMMON_TYPE_SHIFT 1 92 #define RDMA_CQE_COMMON_RESERVED2_MASK 0x1F 93 #define RDMA_CQE_COMMON_RESERVED2_SHIFT 3 94 u8 status; 95 }; 96 97 /* rdma completion queue element */ 98 union rdma_cqe { 99 struct rdma_cqe_responder resp; 100 struct rdma_cqe_requester req; 101 struct rdma_cqe_common cmn; 102 }; 103 104 /* * CQE requester status enumeration */ 105 enum rdma_cqe_requester_status_enum { 106 RDMA_CQE_REQ_STS_OK, 107 RDMA_CQE_REQ_STS_BAD_RESPONSE_ERR, 108 RDMA_CQE_REQ_STS_LOCAL_LENGTH_ERR, 109 RDMA_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR, 110 RDMA_CQE_REQ_STS_LOCAL_PROTECTION_ERR, 111 RDMA_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR, 112 RDMA_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR, 113 RDMA_CQE_REQ_STS_REMOTE_ACCESS_ERR, 114 RDMA_CQE_REQ_STS_REMOTE_OPERATION_ERR, 115 RDMA_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR, 116 RDMA_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR, 117 RDMA_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR, 118 RDMA_CQE_REQ_STS_XRC_VOILATION_ERR, 119 RDMA_CQE_REQ_STS_SIG_ERR, 120 MAX_RDMA_CQE_REQUESTER_STATUS_ENUM 121 }; 122 123 /* CQE responder status enumeration */ 124 enum rdma_cqe_responder_status_enum { 125 RDMA_CQE_RESP_STS_OK, 126 RDMA_CQE_RESP_STS_LOCAL_ACCESS_ERR, 127 RDMA_CQE_RESP_STS_LOCAL_LENGTH_ERR, 128 RDMA_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR, 129 RDMA_CQE_RESP_STS_LOCAL_PROTECTION_ERR, 130 RDMA_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR, 131 RDMA_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR, 132 RDMA_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR, 133 MAX_RDMA_CQE_RESPONDER_STATUS_ENUM 134 }; 135 136 /* CQE type enumeration */ 137 enum rdma_cqe_type { 138 RDMA_CQE_TYPE_REQUESTER, 139 RDMA_CQE_TYPE_RESPONDER_RQ, 140 RDMA_CQE_TYPE_RESPONDER_SRQ, 141 RDMA_CQE_TYPE_RESPONDER_XRC_SRQ, 142 RDMA_CQE_TYPE_INVALID, 143 MAX_RDMA_CQE_TYPE 144 }; 145 146 struct rdma_sq_sge { 147 __le32 length; 148 struct regpair addr; 149 __le32 l_key; 150 }; 151 152 struct rdma_rq_sge { 153 struct regpair addr; 154 __le32 length; 155 __le32 flags; 156 #define RDMA_RQ_SGE_L_KEY_LO_MASK 0x3FFFFFF 157 #define RDMA_RQ_SGE_L_KEY_LO_SHIFT 0 158 #define RDMA_RQ_SGE_NUM_SGES_MASK 0x7 159 #define RDMA_RQ_SGE_NUM_SGES_SHIFT 26 160 #define RDMA_RQ_SGE_L_KEY_HI_MASK 0x7 161 #define RDMA_RQ_SGE_L_KEY_HI_SHIFT 29 162 }; 163 164 struct rdma_srq_sge { 165 struct regpair addr; 166 __le32 length; 167 __le32 l_key; 168 }; 169 170 /* Rdma doorbell data for flags update */ 171 struct rdma_pwm_flags_data { 172 __le16 icid; /* internal CID */ 173 u8 agg_flags; /* aggregative flags */ 174 u8 reserved; 175 }; 176 177 /* Rdma doorbell data for SQ and RQ */ 178 struct rdma_pwm_val16_data { 179 __le16 icid; 180 __le16 value; 181 }; 182 183 union rdma_pwm_val16_data_union { 184 struct rdma_pwm_val16_data as_struct; 185 __le32 as_dword; 186 }; 187 188 /* Rdma doorbell data for CQ */ 189 struct rdma_pwm_val32_data { 190 __le16 icid; 191 u8 agg_flags; 192 u8 params; 193 #define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 194 #define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 195 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 196 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 197 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1 198 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT 3 199 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK 0x1 200 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_SHIFT 4 201 #define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x7 202 #define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT 5 203 __le32 value; 204 }; 205 206 /* DIF Block size options */ 207 enum rdma_dif_block_size { 208 RDMA_DIF_BLOCK_512 = 0, 209 RDMA_DIF_BLOCK_4096 = 1, 210 MAX_RDMA_DIF_BLOCK_SIZE 211 }; 212 213 /* DIF CRC initial value */ 214 enum rdma_dif_crc_seed { 215 RDMA_DIF_CRC_SEED_0000 = 0, 216 RDMA_DIF_CRC_SEED_FFFF = 1, 217 MAX_RDMA_DIF_CRC_SEED 218 }; 219 220 /* RDMA DIF Error Result Structure */ 221 struct rdma_dif_error_result { 222 __le32 error_intervals; 223 __le32 dif_error_1st_interval; 224 u8 flags; 225 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK 0x1 226 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_SHIFT 0 227 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK 0x1 228 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_SHIFT 1 229 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK 0x1 230 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_SHIFT 2 231 #define RDMA_DIF_ERROR_RESULT_RESERVED0_MASK 0xF 232 #define RDMA_DIF_ERROR_RESULT_RESERVED0_SHIFT 3 233 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK 0x1 234 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_SHIFT 7 235 u8 reserved1[55]; 236 }; 237 238 /* DIF IO direction */ 239 enum rdma_dif_io_direction_flg { 240 RDMA_DIF_DIR_RX = 0, 241 RDMA_DIF_DIR_TX = 1, 242 MAX_RDMA_DIF_IO_DIRECTION_FLG 243 }; 244 245 struct rdma_dif_params { 246 __le32 base_ref_tag; 247 __le16 app_tag; 248 __le16 app_tag_mask; 249 __le16 runt_crc_value; 250 __le16 flags; 251 #define RDMA_DIF_PARAMS_IO_DIRECTION_FLG_MASK 0x1 252 #define RDMA_DIF_PARAMS_IO_DIRECTION_FLG_SHIFT 0 253 #define RDMA_DIF_PARAMS_BLOCK_SIZE_MASK 0x1 254 #define RDMA_DIF_PARAMS_BLOCK_SIZE_SHIFT 1 255 #define RDMA_DIF_PARAMS_RUNT_VALID_FLG_MASK 0x1 256 #define RDMA_DIF_PARAMS_RUNT_VALID_FLG_SHIFT 2 257 #define RDMA_DIF_PARAMS_VALIDATE_CRC_GUARD_MASK 0x1 258 #define RDMA_DIF_PARAMS_VALIDATE_CRC_GUARD_SHIFT 3 259 #define RDMA_DIF_PARAMS_VALIDATE_REF_TAG_MASK 0x1 260 #define RDMA_DIF_PARAMS_VALIDATE_REF_TAG_SHIFT 4 261 #define RDMA_DIF_PARAMS_VALIDATE_APP_TAG_MASK 0x1 262 #define RDMA_DIF_PARAMS_VALIDATE_APP_TAG_SHIFT 5 263 #define RDMA_DIF_PARAMS_CRC_SEED_MASK 0x1 264 #define RDMA_DIF_PARAMS_CRC_SEED_SHIFT 6 265 #define RDMA_DIF_PARAMS_RX_REF_TAG_CONST_MASK 0x1 266 #define RDMA_DIF_PARAMS_RX_REF_TAG_CONST_SHIFT 7 267 #define RDMA_DIF_PARAMS_BLOCK_GUARD_TYPE_MASK 0x1 268 #define RDMA_DIF_PARAMS_BLOCK_GUARD_TYPE_SHIFT 8 269 #define RDMA_DIF_PARAMS_APP_ESCAPE_MASK 0x1 270 #define RDMA_DIF_PARAMS_APP_ESCAPE_SHIFT 9 271 #define RDMA_DIF_PARAMS_REF_ESCAPE_MASK 0x1 272 #define RDMA_DIF_PARAMS_REF_ESCAPE_SHIFT 10 273 #define RDMA_DIF_PARAMS_RESERVED4_MASK 0x1F 274 #define RDMA_DIF_PARAMS_RESERVED4_SHIFT 11 275 __le32 reserved5; 276 }; 277 278 279 struct rdma_sq_atomic_wqe { 280 __le32 reserved1; 281 __le32 length; 282 __le32 xrc_srq; 283 u8 req_type; 284 u8 flags; 285 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1 286 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0 287 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1 288 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT 1 289 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1 290 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT 2 291 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1 292 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_SHIFT 3 293 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1 294 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT 4 295 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_MASK 0x1 296 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_SHIFT 5 297 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_MASK 0x3 298 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_SHIFT 6 299 u8 wqe_size; 300 u8 prev_wqe_size; 301 struct regpair remote_va; 302 __le32 r_key; 303 __le32 reserved2; 304 struct regpair cmp_data; 305 struct regpair swap_data; 306 }; 307 308 /* First element (16 bytes) of atomic wqe */ 309 struct rdma_sq_atomic_wqe_1st { 310 __le32 reserved1; 311 __le32 length; 312 __le32 xrc_srq; 313 u8 req_type; 314 u8 flags; 315 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1 316 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0 317 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1 318 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT 1 319 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1 320 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2 321 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1 322 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT 3 323 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1 324 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT 4 325 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7 326 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT 5 327 u8 wqe_size; 328 u8 prev_wqe_size; 329 }; 330 331 /* Second element (16 bytes) of atomic wqe */ 332 struct rdma_sq_atomic_wqe_2nd { 333 struct regpair remote_va; 334 __le32 r_key; 335 __le32 reserved2; 336 }; 337 338 /* Third element (16 bytes) of atomic wqe */ 339 struct rdma_sq_atomic_wqe_3rd { 340 struct regpair cmp_data; 341 struct regpair swap_data; 342 }; 343 344 struct rdma_sq_bind_wqe { 345 struct regpair addr; 346 __le32 l_key; 347 u8 req_type; 348 u8 flags; 349 #define RDMA_SQ_BIND_WQE_COMP_FLG_MASK 0x1 350 #define RDMA_SQ_BIND_WQE_COMP_FLG_SHIFT 0 351 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1 352 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT 1 353 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1 354 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2 355 #define RDMA_SQ_BIND_WQE_SE_FLG_MASK 0x1 356 #define RDMA_SQ_BIND_WQE_SE_FLG_SHIFT 3 357 #define RDMA_SQ_BIND_WQE_INLINE_FLG_MASK 0x1 358 #define RDMA_SQ_BIND_WQE_INLINE_FLG_SHIFT 4 359 #define RDMA_SQ_BIND_WQE_DIF_ON_HOST_FLG_MASK 0x1 360 #define RDMA_SQ_BIND_WQE_DIF_ON_HOST_FLG_SHIFT 5 361 #define RDMA_SQ_BIND_WQE_RESERVED0_MASK 0x3 362 #define RDMA_SQ_BIND_WQE_RESERVED0_SHIFT 6 363 u8 wqe_size; 364 u8 prev_wqe_size; 365 u8 bind_ctrl; 366 #define RDMA_SQ_BIND_WQE_ZERO_BASED_MASK 0x1 367 #define RDMA_SQ_BIND_WQE_ZERO_BASED_SHIFT 0 368 #define RDMA_SQ_BIND_WQE_RESERVED1_MASK 0x7F 369 #define RDMA_SQ_BIND_WQE_RESERVED1_SHIFT 1 370 u8 access_ctrl; 371 #define RDMA_SQ_BIND_WQE_REMOTE_READ_MASK 0x1 372 #define RDMA_SQ_BIND_WQE_REMOTE_READ_SHIFT 0 373 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1 374 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_SHIFT 1 375 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1 376 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2 377 #define RDMA_SQ_BIND_WQE_LOCAL_READ_MASK 0x1 378 #define RDMA_SQ_BIND_WQE_LOCAL_READ_SHIFT 3 379 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1 380 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_SHIFT 4 381 #define RDMA_SQ_BIND_WQE_RESERVED2_MASK 0x7 382 #define RDMA_SQ_BIND_WQE_RESERVED2_SHIFT 5 383 u8 reserved3; 384 u8 length_hi; 385 __le32 length_lo; 386 __le32 parent_l_key; 387 __le32 reserved4; 388 struct rdma_dif_params dif_params; 389 }; 390 391 /* First element (16 bytes) of bind wqe */ 392 struct rdma_sq_bind_wqe_1st { 393 struct regpair addr; 394 __le32 l_key; 395 u8 req_type; 396 u8 flags; 397 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1 398 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0 399 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 400 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 401 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 402 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 403 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1 404 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_SHIFT 3 405 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1 406 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT 4 407 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7 408 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_SHIFT 5 409 u8 wqe_size; 410 u8 prev_wqe_size; 411 }; 412 413 /* Second element (16 bytes) of bind wqe */ 414 struct rdma_sq_bind_wqe_2nd { 415 u8 bind_ctrl; 416 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1 417 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0 418 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_MASK 0x7F 419 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_SHIFT 1 420 u8 access_ctrl; 421 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_MASK 0x1 422 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_SHIFT 0 423 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_MASK 0x1 424 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_SHIFT 1 425 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_MASK 0x1 426 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_SHIFT 2 427 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_MASK 0x1 428 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_SHIFT 3 429 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_MASK 0x1 430 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_SHIFT 4 431 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x7 432 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_SHIFT 5 433 u8 reserved3; 434 u8 length_hi; 435 __le32 length_lo; 436 __le32 parent_l_key; 437 __le32 reserved4; 438 }; 439 440 /* Third element (16 bytes) of bind wqe */ 441 struct rdma_sq_bind_wqe_3rd { 442 struct rdma_dif_params dif_params; 443 }; 444 445 /* Structure with only the SQ WQE common 446 * fields. Size is of one SQ element (16B) 447 */ 448 struct rdma_sq_common_wqe { 449 __le32 reserved1[3]; 450 u8 req_type; 451 u8 flags; 452 #define RDMA_SQ_COMMON_WQE_COMP_FLG_MASK 0x1 453 #define RDMA_SQ_COMMON_WQE_COMP_FLG_SHIFT 0 454 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1 455 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT 1 456 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1 457 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2 458 #define RDMA_SQ_COMMON_WQE_SE_FLG_MASK 0x1 459 #define RDMA_SQ_COMMON_WQE_SE_FLG_SHIFT 3 460 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1 461 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_SHIFT 4 462 #define RDMA_SQ_COMMON_WQE_RESERVED0_MASK 0x7 463 #define RDMA_SQ_COMMON_WQE_RESERVED0_SHIFT 5 464 u8 wqe_size; 465 u8 prev_wqe_size; 466 }; 467 468 struct rdma_sq_fmr_wqe { 469 struct regpair addr; 470 __le32 l_key; 471 u8 req_type; 472 u8 flags; 473 #define RDMA_SQ_FMR_WQE_COMP_FLG_MASK 0x1 474 #define RDMA_SQ_FMR_WQE_COMP_FLG_SHIFT 0 475 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1 476 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT 1 477 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1 478 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT 2 479 #define RDMA_SQ_FMR_WQE_SE_FLG_MASK 0x1 480 #define RDMA_SQ_FMR_WQE_SE_FLG_SHIFT 3 481 #define RDMA_SQ_FMR_WQE_INLINE_FLG_MASK 0x1 482 #define RDMA_SQ_FMR_WQE_INLINE_FLG_SHIFT 4 483 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_MASK 0x1 484 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_SHIFT 5 485 #define RDMA_SQ_FMR_WQE_RESERVED0_MASK 0x3 486 #define RDMA_SQ_FMR_WQE_RESERVED0_SHIFT 6 487 u8 wqe_size; 488 u8 prev_wqe_size; 489 u8 fmr_ctrl; 490 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F 491 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0 492 #define RDMA_SQ_FMR_WQE_ZERO_BASED_MASK 0x1 493 #define RDMA_SQ_FMR_WQE_ZERO_BASED_SHIFT 5 494 #define RDMA_SQ_FMR_WQE_BIND_EN_MASK 0x1 495 #define RDMA_SQ_FMR_WQE_BIND_EN_SHIFT 6 496 #define RDMA_SQ_FMR_WQE_RESERVED1_MASK 0x1 497 #define RDMA_SQ_FMR_WQE_RESERVED1_SHIFT 7 498 u8 access_ctrl; 499 #define RDMA_SQ_FMR_WQE_REMOTE_READ_MASK 0x1 500 #define RDMA_SQ_FMR_WQE_REMOTE_READ_SHIFT 0 501 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1 502 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_SHIFT 1 503 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1 504 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT 2 505 #define RDMA_SQ_FMR_WQE_LOCAL_READ_MASK 0x1 506 #define RDMA_SQ_FMR_WQE_LOCAL_READ_SHIFT 3 507 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1 508 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_SHIFT 4 509 #define RDMA_SQ_FMR_WQE_RESERVED2_MASK 0x7 510 #define RDMA_SQ_FMR_WQE_RESERVED2_SHIFT 5 511 u8 reserved3; 512 u8 length_hi; 513 __le32 length_lo; 514 struct regpair pbl_addr; 515 }; 516 517 /* First element (16 bytes) of fmr wqe */ 518 struct rdma_sq_fmr_wqe_1st { 519 struct regpair addr; 520 __le32 l_key; 521 u8 req_type; 522 u8 flags; 523 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1 524 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0 525 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1 526 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT 1 527 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1 528 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT 2 529 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1 530 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_SHIFT 3 531 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1 532 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT 4 533 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1 534 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5 535 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x3 536 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_SHIFT 6 537 u8 wqe_size; 538 u8 prev_wqe_size; 539 }; 540 541 /* Second element (16 bytes) of fmr wqe */ 542 struct rdma_sq_fmr_wqe_2nd { 543 u8 fmr_ctrl; 544 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F 545 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0 546 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1 547 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT 5 548 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1 549 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_SHIFT 6 550 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_MASK 0x1 551 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_SHIFT 7 552 u8 access_ctrl; 553 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_MASK 0x1 554 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_SHIFT 0 555 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_MASK 0x1 556 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_SHIFT 1 557 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_MASK 0x1 558 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_SHIFT 2 559 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_MASK 0x1 560 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_SHIFT 3 561 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_MASK 0x1 562 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_SHIFT 4 563 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x7 564 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_SHIFT 5 565 u8 reserved3; 566 u8 length_hi; 567 __le32 length_lo; 568 struct regpair pbl_addr; 569 }; 570 571 572 struct rdma_sq_local_inv_wqe { 573 struct regpair reserved; 574 __le32 inv_l_key; 575 u8 req_type; 576 u8 flags; 577 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1 578 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0 579 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1 580 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT 1 581 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1 582 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT 2 583 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1 584 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT 3 585 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1 586 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT 4 587 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_MASK 0x1 588 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_SHIFT 5 589 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x3 590 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT 6 591 u8 wqe_size; 592 u8 prev_wqe_size; 593 }; 594 595 struct rdma_sq_rdma_wqe { 596 __le32 imm_data; 597 __le32 length; 598 __le32 xrc_srq; 599 u8 req_type; 600 u8 flags; 601 #define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK 0x1 602 #define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT 0 603 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1 604 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1 605 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1 606 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2 607 #define RDMA_SQ_RDMA_WQE_SE_FLG_MASK 0x1 608 #define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT 3 609 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1 610 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4 611 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1 612 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT 5 613 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK 0x1 614 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_SHIFT 6 615 #define RDMA_SQ_RDMA_WQE_RESERVED1_MASK 0x1 616 #define RDMA_SQ_RDMA_WQE_RESERVED1_SHIFT 7 617 u8 wqe_size; 618 u8 prev_wqe_size; 619 struct regpair remote_va; 620 __le32 r_key; 621 u8 dif_flags; 622 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_MASK 0x1 623 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_SHIFT 0 624 #define RDMA_SQ_RDMA_WQE_RESERVED2_MASK 0x7F 625 #define RDMA_SQ_RDMA_WQE_RESERVED2_SHIFT 1 626 u8 reserved3[3]; 627 }; 628 629 /* First element (16 bytes) of rdma wqe */ 630 struct rdma_sq_rdma_wqe_1st { 631 __le32 imm_data; 632 __le32 length; 633 __le32 xrc_srq; 634 u8 req_type; 635 u8 flags; 636 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1 637 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0 638 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1 639 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT 1 640 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1 641 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT 2 642 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1 643 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT 3 644 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1 645 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4 646 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1 647 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_SHIFT 5 648 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK 0x1 649 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_SHIFT 6 650 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x1 651 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 7 652 u8 wqe_size; 653 u8 prev_wqe_size; 654 }; 655 656 /* Second element (16 bytes) of rdma wqe */ 657 struct rdma_sq_rdma_wqe_2nd { 658 struct regpair remote_va; 659 __le32 r_key; 660 u8 dif_flags; 661 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_MASK 0x1 662 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_SHIFT 0 663 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_MASK 0x1 664 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_SHIFT 1 665 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_MASK 0x1 666 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_SHIFT 2 667 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_MASK 0x1F 668 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_SHIFT 3 669 u8 reserved2[3]; 670 }; 671 672 /* SQ WQE req type enumeration */ 673 enum rdma_sq_req_type { 674 RDMA_SQ_REQ_TYPE_SEND, 675 RDMA_SQ_REQ_TYPE_SEND_WITH_IMM, 676 RDMA_SQ_REQ_TYPE_SEND_WITH_INVALIDATE, 677 RDMA_SQ_REQ_TYPE_RDMA_WR, 678 RDMA_SQ_REQ_TYPE_RDMA_WR_WITH_IMM, 679 RDMA_SQ_REQ_TYPE_RDMA_RD, 680 RDMA_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP, 681 RDMA_SQ_REQ_TYPE_ATOMIC_ADD, 682 RDMA_SQ_REQ_TYPE_LOCAL_INVALIDATE, 683 RDMA_SQ_REQ_TYPE_FAST_MR, 684 RDMA_SQ_REQ_TYPE_BIND, 685 RDMA_SQ_REQ_TYPE_INVALID, 686 MAX_RDMA_SQ_REQ_TYPE 687 }; 688 689 struct rdma_sq_send_wqe { 690 __le32 inv_key_or_imm_data; 691 __le32 length; 692 __le32 xrc_srq; 693 u8 req_type; 694 u8 flags; 695 #define RDMA_SQ_SEND_WQE_COMP_FLG_MASK 0x1 696 #define RDMA_SQ_SEND_WQE_COMP_FLG_SHIFT 0 697 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1 698 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT 1 699 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1 700 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT 2 701 #define RDMA_SQ_SEND_WQE_SE_FLG_MASK 0x1 702 #define RDMA_SQ_SEND_WQE_SE_FLG_SHIFT 3 703 #define RDMA_SQ_SEND_WQE_INLINE_FLG_MASK 0x1 704 #define RDMA_SQ_SEND_WQE_INLINE_FLG_SHIFT 4 705 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_MASK 0x1 706 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_SHIFT 5 707 #define RDMA_SQ_SEND_WQE_RESERVED0_MASK 0x3 708 #define RDMA_SQ_SEND_WQE_RESERVED0_SHIFT 6 709 u8 wqe_size; 710 u8 prev_wqe_size; 711 __le32 reserved1[4]; 712 }; 713 714 struct rdma_sq_send_wqe_1st { 715 __le32 inv_key_or_imm_data; 716 __le32 length; 717 __le32 xrc_srq; 718 u8 req_type; 719 u8 flags; 720 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_MASK 0x1 721 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_SHIFT 0 722 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 723 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 724 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 725 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 726 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_MASK 0x1 727 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_SHIFT 3 728 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_MASK 0x1 729 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_SHIFT 4 730 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_MASK 0x7 731 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_SHIFT 5 732 u8 wqe_size; 733 u8 prev_wqe_size; 734 }; 735 736 struct rdma_sq_send_wqe_2st { 737 __le32 reserved1[4]; 738 }; 739 740 #endif /* __QED_HSI_RDMA__ */ 741