1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QEDR_H__ 33 #define __QEDR_H__ 34 35 #include <linux/pci.h> 36 #include <rdma/ib_addr.h> 37 #include <linux/qed/qed_if.h> 38 #include <linux/qed/qed_chain.h> 39 #include <linux/qed/qed_roce_if.h> 40 #include <linux/qed/qede_roce.h> 41 #include <linux/qed/roce_common.h> 42 #include "qedr_hsi_rdma.h" 43 44 #define QEDR_MODULE_VERSION "8.10.10.0" 45 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 46 #define DP_NAME(dev) ((dev)->ibdev.name) 47 48 #define DP_DEBUG(dev, module, fmt, ...) \ 49 pr_debug("(%s) " module ": " fmt, \ 50 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 51 52 #define QEDR_MSG_INIT "INIT" 53 #define QEDR_MSG_MISC "MISC" 54 #define QEDR_MSG_CQ " CQ" 55 #define QEDR_MSG_MR " MR" 56 #define QEDR_MSG_RQ " RQ" 57 #define QEDR_MSG_SQ " SQ" 58 #define QEDR_MSG_QP " QP" 59 #define QEDR_MSG_GSI " GSI" 60 61 #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 62 63 #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) 64 #define FW_PAGE_SHIFT (12) 65 66 struct qedr_dev; 67 68 struct qedr_cnq { 69 struct qedr_dev *dev; 70 struct qed_chain pbl; 71 struct qed_sb_info *sb; 72 char name[32]; 73 u64 n_comp; 74 __le16 *hw_cons_ptr; 75 u8 index; 76 }; 77 78 #define QEDR_MAX_SGID 128 79 80 struct qedr_device_attr { 81 u32 vendor_id; 82 u32 vendor_part_id; 83 u32 hw_ver; 84 u64 fw_ver; 85 u64 node_guid; 86 u64 sys_image_guid; 87 u8 max_cnq; 88 u8 max_sge; 89 u16 max_inline; 90 u32 max_sqe; 91 u32 max_rqe; 92 u8 max_qp_resp_rd_atomic_resc; 93 u8 max_qp_req_rd_atomic_resc; 94 u64 max_dev_resp_rd_atomic_resc; 95 u32 max_cq; 96 u32 max_qp; 97 u32 max_mr; 98 u64 max_mr_size; 99 u32 max_cqe; 100 u32 max_mw; 101 u32 max_fmr; 102 u32 max_mr_mw_fmr_pbl; 103 u64 max_mr_mw_fmr_size; 104 u32 max_pd; 105 u32 max_ah; 106 u8 max_pkey; 107 u32 max_srq; 108 u32 max_srq_wr; 109 u8 max_srq_sge; 110 u8 max_stats_queues; 111 u32 dev_caps; 112 113 u64 page_size_caps; 114 u8 dev_ack_delay; 115 u32 reserved_lkey; 116 u32 bad_pkey_counter; 117 struct qed_rdma_events events; 118 }; 119 120 #define QEDR_ENET_STATE_BIT (0) 121 122 struct qedr_dev { 123 struct ib_device ibdev; 124 struct qed_dev *cdev; 125 struct pci_dev *pdev; 126 struct net_device *ndev; 127 128 enum ib_atomic_cap atomic_cap; 129 130 void *rdma_ctx; 131 struct qedr_device_attr attr; 132 133 const struct qed_rdma_ops *ops; 134 struct qed_int_info int_info; 135 136 struct qed_sb_info *sb_array; 137 struct qedr_cnq *cnq_array; 138 int num_cnq; 139 int sb_start; 140 141 void __iomem *db_addr; 142 u64 db_phys_addr; 143 u32 db_size; 144 u16 dpi; 145 146 union ib_gid *sgid_tbl; 147 148 /* Lock for sgid table */ 149 spinlock_t sgid_lock; 150 151 u64 guid; 152 153 u32 dp_module; 154 u8 dp_level; 155 u8 num_hwfns; 156 uint wq_multiplier; 157 u8 gsi_ll2_mac_address[ETH_ALEN]; 158 int gsi_qp_created; 159 struct qedr_cq *gsi_sqcq; 160 struct qedr_cq *gsi_rqcq; 161 struct qedr_qp *gsi_qp; 162 163 unsigned long enet_state; 164 }; 165 166 #define QEDR_MAX_SQ_PBL (0x8000) 167 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 168 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 169 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 170 QEDR_SQE_ELEMENT_SIZE) 171 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 172 QEDR_SQE_ELEMENT_SIZE) 173 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 174 (RDMA_RING_PAGE_SIZE) / \ 175 (QEDR_SQE_ELEMENT_SIZE) /\ 176 (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 177 /* RQ */ 178 #define QEDR_MAX_RQ_PBL (0x2000) 179 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 180 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 181 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 182 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 183 QEDR_RQE_ELEMENT_SIZE) 184 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 185 (RDMA_RING_PAGE_SIZE) / \ 186 (QEDR_RQE_ELEMENT_SIZE) /\ 187 (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 188 189 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 190 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 191 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 192 sizeof(u64)) - 1) 193 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 194 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 195 196 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 197 198 #define QEDR_MAX_PORT (1) 199 #define QEDR_PORT (1) 200 201 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 202 203 #define QEDR_ROCE_PKEY_MAX 1 204 #define QEDR_ROCE_PKEY_TABLE_LEN 1 205 #define QEDR_ROCE_PKEY_DEFAULT 0xffff 206 207 struct qedr_pbl { 208 struct list_head list_entry; 209 void *va; 210 dma_addr_t pa; 211 }; 212 213 struct qedr_ucontext { 214 struct ib_ucontext ibucontext; 215 struct qedr_dev *dev; 216 struct qedr_pd *pd; 217 u64 dpi_addr; 218 u64 dpi_phys_addr; 219 u32 dpi_size; 220 u16 dpi; 221 222 struct list_head mm_head; 223 224 /* Lock to protect mm list */ 225 struct mutex mm_list_lock; 226 }; 227 228 union db_prod64 { 229 struct rdma_pwm_val32_data data; 230 u64 raw; 231 }; 232 233 enum qedr_cq_type { 234 QEDR_CQ_TYPE_GSI, 235 QEDR_CQ_TYPE_KERNEL, 236 QEDR_CQ_TYPE_USER, 237 }; 238 239 struct qedr_pbl_info { 240 u32 num_pbls; 241 u32 num_pbes; 242 u32 pbl_size; 243 u32 pbe_size; 244 bool two_layered; 245 }; 246 247 struct qedr_userq { 248 struct ib_umem *umem; 249 struct qedr_pbl_info pbl_info; 250 struct qedr_pbl *pbl_tbl; 251 u64 buf_addr; 252 size_t buf_len; 253 }; 254 255 struct qedr_cq { 256 struct ib_cq ibcq; 257 258 enum qedr_cq_type cq_type; 259 u32 sig; 260 261 u16 icid; 262 263 /* Lock to protect multiplem CQ's */ 264 spinlock_t cq_lock; 265 u8 arm_flags; 266 struct qed_chain pbl; 267 268 void __iomem *db_addr; 269 union db_prod64 db; 270 271 u8 pbl_toggle; 272 union rdma_cqe *latest_cqe; 273 union rdma_cqe *toggle_cqe; 274 275 u32 cq_cons; 276 277 struct qedr_userq q; 278 u8 destroyed; 279 u16 cnq_notif; 280 }; 281 282 struct qedr_pd { 283 struct ib_pd ibpd; 284 u32 pd_id; 285 struct qedr_ucontext *uctx; 286 }; 287 288 struct qedr_mm { 289 struct { 290 u64 phy_addr; 291 unsigned long len; 292 } key; 293 struct list_head entry; 294 }; 295 296 union db_prod32 { 297 struct rdma_pwm_val16_data data; 298 u32 raw; 299 }; 300 301 struct qedr_qp_hwq_info { 302 /* WQE Elements */ 303 struct qed_chain pbl; 304 u64 p_phys_addr_tbl; 305 u32 max_sges; 306 307 /* WQE */ 308 u16 prod; 309 u16 cons; 310 u16 wqe_cons; 311 u16 gsi_cons; 312 u16 max_wr; 313 314 /* DB */ 315 void __iomem *db; 316 union db_prod32 db_data; 317 }; 318 319 #define QEDR_INC_SW_IDX(p_info, index) \ 320 do { \ 321 p_info->index = (p_info->index + 1) & \ 322 qed_chain_get_capacity(p_info->pbl) \ 323 } while (0) 324 325 enum qedr_qp_err_bitmap { 326 QEDR_QP_ERR_SQ_FULL = 1, 327 QEDR_QP_ERR_RQ_FULL = 2, 328 QEDR_QP_ERR_BAD_SR = 4, 329 QEDR_QP_ERR_BAD_RR = 8, 330 QEDR_QP_ERR_SQ_PBL_FULL = 16, 331 QEDR_QP_ERR_RQ_PBL_FULL = 32, 332 }; 333 334 struct qedr_qp { 335 struct ib_qp ibqp; /* must be first */ 336 struct qedr_dev *dev; 337 338 struct qedr_qp_hwq_info sq; 339 struct qedr_qp_hwq_info rq; 340 341 u32 max_inline_data; 342 343 /* Lock for QP's */ 344 spinlock_t q_lock; 345 struct qedr_cq *sq_cq; 346 struct qedr_cq *rq_cq; 347 struct qedr_srq *srq; 348 enum qed_roce_qp_state state; 349 u32 id; 350 struct qedr_pd *pd; 351 enum ib_qp_type qp_type; 352 struct qed_rdma_qp *qed_qp; 353 u32 qp_id; 354 u16 icid; 355 u16 mtu; 356 int sgid_idx; 357 u32 rq_psn; 358 u32 sq_psn; 359 u32 qkey; 360 u32 dest_qp_num; 361 362 /* Relevant to qps created from kernel space only (ULPs) */ 363 u8 prev_wqe_size; 364 u16 wqe_cons; 365 u32 err_bitmap; 366 bool signaled; 367 368 /* SQ shadow */ 369 struct { 370 u64 wr_id; 371 enum ib_wc_opcode opcode; 372 u32 bytes_len; 373 u8 wqe_size; 374 bool signaled; 375 dma_addr_t icrc_mapping; 376 u32 *icrc; 377 struct qedr_mr *mr; 378 } *wqe_wr_id; 379 380 /* RQ shadow */ 381 struct { 382 u64 wr_id; 383 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 384 u8 wqe_size; 385 386 u8 smac[ETH_ALEN]; 387 u16 vlan_id; 388 int rc; 389 } *rqe_wr_id; 390 391 /* Relevant to qps created from user space only (applications) */ 392 struct qedr_userq usq; 393 struct qedr_userq urq; 394 }; 395 396 struct qedr_ah { 397 struct ib_ah ibah; 398 struct rdma_ah_attr attr; 399 }; 400 401 enum qedr_mr_type { 402 QEDR_MR_USER, 403 QEDR_MR_KERNEL, 404 QEDR_MR_DMA, 405 QEDR_MR_FRMR, 406 }; 407 408 struct mr_info { 409 struct qedr_pbl *pbl_table; 410 struct qedr_pbl_info pbl_info; 411 struct list_head free_pbl_list; 412 struct list_head inuse_pbl_list; 413 u32 completed; 414 u32 completed_handled; 415 }; 416 417 struct qedr_mr { 418 struct ib_mr ibmr; 419 struct ib_umem *umem; 420 421 struct qed_rdma_register_tid_in_params hw_mr; 422 enum qedr_mr_type type; 423 424 struct qedr_dev *dev; 425 struct mr_info info; 426 427 u64 *pages; 428 u32 npages; 429 }; 430 431 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) 432 433 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 434 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 435 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 436 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 437 #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ 438 RDMA_CQE_RESPONDER_INV_FLG_SHIFT) 439 440 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) 441 { 442 info->cons = (info->cons + 1) % info->max_wr; 443 info->wqe_cons++; 444 } 445 446 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) 447 { 448 info->prod = (info->prod + 1) % info->max_wr; 449 } 450 451 static inline int qedr_get_dmac(struct qedr_dev *dev, 452 struct rdma_ah_attr *ah_attr, u8 *mac_addr) 453 { 454 union ib_gid zero_sgid = { { 0 } }; 455 struct in6_addr in6; 456 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 457 u8 *dmac; 458 459 if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) { 460 DP_ERR(dev, "Local port GID not supported\n"); 461 eth_zero_addr(mac_addr); 462 return -EINVAL; 463 } 464 465 memcpy(&in6, grh->dgid.raw, sizeof(in6)); 466 dmac = rdma_ah_retrieve_dmac(ah_attr); 467 if (!dmac) 468 return -EINVAL; 469 ether_addr_copy(mac_addr, dmac); 470 471 return 0; 472 } 473 474 static inline 475 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 476 { 477 return container_of(ibucontext, struct qedr_ucontext, ibucontext); 478 } 479 480 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 481 { 482 return container_of(ibdev, struct qedr_dev, ibdev); 483 } 484 485 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 486 { 487 return container_of(ibpd, struct qedr_pd, ibpd); 488 } 489 490 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 491 { 492 return container_of(ibcq, struct qedr_cq, ibcq); 493 } 494 495 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 496 { 497 return container_of(ibqp, struct qedr_qp, ibqp); 498 } 499 500 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) 501 { 502 return container_of(ibah, struct qedr_ah, ibah); 503 } 504 505 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) 506 { 507 return container_of(ibmr, struct qedr_mr, ibmr); 508 } 509 #endif 510