1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QEDR_H__ 33 #define __QEDR_H__ 34 35 #include <linux/pci.h> 36 #include <linux/xarray.h> 37 #include <rdma/ib_addr.h> 38 #include <linux/qed/qed_if.h> 39 #include <linux/qed/qed_chain.h> 40 #include <linux/qed/qed_rdma_if.h> 41 #include <linux/qed/qede_rdma.h> 42 #include <linux/qed/roce_common.h> 43 #include "qedr_hsi_rdma.h" 44 45 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 46 #define DP_NAME(_dev) dev_name(&(_dev)->ibdev.dev) 47 #define IS_IWARP(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_IWARP) 48 #define IS_ROCE(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_ROCE) 49 50 #define DP_DEBUG(dev, module, fmt, ...) \ 51 pr_debug("(%s) " module ": " fmt, \ 52 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 53 54 #define QEDR_MSG_INIT "INIT" 55 #define QEDR_MSG_MISC "MISC" 56 #define QEDR_MSG_CQ " CQ" 57 #define QEDR_MSG_MR " MR" 58 #define QEDR_MSG_RQ " RQ" 59 #define QEDR_MSG_SQ " SQ" 60 #define QEDR_MSG_QP " QP" 61 #define QEDR_MSG_SRQ " SRQ" 62 #define QEDR_MSG_GSI " GSI" 63 #define QEDR_MSG_IWARP " IW" 64 65 #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 66 67 #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) 68 #define FW_PAGE_SHIFT (12) 69 70 struct qedr_dev; 71 72 struct qedr_cnq { 73 struct qedr_dev *dev; 74 struct qed_chain pbl; 75 struct qed_sb_info *sb; 76 char name[32]; 77 u64 n_comp; 78 __le16 *hw_cons_ptr; 79 u8 index; 80 }; 81 82 #define QEDR_MAX_SGID 128 83 84 struct qedr_device_attr { 85 u32 vendor_id; 86 u32 vendor_part_id; 87 u32 hw_ver; 88 u64 fw_ver; 89 u64 node_guid; 90 u64 sys_image_guid; 91 u8 max_cnq; 92 u8 max_sge; 93 u16 max_inline; 94 u32 max_sqe; 95 u32 max_rqe; 96 u8 max_qp_resp_rd_atomic_resc; 97 u8 max_qp_req_rd_atomic_resc; 98 u64 max_dev_resp_rd_atomic_resc; 99 u32 max_cq; 100 u32 max_qp; 101 u32 max_mr; 102 u64 max_mr_size; 103 u32 max_cqe; 104 u32 max_mw; 105 u32 max_fmr; 106 u32 max_mr_mw_fmr_pbl; 107 u64 max_mr_mw_fmr_size; 108 u32 max_pd; 109 u32 max_ah; 110 u8 max_pkey; 111 u32 max_srq; 112 u32 max_srq_wr; 113 u8 max_srq_sge; 114 u8 max_stats_queues; 115 u32 dev_caps; 116 117 u64 page_size_caps; 118 u8 dev_ack_delay; 119 u32 reserved_lkey; 120 u32 bad_pkey_counter; 121 struct qed_rdma_events events; 122 }; 123 124 #define QEDR_ENET_STATE_BIT (0) 125 126 struct qedr_dev { 127 struct ib_device ibdev; 128 struct qed_dev *cdev; 129 struct pci_dev *pdev; 130 struct net_device *ndev; 131 132 enum ib_atomic_cap atomic_cap; 133 134 void *rdma_ctx; 135 struct qedr_device_attr attr; 136 137 const struct qed_rdma_ops *ops; 138 struct qed_int_info int_info; 139 140 struct qed_sb_info *sb_array; 141 struct qedr_cnq *cnq_array; 142 int num_cnq; 143 int sb_start; 144 145 void __iomem *db_addr; 146 u64 db_phys_addr; 147 u32 db_size; 148 u16 dpi; 149 150 union ib_gid *sgid_tbl; 151 152 /* Lock for sgid table */ 153 spinlock_t sgid_lock; 154 155 u64 guid; 156 157 u32 dp_module; 158 u8 dp_level; 159 u8 num_hwfns; 160 u8 gsi_ll2_handle; 161 162 uint wq_multiplier; 163 u8 gsi_ll2_mac_address[ETH_ALEN]; 164 int gsi_qp_created; 165 struct qedr_cq *gsi_sqcq; 166 struct qedr_cq *gsi_rqcq; 167 struct qedr_qp *gsi_qp; 168 enum qed_rdma_type rdma_type; 169 struct xarray qps; 170 struct xarray srqs; 171 struct workqueue_struct *iwarp_wq; 172 u16 iwarp_max_mtu; 173 174 unsigned long enet_state; 175 176 u8 user_dpm_enabled; 177 }; 178 179 #define QEDR_MAX_SQ_PBL (0x8000) 180 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 181 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 182 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 183 QEDR_SQE_ELEMENT_SIZE) 184 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 185 QEDR_SQE_ELEMENT_SIZE) 186 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 187 (RDMA_RING_PAGE_SIZE) / \ 188 (QEDR_SQE_ELEMENT_SIZE) /\ 189 (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 190 /* RQ */ 191 #define QEDR_MAX_RQ_PBL (0x2000) 192 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 193 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 194 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 195 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 196 QEDR_RQE_ELEMENT_SIZE) 197 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 198 (RDMA_RING_PAGE_SIZE) / \ 199 (QEDR_RQE_ELEMENT_SIZE) /\ 200 (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 201 202 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 203 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 204 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 205 sizeof(u64)) - 1) 206 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 207 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 208 209 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 210 211 #define QEDR_MAX_PORT (1) 212 #define QEDR_PORT (1) 213 214 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 215 216 #define QEDR_ROCE_PKEY_MAX 1 217 #define QEDR_ROCE_PKEY_TABLE_LEN 1 218 #define QEDR_ROCE_PKEY_DEFAULT 0xffff 219 220 struct qedr_pbl { 221 struct list_head list_entry; 222 void *va; 223 dma_addr_t pa; 224 }; 225 226 struct qedr_ucontext { 227 struct ib_ucontext ibucontext; 228 struct qedr_dev *dev; 229 struct qedr_pd *pd; 230 u64 dpi_addr; 231 u64 dpi_phys_addr; 232 u32 dpi_size; 233 u16 dpi; 234 235 struct list_head mm_head; 236 237 /* Lock to protect mm list */ 238 struct mutex mm_list_lock; 239 }; 240 241 union db_prod64 { 242 struct rdma_pwm_val32_data data; 243 u64 raw; 244 }; 245 246 enum qedr_cq_type { 247 QEDR_CQ_TYPE_GSI, 248 QEDR_CQ_TYPE_KERNEL, 249 QEDR_CQ_TYPE_USER, 250 }; 251 252 struct qedr_pbl_info { 253 u32 num_pbls; 254 u32 num_pbes; 255 u32 pbl_size; 256 u32 pbe_size; 257 bool two_layered; 258 }; 259 260 struct qedr_userq { 261 struct ib_umem *umem; 262 struct qedr_pbl_info pbl_info; 263 struct qedr_pbl *pbl_tbl; 264 u64 buf_addr; 265 size_t buf_len; 266 }; 267 268 struct qedr_cq { 269 struct ib_cq ibcq; 270 271 enum qedr_cq_type cq_type; 272 u32 sig; 273 274 u16 icid; 275 276 /* Lock to protect multiplem CQ's */ 277 spinlock_t cq_lock; 278 u8 arm_flags; 279 struct qed_chain pbl; 280 281 void __iomem *db_addr; 282 union db_prod64 db; 283 284 u8 pbl_toggle; 285 union rdma_cqe *latest_cqe; 286 union rdma_cqe *toggle_cqe; 287 288 u32 cq_cons; 289 290 struct qedr_userq q; 291 u8 destroyed; 292 u16 cnq_notif; 293 }; 294 295 struct qedr_pd { 296 struct ib_pd ibpd; 297 u32 pd_id; 298 struct qedr_ucontext *uctx; 299 }; 300 301 struct qedr_mm { 302 struct { 303 u64 phy_addr; 304 unsigned long len; 305 } key; 306 struct list_head entry; 307 }; 308 309 union db_prod32 { 310 struct rdma_pwm_val16_data data; 311 u32 raw; 312 }; 313 314 struct qedr_qp_hwq_info { 315 /* WQE Elements */ 316 struct qed_chain pbl; 317 u64 p_phys_addr_tbl; 318 u32 max_sges; 319 320 /* WQE */ 321 u16 prod; 322 u16 cons; 323 u16 wqe_cons; 324 u16 gsi_cons; 325 u16 max_wr; 326 327 /* DB */ 328 void __iomem *db; 329 union db_prod32 db_data; 330 331 void __iomem *iwarp_db2; 332 union db_prod32 iwarp_db2_data; 333 }; 334 335 #define QEDR_INC_SW_IDX(p_info, index) \ 336 do { \ 337 p_info->index = (p_info->index + 1) & \ 338 qed_chain_get_capacity(p_info->pbl) \ 339 } while (0) 340 341 struct qedr_srq_hwq_info { 342 u32 max_sges; 343 u32 max_wr; 344 struct qed_chain pbl; 345 u64 p_phys_addr_tbl; 346 u32 wqe_prod; 347 u32 sge_prod; 348 u32 wr_prod_cnt; 349 u32 wr_cons_cnt; 350 u32 num_elems; 351 352 u32 *virt_prod_pair_addr; 353 dma_addr_t phy_prod_pair_addr; 354 }; 355 356 struct qedr_srq { 357 struct ib_srq ibsrq; 358 struct qedr_dev *dev; 359 360 struct qedr_userq usrq; 361 struct qedr_srq_hwq_info hw_srq; 362 struct ib_umem *prod_umem; 363 u16 srq_id; 364 u32 srq_limit; 365 /* lock to protect srq recv post */ 366 spinlock_t lock; 367 }; 368 369 enum qedr_qp_err_bitmap { 370 QEDR_QP_ERR_SQ_FULL = 1, 371 QEDR_QP_ERR_RQ_FULL = 2, 372 QEDR_QP_ERR_BAD_SR = 4, 373 QEDR_QP_ERR_BAD_RR = 8, 374 QEDR_QP_ERR_SQ_PBL_FULL = 16, 375 QEDR_QP_ERR_RQ_PBL_FULL = 32, 376 }; 377 378 struct qedr_qp { 379 struct ib_qp ibqp; /* must be first */ 380 struct qedr_dev *dev; 381 struct qedr_iw_ep *ep; 382 struct qedr_qp_hwq_info sq; 383 struct qedr_qp_hwq_info rq; 384 385 u32 max_inline_data; 386 387 /* Lock for QP's */ 388 spinlock_t q_lock; 389 struct qedr_cq *sq_cq; 390 struct qedr_cq *rq_cq; 391 struct qedr_srq *srq; 392 enum qed_roce_qp_state state; 393 u32 id; 394 struct qedr_pd *pd; 395 enum ib_qp_type qp_type; 396 struct qed_rdma_qp *qed_qp; 397 u32 qp_id; 398 u16 icid; 399 u16 mtu; 400 int sgid_idx; 401 u32 rq_psn; 402 u32 sq_psn; 403 u32 qkey; 404 u32 dest_qp_num; 405 406 /* Relevant to qps created from kernel space only (ULPs) */ 407 u8 prev_wqe_size; 408 u16 wqe_cons; 409 u32 err_bitmap; 410 bool signaled; 411 412 /* SQ shadow */ 413 struct { 414 u64 wr_id; 415 enum ib_wc_opcode opcode; 416 u32 bytes_len; 417 u8 wqe_size; 418 bool signaled; 419 dma_addr_t icrc_mapping; 420 u32 *icrc; 421 struct qedr_mr *mr; 422 } *wqe_wr_id; 423 424 /* RQ shadow */ 425 struct { 426 u64 wr_id; 427 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 428 u8 wqe_size; 429 430 u8 smac[ETH_ALEN]; 431 u16 vlan; 432 int rc; 433 } *rqe_wr_id; 434 435 /* Relevant to qps created from user space only (applications) */ 436 struct qedr_userq usq; 437 struct qedr_userq urq; 438 atomic_t refcnt; 439 bool destroyed; 440 }; 441 442 struct qedr_ah { 443 struct ib_ah ibah; 444 struct rdma_ah_attr attr; 445 }; 446 447 enum qedr_mr_type { 448 QEDR_MR_USER, 449 QEDR_MR_KERNEL, 450 QEDR_MR_DMA, 451 QEDR_MR_FRMR, 452 }; 453 454 struct mr_info { 455 struct qedr_pbl *pbl_table; 456 struct qedr_pbl_info pbl_info; 457 struct list_head free_pbl_list; 458 struct list_head inuse_pbl_list; 459 u32 completed; 460 u32 completed_handled; 461 }; 462 463 struct qedr_mr { 464 struct ib_mr ibmr; 465 struct ib_umem *umem; 466 467 struct qed_rdma_register_tid_in_params hw_mr; 468 enum qedr_mr_type type; 469 470 struct qedr_dev *dev; 471 struct mr_info info; 472 473 u64 *pages; 474 u32 npages; 475 }; 476 477 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) 478 479 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 480 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 481 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 482 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 483 #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ 484 RDMA_CQE_RESPONDER_INV_FLG_SHIFT) 485 486 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) 487 { 488 info->cons = (info->cons + 1) % info->max_wr; 489 info->wqe_cons++; 490 } 491 492 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) 493 { 494 info->prod = (info->prod + 1) % info->max_wr; 495 } 496 497 static inline int qedr_get_dmac(struct qedr_dev *dev, 498 struct rdma_ah_attr *ah_attr, u8 *mac_addr) 499 { 500 union ib_gid zero_sgid = { { 0 } }; 501 struct in6_addr in6; 502 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 503 u8 *dmac; 504 505 if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) { 506 DP_ERR(dev, "Local port GID not supported\n"); 507 eth_zero_addr(mac_addr); 508 return -EINVAL; 509 } 510 511 memcpy(&in6, grh->dgid.raw, sizeof(in6)); 512 dmac = rdma_ah_retrieve_dmac(ah_attr); 513 if (!dmac) 514 return -EINVAL; 515 ether_addr_copy(mac_addr, dmac); 516 517 return 0; 518 } 519 520 struct qedr_iw_listener { 521 struct qedr_dev *dev; 522 struct iw_cm_id *cm_id; 523 int backlog; 524 void *qed_handle; 525 }; 526 527 struct qedr_iw_ep { 528 struct qedr_dev *dev; 529 struct iw_cm_id *cm_id; 530 struct qedr_qp *qp; 531 void *qed_context; 532 u8 during_connect; 533 }; 534 535 static inline 536 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 537 { 538 return container_of(ibucontext, struct qedr_ucontext, ibucontext); 539 } 540 541 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 542 { 543 return container_of(ibdev, struct qedr_dev, ibdev); 544 } 545 546 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 547 { 548 return container_of(ibpd, struct qedr_pd, ibpd); 549 } 550 551 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 552 { 553 return container_of(ibcq, struct qedr_cq, ibcq); 554 } 555 556 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 557 { 558 return container_of(ibqp, struct qedr_qp, ibqp); 559 } 560 561 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) 562 { 563 return container_of(ibah, struct qedr_ah, ibah); 564 } 565 566 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) 567 { 568 return container_of(ibmr, struct qedr_mr, ibmr); 569 } 570 571 static inline struct qedr_srq *get_qedr_srq(struct ib_srq *ibsrq) 572 { 573 return container_of(ibsrq, struct qedr_srq, ibsrq); 574 } 575 #endif 576