1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QEDR_H__ 33 #define __QEDR_H__ 34 35 #include <linux/pci.h> 36 #include <rdma/ib_addr.h> 37 #include <linux/qed/qed_if.h> 38 #include <linux/qed/qed_chain.h> 39 #include <linux/qed/qed_roce_if.h> 40 #include <linux/qed/qede_roce.h> 41 #include <linux/qed/roce_common.h> 42 #include "qedr_hsi_rdma.h" 43 44 #define QEDR_MODULE_VERSION "8.10.10.0" 45 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 46 #define DP_NAME(dev) ((dev)->ibdev.name) 47 48 #define DP_DEBUG(dev, module, fmt, ...) \ 49 pr_debug("(%s) " module ": " fmt, \ 50 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 51 52 #define QEDR_MSG_INIT "INIT" 53 #define QEDR_MSG_MISC "MISC" 54 #define QEDR_MSG_CQ " CQ" 55 #define QEDR_MSG_MR " MR" 56 #define QEDR_MSG_RQ " RQ" 57 #define QEDR_MSG_SQ " SQ" 58 #define QEDR_MSG_QP " QP" 59 #define QEDR_MSG_GSI " GSI" 60 61 #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 62 63 struct qedr_dev; 64 65 struct qedr_cnq { 66 struct qedr_dev *dev; 67 struct qed_chain pbl; 68 struct qed_sb_info *sb; 69 char name[32]; 70 u64 n_comp; 71 __le16 *hw_cons_ptr; 72 u8 index; 73 }; 74 75 #define QEDR_MAX_SGID 128 76 77 struct qedr_device_attr { 78 u32 vendor_id; 79 u32 vendor_part_id; 80 u32 hw_ver; 81 u64 fw_ver; 82 u64 node_guid; 83 u64 sys_image_guid; 84 u8 max_cnq; 85 u8 max_sge; 86 u16 max_inline; 87 u32 max_sqe; 88 u32 max_rqe; 89 u8 max_qp_resp_rd_atomic_resc; 90 u8 max_qp_req_rd_atomic_resc; 91 u64 max_dev_resp_rd_atomic_resc; 92 u32 max_cq; 93 u32 max_qp; 94 u32 max_mr; 95 u64 max_mr_size; 96 u32 max_cqe; 97 u32 max_mw; 98 u32 max_fmr; 99 u32 max_mr_mw_fmr_pbl; 100 u64 max_mr_mw_fmr_size; 101 u32 max_pd; 102 u32 max_ah; 103 u8 max_pkey; 104 u32 max_srq; 105 u32 max_srq_wr; 106 u8 max_srq_sge; 107 u8 max_stats_queues; 108 u32 dev_caps; 109 110 u64 page_size_caps; 111 u8 dev_ack_delay; 112 u32 reserved_lkey; 113 u32 bad_pkey_counter; 114 struct qed_rdma_events events; 115 }; 116 117 #define QEDR_ENET_STATE_BIT (0) 118 119 struct qedr_dev { 120 struct ib_device ibdev; 121 struct qed_dev *cdev; 122 struct pci_dev *pdev; 123 struct net_device *ndev; 124 125 enum ib_atomic_cap atomic_cap; 126 127 void *rdma_ctx; 128 struct qedr_device_attr attr; 129 130 const struct qed_rdma_ops *ops; 131 struct qed_int_info int_info; 132 133 struct qed_sb_info *sb_array; 134 struct qedr_cnq *cnq_array; 135 int num_cnq; 136 int sb_start; 137 138 void __iomem *db_addr; 139 u64 db_phys_addr; 140 u32 db_size; 141 u16 dpi; 142 143 union ib_gid *sgid_tbl; 144 145 /* Lock for sgid table */ 146 spinlock_t sgid_lock; 147 148 u64 guid; 149 150 u32 dp_module; 151 u8 dp_level; 152 u8 num_hwfns; 153 uint wq_multiplier; 154 u8 gsi_ll2_mac_address[ETH_ALEN]; 155 int gsi_qp_created; 156 struct qedr_cq *gsi_sqcq; 157 struct qedr_cq *gsi_rqcq; 158 struct qedr_qp *gsi_qp; 159 160 unsigned long enet_state; 161 }; 162 163 #define QEDR_MAX_SQ_PBL (0x8000) 164 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 165 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 166 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 167 QEDR_SQE_ELEMENT_SIZE) 168 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 169 QEDR_SQE_ELEMENT_SIZE) 170 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 171 (RDMA_RING_PAGE_SIZE) / \ 172 (QEDR_SQE_ELEMENT_SIZE) /\ 173 (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 174 /* RQ */ 175 #define QEDR_MAX_RQ_PBL (0x2000) 176 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 177 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 178 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 179 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 180 QEDR_RQE_ELEMENT_SIZE) 181 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 182 (RDMA_RING_PAGE_SIZE) / \ 183 (QEDR_RQE_ELEMENT_SIZE) /\ 184 (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 185 186 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 187 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 188 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 189 sizeof(u64)) - 1) 190 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 191 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 192 193 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 194 195 #define QEDR_MAX_PORT (1) 196 #define QEDR_PORT (1) 197 198 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 199 200 #define QEDR_ROCE_PKEY_MAX 1 201 #define QEDR_ROCE_PKEY_TABLE_LEN 1 202 #define QEDR_ROCE_PKEY_DEFAULT 0xffff 203 204 struct qedr_pbl { 205 struct list_head list_entry; 206 void *va; 207 dma_addr_t pa; 208 }; 209 210 struct qedr_ucontext { 211 struct ib_ucontext ibucontext; 212 struct qedr_dev *dev; 213 struct qedr_pd *pd; 214 u64 dpi_addr; 215 u64 dpi_phys_addr; 216 u32 dpi_size; 217 u16 dpi; 218 219 struct list_head mm_head; 220 221 /* Lock to protect mm list */ 222 struct mutex mm_list_lock; 223 }; 224 225 union db_prod64 { 226 struct rdma_pwm_val32_data data; 227 u64 raw; 228 }; 229 230 enum qedr_cq_type { 231 QEDR_CQ_TYPE_GSI, 232 QEDR_CQ_TYPE_KERNEL, 233 QEDR_CQ_TYPE_USER, 234 }; 235 236 struct qedr_pbl_info { 237 u32 num_pbls; 238 u32 num_pbes; 239 u32 pbl_size; 240 u32 pbe_size; 241 bool two_layered; 242 }; 243 244 struct qedr_userq { 245 struct ib_umem *umem; 246 struct qedr_pbl_info pbl_info; 247 struct qedr_pbl *pbl_tbl; 248 u64 buf_addr; 249 size_t buf_len; 250 }; 251 252 struct qedr_cq { 253 struct ib_cq ibcq; 254 255 enum qedr_cq_type cq_type; 256 u32 sig; 257 258 u16 icid; 259 260 /* Lock to protect multiplem CQ's */ 261 spinlock_t cq_lock; 262 u8 arm_flags; 263 struct qed_chain pbl; 264 265 void __iomem *db_addr; 266 union db_prod64 db; 267 268 u8 pbl_toggle; 269 union rdma_cqe *latest_cqe; 270 union rdma_cqe *toggle_cqe; 271 272 u32 cq_cons; 273 274 struct qedr_userq q; 275 }; 276 277 struct qedr_pd { 278 struct ib_pd ibpd; 279 u32 pd_id; 280 struct qedr_ucontext *uctx; 281 }; 282 283 struct qedr_mm { 284 struct { 285 u64 phy_addr; 286 unsigned long len; 287 } key; 288 struct list_head entry; 289 }; 290 291 union db_prod32 { 292 struct rdma_pwm_val16_data data; 293 u32 raw; 294 }; 295 296 struct qedr_qp_hwq_info { 297 /* WQE Elements */ 298 struct qed_chain pbl; 299 u64 p_phys_addr_tbl; 300 u32 max_sges; 301 302 /* WQE */ 303 u16 prod; 304 u16 cons; 305 u16 wqe_cons; 306 u16 gsi_cons; 307 u16 max_wr; 308 309 /* DB */ 310 void __iomem *db; 311 union db_prod32 db_data; 312 }; 313 314 #define QEDR_INC_SW_IDX(p_info, index) \ 315 do { \ 316 p_info->index = (p_info->index + 1) & \ 317 qed_chain_get_capacity(p_info->pbl) \ 318 } while (0) 319 320 enum qedr_qp_err_bitmap { 321 QEDR_QP_ERR_SQ_FULL = 1, 322 QEDR_QP_ERR_RQ_FULL = 2, 323 QEDR_QP_ERR_BAD_SR = 4, 324 QEDR_QP_ERR_BAD_RR = 8, 325 QEDR_QP_ERR_SQ_PBL_FULL = 16, 326 QEDR_QP_ERR_RQ_PBL_FULL = 32, 327 }; 328 329 struct qedr_qp { 330 struct ib_qp ibqp; /* must be first */ 331 struct qedr_dev *dev; 332 333 struct qedr_qp_hwq_info sq; 334 struct qedr_qp_hwq_info rq; 335 336 u32 max_inline_data; 337 338 /* Lock for QP's */ 339 spinlock_t q_lock; 340 struct qedr_cq *sq_cq; 341 struct qedr_cq *rq_cq; 342 struct qedr_srq *srq; 343 enum qed_roce_qp_state state; 344 u32 id; 345 struct qedr_pd *pd; 346 enum ib_qp_type qp_type; 347 struct qed_rdma_qp *qed_qp; 348 u32 qp_id; 349 u16 icid; 350 u16 mtu; 351 int sgid_idx; 352 u32 rq_psn; 353 u32 sq_psn; 354 u32 qkey; 355 u32 dest_qp_num; 356 357 /* Relevant to qps created from kernel space only (ULPs) */ 358 u8 prev_wqe_size; 359 u16 wqe_cons; 360 u32 err_bitmap; 361 bool signaled; 362 363 /* SQ shadow */ 364 struct { 365 u64 wr_id; 366 enum ib_wc_opcode opcode; 367 u32 bytes_len; 368 u8 wqe_size; 369 bool signaled; 370 dma_addr_t icrc_mapping; 371 u32 *icrc; 372 struct qedr_mr *mr; 373 } *wqe_wr_id; 374 375 /* RQ shadow */ 376 struct { 377 u64 wr_id; 378 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 379 u8 wqe_size; 380 381 u8 smac[ETH_ALEN]; 382 u16 vlan_id; 383 int rc; 384 } *rqe_wr_id; 385 386 /* Relevant to qps created from user space only (applications) */ 387 struct qedr_userq usq; 388 struct qedr_userq urq; 389 }; 390 391 struct qedr_ah { 392 struct ib_ah ibah; 393 struct ib_ah_attr attr; 394 }; 395 396 enum qedr_mr_type { 397 QEDR_MR_USER, 398 QEDR_MR_KERNEL, 399 QEDR_MR_DMA, 400 QEDR_MR_FRMR, 401 }; 402 403 struct mr_info { 404 struct qedr_pbl *pbl_table; 405 struct qedr_pbl_info pbl_info; 406 struct list_head free_pbl_list; 407 struct list_head inuse_pbl_list; 408 u32 completed; 409 u32 completed_handled; 410 }; 411 412 struct qedr_mr { 413 struct ib_mr ibmr; 414 struct ib_umem *umem; 415 416 struct qed_rdma_register_tid_in_params hw_mr; 417 enum qedr_mr_type type; 418 419 struct qedr_dev *dev; 420 struct mr_info info; 421 422 u64 *pages; 423 u32 npages; 424 }; 425 426 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) 427 428 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 429 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 430 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 431 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 432 #define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM | QEDR_RESP_RDMA) 433 434 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) 435 { 436 info->cons = (info->cons + 1) % info->max_wr; 437 info->wqe_cons++; 438 } 439 440 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) 441 { 442 info->prod = (info->prod + 1) % info->max_wr; 443 } 444 445 static inline int qedr_get_dmac(struct qedr_dev *dev, 446 struct ib_ah_attr *ah_attr, u8 *mac_addr) 447 { 448 union ib_gid zero_sgid = { { 0 } }; 449 struct in6_addr in6; 450 451 if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) { 452 DP_ERR(dev, "Local port GID not supported\n"); 453 eth_zero_addr(mac_addr); 454 return -EINVAL; 455 } 456 457 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6)); 458 ether_addr_copy(mac_addr, ah_attr->dmac); 459 460 return 0; 461 } 462 463 static inline 464 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 465 { 466 return container_of(ibucontext, struct qedr_ucontext, ibucontext); 467 } 468 469 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 470 { 471 return container_of(ibdev, struct qedr_dev, ibdev); 472 } 473 474 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 475 { 476 return container_of(ibpd, struct qedr_pd, ibpd); 477 } 478 479 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 480 { 481 return container_of(ibcq, struct qedr_cq, ibcq); 482 } 483 484 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 485 { 486 return container_of(ibqp, struct qedr_qp, ibqp); 487 } 488 489 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) 490 { 491 return container_of(ibah, struct qedr_ah, ibah); 492 } 493 494 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) 495 { 496 return container_of(ibmr, struct qedr_mr, ibmr); 497 } 498 #endif 499