1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QEDR_H__ 33 #define __QEDR_H__ 34 35 #include <linux/pci.h> 36 #include <rdma/ib_addr.h> 37 #include <linux/qed/qed_if.h> 38 #include <linux/qed/qed_chain.h> 39 #include <linux/qed/qed_rdma_if.h> 40 #include <linux/qed/qede_rdma.h> 41 #include <linux/qed/roce_common.h> 42 #include "qedr_hsi_rdma.h" 43 44 #define QEDR_MODULE_VERSION "8.10.10.0" 45 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 46 #define DP_NAME(dev) ((dev)->ibdev.name) 47 48 #define DP_DEBUG(dev, module, fmt, ...) \ 49 pr_debug("(%s) " module ": " fmt, \ 50 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 51 52 #define QEDR_MSG_INIT "INIT" 53 #define QEDR_MSG_MISC "MISC" 54 #define QEDR_MSG_CQ " CQ" 55 #define QEDR_MSG_MR " MR" 56 #define QEDR_MSG_RQ " RQ" 57 #define QEDR_MSG_SQ " SQ" 58 #define QEDR_MSG_QP " QP" 59 #define QEDR_MSG_GSI " GSI" 60 61 #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 62 63 #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) 64 #define FW_PAGE_SHIFT (12) 65 66 struct qedr_dev; 67 68 struct qedr_cnq { 69 struct qedr_dev *dev; 70 struct qed_chain pbl; 71 struct qed_sb_info *sb; 72 char name[32]; 73 u64 n_comp; 74 __le16 *hw_cons_ptr; 75 u8 index; 76 }; 77 78 #define QEDR_MAX_SGID 128 79 80 struct qedr_device_attr { 81 u32 vendor_id; 82 u32 vendor_part_id; 83 u32 hw_ver; 84 u64 fw_ver; 85 u64 node_guid; 86 u64 sys_image_guid; 87 u8 max_cnq; 88 u8 max_sge; 89 u16 max_inline; 90 u32 max_sqe; 91 u32 max_rqe; 92 u8 max_qp_resp_rd_atomic_resc; 93 u8 max_qp_req_rd_atomic_resc; 94 u64 max_dev_resp_rd_atomic_resc; 95 u32 max_cq; 96 u32 max_qp; 97 u32 max_mr; 98 u64 max_mr_size; 99 u32 max_cqe; 100 u32 max_mw; 101 u32 max_fmr; 102 u32 max_mr_mw_fmr_pbl; 103 u64 max_mr_mw_fmr_size; 104 u32 max_pd; 105 u32 max_ah; 106 u8 max_pkey; 107 u32 max_srq; 108 u32 max_srq_wr; 109 u8 max_srq_sge; 110 u8 max_stats_queues; 111 u32 dev_caps; 112 113 u64 page_size_caps; 114 u8 dev_ack_delay; 115 u32 reserved_lkey; 116 u32 bad_pkey_counter; 117 struct qed_rdma_events events; 118 }; 119 120 #define QEDR_ENET_STATE_BIT (0) 121 122 struct qedr_dev { 123 struct ib_device ibdev; 124 struct qed_dev *cdev; 125 struct pci_dev *pdev; 126 struct net_device *ndev; 127 128 enum ib_atomic_cap atomic_cap; 129 130 void *rdma_ctx; 131 struct qedr_device_attr attr; 132 133 const struct qed_rdma_ops *ops; 134 struct qed_int_info int_info; 135 136 struct qed_sb_info *sb_array; 137 struct qedr_cnq *cnq_array; 138 int num_cnq; 139 int sb_start; 140 141 void __iomem *db_addr; 142 u64 db_phys_addr; 143 u32 db_size; 144 u16 dpi; 145 146 union ib_gid *sgid_tbl; 147 148 /* Lock for sgid table */ 149 spinlock_t sgid_lock; 150 151 u64 guid; 152 153 u32 dp_module; 154 u8 dp_level; 155 u8 num_hwfns; 156 u8 gsi_ll2_handle; 157 158 uint wq_multiplier; 159 u8 gsi_ll2_mac_address[ETH_ALEN]; 160 int gsi_qp_created; 161 struct qedr_cq *gsi_sqcq; 162 struct qedr_cq *gsi_rqcq; 163 struct qedr_qp *gsi_qp; 164 165 unsigned long enet_state; 166 }; 167 168 #define QEDR_MAX_SQ_PBL (0x8000) 169 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 170 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 171 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 172 QEDR_SQE_ELEMENT_SIZE) 173 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 174 QEDR_SQE_ELEMENT_SIZE) 175 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 176 (RDMA_RING_PAGE_SIZE) / \ 177 (QEDR_SQE_ELEMENT_SIZE) /\ 178 (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 179 /* RQ */ 180 #define QEDR_MAX_RQ_PBL (0x2000) 181 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 182 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 183 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 184 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 185 QEDR_RQE_ELEMENT_SIZE) 186 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 187 (RDMA_RING_PAGE_SIZE) / \ 188 (QEDR_RQE_ELEMENT_SIZE) /\ 189 (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 190 191 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 192 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 193 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 194 sizeof(u64)) - 1) 195 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 196 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 197 198 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 199 200 #define QEDR_MAX_PORT (1) 201 #define QEDR_PORT (1) 202 203 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 204 205 #define QEDR_ROCE_PKEY_MAX 1 206 #define QEDR_ROCE_PKEY_TABLE_LEN 1 207 #define QEDR_ROCE_PKEY_DEFAULT 0xffff 208 209 struct qedr_pbl { 210 struct list_head list_entry; 211 void *va; 212 dma_addr_t pa; 213 }; 214 215 struct qedr_ucontext { 216 struct ib_ucontext ibucontext; 217 struct qedr_dev *dev; 218 struct qedr_pd *pd; 219 u64 dpi_addr; 220 u64 dpi_phys_addr; 221 u32 dpi_size; 222 u16 dpi; 223 224 struct list_head mm_head; 225 226 /* Lock to protect mm list */ 227 struct mutex mm_list_lock; 228 }; 229 230 union db_prod64 { 231 struct rdma_pwm_val32_data data; 232 u64 raw; 233 }; 234 235 enum qedr_cq_type { 236 QEDR_CQ_TYPE_GSI, 237 QEDR_CQ_TYPE_KERNEL, 238 QEDR_CQ_TYPE_USER, 239 }; 240 241 struct qedr_pbl_info { 242 u32 num_pbls; 243 u32 num_pbes; 244 u32 pbl_size; 245 u32 pbe_size; 246 bool two_layered; 247 }; 248 249 struct qedr_userq { 250 struct ib_umem *umem; 251 struct qedr_pbl_info pbl_info; 252 struct qedr_pbl *pbl_tbl; 253 u64 buf_addr; 254 size_t buf_len; 255 }; 256 257 struct qedr_cq { 258 struct ib_cq ibcq; 259 260 enum qedr_cq_type cq_type; 261 u32 sig; 262 263 u16 icid; 264 265 /* Lock to protect multiplem CQ's */ 266 spinlock_t cq_lock; 267 u8 arm_flags; 268 struct qed_chain pbl; 269 270 void __iomem *db_addr; 271 union db_prod64 db; 272 273 u8 pbl_toggle; 274 union rdma_cqe *latest_cqe; 275 union rdma_cqe *toggle_cqe; 276 277 u32 cq_cons; 278 279 struct qedr_userq q; 280 u8 destroyed; 281 u16 cnq_notif; 282 }; 283 284 struct qedr_pd { 285 struct ib_pd ibpd; 286 u32 pd_id; 287 struct qedr_ucontext *uctx; 288 }; 289 290 struct qedr_mm { 291 struct { 292 u64 phy_addr; 293 unsigned long len; 294 } key; 295 struct list_head entry; 296 }; 297 298 union db_prod32 { 299 struct rdma_pwm_val16_data data; 300 u32 raw; 301 }; 302 303 struct qedr_qp_hwq_info { 304 /* WQE Elements */ 305 struct qed_chain pbl; 306 u64 p_phys_addr_tbl; 307 u32 max_sges; 308 309 /* WQE */ 310 u16 prod; 311 u16 cons; 312 u16 wqe_cons; 313 u16 gsi_cons; 314 u16 max_wr; 315 316 /* DB */ 317 void __iomem *db; 318 union db_prod32 db_data; 319 }; 320 321 #define QEDR_INC_SW_IDX(p_info, index) \ 322 do { \ 323 p_info->index = (p_info->index + 1) & \ 324 qed_chain_get_capacity(p_info->pbl) \ 325 } while (0) 326 327 enum qedr_qp_err_bitmap { 328 QEDR_QP_ERR_SQ_FULL = 1, 329 QEDR_QP_ERR_RQ_FULL = 2, 330 QEDR_QP_ERR_BAD_SR = 4, 331 QEDR_QP_ERR_BAD_RR = 8, 332 QEDR_QP_ERR_SQ_PBL_FULL = 16, 333 QEDR_QP_ERR_RQ_PBL_FULL = 32, 334 }; 335 336 struct qedr_qp { 337 struct ib_qp ibqp; /* must be first */ 338 struct qedr_dev *dev; 339 340 struct qedr_qp_hwq_info sq; 341 struct qedr_qp_hwq_info rq; 342 343 u32 max_inline_data; 344 345 /* Lock for QP's */ 346 spinlock_t q_lock; 347 struct qedr_cq *sq_cq; 348 struct qedr_cq *rq_cq; 349 struct qedr_srq *srq; 350 enum qed_roce_qp_state state; 351 u32 id; 352 struct qedr_pd *pd; 353 enum ib_qp_type qp_type; 354 struct qed_rdma_qp *qed_qp; 355 u32 qp_id; 356 u16 icid; 357 u16 mtu; 358 int sgid_idx; 359 u32 rq_psn; 360 u32 sq_psn; 361 u32 qkey; 362 u32 dest_qp_num; 363 364 /* Relevant to qps created from kernel space only (ULPs) */ 365 u8 prev_wqe_size; 366 u16 wqe_cons; 367 u32 err_bitmap; 368 bool signaled; 369 370 /* SQ shadow */ 371 struct { 372 u64 wr_id; 373 enum ib_wc_opcode opcode; 374 u32 bytes_len; 375 u8 wqe_size; 376 bool signaled; 377 dma_addr_t icrc_mapping; 378 u32 *icrc; 379 struct qedr_mr *mr; 380 } *wqe_wr_id; 381 382 /* RQ shadow */ 383 struct { 384 u64 wr_id; 385 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 386 u8 wqe_size; 387 388 u8 smac[ETH_ALEN]; 389 u16 vlan_id; 390 int rc; 391 } *rqe_wr_id; 392 393 /* Relevant to qps created from user space only (applications) */ 394 struct qedr_userq usq; 395 struct qedr_userq urq; 396 }; 397 398 struct qedr_ah { 399 struct ib_ah ibah; 400 struct rdma_ah_attr attr; 401 }; 402 403 enum qedr_mr_type { 404 QEDR_MR_USER, 405 QEDR_MR_KERNEL, 406 QEDR_MR_DMA, 407 QEDR_MR_FRMR, 408 }; 409 410 struct mr_info { 411 struct qedr_pbl *pbl_table; 412 struct qedr_pbl_info pbl_info; 413 struct list_head free_pbl_list; 414 struct list_head inuse_pbl_list; 415 u32 completed; 416 u32 completed_handled; 417 }; 418 419 struct qedr_mr { 420 struct ib_mr ibmr; 421 struct ib_umem *umem; 422 423 struct qed_rdma_register_tid_in_params hw_mr; 424 enum qedr_mr_type type; 425 426 struct qedr_dev *dev; 427 struct mr_info info; 428 429 u64 *pages; 430 u32 npages; 431 }; 432 433 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) 434 435 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 436 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 437 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 438 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 439 #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ 440 RDMA_CQE_RESPONDER_INV_FLG_SHIFT) 441 442 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) 443 { 444 info->cons = (info->cons + 1) % info->max_wr; 445 info->wqe_cons++; 446 } 447 448 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) 449 { 450 info->prod = (info->prod + 1) % info->max_wr; 451 } 452 453 static inline int qedr_get_dmac(struct qedr_dev *dev, 454 struct rdma_ah_attr *ah_attr, u8 *mac_addr) 455 { 456 union ib_gid zero_sgid = { { 0 } }; 457 struct in6_addr in6; 458 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 459 u8 *dmac; 460 461 if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) { 462 DP_ERR(dev, "Local port GID not supported\n"); 463 eth_zero_addr(mac_addr); 464 return -EINVAL; 465 } 466 467 memcpy(&in6, grh->dgid.raw, sizeof(in6)); 468 dmac = rdma_ah_retrieve_dmac(ah_attr); 469 if (!dmac) 470 return -EINVAL; 471 ether_addr_copy(mac_addr, dmac); 472 473 return 0; 474 } 475 476 static inline 477 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 478 { 479 return container_of(ibucontext, struct qedr_ucontext, ibucontext); 480 } 481 482 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 483 { 484 return container_of(ibdev, struct qedr_dev, ibdev); 485 } 486 487 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 488 { 489 return container_of(ibpd, struct qedr_pd, ibpd); 490 } 491 492 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 493 { 494 return container_of(ibcq, struct qedr_cq, ibcq); 495 } 496 497 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 498 { 499 return container_of(ibqp, struct qedr_qp, ibqp); 500 } 501 502 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) 503 { 504 return container_of(ibah, struct qedr_ah, ibah); 505 } 506 507 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) 508 { 509 return container_of(ibmr, struct qedr_mr, ibmr); 510 } 511 #endif 512