1 /* QLogic qedr NIC Driver 2 * Copyright (c) 2015-2016 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __QEDR_H__ 33 #define __QEDR_H__ 34 35 #include <linux/pci.h> 36 #include <linux/xarray.h> 37 #include <rdma/ib_addr.h> 38 #include <linux/qed/qed_if.h> 39 #include <linux/qed/qed_chain.h> 40 #include <linux/qed/qed_rdma_if.h> 41 #include <linux/qed/qede_rdma.h> 42 #include <linux/qed/roce_common.h> 43 #include <linux/completion.h> 44 #include "qedr_hsi_rdma.h" 45 46 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 47 #define DP_NAME(_dev) dev_name(&(_dev)->ibdev.dev) 48 #define IS_IWARP(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_IWARP) 49 #define IS_ROCE(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_ROCE) 50 51 #define DP_DEBUG(dev, module, fmt, ...) \ 52 pr_debug("(%s) " module ": " fmt, \ 53 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 54 55 #define QEDR_MSG_INIT "INIT" 56 #define QEDR_MSG_MISC "MISC" 57 #define QEDR_MSG_CQ " CQ" 58 #define QEDR_MSG_MR " MR" 59 #define QEDR_MSG_RQ " RQ" 60 #define QEDR_MSG_SQ " SQ" 61 #define QEDR_MSG_QP " QP" 62 #define QEDR_MSG_SRQ " SRQ" 63 #define QEDR_MSG_GSI " GSI" 64 #define QEDR_MSG_IWARP " IW" 65 66 #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 67 68 #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) 69 #define FW_PAGE_SHIFT (12) 70 71 struct qedr_dev; 72 73 struct qedr_cnq { 74 struct qedr_dev *dev; 75 struct qed_chain pbl; 76 struct qed_sb_info *sb; 77 char name[32]; 78 u64 n_comp; 79 __le16 *hw_cons_ptr; 80 u8 index; 81 }; 82 83 #define QEDR_MAX_SGID 128 84 85 struct qedr_device_attr { 86 u32 vendor_id; 87 u32 vendor_part_id; 88 u32 hw_ver; 89 u64 fw_ver; 90 u64 node_guid; 91 u64 sys_image_guid; 92 u8 max_cnq; 93 u8 max_sge; 94 u16 max_inline; 95 u32 max_sqe; 96 u32 max_rqe; 97 u8 max_qp_resp_rd_atomic_resc; 98 u8 max_qp_req_rd_atomic_resc; 99 u64 max_dev_resp_rd_atomic_resc; 100 u32 max_cq; 101 u32 max_qp; 102 u32 max_mr; 103 u64 max_mr_size; 104 u32 max_cqe; 105 u32 max_mw; 106 u32 max_mr_mw_fmr_pbl; 107 u64 max_mr_mw_fmr_size; 108 u32 max_pd; 109 u32 max_ah; 110 u8 max_pkey; 111 u32 max_srq; 112 u32 max_srq_wr; 113 u8 max_srq_sge; 114 u8 max_stats_queues; 115 u32 dev_caps; 116 117 u64 page_size_caps; 118 u8 dev_ack_delay; 119 u32 reserved_lkey; 120 u32 bad_pkey_counter; 121 struct qed_rdma_events events; 122 }; 123 124 #define QEDR_ENET_STATE_BIT (0) 125 126 struct qedr_dev { 127 struct ib_device ibdev; 128 struct qed_dev *cdev; 129 struct pci_dev *pdev; 130 struct net_device *ndev; 131 132 enum ib_atomic_cap atomic_cap; 133 134 void *rdma_ctx; 135 struct qedr_device_attr attr; 136 137 const struct qed_rdma_ops *ops; 138 struct qed_int_info int_info; 139 140 struct qed_sb_info *sb_array; 141 struct qedr_cnq *cnq_array; 142 int num_cnq; 143 int sb_start; 144 145 void __iomem *db_addr; 146 u64 db_phys_addr; 147 u32 db_size; 148 u16 dpi; 149 150 union ib_gid *sgid_tbl; 151 152 /* Lock for sgid table */ 153 spinlock_t sgid_lock; 154 155 u64 guid; 156 157 u32 dp_module; 158 u8 dp_level; 159 u8 num_hwfns; 160 #define QEDR_IS_CMT(dev) ((dev)->num_hwfns > 1) 161 u8 affin_hwfn_idx; 162 u8 gsi_ll2_handle; 163 164 uint wq_multiplier; 165 u8 gsi_ll2_mac_address[ETH_ALEN]; 166 int gsi_qp_created; 167 struct qedr_cq *gsi_sqcq; 168 struct qedr_cq *gsi_rqcq; 169 struct qedr_qp *gsi_qp; 170 enum qed_rdma_type rdma_type; 171 struct xarray qps; 172 struct xarray srqs; 173 struct workqueue_struct *iwarp_wq; 174 u16 iwarp_max_mtu; 175 176 unsigned long enet_state; 177 178 u8 user_dpm_enabled; 179 }; 180 181 #define QEDR_MAX_SQ_PBL (0x8000) 182 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 183 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 184 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 185 QEDR_SQE_ELEMENT_SIZE) 186 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 187 QEDR_SQE_ELEMENT_SIZE) 188 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 189 (RDMA_RING_PAGE_SIZE) / \ 190 (QEDR_SQE_ELEMENT_SIZE) /\ 191 (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 192 /* RQ */ 193 #define QEDR_MAX_RQ_PBL (0x2000) 194 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 195 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 196 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 197 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 198 QEDR_RQE_ELEMENT_SIZE) 199 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 200 (RDMA_RING_PAGE_SIZE) / \ 201 (QEDR_RQE_ELEMENT_SIZE) /\ 202 (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 203 204 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 205 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 206 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 207 sizeof(u64)) - 1) 208 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 209 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 210 211 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 212 213 #define QEDR_MAX_PORT (1) 214 #define QEDR_PORT (1) 215 216 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 217 218 #define QEDR_ROCE_PKEY_MAX 1 219 #define QEDR_ROCE_PKEY_TABLE_LEN 1 220 #define QEDR_ROCE_PKEY_DEFAULT 0xffff 221 222 struct qedr_pbl { 223 struct list_head list_entry; 224 void *va; 225 dma_addr_t pa; 226 }; 227 228 struct qedr_ucontext { 229 struct ib_ucontext ibucontext; 230 struct qedr_dev *dev; 231 struct qedr_pd *pd; 232 void __iomem *dpi_addr; 233 struct rdma_user_mmap_entry *db_mmap_entry; 234 u64 dpi_phys_addr; 235 u32 dpi_size; 236 u16 dpi; 237 bool db_rec; 238 }; 239 240 union db_prod32 { 241 struct rdma_pwm_val16_data data; 242 u32 raw; 243 }; 244 245 union db_prod64 { 246 struct rdma_pwm_val32_data data; 247 u64 raw; 248 }; 249 250 enum qedr_cq_type { 251 QEDR_CQ_TYPE_GSI, 252 QEDR_CQ_TYPE_KERNEL, 253 QEDR_CQ_TYPE_USER, 254 }; 255 256 struct qedr_pbl_info { 257 u32 num_pbls; 258 u32 num_pbes; 259 u32 pbl_size; 260 u32 pbe_size; 261 bool two_layered; 262 }; 263 264 struct qedr_userq { 265 struct ib_umem *umem; 266 struct qedr_pbl_info pbl_info; 267 struct qedr_pbl *pbl_tbl; 268 u64 buf_addr; 269 size_t buf_len; 270 271 /* doorbell recovery */ 272 void __iomem *db_addr; 273 struct qedr_user_db_rec *db_rec_data; 274 struct rdma_user_mmap_entry *db_mmap_entry; 275 void __iomem *db_rec_db2_addr; 276 union db_prod32 db_rec_db2_data; 277 }; 278 279 struct qedr_cq { 280 struct ib_cq ibcq; 281 282 enum qedr_cq_type cq_type; 283 u32 sig; 284 285 u16 icid; 286 287 /* Lock to protect multiplem CQ's */ 288 spinlock_t cq_lock; 289 u8 arm_flags; 290 struct qed_chain pbl; 291 292 void __iomem *db_addr; 293 union db_prod64 db; 294 295 u8 pbl_toggle; 296 union rdma_cqe *latest_cqe; 297 union rdma_cqe *toggle_cqe; 298 299 u32 cq_cons; 300 301 struct qedr_userq q; 302 u8 destroyed; 303 u16 cnq_notif; 304 }; 305 306 struct qedr_pd { 307 struct ib_pd ibpd; 308 u32 pd_id; 309 struct qedr_ucontext *uctx; 310 }; 311 312 struct qedr_qp_hwq_info { 313 /* WQE Elements */ 314 struct qed_chain pbl; 315 u64 p_phys_addr_tbl; 316 u32 max_sges; 317 318 /* WQE */ 319 u16 prod; 320 u16 cons; 321 u16 wqe_cons; 322 u16 gsi_cons; 323 u16 max_wr; 324 325 /* DB */ 326 void __iomem *db; 327 union db_prod32 db_data; 328 329 void __iomem *iwarp_db2; 330 union db_prod32 iwarp_db2_data; 331 }; 332 333 #define QEDR_INC_SW_IDX(p_info, index) \ 334 do { \ 335 p_info->index = (p_info->index + 1) & \ 336 qed_chain_get_capacity(p_info->pbl) \ 337 } while (0) 338 339 struct qedr_srq_hwq_info { 340 u32 max_sges; 341 u32 max_wr; 342 struct qed_chain pbl; 343 u64 p_phys_addr_tbl; 344 u32 wqe_prod; 345 u32 sge_prod; 346 u32 wr_prod_cnt; 347 u32 wr_cons_cnt; 348 u32 num_elems; 349 350 u32 *virt_prod_pair_addr; 351 dma_addr_t phy_prod_pair_addr; 352 }; 353 354 struct qedr_srq { 355 struct ib_srq ibsrq; 356 struct qedr_dev *dev; 357 358 struct qedr_userq usrq; 359 struct qedr_srq_hwq_info hw_srq; 360 struct ib_umem *prod_umem; 361 u16 srq_id; 362 u32 srq_limit; 363 /* lock to protect srq recv post */ 364 spinlock_t lock; 365 }; 366 367 enum qedr_qp_err_bitmap { 368 QEDR_QP_ERR_SQ_FULL = 1, 369 QEDR_QP_ERR_RQ_FULL = 2, 370 QEDR_QP_ERR_BAD_SR = 4, 371 QEDR_QP_ERR_BAD_RR = 8, 372 QEDR_QP_ERR_SQ_PBL_FULL = 16, 373 QEDR_QP_ERR_RQ_PBL_FULL = 32, 374 }; 375 376 enum qedr_qp_create_type { 377 QEDR_QP_CREATE_NONE, 378 QEDR_QP_CREATE_USER, 379 QEDR_QP_CREATE_KERNEL, 380 }; 381 382 enum qedr_iwarp_cm_flags { 383 QEDR_IWARP_CM_WAIT_FOR_CONNECT = BIT(0), 384 QEDR_IWARP_CM_WAIT_FOR_DISCONNECT = BIT(1), 385 }; 386 387 struct qedr_qp { 388 struct ib_qp ibqp; /* must be first */ 389 struct qedr_dev *dev; 390 struct qedr_qp_hwq_info sq; 391 struct qedr_qp_hwq_info rq; 392 393 u32 max_inline_data; 394 395 /* Lock for QP's */ 396 spinlock_t q_lock; 397 struct qedr_cq *sq_cq; 398 struct qedr_cq *rq_cq; 399 struct qedr_srq *srq; 400 enum qed_roce_qp_state state; 401 u32 id; 402 struct qedr_pd *pd; 403 enum ib_qp_type qp_type; 404 enum qedr_qp_create_type create_type; 405 struct qed_rdma_qp *qed_qp; 406 u32 qp_id; 407 u16 icid; 408 u16 mtu; 409 int sgid_idx; 410 u32 rq_psn; 411 u32 sq_psn; 412 u32 qkey; 413 u32 dest_qp_num; 414 415 /* Relevant to qps created from kernel space only (ULPs) */ 416 u8 prev_wqe_size; 417 u16 wqe_cons; 418 u32 err_bitmap; 419 bool signaled; 420 421 /* SQ shadow */ 422 struct { 423 u64 wr_id; 424 enum ib_wc_opcode opcode; 425 u32 bytes_len; 426 u8 wqe_size; 427 bool signaled; 428 dma_addr_t icrc_mapping; 429 u32 *icrc; 430 struct qedr_mr *mr; 431 } *wqe_wr_id; 432 433 /* RQ shadow */ 434 struct { 435 u64 wr_id; 436 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 437 u8 wqe_size; 438 439 u8 smac[ETH_ALEN]; 440 u16 vlan; 441 int rc; 442 } *rqe_wr_id; 443 444 /* Relevant to qps created from user space only (applications) */ 445 struct qedr_userq usq; 446 struct qedr_userq urq; 447 448 /* synchronization objects used with iwarp ep */ 449 struct kref refcnt; 450 struct completion iwarp_cm_comp; 451 unsigned long iwarp_cm_flags; /* enum iwarp_cm_flags */ 452 }; 453 454 struct qedr_ah { 455 struct ib_ah ibah; 456 struct rdma_ah_attr attr; 457 }; 458 459 enum qedr_mr_type { 460 QEDR_MR_USER, 461 QEDR_MR_KERNEL, 462 QEDR_MR_DMA, 463 QEDR_MR_FRMR, 464 }; 465 466 struct mr_info { 467 struct qedr_pbl *pbl_table; 468 struct qedr_pbl_info pbl_info; 469 struct list_head free_pbl_list; 470 struct list_head inuse_pbl_list; 471 u32 completed; 472 u32 completed_handled; 473 }; 474 475 struct qedr_mr { 476 struct ib_mr ibmr; 477 struct ib_umem *umem; 478 479 struct qed_rdma_register_tid_in_params hw_mr; 480 enum qedr_mr_type type; 481 482 struct qedr_dev *dev; 483 struct mr_info info; 484 485 u64 *pages; 486 u32 npages; 487 }; 488 489 struct qedr_user_mmap_entry { 490 struct rdma_user_mmap_entry rdma_entry; 491 struct qedr_dev *dev; 492 union { 493 u64 io_address; 494 void *address; 495 }; 496 size_t length; 497 u16 dpi; 498 u8 mmap_flag; 499 }; 500 501 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) 502 503 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 504 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 505 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 506 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 507 #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ 508 RDMA_CQE_RESPONDER_INV_FLG_SHIFT) 509 510 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) 511 { 512 info->cons = (info->cons + 1) % info->max_wr; 513 info->wqe_cons++; 514 } 515 516 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) 517 { 518 info->prod = (info->prod + 1) % info->max_wr; 519 } 520 521 static inline int qedr_get_dmac(struct qedr_dev *dev, 522 struct rdma_ah_attr *ah_attr, u8 *mac_addr) 523 { 524 union ib_gid zero_sgid = { { 0 } }; 525 struct in6_addr in6; 526 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 527 u8 *dmac; 528 529 if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) { 530 DP_ERR(dev, "Local port GID not supported\n"); 531 eth_zero_addr(mac_addr); 532 return -EINVAL; 533 } 534 535 memcpy(&in6, grh->dgid.raw, sizeof(in6)); 536 dmac = rdma_ah_retrieve_dmac(ah_attr); 537 if (!dmac) 538 return -EINVAL; 539 ether_addr_copy(mac_addr, dmac); 540 541 return 0; 542 } 543 544 struct qedr_iw_listener { 545 struct qedr_dev *dev; 546 struct iw_cm_id *cm_id; 547 int backlog; 548 void *qed_handle; 549 }; 550 551 struct qedr_iw_ep { 552 struct qedr_dev *dev; 553 struct iw_cm_id *cm_id; 554 struct qedr_qp *qp; 555 void *qed_context; 556 struct kref refcnt; 557 }; 558 559 static inline 560 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 561 { 562 return container_of(ibucontext, struct qedr_ucontext, ibucontext); 563 } 564 565 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 566 { 567 return container_of(ibdev, struct qedr_dev, ibdev); 568 } 569 570 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 571 { 572 return container_of(ibpd, struct qedr_pd, ibpd); 573 } 574 575 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 576 { 577 return container_of(ibcq, struct qedr_cq, ibcq); 578 } 579 580 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 581 { 582 return container_of(ibqp, struct qedr_qp, ibqp); 583 } 584 585 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) 586 { 587 return container_of(ibah, struct qedr_ah, ibah); 588 } 589 590 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) 591 { 592 return container_of(ibmr, struct qedr_mr, ibmr); 593 } 594 595 static inline struct qedr_srq *get_qedr_srq(struct ib_srq *ibsrq) 596 { 597 return container_of(ibsrq, struct qedr_srq, ibsrq); 598 } 599 600 static inline struct qedr_user_mmap_entry * 601 get_qedr_mmap_entry(struct rdma_user_mmap_entry *rdma_entry) 602 { 603 return container_of(rdma_entry, struct qedr_user_mmap_entry, 604 rdma_entry); 605 } 606 #endif 607