12e0cbc4dSRam Amrani /* QLogic qedr NIC Driver 22e0cbc4dSRam Amrani * Copyright (c) 2015-2016 QLogic Corporation 32e0cbc4dSRam Amrani * 42e0cbc4dSRam Amrani * This software is available to you under a choice of one of two 52e0cbc4dSRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 62e0cbc4dSRam Amrani * General Public License (GPL) Version 2, available from the file 72e0cbc4dSRam Amrani * COPYING in the main directory of this source tree, or the 82e0cbc4dSRam Amrani * OpenIB.org BSD license below: 92e0cbc4dSRam Amrani * 102e0cbc4dSRam Amrani * Redistribution and use in source and binary forms, with or 112e0cbc4dSRam Amrani * without modification, are permitted provided that the following 122e0cbc4dSRam Amrani * conditions are met: 132e0cbc4dSRam Amrani * 142e0cbc4dSRam Amrani * - Redistributions of source code must retain the above 152e0cbc4dSRam Amrani * copyright notice, this list of conditions and the following 162e0cbc4dSRam Amrani * disclaimer. 172e0cbc4dSRam Amrani * 182e0cbc4dSRam Amrani * - Redistributions in binary form must reproduce the above 192e0cbc4dSRam Amrani * copyright notice, this list of conditions and the following 202e0cbc4dSRam Amrani * disclaimer in the documentation and /or other materials 212e0cbc4dSRam Amrani * provided with the distribution. 222e0cbc4dSRam Amrani * 232e0cbc4dSRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 242e0cbc4dSRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 252e0cbc4dSRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 262e0cbc4dSRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 272e0cbc4dSRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 282e0cbc4dSRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 292e0cbc4dSRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 302e0cbc4dSRam Amrani * SOFTWARE. 312e0cbc4dSRam Amrani */ 322e0cbc4dSRam Amrani #ifndef __QEDR_H__ 332e0cbc4dSRam Amrani #define __QEDR_H__ 342e0cbc4dSRam Amrani 352e0cbc4dSRam Amrani #include <linux/pci.h> 362e0cbc4dSRam Amrani #include <rdma/ib_addr.h> 372e0cbc4dSRam Amrani #include <linux/qed/qed_if.h> 38ec72fce4SRam Amrani #include <linux/qed/qed_chain.h> 397003cdd6SKalderon, Michal #include <linux/qed/qed_rdma_if.h> 40b262a06eSMichal Kalderon #include <linux/qed/qede_rdma.h> 41be086e7cSMintz, Yuval #include <linux/qed/roce_common.h> 42be086e7cSMintz, Yuval #include "qedr_hsi_rdma.h" 432e0cbc4dSRam Amrani 442e0cbc4dSRam Amrani #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 452e0cbc4dSRam Amrani #define DP_NAME(dev) ((dev)->ibdev.name) 462e0cbc4dSRam Amrani 472e0cbc4dSRam Amrani #define DP_DEBUG(dev, module, fmt, ...) \ 482e0cbc4dSRam Amrani pr_debug("(%s) " module ": " fmt, \ 492e0cbc4dSRam Amrani DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 502e0cbc4dSRam Amrani 512e0cbc4dSRam Amrani #define QEDR_MSG_INIT "INIT" 52ac1b36e5SRam Amrani #define QEDR_MSG_MISC "MISC" 53a7efd777SRam Amrani #define QEDR_MSG_CQ " CQ" 54a7efd777SRam Amrani #define QEDR_MSG_MR " MR" 55cecbcddfSRam Amrani #define QEDR_MSG_RQ " RQ" 56cecbcddfSRam Amrani #define QEDR_MSG_SQ " SQ" 57cecbcddfSRam Amrani #define QEDR_MSG_QP " QP" 5804886779SRam Amrani #define QEDR_MSG_GSI " GSI" 59a7efd777SRam Amrani 60a7efd777SRam Amrani #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 61e57bb6beSRam Amrani 62e57bb6beSRam Amrani #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) 63e57bb6beSRam Amrani #define FW_PAGE_SHIFT (12) 642e0cbc4dSRam Amrani 65ec72fce4SRam Amrani struct qedr_dev; 66ec72fce4SRam Amrani 67ec72fce4SRam Amrani struct qedr_cnq { 68ec72fce4SRam Amrani struct qedr_dev *dev; 69ec72fce4SRam Amrani struct qed_chain pbl; 70ec72fce4SRam Amrani struct qed_sb_info *sb; 71ec72fce4SRam Amrani char name[32]; 72ec72fce4SRam Amrani u64 n_comp; 73ec72fce4SRam Amrani __le16 *hw_cons_ptr; 74ec72fce4SRam Amrani u8 index; 75ec72fce4SRam Amrani }; 76ec72fce4SRam Amrani 77ec72fce4SRam Amrani #define QEDR_MAX_SGID 128 78ec72fce4SRam Amrani 79ec72fce4SRam Amrani struct qedr_device_attr { 80ec72fce4SRam Amrani u32 vendor_id; 81ec72fce4SRam Amrani u32 vendor_part_id; 82ec72fce4SRam Amrani u32 hw_ver; 83ec72fce4SRam Amrani u64 fw_ver; 84ec72fce4SRam Amrani u64 node_guid; 85ec72fce4SRam Amrani u64 sys_image_guid; 86ec72fce4SRam Amrani u8 max_cnq; 87ec72fce4SRam Amrani u8 max_sge; 88ec72fce4SRam Amrani u16 max_inline; 89ec72fce4SRam Amrani u32 max_sqe; 90ec72fce4SRam Amrani u32 max_rqe; 91ec72fce4SRam Amrani u8 max_qp_resp_rd_atomic_resc; 92ec72fce4SRam Amrani u8 max_qp_req_rd_atomic_resc; 93ec72fce4SRam Amrani u64 max_dev_resp_rd_atomic_resc; 94ec72fce4SRam Amrani u32 max_cq; 95ec72fce4SRam Amrani u32 max_qp; 96ec72fce4SRam Amrani u32 max_mr; 97ec72fce4SRam Amrani u64 max_mr_size; 98ec72fce4SRam Amrani u32 max_cqe; 99ec72fce4SRam Amrani u32 max_mw; 100ec72fce4SRam Amrani u32 max_fmr; 101ec72fce4SRam Amrani u32 max_mr_mw_fmr_pbl; 102ec72fce4SRam Amrani u64 max_mr_mw_fmr_size; 103ec72fce4SRam Amrani u32 max_pd; 104ec72fce4SRam Amrani u32 max_ah; 105ec72fce4SRam Amrani u8 max_pkey; 106ec72fce4SRam Amrani u32 max_srq; 107ec72fce4SRam Amrani u32 max_srq_wr; 108ec72fce4SRam Amrani u8 max_srq_sge; 109ec72fce4SRam Amrani u8 max_stats_queues; 110ec72fce4SRam Amrani u32 dev_caps; 111ec72fce4SRam Amrani 112ec72fce4SRam Amrani u64 page_size_caps; 113ec72fce4SRam Amrani u8 dev_ack_delay; 114ec72fce4SRam Amrani u32 reserved_lkey; 115ec72fce4SRam Amrani u32 bad_pkey_counter; 116ec72fce4SRam Amrani struct qed_rdma_events events; 117ec72fce4SRam Amrani }; 118ec72fce4SRam Amrani 119f449c7a2SRam Amrani #define QEDR_ENET_STATE_BIT (0) 120f449c7a2SRam Amrani 1212e0cbc4dSRam Amrani struct qedr_dev { 1222e0cbc4dSRam Amrani struct ib_device ibdev; 1232e0cbc4dSRam Amrani struct qed_dev *cdev; 1242e0cbc4dSRam Amrani struct pci_dev *pdev; 1252e0cbc4dSRam Amrani struct net_device *ndev; 1262e0cbc4dSRam Amrani 1272e0cbc4dSRam Amrani enum ib_atomic_cap atomic_cap; 1282e0cbc4dSRam Amrani 129ec72fce4SRam Amrani void *rdma_ctx; 130ec72fce4SRam Amrani struct qedr_device_attr attr; 131ec72fce4SRam Amrani 132ec72fce4SRam Amrani const struct qed_rdma_ops *ops; 133ec72fce4SRam Amrani struct qed_int_info int_info; 134ec72fce4SRam Amrani 135ec72fce4SRam Amrani struct qed_sb_info *sb_array; 136ec72fce4SRam Amrani struct qedr_cnq *cnq_array; 137ec72fce4SRam Amrani int num_cnq; 138ec72fce4SRam Amrani int sb_start; 139ec72fce4SRam Amrani 140ec72fce4SRam Amrani void __iomem *db_addr; 141ec72fce4SRam Amrani u64 db_phys_addr; 142ec72fce4SRam Amrani u32 db_size; 143ec72fce4SRam Amrani u16 dpi; 144ec72fce4SRam Amrani 145ec72fce4SRam Amrani union ib_gid *sgid_tbl; 146ec72fce4SRam Amrani 147ec72fce4SRam Amrani /* Lock for sgid table */ 148ec72fce4SRam Amrani spinlock_t sgid_lock; 149ec72fce4SRam Amrani 150ec72fce4SRam Amrani u64 guid; 151ec72fce4SRam Amrani 1522e0cbc4dSRam Amrani u32 dp_module; 1532e0cbc4dSRam Amrani u8 dp_level; 154ec72fce4SRam Amrani u8 num_hwfns; 1550518c12fSMichal Kalderon u8 gsi_ll2_handle; 1560518c12fSMichal Kalderon 157cecbcddfSRam Amrani uint wq_multiplier; 1581d1424c8SRam Amrani u8 gsi_ll2_mac_address[ETH_ALEN]; 15904886779SRam Amrani int gsi_qp_created; 16004886779SRam Amrani struct qedr_cq *gsi_sqcq; 16104886779SRam Amrani struct qedr_cq *gsi_rqcq; 16204886779SRam Amrani struct qedr_qp *gsi_qp; 163f449c7a2SRam Amrani 164f449c7a2SRam Amrani unsigned long enet_state; 165ad84dad2SAmrani, Ram 166ad84dad2SAmrani, Ram u8 user_dpm_enabled; 1672e0cbc4dSRam Amrani }; 168ec72fce4SRam Amrani 169ec72fce4SRam Amrani #define QEDR_MAX_SQ_PBL (0x8000) 170ec72fce4SRam Amrani #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 171ec72fce4SRam Amrani #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 172ec72fce4SRam Amrani #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 173ec72fce4SRam Amrani QEDR_SQE_ELEMENT_SIZE) 174ec72fce4SRam Amrani #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 175ec72fce4SRam Amrani QEDR_SQE_ELEMENT_SIZE) 176ec72fce4SRam Amrani #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 177ec72fce4SRam Amrani (RDMA_RING_PAGE_SIZE) / \ 178ec72fce4SRam Amrani (QEDR_SQE_ELEMENT_SIZE) /\ 179ec72fce4SRam Amrani (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 180ec72fce4SRam Amrani /* RQ */ 181ec72fce4SRam Amrani #define QEDR_MAX_RQ_PBL (0x2000) 182ec72fce4SRam Amrani #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 183ec72fce4SRam Amrani #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 184ec72fce4SRam Amrani #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 185ec72fce4SRam Amrani #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 186ec72fce4SRam Amrani QEDR_RQE_ELEMENT_SIZE) 187ec72fce4SRam Amrani #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 188ec72fce4SRam Amrani (RDMA_RING_PAGE_SIZE) / \ 189ec72fce4SRam Amrani (QEDR_RQE_ELEMENT_SIZE) /\ 190ec72fce4SRam Amrani (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 191ec72fce4SRam Amrani 192ec72fce4SRam Amrani #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 193ec72fce4SRam Amrani #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 194ec72fce4SRam Amrani #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 195ec72fce4SRam Amrani sizeof(u64)) - 1) 196ec72fce4SRam Amrani #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 197ec72fce4SRam Amrani (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 198ec72fce4SRam Amrani 199ec72fce4SRam Amrani #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 200ec72fce4SRam Amrani 201ec72fce4SRam Amrani #define QEDR_MAX_PORT (1) 202f449c7a2SRam Amrani #define QEDR_PORT (1) 203ec72fce4SRam Amrani 204ec72fce4SRam Amrani #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 205ec72fce4SRam Amrani 206ac1b36e5SRam Amrani #define QEDR_ROCE_PKEY_MAX 1 207ac1b36e5SRam Amrani #define QEDR_ROCE_PKEY_TABLE_LEN 1 208ac1b36e5SRam Amrani #define QEDR_ROCE_PKEY_DEFAULT 0xffff 209ac1b36e5SRam Amrani 210a7efd777SRam Amrani struct qedr_pbl { 211a7efd777SRam Amrani struct list_head list_entry; 212a7efd777SRam Amrani void *va; 213a7efd777SRam Amrani dma_addr_t pa; 214a7efd777SRam Amrani }; 215a7efd777SRam Amrani 216ac1b36e5SRam Amrani struct qedr_ucontext { 217ac1b36e5SRam Amrani struct ib_ucontext ibucontext; 218ac1b36e5SRam Amrani struct qedr_dev *dev; 219ac1b36e5SRam Amrani struct qedr_pd *pd; 220ac1b36e5SRam Amrani u64 dpi_addr; 221ac1b36e5SRam Amrani u64 dpi_phys_addr; 222ac1b36e5SRam Amrani u32 dpi_size; 223ac1b36e5SRam Amrani u16 dpi; 224ac1b36e5SRam Amrani 225ac1b36e5SRam Amrani struct list_head mm_head; 226ac1b36e5SRam Amrani 227ac1b36e5SRam Amrani /* Lock to protect mm list */ 228ac1b36e5SRam Amrani struct mutex mm_list_lock; 229ac1b36e5SRam Amrani }; 230ac1b36e5SRam Amrani 231a7efd777SRam Amrani union db_prod64 { 232a7efd777SRam Amrani struct rdma_pwm_val32_data data; 233a7efd777SRam Amrani u64 raw; 234a7efd777SRam Amrani }; 235a7efd777SRam Amrani 236a7efd777SRam Amrani enum qedr_cq_type { 237a7efd777SRam Amrani QEDR_CQ_TYPE_GSI, 238a7efd777SRam Amrani QEDR_CQ_TYPE_KERNEL, 239a7efd777SRam Amrani QEDR_CQ_TYPE_USER, 240a7efd777SRam Amrani }; 241a7efd777SRam Amrani 242a7efd777SRam Amrani struct qedr_pbl_info { 243a7efd777SRam Amrani u32 num_pbls; 244a7efd777SRam Amrani u32 num_pbes; 245a7efd777SRam Amrani u32 pbl_size; 246a7efd777SRam Amrani u32 pbe_size; 247a7efd777SRam Amrani bool two_layered; 248a7efd777SRam Amrani }; 249a7efd777SRam Amrani 250a7efd777SRam Amrani struct qedr_userq { 251a7efd777SRam Amrani struct ib_umem *umem; 252a7efd777SRam Amrani struct qedr_pbl_info pbl_info; 253a7efd777SRam Amrani struct qedr_pbl *pbl_tbl; 254a7efd777SRam Amrani u64 buf_addr; 255a7efd777SRam Amrani size_t buf_len; 256a7efd777SRam Amrani }; 257a7efd777SRam Amrani 258a7efd777SRam Amrani struct qedr_cq { 259a7efd777SRam Amrani struct ib_cq ibcq; 260a7efd777SRam Amrani 261a7efd777SRam Amrani enum qedr_cq_type cq_type; 262a7efd777SRam Amrani u32 sig; 263a7efd777SRam Amrani 264a7efd777SRam Amrani u16 icid; 265a7efd777SRam Amrani 266a7efd777SRam Amrani /* Lock to protect multiplem CQ's */ 267a7efd777SRam Amrani spinlock_t cq_lock; 268a7efd777SRam Amrani u8 arm_flags; 269a7efd777SRam Amrani struct qed_chain pbl; 270a7efd777SRam Amrani 271a7efd777SRam Amrani void __iomem *db_addr; 272a7efd777SRam Amrani union db_prod64 db; 273a7efd777SRam Amrani 274a7efd777SRam Amrani u8 pbl_toggle; 275a7efd777SRam Amrani union rdma_cqe *latest_cqe; 276a7efd777SRam Amrani union rdma_cqe *toggle_cqe; 277a7efd777SRam Amrani 278a7efd777SRam Amrani u32 cq_cons; 279a7efd777SRam Amrani 280a7efd777SRam Amrani struct qedr_userq q; 2814dd72636SAmrani, Ram u8 destroyed; 2824dd72636SAmrani, Ram u16 cnq_notif; 283a7efd777SRam Amrani }; 284a7efd777SRam Amrani 285a7efd777SRam Amrani struct qedr_pd { 286a7efd777SRam Amrani struct ib_pd ibpd; 287a7efd777SRam Amrani u32 pd_id; 288a7efd777SRam Amrani struct qedr_ucontext *uctx; 289a7efd777SRam Amrani }; 290a7efd777SRam Amrani 291ac1b36e5SRam Amrani struct qedr_mm { 292ac1b36e5SRam Amrani struct { 293ac1b36e5SRam Amrani u64 phy_addr; 294ac1b36e5SRam Amrani unsigned long len; 295ac1b36e5SRam Amrani } key; 296ac1b36e5SRam Amrani struct list_head entry; 297ac1b36e5SRam Amrani }; 298ac1b36e5SRam Amrani 299cecbcddfSRam Amrani union db_prod32 { 300cecbcddfSRam Amrani struct rdma_pwm_val16_data data; 301cecbcddfSRam Amrani u32 raw; 302cecbcddfSRam Amrani }; 303cecbcddfSRam Amrani 304cecbcddfSRam Amrani struct qedr_qp_hwq_info { 305cecbcddfSRam Amrani /* WQE Elements */ 306cecbcddfSRam Amrani struct qed_chain pbl; 307cecbcddfSRam Amrani u64 p_phys_addr_tbl; 308cecbcddfSRam Amrani u32 max_sges; 309cecbcddfSRam Amrani 310cecbcddfSRam Amrani /* WQE */ 311cecbcddfSRam Amrani u16 prod; 312cecbcddfSRam Amrani u16 cons; 313cecbcddfSRam Amrani u16 wqe_cons; 31404886779SRam Amrani u16 gsi_cons; 315cecbcddfSRam Amrani u16 max_wr; 316cecbcddfSRam Amrani 317cecbcddfSRam Amrani /* DB */ 318cecbcddfSRam Amrani void __iomem *db; 319cecbcddfSRam Amrani union db_prod32 db_data; 320cecbcddfSRam Amrani }; 321cecbcddfSRam Amrani 322cecbcddfSRam Amrani #define QEDR_INC_SW_IDX(p_info, index) \ 323cecbcddfSRam Amrani do { \ 324cecbcddfSRam Amrani p_info->index = (p_info->index + 1) & \ 325cecbcddfSRam Amrani qed_chain_get_capacity(p_info->pbl) \ 326cecbcddfSRam Amrani } while (0) 327cecbcddfSRam Amrani 328cecbcddfSRam Amrani enum qedr_qp_err_bitmap { 329cecbcddfSRam Amrani QEDR_QP_ERR_SQ_FULL = 1, 330cecbcddfSRam Amrani QEDR_QP_ERR_RQ_FULL = 2, 331cecbcddfSRam Amrani QEDR_QP_ERR_BAD_SR = 4, 332cecbcddfSRam Amrani QEDR_QP_ERR_BAD_RR = 8, 333cecbcddfSRam Amrani QEDR_QP_ERR_SQ_PBL_FULL = 16, 334cecbcddfSRam Amrani QEDR_QP_ERR_RQ_PBL_FULL = 32, 335cecbcddfSRam Amrani }; 336cecbcddfSRam Amrani 337cecbcddfSRam Amrani struct qedr_qp { 338cecbcddfSRam Amrani struct ib_qp ibqp; /* must be first */ 339cecbcddfSRam Amrani struct qedr_dev *dev; 340cecbcddfSRam Amrani 341cecbcddfSRam Amrani struct qedr_qp_hwq_info sq; 342cecbcddfSRam Amrani struct qedr_qp_hwq_info rq; 343cecbcddfSRam Amrani 344cecbcddfSRam Amrani u32 max_inline_data; 345cecbcddfSRam Amrani 346cecbcddfSRam Amrani /* Lock for QP's */ 347cecbcddfSRam Amrani spinlock_t q_lock; 348cecbcddfSRam Amrani struct qedr_cq *sq_cq; 349cecbcddfSRam Amrani struct qedr_cq *rq_cq; 350cecbcddfSRam Amrani struct qedr_srq *srq; 351cecbcddfSRam Amrani enum qed_roce_qp_state state; 352cecbcddfSRam Amrani u32 id; 353cecbcddfSRam Amrani struct qedr_pd *pd; 354cecbcddfSRam Amrani enum ib_qp_type qp_type; 355cecbcddfSRam Amrani struct qed_rdma_qp *qed_qp; 356cecbcddfSRam Amrani u32 qp_id; 357cecbcddfSRam Amrani u16 icid; 358cecbcddfSRam Amrani u16 mtu; 359cecbcddfSRam Amrani int sgid_idx; 360cecbcddfSRam Amrani u32 rq_psn; 361cecbcddfSRam Amrani u32 sq_psn; 362cecbcddfSRam Amrani u32 qkey; 363cecbcddfSRam Amrani u32 dest_qp_num; 364cecbcddfSRam Amrani 365cecbcddfSRam Amrani /* Relevant to qps created from kernel space only (ULPs) */ 366cecbcddfSRam Amrani u8 prev_wqe_size; 367cecbcddfSRam Amrani u16 wqe_cons; 368cecbcddfSRam Amrani u32 err_bitmap; 369cecbcddfSRam Amrani bool signaled; 370cecbcddfSRam Amrani 371cecbcddfSRam Amrani /* SQ shadow */ 372cecbcddfSRam Amrani struct { 373cecbcddfSRam Amrani u64 wr_id; 374cecbcddfSRam Amrani enum ib_wc_opcode opcode; 375cecbcddfSRam Amrani u32 bytes_len; 376cecbcddfSRam Amrani u8 wqe_size; 377cecbcddfSRam Amrani bool signaled; 378cecbcddfSRam Amrani dma_addr_t icrc_mapping; 379cecbcddfSRam Amrani u32 *icrc; 380cecbcddfSRam Amrani struct qedr_mr *mr; 381cecbcddfSRam Amrani } *wqe_wr_id; 382cecbcddfSRam Amrani 383cecbcddfSRam Amrani /* RQ shadow */ 384cecbcddfSRam Amrani struct { 385cecbcddfSRam Amrani u64 wr_id; 386cecbcddfSRam Amrani struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 387cecbcddfSRam Amrani u8 wqe_size; 388cecbcddfSRam Amrani 38904886779SRam Amrani u8 smac[ETH_ALEN]; 390efe63c22SAmrani, Ram u16 vlan; 391cecbcddfSRam Amrani int rc; 392cecbcddfSRam Amrani } *rqe_wr_id; 393cecbcddfSRam Amrani 394cecbcddfSRam Amrani /* Relevant to qps created from user space only (applications) */ 395cecbcddfSRam Amrani struct qedr_userq usq; 396cecbcddfSRam Amrani struct qedr_userq urq; 397cecbcddfSRam Amrani }; 398cecbcddfSRam Amrani 399e0290cceSRam Amrani struct qedr_ah { 400e0290cceSRam Amrani struct ib_ah ibah; 40190898850SDasaratharaman Chandramouli struct rdma_ah_attr attr; 402e0290cceSRam Amrani }; 403e0290cceSRam Amrani 404e0290cceSRam Amrani enum qedr_mr_type { 405e0290cceSRam Amrani QEDR_MR_USER, 406e0290cceSRam Amrani QEDR_MR_KERNEL, 407e0290cceSRam Amrani QEDR_MR_DMA, 408e0290cceSRam Amrani QEDR_MR_FRMR, 409e0290cceSRam Amrani }; 410e0290cceSRam Amrani 411e0290cceSRam Amrani struct mr_info { 412e0290cceSRam Amrani struct qedr_pbl *pbl_table; 413e0290cceSRam Amrani struct qedr_pbl_info pbl_info; 414e0290cceSRam Amrani struct list_head free_pbl_list; 415e0290cceSRam Amrani struct list_head inuse_pbl_list; 416e0290cceSRam Amrani u32 completed; 417e0290cceSRam Amrani u32 completed_handled; 418e0290cceSRam Amrani }; 419e0290cceSRam Amrani 420e0290cceSRam Amrani struct qedr_mr { 421e0290cceSRam Amrani struct ib_mr ibmr; 422e0290cceSRam Amrani struct ib_umem *umem; 423e0290cceSRam Amrani 424e0290cceSRam Amrani struct qed_rdma_register_tid_in_params hw_mr; 425e0290cceSRam Amrani enum qedr_mr_type type; 426e0290cceSRam Amrani 427e0290cceSRam Amrani struct qedr_dev *dev; 428e0290cceSRam Amrani struct mr_info info; 429e0290cceSRam Amrani 430e0290cceSRam Amrani u64 *pages; 431e0290cceSRam Amrani u32 npages; 432e0290cceSRam Amrani }; 433e0290cceSRam Amrani 434afa0e13bSRam Amrani #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) 435afa0e13bSRam Amrani 436afa0e13bSRam Amrani #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 437afa0e13bSRam Amrani RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 438afa0e13bSRam Amrani #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 439afa0e13bSRam Amrani RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 440b6acd71fSAmrani, Ram #define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ 441b6acd71fSAmrani, Ram RDMA_CQE_RESPONDER_INV_FLG_SHIFT) 442afa0e13bSRam Amrani 443afa0e13bSRam Amrani static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) 444afa0e13bSRam Amrani { 445afa0e13bSRam Amrani info->cons = (info->cons + 1) % info->max_wr; 446afa0e13bSRam Amrani info->wqe_cons++; 447afa0e13bSRam Amrani } 448afa0e13bSRam Amrani 449afa0e13bSRam Amrani static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) 450afa0e13bSRam Amrani { 451afa0e13bSRam Amrani info->prod = (info->prod + 1) % info->max_wr; 452afa0e13bSRam Amrani } 453afa0e13bSRam Amrani 454cecbcddfSRam Amrani static inline int qedr_get_dmac(struct qedr_dev *dev, 45590898850SDasaratharaman Chandramouli struct rdma_ah_attr *ah_attr, u8 *mac_addr) 456cecbcddfSRam Amrani { 457cecbcddfSRam Amrani union ib_gid zero_sgid = { { 0 } }; 458cecbcddfSRam Amrani struct in6_addr in6; 459d8966fcdSDasaratharaman Chandramouli const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 460d8966fcdSDasaratharaman Chandramouli u8 *dmac; 461cecbcddfSRam Amrani 462d8966fcdSDasaratharaman Chandramouli if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) { 463cecbcddfSRam Amrani DP_ERR(dev, "Local port GID not supported\n"); 464cecbcddfSRam Amrani eth_zero_addr(mac_addr); 465cecbcddfSRam Amrani return -EINVAL; 466cecbcddfSRam Amrani } 467cecbcddfSRam Amrani 468d8966fcdSDasaratharaman Chandramouli memcpy(&in6, grh->dgid.raw, sizeof(in6)); 469d8966fcdSDasaratharaman Chandramouli dmac = rdma_ah_retrieve_dmac(ah_attr); 470d8966fcdSDasaratharaman Chandramouli if (!dmac) 471d8966fcdSDasaratharaman Chandramouli return -EINVAL; 472d8966fcdSDasaratharaman Chandramouli ether_addr_copy(mac_addr, dmac); 473cecbcddfSRam Amrani 474cecbcddfSRam Amrani return 0; 475cecbcddfSRam Amrani } 476cecbcddfSRam Amrani 477ac1b36e5SRam Amrani static inline 478ac1b36e5SRam Amrani struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 479ac1b36e5SRam Amrani { 480ac1b36e5SRam Amrani return container_of(ibucontext, struct qedr_ucontext, ibucontext); 481ac1b36e5SRam Amrani } 482ac1b36e5SRam Amrani 483ec72fce4SRam Amrani static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 484ec72fce4SRam Amrani { 485ec72fce4SRam Amrani return container_of(ibdev, struct qedr_dev, ibdev); 486ec72fce4SRam Amrani } 487ec72fce4SRam Amrani 488a7efd777SRam Amrani static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 489a7efd777SRam Amrani { 490a7efd777SRam Amrani return container_of(ibpd, struct qedr_pd, ibpd); 491a7efd777SRam Amrani } 492a7efd777SRam Amrani 493a7efd777SRam Amrani static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 494a7efd777SRam Amrani { 495a7efd777SRam Amrani return container_of(ibcq, struct qedr_cq, ibcq); 496a7efd777SRam Amrani } 497a7efd777SRam Amrani 498cecbcddfSRam Amrani static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 499cecbcddfSRam Amrani { 500cecbcddfSRam Amrani return container_of(ibqp, struct qedr_qp, ibqp); 501cecbcddfSRam Amrani } 502e0290cceSRam Amrani 50304886779SRam Amrani static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) 50404886779SRam Amrani { 50504886779SRam Amrani return container_of(ibah, struct qedr_ah, ibah); 50604886779SRam Amrani } 50704886779SRam Amrani 508e0290cceSRam Amrani static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) 509e0290cceSRam Amrani { 510e0290cceSRam Amrani return container_of(ibmr, struct qedr_mr, ibmr); 511e0290cceSRam Amrani } 5122e0cbc4dSRam Amrani #endif 513