12e0cbc4dSRam Amrani /* QLogic qedr NIC Driver 22e0cbc4dSRam Amrani * Copyright (c) 2015-2016 QLogic Corporation 32e0cbc4dSRam Amrani * 42e0cbc4dSRam Amrani * This software is available to you under a choice of one of two 52e0cbc4dSRam Amrani * licenses. You may choose to be licensed under the terms of the GNU 62e0cbc4dSRam Amrani * General Public License (GPL) Version 2, available from the file 72e0cbc4dSRam Amrani * COPYING in the main directory of this source tree, or the 82e0cbc4dSRam Amrani * OpenIB.org BSD license below: 92e0cbc4dSRam Amrani * 102e0cbc4dSRam Amrani * Redistribution and use in source and binary forms, with or 112e0cbc4dSRam Amrani * without modification, are permitted provided that the following 122e0cbc4dSRam Amrani * conditions are met: 132e0cbc4dSRam Amrani * 142e0cbc4dSRam Amrani * - Redistributions of source code must retain the above 152e0cbc4dSRam Amrani * copyright notice, this list of conditions and the following 162e0cbc4dSRam Amrani * disclaimer. 172e0cbc4dSRam Amrani * 182e0cbc4dSRam Amrani * - Redistributions in binary form must reproduce the above 192e0cbc4dSRam Amrani * copyright notice, this list of conditions and the following 202e0cbc4dSRam Amrani * disclaimer in the documentation and /or other materials 212e0cbc4dSRam Amrani * provided with the distribution. 222e0cbc4dSRam Amrani * 232e0cbc4dSRam Amrani * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 242e0cbc4dSRam Amrani * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 252e0cbc4dSRam Amrani * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 262e0cbc4dSRam Amrani * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 272e0cbc4dSRam Amrani * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 282e0cbc4dSRam Amrani * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 292e0cbc4dSRam Amrani * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 302e0cbc4dSRam Amrani * SOFTWARE. 312e0cbc4dSRam Amrani */ 322e0cbc4dSRam Amrani #ifndef __QEDR_H__ 332e0cbc4dSRam Amrani #define __QEDR_H__ 342e0cbc4dSRam Amrani 352e0cbc4dSRam Amrani #include <linux/pci.h> 362e0cbc4dSRam Amrani #include <rdma/ib_addr.h> 372e0cbc4dSRam Amrani #include <linux/qed/qed_if.h> 38ec72fce4SRam Amrani #include <linux/qed/qed_chain.h> 39ec72fce4SRam Amrani #include <linux/qed/qed_roce_if.h> 402e0cbc4dSRam Amrani #include <linux/qed/qede_roce.h> 41ec72fce4SRam Amrani #include "qedr_hsi.h" 422e0cbc4dSRam Amrani 432e0cbc4dSRam Amrani #define QEDR_MODULE_VERSION "8.10.10.0" 442e0cbc4dSRam Amrani #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" 452e0cbc4dSRam Amrani #define DP_NAME(dev) ((dev)->ibdev.name) 462e0cbc4dSRam Amrani 472e0cbc4dSRam Amrani #define DP_DEBUG(dev, module, fmt, ...) \ 482e0cbc4dSRam Amrani pr_debug("(%s) " module ": " fmt, \ 492e0cbc4dSRam Amrani DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) 502e0cbc4dSRam Amrani 512e0cbc4dSRam Amrani #define QEDR_MSG_INIT "INIT" 52ac1b36e5SRam Amrani #define QEDR_MSG_MISC "MISC" 53a7efd777SRam Amrani #define QEDR_MSG_CQ " CQ" 54a7efd777SRam Amrani #define QEDR_MSG_MR " MR" 55cecbcddfSRam Amrani #define QEDR_MSG_RQ " RQ" 56cecbcddfSRam Amrani #define QEDR_MSG_SQ " SQ" 57cecbcddfSRam Amrani #define QEDR_MSG_QP " QP" 58a7efd777SRam Amrani 59a7efd777SRam Amrani #define QEDR_CQ_MAGIC_NUMBER (0x11223344) 602e0cbc4dSRam Amrani 61ec72fce4SRam Amrani struct qedr_dev; 62ec72fce4SRam Amrani 63ec72fce4SRam Amrani struct qedr_cnq { 64ec72fce4SRam Amrani struct qedr_dev *dev; 65ec72fce4SRam Amrani struct qed_chain pbl; 66ec72fce4SRam Amrani struct qed_sb_info *sb; 67ec72fce4SRam Amrani char name[32]; 68ec72fce4SRam Amrani u64 n_comp; 69ec72fce4SRam Amrani __le16 *hw_cons_ptr; 70ec72fce4SRam Amrani u8 index; 71ec72fce4SRam Amrani }; 72ec72fce4SRam Amrani 73ec72fce4SRam Amrani #define QEDR_MAX_SGID 128 74ec72fce4SRam Amrani 75ec72fce4SRam Amrani struct qedr_device_attr { 76ec72fce4SRam Amrani u32 vendor_id; 77ec72fce4SRam Amrani u32 vendor_part_id; 78ec72fce4SRam Amrani u32 hw_ver; 79ec72fce4SRam Amrani u64 fw_ver; 80ec72fce4SRam Amrani u64 node_guid; 81ec72fce4SRam Amrani u64 sys_image_guid; 82ec72fce4SRam Amrani u8 max_cnq; 83ec72fce4SRam Amrani u8 max_sge; 84ec72fce4SRam Amrani u16 max_inline; 85ec72fce4SRam Amrani u32 max_sqe; 86ec72fce4SRam Amrani u32 max_rqe; 87ec72fce4SRam Amrani u8 max_qp_resp_rd_atomic_resc; 88ec72fce4SRam Amrani u8 max_qp_req_rd_atomic_resc; 89ec72fce4SRam Amrani u64 max_dev_resp_rd_atomic_resc; 90ec72fce4SRam Amrani u32 max_cq; 91ec72fce4SRam Amrani u32 max_qp; 92ec72fce4SRam Amrani u32 max_mr; 93ec72fce4SRam Amrani u64 max_mr_size; 94ec72fce4SRam Amrani u32 max_cqe; 95ec72fce4SRam Amrani u32 max_mw; 96ec72fce4SRam Amrani u32 max_fmr; 97ec72fce4SRam Amrani u32 max_mr_mw_fmr_pbl; 98ec72fce4SRam Amrani u64 max_mr_mw_fmr_size; 99ec72fce4SRam Amrani u32 max_pd; 100ec72fce4SRam Amrani u32 max_ah; 101ec72fce4SRam Amrani u8 max_pkey; 102ec72fce4SRam Amrani u32 max_srq; 103ec72fce4SRam Amrani u32 max_srq_wr; 104ec72fce4SRam Amrani u8 max_srq_sge; 105ec72fce4SRam Amrani u8 max_stats_queues; 106ec72fce4SRam Amrani u32 dev_caps; 107ec72fce4SRam Amrani 108ec72fce4SRam Amrani u64 page_size_caps; 109ec72fce4SRam Amrani u8 dev_ack_delay; 110ec72fce4SRam Amrani u32 reserved_lkey; 111ec72fce4SRam Amrani u32 bad_pkey_counter; 112ec72fce4SRam Amrani struct qed_rdma_events events; 113ec72fce4SRam Amrani }; 114ec72fce4SRam Amrani 1152e0cbc4dSRam Amrani struct qedr_dev { 1162e0cbc4dSRam Amrani struct ib_device ibdev; 1172e0cbc4dSRam Amrani struct qed_dev *cdev; 1182e0cbc4dSRam Amrani struct pci_dev *pdev; 1192e0cbc4dSRam Amrani struct net_device *ndev; 1202e0cbc4dSRam Amrani 1212e0cbc4dSRam Amrani enum ib_atomic_cap atomic_cap; 1222e0cbc4dSRam Amrani 123ec72fce4SRam Amrani void *rdma_ctx; 124ec72fce4SRam Amrani struct qedr_device_attr attr; 125ec72fce4SRam Amrani 126ec72fce4SRam Amrani const struct qed_rdma_ops *ops; 127ec72fce4SRam Amrani struct qed_int_info int_info; 128ec72fce4SRam Amrani 129ec72fce4SRam Amrani struct qed_sb_info *sb_array; 130ec72fce4SRam Amrani struct qedr_cnq *cnq_array; 131ec72fce4SRam Amrani int num_cnq; 132ec72fce4SRam Amrani int sb_start; 133ec72fce4SRam Amrani 134ec72fce4SRam Amrani void __iomem *db_addr; 135ec72fce4SRam Amrani u64 db_phys_addr; 136ec72fce4SRam Amrani u32 db_size; 137ec72fce4SRam Amrani u16 dpi; 138ec72fce4SRam Amrani 139ec72fce4SRam Amrani union ib_gid *sgid_tbl; 140ec72fce4SRam Amrani 141ec72fce4SRam Amrani /* Lock for sgid table */ 142ec72fce4SRam Amrani spinlock_t sgid_lock; 143ec72fce4SRam Amrani 144ec72fce4SRam Amrani u64 guid; 145ec72fce4SRam Amrani 1462e0cbc4dSRam Amrani u32 dp_module; 1472e0cbc4dSRam Amrani u8 dp_level; 148ec72fce4SRam Amrani u8 num_hwfns; 149cecbcddfSRam Amrani uint wq_multiplier; 150cecbcddfSRam Amrani 1512e0cbc4dSRam Amrani }; 152ec72fce4SRam Amrani 153ec72fce4SRam Amrani #define QEDR_MAX_SQ_PBL (0x8000) 154ec72fce4SRam Amrani #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 155ec72fce4SRam Amrani #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) 156ec72fce4SRam Amrani #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 157ec72fce4SRam Amrani QEDR_SQE_ELEMENT_SIZE) 158ec72fce4SRam Amrani #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 159ec72fce4SRam Amrani QEDR_SQE_ELEMENT_SIZE) 160ec72fce4SRam Amrani #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ 161ec72fce4SRam Amrani (RDMA_RING_PAGE_SIZE) / \ 162ec72fce4SRam Amrani (QEDR_SQE_ELEMENT_SIZE) /\ 163ec72fce4SRam Amrani (QEDR_MAX_SQE_ELEMENTS_PER_SQE)) 164ec72fce4SRam Amrani /* RQ */ 165ec72fce4SRam Amrani #define QEDR_MAX_RQ_PBL (0x2000) 166ec72fce4SRam Amrani #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) 167ec72fce4SRam Amrani #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) 168ec72fce4SRam Amrani #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) 169ec72fce4SRam Amrani #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 170ec72fce4SRam Amrani QEDR_RQE_ELEMENT_SIZE) 171ec72fce4SRam Amrani #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ 172ec72fce4SRam Amrani (RDMA_RING_PAGE_SIZE) / \ 173ec72fce4SRam Amrani (QEDR_RQE_ELEMENT_SIZE) /\ 174ec72fce4SRam Amrani (QEDR_MAX_RQE_ELEMENTS_PER_RQE)) 175ec72fce4SRam Amrani 176ec72fce4SRam Amrani #define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) 177ec72fce4SRam Amrani #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) 178ec72fce4SRam Amrani #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ 179ec72fce4SRam Amrani sizeof(u64)) - 1) 180ec72fce4SRam Amrani #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ 181ec72fce4SRam Amrani (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) 182ec72fce4SRam Amrani 183ec72fce4SRam Amrani #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) 184ec72fce4SRam Amrani 185ec72fce4SRam Amrani #define QEDR_MAX_PORT (1) 186ec72fce4SRam Amrani 187ec72fce4SRam Amrani #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 188ec72fce4SRam Amrani 189ac1b36e5SRam Amrani #define QEDR_ROCE_PKEY_MAX 1 190ac1b36e5SRam Amrani #define QEDR_ROCE_PKEY_TABLE_LEN 1 191ac1b36e5SRam Amrani #define QEDR_ROCE_PKEY_DEFAULT 0xffff 192ac1b36e5SRam Amrani 193a7efd777SRam Amrani struct qedr_pbl { 194a7efd777SRam Amrani struct list_head list_entry; 195a7efd777SRam Amrani void *va; 196a7efd777SRam Amrani dma_addr_t pa; 197a7efd777SRam Amrani }; 198a7efd777SRam Amrani 199ac1b36e5SRam Amrani struct qedr_ucontext { 200ac1b36e5SRam Amrani struct ib_ucontext ibucontext; 201ac1b36e5SRam Amrani struct qedr_dev *dev; 202ac1b36e5SRam Amrani struct qedr_pd *pd; 203ac1b36e5SRam Amrani u64 dpi_addr; 204ac1b36e5SRam Amrani u64 dpi_phys_addr; 205ac1b36e5SRam Amrani u32 dpi_size; 206ac1b36e5SRam Amrani u16 dpi; 207ac1b36e5SRam Amrani 208ac1b36e5SRam Amrani struct list_head mm_head; 209ac1b36e5SRam Amrani 210ac1b36e5SRam Amrani /* Lock to protect mm list */ 211ac1b36e5SRam Amrani struct mutex mm_list_lock; 212ac1b36e5SRam Amrani }; 213ac1b36e5SRam Amrani 214a7efd777SRam Amrani union db_prod64 { 215a7efd777SRam Amrani struct rdma_pwm_val32_data data; 216a7efd777SRam Amrani u64 raw; 217a7efd777SRam Amrani }; 218a7efd777SRam Amrani 219a7efd777SRam Amrani enum qedr_cq_type { 220a7efd777SRam Amrani QEDR_CQ_TYPE_GSI, 221a7efd777SRam Amrani QEDR_CQ_TYPE_KERNEL, 222a7efd777SRam Amrani QEDR_CQ_TYPE_USER, 223a7efd777SRam Amrani }; 224a7efd777SRam Amrani 225a7efd777SRam Amrani struct qedr_pbl_info { 226a7efd777SRam Amrani u32 num_pbls; 227a7efd777SRam Amrani u32 num_pbes; 228a7efd777SRam Amrani u32 pbl_size; 229a7efd777SRam Amrani u32 pbe_size; 230a7efd777SRam Amrani bool two_layered; 231a7efd777SRam Amrani }; 232a7efd777SRam Amrani 233a7efd777SRam Amrani struct qedr_userq { 234a7efd777SRam Amrani struct ib_umem *umem; 235a7efd777SRam Amrani struct qedr_pbl_info pbl_info; 236a7efd777SRam Amrani struct qedr_pbl *pbl_tbl; 237a7efd777SRam Amrani u64 buf_addr; 238a7efd777SRam Amrani size_t buf_len; 239a7efd777SRam Amrani }; 240a7efd777SRam Amrani 241a7efd777SRam Amrani struct qedr_cq { 242a7efd777SRam Amrani struct ib_cq ibcq; 243a7efd777SRam Amrani 244a7efd777SRam Amrani enum qedr_cq_type cq_type; 245a7efd777SRam Amrani u32 sig; 246a7efd777SRam Amrani 247a7efd777SRam Amrani u16 icid; 248a7efd777SRam Amrani 249a7efd777SRam Amrani /* Lock to protect multiplem CQ's */ 250a7efd777SRam Amrani spinlock_t cq_lock; 251a7efd777SRam Amrani u8 arm_flags; 252a7efd777SRam Amrani struct qed_chain pbl; 253a7efd777SRam Amrani 254a7efd777SRam Amrani void __iomem *db_addr; 255a7efd777SRam Amrani union db_prod64 db; 256a7efd777SRam Amrani 257a7efd777SRam Amrani u8 pbl_toggle; 258a7efd777SRam Amrani union rdma_cqe *latest_cqe; 259a7efd777SRam Amrani union rdma_cqe *toggle_cqe; 260a7efd777SRam Amrani 261a7efd777SRam Amrani u32 cq_cons; 262a7efd777SRam Amrani 263a7efd777SRam Amrani struct qedr_userq q; 264a7efd777SRam Amrani }; 265a7efd777SRam Amrani 266a7efd777SRam Amrani struct qedr_pd { 267a7efd777SRam Amrani struct ib_pd ibpd; 268a7efd777SRam Amrani u32 pd_id; 269a7efd777SRam Amrani struct qedr_ucontext *uctx; 270a7efd777SRam Amrani }; 271a7efd777SRam Amrani 272ac1b36e5SRam Amrani struct qedr_mm { 273ac1b36e5SRam Amrani struct { 274ac1b36e5SRam Amrani u64 phy_addr; 275ac1b36e5SRam Amrani unsigned long len; 276ac1b36e5SRam Amrani } key; 277ac1b36e5SRam Amrani struct list_head entry; 278ac1b36e5SRam Amrani }; 279ac1b36e5SRam Amrani 280cecbcddfSRam Amrani union db_prod32 { 281cecbcddfSRam Amrani struct rdma_pwm_val16_data data; 282cecbcddfSRam Amrani u32 raw; 283cecbcddfSRam Amrani }; 284cecbcddfSRam Amrani 285cecbcddfSRam Amrani struct qedr_qp_hwq_info { 286cecbcddfSRam Amrani /* WQE Elements */ 287cecbcddfSRam Amrani struct qed_chain pbl; 288cecbcddfSRam Amrani u64 p_phys_addr_tbl; 289cecbcddfSRam Amrani u32 max_sges; 290cecbcddfSRam Amrani 291cecbcddfSRam Amrani /* WQE */ 292cecbcddfSRam Amrani u16 prod; 293cecbcddfSRam Amrani u16 cons; 294cecbcddfSRam Amrani u16 wqe_cons; 295cecbcddfSRam Amrani u16 max_wr; 296cecbcddfSRam Amrani 297cecbcddfSRam Amrani /* DB */ 298cecbcddfSRam Amrani void __iomem *db; 299cecbcddfSRam Amrani union db_prod32 db_data; 300cecbcddfSRam Amrani }; 301cecbcddfSRam Amrani 302cecbcddfSRam Amrani #define QEDR_INC_SW_IDX(p_info, index) \ 303cecbcddfSRam Amrani do { \ 304cecbcddfSRam Amrani p_info->index = (p_info->index + 1) & \ 305cecbcddfSRam Amrani qed_chain_get_capacity(p_info->pbl) \ 306cecbcddfSRam Amrani } while (0) 307cecbcddfSRam Amrani 308cecbcddfSRam Amrani enum qedr_qp_err_bitmap { 309cecbcddfSRam Amrani QEDR_QP_ERR_SQ_FULL = 1, 310cecbcddfSRam Amrani QEDR_QP_ERR_RQ_FULL = 2, 311cecbcddfSRam Amrani QEDR_QP_ERR_BAD_SR = 4, 312cecbcddfSRam Amrani QEDR_QP_ERR_BAD_RR = 8, 313cecbcddfSRam Amrani QEDR_QP_ERR_SQ_PBL_FULL = 16, 314cecbcddfSRam Amrani QEDR_QP_ERR_RQ_PBL_FULL = 32, 315cecbcddfSRam Amrani }; 316cecbcddfSRam Amrani 317cecbcddfSRam Amrani struct qedr_qp { 318cecbcddfSRam Amrani struct ib_qp ibqp; /* must be first */ 319cecbcddfSRam Amrani struct qedr_dev *dev; 320cecbcddfSRam Amrani 321cecbcddfSRam Amrani struct qedr_qp_hwq_info sq; 322cecbcddfSRam Amrani struct qedr_qp_hwq_info rq; 323cecbcddfSRam Amrani 324cecbcddfSRam Amrani u32 max_inline_data; 325cecbcddfSRam Amrani 326cecbcddfSRam Amrani /* Lock for QP's */ 327cecbcddfSRam Amrani spinlock_t q_lock; 328cecbcddfSRam Amrani struct qedr_cq *sq_cq; 329cecbcddfSRam Amrani struct qedr_cq *rq_cq; 330cecbcddfSRam Amrani struct qedr_srq *srq; 331cecbcddfSRam Amrani enum qed_roce_qp_state state; 332cecbcddfSRam Amrani u32 id; 333cecbcddfSRam Amrani struct qedr_pd *pd; 334cecbcddfSRam Amrani enum ib_qp_type qp_type; 335cecbcddfSRam Amrani struct qed_rdma_qp *qed_qp; 336cecbcddfSRam Amrani u32 qp_id; 337cecbcddfSRam Amrani u16 icid; 338cecbcddfSRam Amrani u16 mtu; 339cecbcddfSRam Amrani int sgid_idx; 340cecbcddfSRam Amrani u32 rq_psn; 341cecbcddfSRam Amrani u32 sq_psn; 342cecbcddfSRam Amrani u32 qkey; 343cecbcddfSRam Amrani u32 dest_qp_num; 344cecbcddfSRam Amrani 345cecbcddfSRam Amrani /* Relevant to qps created from kernel space only (ULPs) */ 346cecbcddfSRam Amrani u8 prev_wqe_size; 347cecbcddfSRam Amrani u16 wqe_cons; 348cecbcddfSRam Amrani u32 err_bitmap; 349cecbcddfSRam Amrani bool signaled; 350cecbcddfSRam Amrani 351cecbcddfSRam Amrani /* SQ shadow */ 352cecbcddfSRam Amrani struct { 353cecbcddfSRam Amrani u64 wr_id; 354cecbcddfSRam Amrani enum ib_wc_opcode opcode; 355cecbcddfSRam Amrani u32 bytes_len; 356cecbcddfSRam Amrani u8 wqe_size; 357cecbcddfSRam Amrani bool signaled; 358cecbcddfSRam Amrani dma_addr_t icrc_mapping; 359cecbcddfSRam Amrani u32 *icrc; 360cecbcddfSRam Amrani struct qedr_mr *mr; 361cecbcddfSRam Amrani } *wqe_wr_id; 362cecbcddfSRam Amrani 363cecbcddfSRam Amrani /* RQ shadow */ 364cecbcddfSRam Amrani struct { 365cecbcddfSRam Amrani u64 wr_id; 366cecbcddfSRam Amrani struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 367cecbcddfSRam Amrani u8 wqe_size; 368cecbcddfSRam Amrani 369cecbcddfSRam Amrani u16 vlan_id; 370cecbcddfSRam Amrani int rc; 371cecbcddfSRam Amrani } *rqe_wr_id; 372cecbcddfSRam Amrani 373cecbcddfSRam Amrani /* Relevant to qps created from user space only (applications) */ 374cecbcddfSRam Amrani struct qedr_userq usq; 375cecbcddfSRam Amrani struct qedr_userq urq; 376cecbcddfSRam Amrani }; 377cecbcddfSRam Amrani 378cecbcddfSRam Amrani static inline int qedr_get_dmac(struct qedr_dev *dev, 379cecbcddfSRam Amrani struct ib_ah_attr *ah_attr, u8 *mac_addr) 380cecbcddfSRam Amrani { 381cecbcddfSRam Amrani union ib_gid zero_sgid = { { 0 } }; 382cecbcddfSRam Amrani struct in6_addr in6; 383cecbcddfSRam Amrani 384cecbcddfSRam Amrani if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) { 385cecbcddfSRam Amrani DP_ERR(dev, "Local port GID not supported\n"); 386cecbcddfSRam Amrani eth_zero_addr(mac_addr); 387cecbcddfSRam Amrani return -EINVAL; 388cecbcddfSRam Amrani } 389cecbcddfSRam Amrani 390cecbcddfSRam Amrani memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6)); 391cecbcddfSRam Amrani ether_addr_copy(mac_addr, ah_attr->dmac); 392cecbcddfSRam Amrani 393cecbcddfSRam Amrani return 0; 394cecbcddfSRam Amrani } 395cecbcddfSRam Amrani 396ac1b36e5SRam Amrani static inline 397ac1b36e5SRam Amrani struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) 398ac1b36e5SRam Amrani { 399ac1b36e5SRam Amrani return container_of(ibucontext, struct qedr_ucontext, ibucontext); 400ac1b36e5SRam Amrani } 401ac1b36e5SRam Amrani 402ec72fce4SRam Amrani static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) 403ec72fce4SRam Amrani { 404ec72fce4SRam Amrani return container_of(ibdev, struct qedr_dev, ibdev); 405ec72fce4SRam Amrani } 406ec72fce4SRam Amrani 407a7efd777SRam Amrani static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) 408a7efd777SRam Amrani { 409a7efd777SRam Amrani return container_of(ibpd, struct qedr_pd, ibpd); 410a7efd777SRam Amrani } 411a7efd777SRam Amrani 412a7efd777SRam Amrani static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) 413a7efd777SRam Amrani { 414a7efd777SRam Amrani return container_of(ibcq, struct qedr_cq, ibcq); 415a7efd777SRam Amrani } 416a7efd777SRam Amrani 417cecbcddfSRam Amrani static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) 418cecbcddfSRam Amrani { 419cecbcddfSRam Amrani return container_of(ibqp, struct qedr_qp, ibqp); 420cecbcddfSRam Amrani } 4212e0cbc4dSRam Amrani #endif 422